Searched full:pcc (Results 1 – 25 of 79) sorted by relevance
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6 * PCC (Platform Communication Channel) is defined in the ACPI 5.0+11 * shared memory regions as defined in the PCC table entries. The PCC12 * specification supports a Doorbell mechanism for the PCC clients14 * is also specified in each PCC table entry.18 * PCC Reads:22 * * Client issues mbox_send_message() which rings the PCC doorbell23 * for its PCC channel.28 * PCC Writes:33 * * Client issues mbox_send_message() which rings the PCC doorbell34 * for its PCC channel.[all …]
80 ``pcc-cpufreq``86 * pcc-cpufreq.txt - PCC interface documentation100 1.1 PCC interface113 Processor Clocking Control (PCC) is an interface between the platform117 The PCC driver (pcc-cpufreq) allows OSPM to take advantage of the PCC120 OS utilizes the PCC interface to inform platform firmware what frequency the126 1.1 PCC interface:128 The complete PCC specification is available here:131 PCC relies on a shared memory region that provides a channel for communication132 between the OS and platform firmware. PCC also implements a "doorbell" that[all …]
6 * The PCC Address Space also referred as PCC Operation Region pertains to the7 * region of PCC subspace that succeeds the PCC signature. The PCC Operation8 * Region works in conjunction with the PCC Table(Platform Communications9 * Channel Table). PCC subspaces that are marked for use as PCC Operation10 * Regions must not be used as PCC subspaces for the standard ACPI features12 * the PCC Table instead.14 * This driver sets up the PCC Address Space and installs an handler to enable15 * handling of PCC OpRegion in the firmware.24 #include <acpi/pcc.h>28 * to PCC commands[all …]
26 * called (PCC) Platform Communication Channel. This is a generic mailbox like28 * See drivers/mailbox/pcc.c for details on PCC.30 * Finer details about the PCC and CPPC spec are available in the ACPI v5.1 and55 bool pending_pcc_write_cmd; /* Any pending/batched PCC write cmds? */56 bool platform_owns_pcc; /* Ownership of PCC subspace */57 unsigned int pcc_write_cnt; /* Running count of PCC write commands */60 * Lock to provide controlled access to the PCC channel.64 * before reading or writing to PCC subspace83 /* Array to represent the PCC channel per subspace ID */91 * include the type of register (e.g. PCC, System IO, FFH etc.)[all …]
287 select PCC553 bool "ACPI PCC Address Space"554 depends on PCC557 The PCC Address Space also referred as PCC Operation Region pertains558 to the region of PCC subspace that succeeds the PCC signature.560 The PCC Operation Region works in conjunction with the PCC Table561 (Platform Communications Channel Table). PCC subspaces that are562 marked for use as PCC Operation Regions must not be used as PCC564 MPST. These standard features must always use the PCC Table instead.566 Enable this feature if you want to set up and install the PCC Address[all …]
727 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING DEA",728 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-DEA function ending with CC=0"734 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 128",735 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-128 function ending with CC=0"741 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING TDEA 192",742 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-TDEA-192 function ending with CC=0"748 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED DEA",749 "PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-DEA function ending with CC=0"755 "BriefDescription": "PCC COMPUTE LAST BLOCK CMAC USING ENCRYPTED TDEA 128",756 …"PublicDescription": "PCC-Compute-Last-Block-CMAC-Using-Encrypted-TDEA- 128 function ending with C…[all …]
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#7 title: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller14 Clock Generation (SCG) modules, Peripheral Clock Control (PCC)28 The Peripheral Clock Control (PCC) is responsible for clock selection,
4 $id: http://devicetree.org/schemas/clock/imx8ulp-pcc-clock.yaml#7 title: NXP i.MX8ULP Peripheral Clock Controller(PCC) Module14 under the control of several CGCs & PCCs modules. The PCC modules control
23 #define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */50 #define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */63 #define KN01_CSR_CRSRTST (1<<12) /* PCC test output */66 #define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
27 #include <acpi/pcc.h>62 * to PCC commands150 /* Copy the message to the PCC comm space */ in xgene_hwmon_pcc_rd()442 * If PCC, send a consumer command to Platform to get info in xgene_hwmon_evt_work()521 * This function is called when the PCC Mailbox received a message663 if (device_property_read_u32(&pdev->dev, "pcc-channel", in xgene_hwmon_probe()665 dev_err(&pdev->dev, "no pcc-channel property\n"); in xgene_hwmon_probe()683 dev_err(&pdev->dev, "PCC IRQ not supported\n"); in xgene_hwmon_probe()704 dev_err(&pdev->dev, "Failed to get PCC comm region\n"); in xgene_hwmon_probe()711 "Failed to ioremap PCC comm region\n"); in xgene_hwmon_probe()
511 struct bpf_mem_caches *cc; struct bpf_mem_caches __percpu *pcc; in bpf_mem_alloc_init() local552 pcc = __alloc_percpu_gfp(sizeof(*cc), 8, GFP_KERNEL); in bpf_mem_alloc_init()553 if (!pcc) in bpf_mem_alloc_init()560 cc = per_cpu_ptr(pcc, cpu); in bpf_mem_alloc_init()573 ma->caches = pcc; in bpf_mem_alloc_init()579 struct bpf_mem_caches __percpu *pcc; in bpf_mem_alloc_percpu_init() local581 pcc = __alloc_percpu_gfp(sizeof(struct bpf_mem_caches), 8, GFP_KERNEL); in bpf_mem_alloc_percpu_init()582 if (!pcc) in bpf_mem_alloc_percpu_init()585 ma->caches = pcc; in bpf_mem_alloc_percpu_init()593 struct bpf_mem_caches *cc; struct bpf_mem_caches __percpu *pcc; in bpf_mem_alloc_percpu_unit_init() local[all …]
139 /* PCC Interface Status Register */156 /* PCC General Control Register */166 /* PCC Card Status Change Register */176 /* PCC Card Status Change Interrupt Enable Register */190 /* PCC Software Control Register */
231 SIOF0, SIOF1, MMC, PCC, enumerator262 INTC_VECT(CMT, 0xf00), INTC_VECT(PCC, 0xf60),275 { 0xA4080006UL, 0, 16, 4, /* IPRI */ { SIOF0, SIOF1, MMC, PCC } },
205 * Reading from a PCC field unit does not require the handler because in acpi_ex_read_data_from_field()209 "PCC FieldRead bits %u\n", in acpi_ex_read_data_from_field()342 "PCC COMD field has been written. Invoking PCC handler now.\n")); in acpi_ex_write_data_to_field()
42 * with this pcc clock. in pcc_gate_enable()84 pr_info("PCC PR is 0 for clk:%s, bypass\n", name); in imx_ulp_clk_hw_composite()
244 USBH, USBF, TPU, PCC, MMCIF, SIM, enumerator281 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),310 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,329 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
113 .name = "pcc",126 /* Using pcc tick timer 1 */
17 #include <acpi/pcc.h>31 /* CPPC specific PCC commands. */
3 * PCC (Platform Communications Channel) methods
14 For ACPI, it is the PCC mailbox.
124 * Dynamic(adaptive)/Static PCC values526 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */527 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */534 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */1079 * PCC Control Registers
220 pr_info("FIE not enabled on systems with registers in PCC\n"); in cppc_freq_invariance_init()324 * The PCC subspace describes the rate at which platform can accept commands325 * on the shared PCC channel (including READs which do not count towards freq326 * transition requests), so ideally we need to use the PCC values as a fallback
27 This driver adds support for the PCC interface.33 module will be called pcc-cpufreq.
456 .pcc = {.name = "pcc", .base = 0x1700,461 .pcc = {.name = "pcc", .base = 0x1700,
4 // Peter Collingbourne <pcc@google.com>