| /linux/include/linux/dma/ |
| H A D | sprd-dma.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * The Spreadtrum DMA controller supports channel 2-stage tansfer, that means
16 * we can request 2 dma channels, one for source channel, and another one for
17 * destination channel. Each channel is independent, and has its own
18 * configurations. Once the source channel's transaction is done, it will
19 * trigger the destination channel's transaction automatically by hardware
22 * To support 2-stage tansfer, we must configure the channel mode and trigger
27 * enum sprd_dma_chn_mode: define the DMA channel mode for 2-stage transfer
28 * @SPRD_DMA_CHN_MODE_NONE: No channel mode setting which means channel doesn't
29 * support the 2-stage transfer.
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| /linux/include/sound/sof/ |
| H A D | channel_map.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
16 * \brief Channel map, specifies transformation of one-to-many or many-to-one.
18 * In case of one-to-many specifies how the output channels are computed out of
19 * a single source channel,
20 * in case of many-to-one specifies how a single target channel is computed
23 * Channel index specifies position of the channel in the stream on the 'one'
29 * Channel mask describes which channels are taken into account on the "many"
30 * side. Bit[i] set to 1 means that i-th channel is used for computation
33 * Channel mask is followed by array of coefficients in Q2.30 format,
34 * one per each channel set in the mask (left to right, LS bit set in the
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-scmi-raw | 7 in little-endian binary format to have it sent to the configured
11 Each write to the entry causes one command request to be built
12 and sent while the replies are read back one message at time
22 in little-endian binary format to have it sent to the configured
29 Each write to the entry causes one command request to be built
30 and sent while the replies are read back one message at time
38 Description: SCMI Raw message errors facility; any kind of timed-out or
41 Each read gives back one message at time (receiving an EOF at
52 Each read gives back one message at time (receiving an EOF at
65 different test-run.
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|
| /linux/Documentation/devicetree/bindings/dma/xilinx/ |
| H A D | xilinx_dma.txt | 2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12 address and a memory-mapped destination address.
19 - compatible: Should be one of-
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
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|
| /linux/Documentation/trace/ |
| H A D | stm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 protocol multiplexing data from multiple trace sources, each one of
10 which is assigned a unique pair of master and channel. While some of
14 master/channel combination from this pool.
17 sources can only be identified by master/channel combination, so in
20 master/channel pairs to the trace sources that it understands.
23 master 7 channel 15, while arbitrary user applications can use masters
34 associated with it, located in "stp-policy" subsystem directory in
40 $ ls /config/stp-policy/dummy_stm.my-policy/user
42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters
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|
| /linux/Documentation/driver-api/iio/ |
| H A D | core.rst | 8 :file:`drivers/iio/industrialio-*`
11 ----------------------
13 * struct iio_dev - industrial I/O device
14 * iio_device_alloc() - allocate an :c:type:`iio_dev` from a driver
15 * iio_device_free() - free an :c:type:`iio_dev` from a driver
16 * iio_device_register() - register a device with the IIO subsystem
17 * iio_device_unregister() - unregister a device from the IIO
63 :file:`Documentation/ABI/testing/sysfs-bus-iio` file in the Linux kernel
69 struct iio_chan_spec - specification of a single channel
71 An IIO device channel is a representation of a data channel. An IIO device can
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|
| /linux/Documentation/driver-api/ |
| H A D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
35 * Channel
37 A memory controller channel, responsible to communicate with a group of
38 DIMMs. Each channel has its own independent control (command) and data
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
48 just one memory stick when an error occurs, as the error correction code
49 is calculated using two DIMMs instead of one. Due to that, it is capable
52 * Single-channel
54 The data accessed by the memory controller is contained into one dimm
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|
| /linux/Documentation/arch/arm/stm32/ |
| H A D | stm32-dma-mdma-chaining.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 STM32 DMA-MDMA chaining
9 ------------
11 This document describes the STM32 DMA-MDMA chaining feature. But before going
44 ----------
46 STM32 DMA-MDMA chaining feature relies on the strengths of STM32 DMA and
50 (when DMA data counter - DMA_SxNDTR - reaches 0), the memory pointers
53 process one memory area while the second memory area is being filled/used by
56 With STM32 MDMA linked-list mode, a single request initiates the data array
57 (collection of nodes) to be transferred until the linked-list pointer for the
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|
| /linux/Documentation/userspace-api/media/v4l/ |
| H A D | vidioc-g-modulator.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_MODULATOR - VIDIOC_S_MODULATOR - Get or set modulator attributes
44 begin at index zero, incrementing by one until the driver returns
52 this is a write-only ioctl, it does not return the actual audio
67 .. flat-table:: struct v4l2_modulator
68 :header-rows: 0
69 :stub-columns: 0
72 * - __u32
73 - ``index``
74 - Identifies the modulator, set by the application.
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|
| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | ti,tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Andrew Davis <afd@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - ti,tlv320adc3140
29 - ti,tlv320adc5140
30 - ti,tlv320adc6140
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|
| /linux/sound/pci/ca0106/ |
| H A D | ca0106.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
12 * Removed noise from Center/LFE channel when in Analog mode.
50 * Implement support for Line-in capture on SB Live 24bit.
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
88 #define IPR_MIDI_TX_A 0x00000002 /* MIDI UART-A Transmit buffer empty */
93 #define INTE_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
94 #define INTE_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
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|
| /linux/drivers/net/wireless/quantenna/qtnfmac/ |
| H A D | qlink.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2015-2016 Quantenna Communications. All rights reserved. */
31 * enum qlink_msg_type - QLINK message types
49 * struct qlink_msg_header - common QLINK protocol message header
53 * @type: Message type, one of &enum qlink_msg_type.
65 * enum qlink_hw_capab - device capabilities.
68 * @QLINK_HW_CAPAB_STA_INACT_TIMEOUT: device implements a logic to kick-out
91 * enum qlink_driver_capab - host driver capabilities.
108 * struct qlink_intf_info - information on virtual interface.
112 * @if_type: Mode of interface operation, one of &enum qlink_iface_type
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|
| /linux/Documentation/staging/ |
| H A D | rpmsg.rst | 17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
25 hardware accelerators, and therefore are often used to offload CPU-intensive
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
37 Rpmsg is a virtio-based messaging bus that allows kernel drivers to communicate
54 Every rpmsg device is a communication channel with a remote processor (thus
59 When a driver starts listening on a channel, its rx callback is bound with
60 a unique rpmsg local address (a 32-bit integer). This way when inbound messages
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|
| /linux/Documentation/arch/mips/ |
| H A D | ingenic-tcu.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
26 - Each TCU channel works in one of two modes:
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|
| /linux/sound/firewire/dice/ |
| H A D | dice-interface.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
11 * block read transactions with at least quadlet-aligned offset and length.
12 * Writes are not allowed except where noted; quadlet-sized registers must be
15 * All values are in big endian. The DICE firmware runs on a little-endian CPU
16 * and just byte-swaps _all_ quadlets on the bus, so values without endianness
17 * (e.g. strings) get scrambled and must be byte-swapped again by the driver.
32 * size values are measured in quadlets. Read-only.
50 * Stores the full 64-bit address (node ID and offset in the node's address
60 * A bitmask with asynchronous events; read-only. When any event(s) happen,
74 /* Other bits may be used for device-specific events. */
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|
| /linux/Documentation/devicetree/bindings/iio/adc/ |
| H A D | xilinx-xadc.txt | 8 frontends for the DRP interface exist. One that is only available on the ZYNQ
9 family as a hardmacro in the SoC portion of the ZYNQ. The other one is available
22 - compatible: Should be one of
23 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
27 * "xlnx,system-management-wiz-1.3": When using the
30 - reg: Address and length of the register set for the device
31 - interrupts: Interrupt for the XADC control interface.
32 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
33 when using the axi-xadc or the axi-system-management-wizard this must be
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|
| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr-channel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
16 - Julius Werner <jwerner@chromium.org>
21 - jedec,lpddr2-channel
22 - jedec,lpddr3-channel
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|
| /linux/Documentation/devicetree/bindings/input/ |
| H A D | azoteq,iqs7222.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
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|
| /linux/Documentation/devicetree/bindings/display/ |
| H A D | dsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/dsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
24 can control one to four virtual channels to one panel. Each virtual
25 channel should have a node "panel" for their virtual channel with their
26 reg-property set to the virtual channel number, usually there is just
27 one virtual channel, number 0.
33 clock-master:
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|
| /linux/Documentation/networking/ |
| H A D | ppp_generic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 PPP Generic Driver and Channel Interface
12 The generic PPP driver in linux-2.4 provides an implementation of the
26 the services of PPP ``channels``. A PPP channel encapsulates a
27 mechanism for transporting PPP frames from one machine to another. A
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
43 ---------------
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|
| /linux/Documentation/fb/ |
| H A D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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|
| /linux/Documentation/filesystems/ |
| H A D | relay.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 to userspace via user-defined 'relay channels'.
11 A 'relay channel' is a kernel->user data relay mechanism implemented
12 as a set of per-cpu kernel buffers ('channel buffers'), each
14 clients write into the channel buffers using efficient write
15 functions; these automatically log into the current cpu's channel
19 are associated with the channel buffers using the API described below.
21 The format of the data logged into the channel buffers is completely
25 filtering - this also is left to the kernel client. The purpose is to
30 functions in the relay interface code - please see that for details.
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|
| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | phy.c | 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
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|
| /linux/drivers/staging/media/tegra-video/ |
| H A D | csi.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <media/media-entity.h>
10 #include <media/v4l2-async.h>
11 #include <media/v4l2-subdev.h>
15 * one x4 port using both CILA and CILB partitions of a CSI brick or can
16 * be used as two x2 ports with one x2 from CILA and the other x2 from
25 /* each CSI channel can have one sink and one source pads */
42 * struct tegra_csi_channel - Tegra CSI channel
45 * @subdev: V4L2 subdevice associated with this channel
51 * channel bus-width
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|
| /linux/sound/pci/emu10k1/ |
| H A D | p16v.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
20 /* One list entry: 4 bytes for DMA address,
22 * One list entry is 8 bytes long.
23 * One list entry for each period in the buffer.
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
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|