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/linux/drivers/staging/media/ipu3/
H A Dipu3-mmu.c21 #include "ipu3-mmu.h"
73 * @mmu: MMU to perform the invalidate operation on
78 static void imgu_mmu_tlb_invalidate(struct imgu_mmu *mmu) in imgu_mmu_tlb_invalidate() argument
80 writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE); in imgu_mmu_tlb_invalidate()
83 static void call_if_imgu_is_powered(struct imgu_mmu *mmu, in call_if_imgu_is_powered() argument
84 void (*func)(struct imgu_mmu *mmu)) in call_if_imgu_is_powered() argument
86 if (!pm_runtime_get_if_in_use(mmu->dev)) in call_if_imgu_is_powered()
89 func(mmu); in call_if_imgu_is_powered()
90 pm_runtime_put(mmu->dev); in call_if_imgu_is_powered()
95 * @mmu: MMU to set the CIO gate bit in.
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dbase.c42 nvkm_mmu_ptp_put(struct nvkm_mmu *mmu, bool force, struct nvkm_mmu_pt *pt) in nvkm_mmu_ptp_put() argument
51 list_add(&ptp->head, &mmu->ptp.list); in nvkm_mmu_ptp_put()
56 nvkm_mmu_ptc_put(mmu, force, &ptp->pt); in nvkm_mmu_ptp_put()
65 nvkm_mmu_ptp_get(struct nvkm_mmu *mmu, u32 size, bool zero) in nvkm_mmu_ptp_get() argument
74 ptp = list_first_entry_or_null(&mmu->ptp.list, typeof(*ptp), head); in nvkm_mmu_ptp_get()
82 ptp->pt = nvkm_mmu_ptc_get(mmu, 0x1000, 0x1000, false); in nvkm_mmu_ptp_get()
93 list_add(&ptp->head, &mmu->ptp.list); in nvkm_mmu_ptp_get()
120 nvkm_mmu_ptc_find(struct nvkm_mmu *mmu, u32 size) in nvkm_mmu_ptc_find() argument
124 list_for_each_entry(ptc, &mmu->ptc.list, head) { in nvkm_mmu_ptc_find()
134 list_add(&ptc->head, &mmu->ptc.list); in nvkm_mmu_ptc_find()
[all …]
H A Dummu.c35 struct nvkm_mmu *mmu = nvkm_ummu(object)->mmu; in nvkm_ummu_sclass() local
37 if (mmu->func->mem.user.oclass) { in nvkm_ummu_sclass()
39 oclass->base = mmu->func->mem.user; in nvkm_ummu_sclass()
45 if (mmu->func->vmm.user.oclass) { in nvkm_ummu_sclass()
47 oclass->base = mmu->func->vmm.user; in nvkm_ummu_sclass()
59 struct nvkm_mmu *mmu = ummu->mmu; in nvkm_ummu_heap() local
67 if ((index = args->v0.index) >= mmu->heap_nr) in nvkm_ummu_heap()
69 args->v0.size = mmu->heap[index].size; in nvkm_ummu_heap()
79 struct nvkm_mmu *mmu = ummu->mmu; in nvkm_ummu_type() local
87 if ((index = args->v0.index) >= mmu->type_nr) in nvkm_ummu_type()
[all …]
H A Dmem.c33 struct nvkm_mmu *mmu; member
88 dma_unmap_page(mem->mmu->subdev.device->dev, in nvkm_mem_dtor()
144 nvkm_mem_new_host(struct nvkm_mmu *mmu, int type, u8 page, u64 size, in nvkm_mem_new_host() argument
147 struct device *dev = mmu->subdev.device->dev; in nvkm_mem_new_host()
157 if ( (mmu->type[type].type & NVKM_MEM_COHERENT) && in nvkm_mem_new_host()
158 !(mmu->type[type].type & NVKM_MEM_UNCACHED)) in nvkm_mem_new_host()
169 mem->mmu = mmu; in nvkm_mem_new_host()
199 if (mmu->dma_bits > 32) in nvkm_mem_new_host()
209 mem->dma[mem->pages] = dma_map_page(mmu->subdev.device->dev, in nvkm_mem_new_host()
224 nvkm_mem_new_type(struct nvkm_mmu *mmu, int type, u8 page, u64 size, in nvkm_mem_new_type() argument
[all …]
/linux/drivers/gpu/drm/nouveau/nvif/
H A Dmmu.c22 #include <nvif/mmu.h>
28 nvif_mmu_dtor(struct nvif_mmu *mmu) in nvif_mmu_dtor() argument
30 if (!nvif_object_constructed(&mmu->object)) in nvif_mmu_dtor()
33 kfree(mmu->kind); in nvif_mmu_dtor()
34 kfree(mmu->type); in nvif_mmu_dtor()
35 kfree(mmu->heap); in nvif_mmu_dtor()
36 nvif_object_dtor(&mmu->object); in nvif_mmu_dtor()
41 struct nvif_mmu *mmu) in nvif_mmu_ctor() argument
53 mmu->heap = NULL; in nvif_mmu_ctor()
54 mmu->type = NULL; in nvif_mmu_ctor()
[all …]
/linux/drivers/iommu/
H A Dipmmu-vmsa.c71 struct ipmmu_vmsa_device *mmu; member
99 /* MMU "context" registers */
149 static bool ipmmu_is_root(struct ipmmu_vmsa_device *mmu) in ipmmu_is_root() argument
151 return mmu->root == mmu; in ipmmu_is_root()
156 struct ipmmu_vmsa_device *mmu = dev_get_drvdata(dev); in __ipmmu_check_device() local
159 if (ipmmu_is_root(mmu)) in __ipmmu_check_device()
160 *rootp = mmu; in __ipmmu_check_device()
177 static u32 ipmmu_read(struct ipmmu_vmsa_device *mmu, unsigned int offset) in ipmmu_read() argument
179 return ioread32(mmu->base + offset); in ipmmu_read()
182 static void ipmmu_write(struct ipmmu_vmsa_device *mmu, unsigned int offset, in ipmmu_write() argument
[all …]
/linux/drivers/staging/media/ipu7/
H A Dipu7-mmu.c31 #include "ipu7-mmu.h"
56 static __maybe_unused void mmu_irq_handler(struct ipu7_mmu *mmu) in mmu_irq_handler() argument
61 for (i = 0; i < mmu->nr_mmus; i++) { in mmu_irq_handler()
62 irq_cause = readl(mmu->mmu_hw[i].base + MMU_REG_IRQ_CAUSE); in mmu_irq_handler()
63 pr_info("mmu %s irq_cause = 0x%x", mmu->mmu_hw[i].name, in mmu_irq_handler()
65 writel(0x1ffff, mmu->mmu_hw[i].base + MMU_REG_IRQ_CLEAR); in mmu_irq_handler()
69 static void tlb_invalidate(struct ipu7_mmu *mmu) in tlb_invalidate() argument
76 spin_lock_irqsave(&mmu->ready_lock, flags); in tlb_invalidate()
77 if (!mmu->ready) { in tlb_invalidate()
78 spin_unlock_irqrestore(&mmu->ready_lock, flags); in tlb_invalidate()
[all …]
H A Dipu7-dma.c19 #include "ipu7-mmu.h"
29 static struct vm_info *get_vm_info(struct ipu7_mmu *mmu, dma_addr_t iova) in get_vm_info() argument
33 list_for_each_entry_safe(info, save, &mmu->vma_list, list) { in get_vm_info()
120 struct ipu7_mmu *mmu = sys->mmu; in ipu7_dma_sync_single() local
122 info = get_vm_info(mmu, dma_handle); in ipu7_dma_sync_single()
159 struct ipu7_mmu *mmu = sys->mmu; in ipu7_dma_alloc() local
174 iova = alloc_iova(&mmu->dmap->iovad, count, in ipu7_dma_alloc()
175 PHYS_PFN(mmu->dmap->mmu_info->aperture_end), 0); in ipu7_dma_alloc()
196 ret = ipu7_mmu_map(mmu->dmap->mmu_info, in ipu7_dma_alloc()
218 list_add(&info->list, &mmu->vma_list); in ipu7_dma_alloc()
[all …]
/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_mmu.c77 /* Wait for the MMU status to indicate there is no active command, in in wait_ready()
95 /* write AS_COMMAND when MMU is ready to accept another command */ in write_cmd()
148 /* Run the MMU operation */ in mmu_hw_do_operation_locked()
156 struct panfrost_mmu *mmu, in mmu_hw_do_operation() argument
162 ret = mmu_hw_do_operation_locked(pfdev, mmu->as, iova, size, op); in mmu_hw_do_operation()
167 static void panfrost_mmu_enable(struct panfrost_device *pfdev, struct panfrost_mmu *mmu) in panfrost_mmu_enable() argument
169 int as_nr = mmu->as; in panfrost_mmu_enable()
170 u64 transtab = mmu->cfg.transtab; in panfrost_mmu_enable()
171 u64 memattr = mmu->cfg.memattr; in panfrost_mmu_enable()
172 u64 transcfg = mmu->cfg.transcfg; in panfrost_mmu_enable()
[all …]
/linux/drivers/media/pci/intel/ipu6/
H A Dipu6-mmu.c29 #include "ipu6-mmu.h"
54 static void tlb_invalidate(struct ipu6_mmu *mmu) in tlb_invalidate() argument
59 spin_lock_irqsave(&mmu->ready_lock, flags); in tlb_invalidate()
60 if (!mmu->ready) { in tlb_invalidate()
61 spin_unlock_irqrestore(&mmu->ready_lock, flags); in tlb_invalidate()
65 for (i = 0; i < mmu->nr_mmus; i++) { in tlb_invalidate()
74 if (mmu->mmu_hw[i].insert_read_before_invalidate) in tlb_invalidate()
75 readl(mmu->mmu_hw[i].base + REG_L1_PHYS); in tlb_invalidate()
77 writel(0xffffffff, mmu->mmu_hw[i].base + in tlb_invalidate()
87 spin_unlock_irqrestore(&mmu->ready_lock, flags); in tlb_invalidate()
[all …]
H A Dipu6-dma.c19 #include "ipu6-mmu.h"
29 static struct vm_info *get_vm_info(struct ipu6_mmu *mmu, dma_addr_t iova) in get_vm_info() argument
33 list_for_each_entry_safe(info, save, &mmu->vma_list, list) { in get_vm_info()
120 struct ipu6_mmu *mmu = sys->mmu; in ipu6_dma_sync_single() local
122 info = get_vm_info(mmu, dma_handle); in ipu6_dma_sync_single()
159 struct ipu6_mmu *mmu = sys->mmu; in ipu6_dma_alloc() local
174 iova = alloc_iova(&mmu->dmap->iovad, count, in ipu6_dma_alloc()
175 PHYS_PFN(mmu->dmap->mmu_info->aperture_end), 0); in ipu6_dma_alloc()
196 ret = ipu6_mmu_map(mmu->dmap->mmu_info, in ipu6_dma_alloc()
218 list_add(&info->list, &mmu->vma_list); in ipu6_dma_alloc()
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_mmu.h17 void (*detach)(struct msm_mmu *mmu);
18 void (*prealloc_count)(struct msm_mmu *mmu, struct msm_mmu_prealloc *p,
20 int (*prealloc_allocate)(struct msm_mmu *mmu, struct msm_mmu_prealloc *p);
21 void (*prealloc_cleanup)(struct msm_mmu *mmu, struct msm_mmu_prealloc *p);
22 int (*map)(struct msm_mmu *mmu, uint64_t iova, struct sg_table *sgt,
24 int (*unmap)(struct msm_mmu *mmu, uint64_t iova, size_t len);
25 void (*destroy)(struct msm_mmu *mmu);
26 void (*set_stall)(struct msm_mmu *mmu, bool enable);
36 * struct msm_mmu_prealloc - Tracking for pre-allocated pages for MMU updates.
44 * @pages: Array of pages preallocated for MMU table updates.
[all …]
/linux/arch/m68k/
H A DKconfig.cpu6 default M68KCLASSIC if MMU
7 default COLDFIRE if !MMU
24 select M68020 if MMU && !(M68030 || M68040 || M68060)
35 select HAVE_PAGE_SIZE_8KB if !MMU
39 depends on MMU
53 def_bool M68KCLASSIC && !MMU
68 a paging MMU.
72 depends on MMU
78 68851 MMU (Memory Management Unit) to run Linux/m68k, except on the
81 if M68KCLASSIC && MMU
[all …]
H A DKconfig8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
21 select GENERIC_IOMAP if HAS_IOPORT && MMU && !COLDFIRE
38 select MMU_GATHER_NO_RANGE if MMU
41 select NO_DMA if !MMU && !COLDFIRE
44 select UACCESS_MEMCPY if !MMU
83 config MMU config
84 bool "MMU-based Paged Memory Management Support"
87 Select if you want MMU-based virtualised addressing space
91 def_bool MMU && M68KCLASSIC
95 def_bool MMU && COLDFIRE
[all …]
/linux/arch/arc/mm/
H A Dtlb.c16 #include <asm/mmu.h>
87 * If Not already present get a free slot from MMU. in tlb_entry_insert()
99 * Commit the Entry to MMU in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
136 struct cpuinfo_arc_mmu *mmu = &mmuinfo; in local_flush_tlb_all() local
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
182 * Only for fork( ) do we need to move parent to a new MMU ctxt, in local_flush_tlb_mm()
245 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
274 * Delete TLB entry in MMU for a given page (??? address)
403 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr) in create_tlb()
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Dsamsung,sysmmu.yaml7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
17 System MMU is an IOMMU and supports identical translation table format to
19 permissions, shareability and security protection. In addition, System MMU has
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
31 * MFC has one System MMU on its left and right bus.
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
35 the other System MMU on the write channel.
37 For information on assigning System MMU controller to its peripheral devices,
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dbranch.json18 …still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off",
21 … still counts when branch prediction is disabled due to the Memory Management Unit (MMU) being off"
24 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off"
30 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off"
36 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
39 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off",
45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off"
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dbranch.json18 …r is retired. This event still counts when branch prediction is disabled due to the MMU being off",
21 …or is retired. This event still counts when branch prediction is disabled due to the MMU being off"
24 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
27 …r the address. This event still counts when branch prediction is disabled due to the MMU being off"
30 … the address. This event still counts when branch prediction is disabled due to the MMU being off",
33 …d the address. This event still counts when branch prediction is disabled due to the MMU being off"
36 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
39 …ion. This event still counts when branch prediction is disabled due to the MMU being off. Conditio…
42 …he condition. This event still counts when branch prediction is disabled due to the MMU being off",
45 …the condition. This event still counts when branch prediction is disabled due to the MMU being off"
[all …]
/linux/arch/riscv/
H A DKconfig30 select ARCH_HAS_DEBUG_VIRTUAL if MMU
49 select ARCH_HAS_PTDUMP if MMU
51 select ARCH_HAS_SET_DIRECT_MAP if MMU
52 select ARCH_HAS_SET_MEMORY if MMU
53 select ARCH_HAS_STRICT_KERNEL_RWX if MMU
54 select ARCH_HAS_STRICT_MODULE_RWX if MMU
62 select ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE if 64BIT && MMU
68 select ARCH_SUPPORTS_DEBUG_PAGEALLOC if MMU
70 select ARCH_SUPPORTS_HUGETLBFS if MMU
73 select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS if 64BIT && MMU
[all …]
/linux/arch/sh/mm/
H A DKconfig4 config MMU config
12 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
15 On other systems (such as the SH-3 and 4) where an MMU exists,
17 MMU implicitly switched off.
20 def_bool !MMU
26 On MMU-less systems, any of these page sizes can be selected
30 default "0x80000000" if MMU
37 default "13" if !MMU
86 default !MMU
90 depends on MMU && CPU_SH4A && !CPU_SH4AL_DSP
[all …]
/linux/tools/testing/selftests/kvm/lib/x86/
H A Dprocessor.c167 static void virt_mmu_init(struct kvm_vm *vm, struct kvm_mmu *mmu, in virt_mmu_init()
171 if (!mmu->pgd_created) { in virt_mmu_init()
172 mmu->pgd = vm_alloc_page_table(vm); in virt_mmu_init()
173 mmu->pgd_created = true; in virt_mmu_init()
174 mmu->arch.pte_masks = *pte_masks; in virt_mmu_init()
177 TEST_ASSERT(mmu->pgtable_levels == 4 || mmu->pgtable_levels == 5, in virt_mmu_init()
178 "Selftests MMU only supports 4-level and 5-level paging, not %u-level paging",
179 mmu->pgtable_levels); in virt_arch_pgd_alloc()
200 virt_mmu_init(vm, &vm->mmu,
164 virt_mmu_init(struct kvm_vm * vm,struct kvm_mmu * mmu,struct pte_masks * pte_masks) virt_mmu_init() argument
209 virt_get_pte(struct kvm_vm * vm,struct kvm_mmu * mmu,u64 * parent_pte,gva_t gva,int level) virt_get_pte() argument
224 virt_create_upper_pte(struct kvm_vm * vm,struct kvm_mmu * mmu,u64 * parent_pte,gva_t gva,gpa_t gpa,int current_level,int target_level) virt_create_upper_pte() argument
259 __virt_pg_map(struct kvm_vm * vm,struct kvm_mmu * mmu,gva_t gva,gpa_t gpa,int level) __virt_pg_map() argument
344 vm_is_target_pte(struct kvm_mmu * mmu,u64 * pte,int * level,int current_level) vm_is_target_pte() argument
358 __vm_get_page_table_entry(struct kvm_vm * vm,struct kvm_mmu * mmu,gva_t gva,int * level) __vm_get_page_table_entry() argument
409 struct kvm_mmu *mmu = &vm->mmu; virt_arch_dump() local
[all...]
/linux/drivers/xen/
H A Dgrant-dma-iommu.c36 struct grant_dma_iommu_device *mmu; in grant_dma_iommu_probe() local
39 mmu = devm_kzalloc(&pdev->dev, sizeof(*mmu), GFP_KERNEL); in grant_dma_iommu_probe()
40 if (!mmu) in grant_dma_iommu_probe()
43 mmu->dev = &pdev->dev; in grant_dma_iommu_probe()
45 ret = iommu_device_register(&mmu->iommu, &grant_dma_iommu_ops, &pdev->dev); in grant_dma_iommu_probe()
49 platform_set_drvdata(pdev, mmu); in grant_dma_iommu_probe()
56 struct grant_dma_iommu_device *mmu = platform_get_drvdata(pdev); in grant_dma_iommu_remove() local
59 iommu_device_unregister(&mmu->iommu); in grant_dma_iommu_remove()
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_mem.c93 struct nvif_mmu *mmu = &drm->mmu; in nouveau_mem_host() local
103 if (mem->kind && !(mmu->type[type].type & NVIF_MEM_KIND)) in nouveau_mem_host()
105 if (mem->comp && !(mmu->type[type].type & NVIF_MEM_COMP)) { in nouveau_mem_host()
106 if (mmu->object.oclass >= NVIF_CLASS_MMU_GF100) in nouveau_mem_host()
107 mem->kind = mmu->kind[mem->kind]; in nouveau_mem_host()
117 ret = nvif_mem_ctor_type(mmu, "ttmHostMem", mmu->mem, type, PAGE_SHIFT, in nouveau_mem_host()
129 struct nvif_mmu *mmu = &drm->mmu; in nouveau_mem_vram() local
134 switch (mmu->mem) { in nouveau_mem_vram()
136 ret = nvif_mem_ctor_type(mmu, "ttmVram", mmu->mem, in nouveau_mem_vram()
144 ret = nvif_mem_ctor_type(mmu, "ttmVram", mmu->mem, in nouveau_mem_vram()
[all …]
/linux/drivers/accel/habanalabs/common/mmu/
H A Dmmu_v2_hr.c9 #include "../../include/hw_ip/mmu/mmu_general.h"
37 * hl_mmu_v2_hr_init() - initialize the MMU module.
55 * hl_mmu_v2_hr_fini() - release the MMU module.
59 * - Disable MMU in H/W.
72 * hl_mmu_v2_hr_ctx_init() - initialize a context for using the MMU module.
86 * hl_mmu_v2_hr_ctx_fini - disable a ctx from using the mmu module
378 * hl_mmu_v2_prepare - prepare mmu_if for working with mmu v2
381 * @mmu_if: pointer to the mmu interface structure
383 void hl_mmu_v2_hr_set_funcs(struct hl_device *hdev, struct hl_mmu_funcs *mmu) in hl_mmu_v2_hr_set_funcs() argument
385 mmu->init = hl_mmu_v2_hr_init; in hl_mmu_v2_hr_set_funcs()
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da2xx_gpummu.c27 static void a2xx_gpummu_detach(struct msm_mmu *mmu) in a2xx_gpummu_detach() argument
31 static int a2xx_gpummu_map(struct msm_mmu *mmu, uint64_t iova, in a2xx_gpummu_map() argument
35 struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu); in a2xx_gpummu_map()
62 static int a2xx_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, size_t len) in a2xx_gpummu_unmap() argument
64 struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu); in a2xx_gpummu_unmap()
77 static void a2xx_gpummu_destroy(struct msm_mmu *mmu) in a2xx_gpummu_destroy() argument
79 struct a2xx_gpummu *gpummu = to_a2xx_gpummu(mmu); in a2xx_gpummu_destroy()
81 dma_free_attrs(mmu->dev, TABLE_SIZE + 32, gpummu->table, gpummu->pt_base, in a2xx_gpummu_destroy()
115 void a2xx_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, in a2xx_gpummu_params() argument
118 dma_addr_t base = to_a2xx_gpummu(mmu)->pt_base; in a2xx_gpummu_params()

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