| /linux/drivers/pps/generators/ |
| H A D | pps_gen.c | 198 pr_debug("generator got cdev (%d:%d)\n", in pps_gen_register_cdev()
221 * pps_gen_register_source() - add a PPS generator in the system
222 * @info: the PPS generator info struct
224 * This function is used to register a new PPS generator in the system.
225 * When it returns successfully the new generator is up and running, and
228 * Return: the PPS generator device in case of success, and ERR_PTR(errno)
260 pr_err("unable to register generator\n"); in pps_gen_register_source()
267 * pps_gen_unregister_source() - remove a PPS generator from the system
268 * @pps_gen: the PPS generator device to be removed
270 * This function is used to deregister a PPS generator from the system. When
[all …]
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| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-driver-xdata | 5 Description: Allows the user to enable the PCIe traffic generator which
7 Endpoint direction or to disable the PCIe traffic generator
18 through this generator in MB/s.
30 Description: Allows the user to enable the PCIe traffic generator which
32 Complex direction or to disable the PCIe traffic generator
43 through this generator in MB/s.
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| H A D | sysfs-timecard | 64 GEN1 output is from frequency generator 1
65 GEN2 output is from frequency generator 2
66 GEN3 output is from frequency generator 3
67 GEN4 output is from frequency generator 4
113 frequency generator <X>.
138 Description: (RO) Either 0 or 1, showing if the signal generator is running.
143 Description: (RO) Shows the time in <sec>.<nsec> that the signal generator
149 Description: (RW) Used to start the signal generator, and summarize
152 The signal generator may be started by writing the signal
161 echo 0 > signal # turn off generator
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| /linux/Documentation/devicetree/bindings/media/xilinx/ |
| H A D | xlnx,v-tc.txt | 4 The Video Timing Controller is a general purpose video timing generator and
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
32 xlnx,generator;
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| /linux/include/linux/ |
| H A D | rslib.h | 23 * @genpoly: Generator polynomial
24 * @nroots: Number of generator roots = number of parity symbols
28 * @gfpoly: The primitive generator polynominal
87 * @gfpoly: the extended Galois field generator polynomial coefficients,
90 * @fcr: the first consecutive root of the rs code generator polynomial
93 * @nroots: RS code generator polynomial degree (number of roots)
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| /linux/arch/m68k/atari/ |
| H A D | atasound.c | 65 /* Disable generator A in mixer control. */ in atari_mksound()
79 /* Set generator A frequency to hz. */ in atari_mksound()
96 /* Use envelope for generator A. */ in atari_mksound()
100 /* Set generator A level to maximum, no envelope. */ in atari_mksound()
104 /* Turn on generator A in mixer control. */ in atari_mksound()
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| /linux/lib/reed_solomon/ |
| H A D | reed_solomon.c | 60 * @gfpoly: Field generator polynomial coefficients
61 * @gffunc: Field generator function
62 * @fcr: first root of RS code generator polynomial, index form
64 * @nroots: RS code generator polynomial degree (number of roots)
133 /* Form RS code generator polynomial from its roots */ in codec_init()
201 * @gfpoly: the extended Galois field generator polynomial coefficients,
207 * @fcr: the first consecutive root of the rs code generator polynomial
210 * @nroots: RS code generator polynomial degree (number of roots)
279 * @gfpoly: the extended Galois field generator polynomial coefficients,
282 * @fcr: the first consecutive root of the rs code generator polynomial
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| /linux/drivers/clk/sophgo/ |
| H A D | Kconfig | 23 tristate "Sophgo SG2042 Clock Generator support"
26 This driver supports the Clock Generator on the
37 This clock IP depends on SG2042 Clock Generator because it uses
38 clock from Clock Generator IP as input.
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| /linux/drivers/tty/serial/ |
| H A D | ip22zilog.h | 168 #define TRxCBR 2 /* TRxC = BR Generator Output */
173 #define TCBR 0x10 /* Transmit clock = BR Generator output */
177 #define RCBR 0x40 /* Receive clock = BR Generator output */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
194 #define SSBR 0x80 /* Set DPLL source = BR generator */
262 /* Read Register 12 (lower byte of baud rate generator constant) */
264 /* Read Register 13 (upper byte of baud rate generator constant) */
|
| H A D | sunzilog.h | 170 #define TRxCBR 2 /* TRxC = BR Generator Output */
175 #define TCBR 0x10 /* Transmit clock = BR Generator output */
179 #define RCBR 0x40 /* Receive clock = BR Generator output */
183 /* Write Register 12 (lower byte of baud rate generator time constant) */
185 /* Write Register 13 (upper byte of baud rate generator time constant) */
188 #define BRENAB 1 /* Baud rate generator enable */
189 #define BRSRC 2 /* Baud rate generator source */
196 #define SSBR 0x80 /* Set DPLL source = BR generator */
270 /* Read Register 12 (lower byte of baud rate generator constant) */
272 /* Read Register 13 (upper byte of baud rate generator constant) */
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| H A D | zs.h | 186 #define TRxCBR 2 /* TRxC = BR Generator Output */
191 #define TCBR 0x10 /* Transmit clock = BR Generator output */
195 #define RCBR 0x40 /* Receive clock = BR Generator output */
199 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
201 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
204 #define BRENABL 1 /* Baud rate generator enable */
205 #define BRSRC 2 /* Baud rate generator source */
212 #define SSBR 0x80 /* Set DPLL source = BR generator */
278 /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
280 /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */
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| H A D | pmac_zilog.h | 251 #define TRxCBR 2 /* TRxC = BR Generator Output */
256 #define TCBR 0x10 /* Transmit clock = BR Generator output */
260 #define RCBR 0x40 /* Receive clock = BR Generator output */
264 /* Write Register 12 (lower byte of baud rate generator time constant) */
266 /* Write Register 13 (upper byte of baud rate generator time constant) */
269 #define BRENAB 1 /* Baud rate generator enable */
270 #define BRSRC 2 /* Baud rate generator source */
277 #define SSBR 0x80 /* Set DPLL source = BR generator */
347 /* Read Register 12 (lower byte of baud rate generator constant) */
349 /* Read Register 13 (upper byte of baud rate generator constant) */
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| /linux/include/soc/fsl/qe/ |
| H A D | qe.h | 35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
44 QE_BRG10, /* Baud Rate Generator 10 */
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| /linux/Documentation/devicetree/bindings/rng/ |
| H A D | microchip,pic32-rng.yaml | 7 title: Microchip PIC32 Random Number Generator
10 The PIC32 RNG provides a pseudo random number generator which can be seeded
11 by another true random number generator.
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| /linux/tools/verification/rvgen/rvgen/ |
| H A D | container.py | 6 # Generator for runtime verification monitor container
8 from . import generator
11 class Container(generator.RVGenerator):
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| /linux/Documentation/admin-guide/ |
| H A D | hw_random.rst | 10 a Random Number Generator (RNG). The software has two parts:
61 The Firmware Hub integrates a Random Number Generator (RNG)
96 Random Number Generator
100 Intel 82802 Firmware HUB Random Number Generator Driver
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| /linux/drivers/clk/ |
| H A D | Kconfig | 77 tristate "Maxim 9485 Programmable Clock Generator"
80 This driver supports Maxim 9485 Programmable Audio Clock Generator
155 generator.
163 generator.
317 Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
402 This driver supports the Renesas 9-series PCIe clock generator
411 This driver supports the SkyWorks Si521xx PCIe clock generator
438 Renesas Versaclock7 is a family of configurable clock generator
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| /linux/drivers/iio/frequency/ |
| H A D | Kconfig | 12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
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| /linux/sound/soc/codecs/ |
| H A D | wm8997.c | 252 SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
459 SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
462 SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
464 SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
702 { name, "Noise Generator", "Noise Generator" }, \
703 { name, "Tone Generator 1", "Tone Generator 1" }, \
704 { name, "Tone Generator 2", "Tone Generator
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| H A D | cs48l32.h | 241 { name, "Tone Generator 1", "Tone Generator 1" }, \
242 { name, "Tone Generator 2", "Tone Generator 2" }, \
243 { name, "Noise Generator", "Noise Generator" }, \
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| H A D | cs47l24.c | 185 SOC_SINGLE_TLV("Noise Generator Volume", ARIZONA_COMFORT_NOISE_GENERATOR,
397 SND_SOC_DAPM_PGA("Noise Generator", ARIZONA_COMFORT_NOISE_GENERATOR,
400 SND_SOC_DAPM_PGA("Tone Generator 1", ARIZONA_TONE_GENERATOR_1,
402 SND_SOC_DAPM_PGA("Tone Generator 2", ARIZONA_TONE_GENERATOR_1,
665 { name, "Noise Generator", "Noise Generator" }, \
666 { name, "Tone Generator 1", "Tone Generator 1" }, \
667 { name, "Tone Generator 2", "Tone Generator
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| /linux/drivers/media/platform/xilinx/ |
| H A D | Kconfig | 25 tristate "Xilinx Video Test Pattern Generator"
29 Driver for the Xilinx Video Test Pattern Generator
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| /linux/crypto/ |
| H A D | Kconfig | 801 tristate "Sequence Number IV Generator"
804 Sequence Number IV generator
806 This IV generator generates an IV based on a sequence number by
812 tristate "Encrypted Chain IV Generator"
815 Encrypted Chain IV generator
817 This IV generator generates an IV based on the encryption of
822 tristate "Encrypted Salt-Sector IV Generator"
825 Encrypted Salt-Sector IV generator
827 This IV generator is used in some cases by fscrypt and/or
1110 tristate "NIST SP800-90A DRBG (Deterministic Random Bit Generator)"
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| /linux/sound/soc/ti/ |
| H A D | omap-mcbsp.h | 16 /* Source clocks for McBSP sample rate generator */
27 OMAP_MCBSP_CLKGDV, /* Sample rate generator divider */
|
| /linux/Documentation/sound/hd-audio/ |
| H A D | realtek-pc-beep.rst | 27 When zero, expose the PC Beep line (from the internal beep generator, when
56 <Beep generator> <PCBEEP pin> <Headphone jack>
97 generator and external PCBEEP pin, depending on if the beep generator is
|