| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
19 - rockchip,rk3588-naneng-combphy
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| /linux/drivers/phy/xilinx/ |
| H A D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
27 #include <dt-bindings/phy/phy.h>
33 /* TX De-emphasis parameters */
62 /* PLL SSC step size offsets */
71 /* SSC step size parameters */
184 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
187 * @steps: number of steps of SSC (Spread Spectrum Clock)
198 * struct xpsgtr_phy - representation of a lane
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| /linux/drivers/clk/ |
| H A D | clk-renesas-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Renesas 9-series PCIe clock generator driver
6 * - 9FGV/9DBV/9DMV/9FGL/9DML/9QXL/9SQ
8 * - 9FGV0241
9 * - 9FGV0441
10 * - 9FGV0841
12 * Copyright (C) 2022 Marek Vasut <marex@denx.de>
15 #include <linux/clk-provider.h>
56 /* Structure to describe features of a particular 9-series model */
74 * Renesas 9-series i2c regmap
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| /linux/drivers/mmc/host/ |
| H A D | sdhci-pci-gli.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * Version: v0.9.0 (2019-08-08)
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
21 #include "sdhci-uhs2.h"
468 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
481 if (!host->tuning_done) { in __sdhci_execute_tuning_9750()
483 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
484 return -ETIMEDOUT; in __sdhci_execute_tuning_9750()
488 mmc_hostname(host->mmc)); in __sdhci_execute_tuning_9750()
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| /linux/drivers/phy/st/ |
| H A D | phy-miphy28lp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <dt-bindings/phy/phy.h>
171 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1
173 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1
211 bool ssc; member
233 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" };
362 void __iomem *base = miphy_phy->base; in miphy28lp_set_reset()
373 /* Bringing the MIPHY-CPU registers out of reset */ in miphy28lp_set_reset()
374 if (miphy_phy->type == PHY_TYPE_PCIE) { in miphy28lp_set_reset()
386 void __iomem *base = miphy_phy->base; in miphy28lp_pll_calibration()
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| /linux/drivers/phy/cadence/ |
| H A D | phy-cadence-torrent.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
243 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
244 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
245 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
334 #define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ argument
339 (((ssc) << SSC_SHIFT) & SSC_MASK))
468 enum cdns_torrent_ssc_mode ssc) in cdns_torrent_get_tbl_vals() argument
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| /linux/drivers/pci/controller/ |
| H A D | pcie-brcmstb.c | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
15 #include <linux/irqchip/irq-msi-lib.h>
27 #include <linux/pci-ecam.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
171 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
173 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
201 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
202 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
203 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
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| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_7nm.c | 2 * SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
9 #include <linux/clk-provider.h>
17 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
22 * +---------+ | +----------+ | +----+
23 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
24 * +---------+ | +----------+ | +----+
28 * | | +----+ | |\ dsi0_pclk_mux
29 * | |--| /2 |--o--| \ |
30 * | | +----+ | \ | +---------+
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| /linux/drivers/phy/ |
| H A D | phy-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
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| /linux/ |
| H A D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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| /linux/drivers/phy/mediatek/ |
| H A D | phy-mtk-tphy.c | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
218 /* CDR Charge Pump P-path current adjustment */
237 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
246 /* I-path capacitance adjustment for Gen1 */
279 * mtk_phy_pdata - SoC specific platform data
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_power.c | 1 /* SPDX-License-Identifier: MIT */
39 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
43 for_each_if(test_bit((__domain), (__power_well)->domains.bits))
232 * intel_display_power_is_enabled - check for a power domain
251 struct i915_power_domains *power_domains = &display->power.domains; in intel_display_power_is_enabled()
254 mutex_lock(&power_domains->lock); in intel_display_power_is_enabled()
256 mutex_unlock(&power_domains->lock); in intel_display_power_is_enabled()
265 struct i915_power_domains *power_domains = &display->power.domains; in sanitize_target_dc_state()
274 for (i = 0; i < ARRAY_SIZE(states) - 1; i++) { in sanitize_target_dc_state()
278 if (power_domains->allowed_dc_mask & target_dc_state) in sanitize_target_dc_state()
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| /linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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| /linux/drivers/gpu/drm/xlnx/ |
| H A D | zynqmp_dp.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 - 2020 Xilinx, Inc.
8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
27 #include <linux/media-bus-format.h>
249 * struct zynqmp_dp_link_config - Common link config between source and sink
259 * struct zynqmp_dp_mode - Configured mode of DisplayPort
273 * struct zynqmp_dp_config - Configuration of DisplayPort from DTS
285 * enum test_pattern - Test patterns for test testing
289 * @TEST_80BIT_CUSTOM: A custom 80-bit pattern
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| /linux/drivers/scsi/ |
| H A D | st.c | 1 // SPDX-License-Identifier: GPL-2.0-only
13 Copyright 1992 - 2016 Kai Makisara
16 Some small formal changes - aeb, 950809
18 Last modified: 18-JAN-1998 Richard Gooch <rgooch@atnf.csiro.au> Devfs support
62 is defined and non-zero. */
159 6-byte SCSI read and write commands. */
160 #if ST_FIXED_BUFFER_SIZE >= (2 << 24 - 1)
161 #error "Buffer size should not exceed (2 << 24 - 1) bytes!"
166 /* Setting these non-zero may risk recognizing resets */
176 /* Remove mode bits and auto-rewind bit (7) */
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | ich8lan.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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