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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc.h19 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
24 * @dsc_disable: disable dsc
25 * @hw_dsc: Pointer to dsc context
30 * @dsc_config: configures dsc encoder
31 * @hw_dsc: Pointer to dsc context
32 * @dsc: panel dsc parameters
33 * @mode: dsc topology mode to be set
37 struct drm_dsc_config *dsc,
43 * @hw_dsc: Pointer to dsc context
44 * @dsc: panel dsc parameters
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H A Ddpu_encoder.c141 * @hw_dsc: Handle to the DSC blocks used for the display.
142 * @dsc_mask: Bitmask of used DSC blocks.
172 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
216 /* DSC configuration */
217 struct drm_dsc_config *dsc; member
295 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
303 return dpu_enc->dsc ? true : false; in dpu_encoder_is_dsc_enabled()
619 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
639 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
640 * This helper function is used by physical encoder to get DSC config
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H A Ddpu_rm.c169 const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; in dpu_rm_init() local
172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); in dpu_rm_init()
174 hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); in dpu_rm_init()
178 DPU_ERROR("failed dsc object creation: err %d\n", rc); in dpu_rm_init()
181 rm->dsc_blks[dsc->id - DSC_0] = &hw->base; in dpu_rm_init()
510 * DSC with even index must be used with the PINGPONG with even index in _dpu_rm_pingpong_dsc_check()
511 * DSC with odd index must be used with the PINGPONG with odd index in _dpu_rm_pingpong_dsc_check()
551 DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n", in _dpu_rm_dsc_alloc()
568 /* only start from even dsc index */ in _dpu_rm_dsc_alloc_pair()
575 /* consective dsc index to be paired */ in _dpu_rm_dsc_alloc_pair()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddsc.h36 /* Input parameters for configuring DSC from the outside of DSC */
48 /* Output parameters for configuring DSC-related part of OPTC */
74 /* DSC encoder capabilities
75 * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
81 uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
106 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
107 …void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_r…
108 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
109 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
111 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
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H A DMakefile11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
H A Drc_calc.c30 * @rc: DC internal DSC parameters
31 * @pps: DRM struct with all required DSC values
33 * This function expects a drm_dsc_config data struct with all the required DSC
35 * computes some of the DSC values.
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c50 /* There's no pipe A DSC engine on ICL */ in is_pipe_dsc()
77 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
78 * Above method use a common formula to derive values for any combination of DSC
106 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: in calculate_rc_params()
265 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in is_dsi_dsc_1_1()
275 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
276 u16 compressed_bpp = fxp_q4_to_int(pipe_config->dsc.compressed_bpp_x16); in intel_dsc_compute_params()
282 pipe_config->dsc.slice_count); in intel_dsc_compute_params()
292 * According to DSC 1.2 specs if colorspace is YCbCr then convert_rgb is 0 in intel_dsc_compute_params()
307 vdsc_cfg->bits_per_pixel = pipe_config->dsc.compressed_bpp_x16; in intel_dsc_compute_params()
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H A Dintel_dp_mst.c143 bool dsc) in intel_dp_mst_max_dpt_bpp() argument
149 if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(display) >= 20 || !dsc) in intel_dp_mst_max_dpt_bpp()
153 * DSC->DPT interface width: in intel_dp_mst_max_dpt_bpp()
250 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) in intel_dp_mtp_tu_compute_config() argument
265 drm_WARN_ON(display->drm, !dsc && (fxp_q4_to_frac(min_bpp_x16) || in intel_dp_mtp_tu_compute_config()
287 * NOTE: The following must reset crtc_state->fec_enable for UHBR/DSC in intel_dp_mtp_tu_compute_config()
291 crtc_state->fec_enable = intel_dp_needs_8b10b_fec(crtc_state, dsc); in intel_dp_mtp_tu_compute_config()
299 if (crtc_state->fec_enable && dsc && in intel_dp_mtp_tu_compute_config()
303 max_dpt_bpp_x16 = fxp_q4_from_int(intel_dp_mst_max_dpt_bpp(crtc_state, dsc)); in intel_dp_mtp_tu_compute_config()
313 if (dsc) { in intel_dp_mtp_tu_compute_config()
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H A Dintel_dp.c101 /* Max DSC line buffer depth supported by HW. */
104 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
107 /* Constants for DP DSC configurations */
115 * With this we can have max of 4 DSC Slices per pipe.
120 * #TODO Split this better to use 4 slices/dsc engine where supported.
474 * the provided SSC, FEC, DSC BW allocation overhead.
852 * 0.453% DSC overhead. This is enough for a 3840 width mode, in intel_dp_bw_fec_overhead()
853 * which has a DSC overhead of up to ~0.2%, but may not be in intel_dp_bw_fec_overhead()
855 * lane DP link, with 2 DSC slices and 8 bpp color depth). in intel_dp_bw_fec_overhead()
908 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ in bigjoiner_bw_max_bpp()
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/linux/include/drm/display/
H A Ddrm_dsc.h13 /* VESA Display Stream Compression DSC 1.2 constants */
21 /* DSC Rate Control Constants */
27 /* DSC PPS constants and macros */
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
47 * This defines different rate control parameters used by the DSC engine
67 * struct drm_dsc_config - Parameters required to configure DSC
89 * @slice_count: Number fo slices per line used by the DSC encoder
239 * @dsc_version_minor: DSC minor version
243 * @dsc_version_major: DSC major version
276 * The VESA DSC standard defines picture parameter set (PPS) which display
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H A Ddrm_dsc_helper.h15 DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
168 struct drm_dsc_config *dsc; member
571 * @dsc: DRM DSC configuration for this DSI output
578 * - For VIDEO mode they are not compressed by DSC and are passed as is.
589 const struct drm_dsc_config *dsc, in dsi_adjust_pclk_for_compression() argument
604 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), in dsi_adjust_pclk_for_compression()
605 dsc->bits_per_component * 3); in dsi_adjust_pclk_for_compression()
616 const struct drm_dsc_config *dsc, bool is_bonded_dsi) in dsi_get_pclk_rate() argument
622 if (dsc) in dsi_get_pclk_rate()
623 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); in dsi_get_pclk_rate()
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/linux/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt37801.c23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
290 /* This panel only supports DSC; unconditionally enable it */ in novatek_nt37801_probe()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c39 #include "dsc.h"
1197 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX
1199 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX
1358 /* function: Read link's DSC & FEC capabilities
1401 * enable DSC on the sink device or on MST branch in dp_dsc_fec_support_show()
1544 /* function: read DSC status on the connector
1547 * returns current status of DSC clock on the connector.
1556 * 1 - means that DSC is currently enabled
1557 * 0 - means that DSC is disabled
1564 struct display_stream_compressor *dsc; in dp_dsc_clock_en_read() local
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H A Damdgpu_dm_mst_types.c273 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 in validate_dsc_caps_on_connector()
280 * because it only check the dsc/fec caps of the "port variable" and not the dock in validate_dsc_caps_on_connector()
282 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display in validate_dsc_caps_on_connector()
933 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
946 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
959 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", in set_dsc_configs_from_fairness_vars()
960 params[i].timing->flags.DSC, in set_dsc_configs_from_fairness_vars()
1154 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); in try_disable_dsc()
1182 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", in log_dsc_params()
1233 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
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H A Damdgpu_dm_helpers.c801 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
804 /* When DSC is enabled on previous boot and reboot with the hub, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
814 DRM_INFO("MST_DSC Send DSC enable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
818 * external monitor occur garbage while disable DSC, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
819 * Disable DSC only when entire link status turn to false, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
823 DRM_INFO("MST_DSC Send DSC disable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
865 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
872 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
880 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
890 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.h8 #include "dsc.h"
9 #include "dsc/dscc_types.h"
13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn35/
H A Ddcn35_hwseq.c55 #include "dsc.h"
329 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in update_dsc_on_stream() local
336 ASSERT(dsc); in update_dsc_on_stream()
346 if (!dsc) { in update_dsc_on_stream()
347 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
351 if (dsc->funcs->dsc_read_state) { in update_dsc_on_stream()
352 dsc->funcs->dsc_read_state(dsc, &dsc_state); in update_dsc_on_stream()
354 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in update_dsc_on_stream()
358 /* Enable DSC hw block */ in update_dsc_on_stream()
369 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg); in update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c55 #include "dsc.h"
751 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
758 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
760 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC in dsc_optc_config_log()
800 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
808 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
818 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in link_set_dsc_on_stream()
825 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
835 /* Enable DSC hw block */ in link_set_dsc_on_stream()
848 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_dsc.h28 /* DP Extended DSC Capabilities */
71 const struct display_stream_compressor *dsc,
81 const struct display_stream_compressor *dsc,
97 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
99 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
102 /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,
H A Ddc_hw_types.h817 uint32_t DSC : 1; /* Use DSC with this timing */ member
867 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
868 uint32_t num_slices_v; /* Number of DSC slices - vertical */
869 uint32_t bits_per_pixel; /* DSC target bitrate in 1/16 of bpp (e.g. 128 -> 8bpp) */
870 bool block_pred_enable; /* DSC block prediction enable */
871 uint32_t linebuf_depth; /* DSC line buffer depth */
872 uint32_t version_minor; /* DSC minor version. Full version is formed as 1.version_minor. */
873 bool ycbcr422_simple; /* Tell DSC engine to convert YCbCr 4:2:2 to 'YCbCr 4:2:2 simple'. */
874 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */
875 bool is_frl; /* indicate if DSC is applied based on HDMI FRL sink's capability */
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn32/
H A Ddcn32_hwseq.c48 #include "dsc.h"
93 DC_LOG_DSC("%s DSC power gate for inst %d", power_gate ? "enable" : "disable", dsc_inst); in dcn32_dsc_pg_control()
1022 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in dcn32_update_dsc_on_stream() local
1032 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in dcn32_update_dsc_on_stream()
1040 ASSERT(dsc); in dcn32_update_dsc_on_stream()
1050 if (!dsc) { in dcn32_update_dsc_on_stream()
1051 DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
1055 if (dsc->funcs->dsc_read_state) { in dcn32_update_dsc_on_stream()
1056 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dcn32_update_dsc_on_stream()
1058 DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dcn32_update_dsc_on_stream()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1092 struct dcn20_dsc *dsc = in dcn20_resource_destruct()
1095 if (!dsc) { in dcn20_resource_destruct()
1100 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); in dcn20_resource_destruct()
1101 return &dsc->base; in dcn20_resource_destruct()
1104 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) in dcn20_resource_destruct()
1106 kfree(container_of(*dsc, struct dcn20_dsc, base)); in dcn20_resource_destruct()
1107 *dsc = NULL; in dcn20_resource_destruct()
1362 struct display_stream_compressor **dsc, in dcn20_release_dsc()
1367 struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_release_dsc()
1369 ASSERT(*dsc in dcn20_release_dsc()
1064 struct dcn20_dsc *dsc = dcn20_dsc_create() local
1076 dcn20_dsc_destroy(struct display_stream_compressor ** dsc) dcn20_dsc_destroy() argument
1328 dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx) dcn20_acquire_dsc() argument
1363 dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc) dcn20_release_dsc() argument
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/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_hw_sequencer.c36 #include "dsc.h"
2262 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; in hwss_dsc_set_config() local
2266 if (dsc && dsc->funcs->dsc_set_config) in hwss_dsc_set_config()
2267 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); in hwss_dsc_set_config()
2272 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; in hwss_dsc_enable() local
2275 if (dsc && dsc->funcs->dsc_enable) in hwss_dsc_enable()
2276 dsc->funcs->dsc_enable(dsc, opp_inst); in hwss_dsc_enable()
2303 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; in hwss_dsc_disconnect() local
2305 if (dsc && dsc->funcs->dsc_disconnect) in hwss_dsc_disconnect()
2306 dsc->funcs->dsc_disconnect(dsc); in hwss_dsc_disconnect()
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/linux/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()

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