| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/ |
| H A D | dcn401_dsc.c | 9 #include "dsc/dscc_types.h"
10 #include "dsc/rc_calc.h"
12 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
16 //static bool dsc401_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config …
43 dsc->ctx->logger
48 void dsc401_construct(struct dcn401_dsc *dsc, in dsc401_construct() argument
55 dsc->base.ctx = ctx; in dsc401_construct()
56 dsc->base.inst = inst; in dsc401_construct()
57 dsc->base.funcs = &dcn401_dsc_funcs; in dsc401_construct()
59 dsc->dsc_regs = dsc_regs; in dsc401_construct()
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| H A D | dcn401_dsc.h | 8 #include "dsc.h"
9 #include "dsc/dscc_types.h"
13 #define TO_DCN401_DSC(dsc)\ argument
14 container_of(dsc, struct dcn401_dsc, base)
328 void dsc401_construct(struct dcn401_dsc *dsc,
337 void dsc401_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
338 bool dsc401_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg…
339 void dsc401_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
341 void dsc401_enable(struct display_stream_compressor *dsc, int opp_pipe);
342 void dsc401_disable(struct display_stream_compressor *dsc);
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| /linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_dsc.h | 19 * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
24 * @dsc_disable: disable dsc
25 * @hw_dsc: Pointer to dsc context
30 * @dsc_config: configures dsc encoder
31 * @hw_dsc: Pointer to dsc context
32 * @dsc: panel dsc parameters
33 * @mode: dsc topology mode to be set
37 struct drm_dsc_config *dsc,
43 * @hw_dsc: Pointer to dsc context
44 * @dsc: panel dsc parameters
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| H A D | dpu_encoder.c | 141 * @hw_dsc: Handle to the DSC blocks used for the display.
142 * @dsc_mask: Bitmask of used DSC blocks.
172 * @dsc: drm_dsc_config pointer, for DSC-enabled encoders
216 /* DSC configuration */
217 struct drm_dsc_config *dsc; member
295 * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled
303 return dpu_enc->dsc ? true : false; in dpu_encoder_is_dsc_enabled()
619 * dpu_encoder_use_dsc_merge - returns true if the encoder uses DSC merge topology.
639 * dpu_encoder_get_dsc_config - get DSC config for the DPU encoder
640 * This helper function is used by physical encoder to get DSC config
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| H A D | dpu_rm.c | 169 const struct dpu_dsc_cfg *dsc = &cat->dsc[i]; in dpu_rm_init() local
172 hw = dpu_hw_dsc_init_1_2(dev, dsc, mmio); in dpu_rm_init()
174 hw = dpu_hw_dsc_init(dev, dsc, mmio, cat->mdss_ver); in dpu_rm_init()
178 DPU_ERROR("failed dsc object creation: err %d\n", rc); in dpu_rm_init()
181 rm->dsc_blks[dsc->id - DSC_0] = &hw->base; in dpu_rm_init()
510 * DSC with even index must be used with the PINGPONG with even index in _dpu_rm_pingpong_dsc_check()
511 * DSC with odd index must be used with the PINGPONG with odd index in _dpu_rm_pingpong_dsc_check()
551 DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n", in _dpu_rm_dsc_alloc()
568 /* only start from even dsc index */ in _dpu_rm_dsc_alloc_pair()
575 /* consective dsc index to be paired */ in _dpu_rm_dsc_alloc_pair()
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| H A D | dpu_hw_pingpong.h | 81 * @enable_dsc: Enable DSC
86 * @disable_dsc: Disable DSC
91 * @setup_dsc: Setup DSC
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/ |
| H A D | dc_dsc.c | 28 #include "dsc.h"
37 dsc->ctx->logger
41 /* default DSC policy target bitrate limit is 16bpp */
44 /* default DSC policy enables DSC only when needed */
69 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
100 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
156 const struct display_stream_compressor *dsc,
177 const struct display_stream_compressor *dsc,
214 dm_error("%s: DPCD DSC buffer size not recognized.\n", __func__); in dsc_buff_block_size_from_dpcd()
230 dm_error("%s: DPCD DSC buffer depth not recognized.\n", __func__); in dsc_line_buff_depth_from_dpcd()
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| H A D | Makefile | 11 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn20/,$(DSC_DCN20))
22 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn35/,$(DSC_DCN35))
30 AMD_DISPLAY_FILES += $(addprefix $(AMDDALPATH)/dc/dsc/dcn401/,$(DSC_DCN401))
34 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o macro
36 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
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| H A D | rc_calc.c | 30 * @rc: DC internal DSC parameters
31 * @pps: DRM struct with all required DSC values
33 * This function expects a drm_dsc_config data struct with all the required DSC
35 * computes some of the DSC values.
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/ |
| H A D | dcn20_dsc.c | 30 #include "dsc/dscc_types.h"
31 #include "dsc/rc_calc.h"
33 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_valu…
59 dsc->ctx->logger
63 void dsc2_construct(struct dcn20_dsc *dsc, in dsc2_construct() argument
70 dsc->base.ctx = ctx; in dsc2_construct()
71 dsc->base.inst = inst; in dsc2_construct()
72 dsc->base.funcs = &dcn20_dsc_funcs; in dsc2_construct()
74 dsc->dsc_regs = dsc_regs; in dsc2_construct()
75 dsc->dsc_shift = dsc_shift; in dsc2_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/dsc/dcn35/ |
| H A D | dcn35_dsc.c | 30 static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
59 dsc->ctx->logger
61 void dsc35_construct(struct dcn20_dsc *dsc, in dsc35_construct() argument
68 dsc->base.ctx = ctx; in dsc35_construct()
69 dsc->base.inst = inst; in dsc35_construct()
70 dsc->base.funcs = &dcn35_dsc_funcs; in dsc35_construct()
72 dsc->dsc_regs = dsc_regs; in dsc35_construct()
73 dsc->dsc_shift = (const struct dcn20_dsc_shift *)(dsc_shift); in dsc35_construct()
74 dsc->dsc_mask = (const struct dcn20_dsc_mask *)(dsc_mask); in dsc35_construct()
76 dsc->max_image_width = 5184; in dsc35_construct()
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| /linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_vdsc.c | 53 * 3 DSC Slices per pipe need 3 DSC engines, which is supported only in intel_dsc_get_slice_config()
62 /* TODO: Consider using 1 DSC engine stream x 4 slices instead. */ in intel_dsc_get_slice_config()
64 /* TODO: Consider using 1 DSC engine stream x 2 slices instead. */ in intel_dsc_get_slice_config()
70 * So there should be at least 2 dsc slices per pipe, in intel_dsc_get_slice_config()
102 /* There's no pipe A DSC engine on ICL */ in is_pipe_dsc()
129 * We are using the method provided in DSC 1.2a C-Model in codec_main.c
130 * Above method use a common formula to derive values for any combination of DSC
158 * According to DSC 1.2 spec in Section 4.1 if native_420 is set: in calculate_rc_params()
317 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in is_dsi_dsc_1_1()
327 struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; in intel_dsc_compute_params()
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| H A D | intel_dp.c | 101 /* Max DSC line buffer depth supported by HW. */
104 /* DP DSC FEC Overhead factor in ppm = 1/(0.972261) = 1.028530 */
107 /* Constants for DP DSC configurations */
460 * the provided SSC, FEC, DSC BW allocation overhead.
843 * 0.453% DSC overhead. This is enough for a 3840 width mode, in intel_dp_bw_fec_overhead()
844 * which has a DSC overhead of up to ~0.2%, but may not be in intel_dp_bw_fec_overhead()
846 * lane DP link, with 2 DSC slices and 8 bpp color depth). in intel_dp_bw_fec_overhead()
899 /* With bigjoiner multiple dsc engines are used in parallel so PPC is 2 */ in bigjoiner_bw_max_bpp()
966 * supported by the eDP sink, to allow using fewer DSC engines. in intel_dp_dsc_min_slice_count()
1007 * Due to some DSC engine BW limitations, we need to enable second in intel_dp_dsc_min_slice_count()
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| /linux/include/drm/display/ |
| H A D | drm_dsc.h | 13 /* VESA Display Stream Compression DSC 1.2 constants */
21 /* DSC Rate Control Constants */
27 /* DSC PPS constants and macros */
45 * struct drm_dsc_rc_range_parameters - DSC Rate Control range parameters
47 * This defines different rate control parameters used by the DSC engine
67 * struct drm_dsc_config - Parameters required to configure DSC
89 * @slice_count: Number fo slices per line used by the DSC encoder
239 * @dsc_version_minor: DSC minor version
243 * @dsc_version_major: DSC major version
276 * The VESA DSC standard defines picture parameter set (PPS) which display
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| H A D | drm_dsc_helper.h | 15 DRM_DSC_1_1_PRE_SCR, /* legacy params from DSC 1.1 */
30 u8 drm_dsc_initial_scale_value(const struct drm_dsc_config *dsc);
31 u32 drm_dsc_flatness_det_thresh(const struct drm_dsc_config *dsc);
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| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-novatek-nt37801.c | 23 struct drm_dsc_config dsc; member
146 drm_dsc_pps_payload_pack(&pps, &ctx->dsc); in novatek_nt37801_prepare()
290 /* This panel only supports DSC; unconditionally enable it */ in novatek_nt37801_probe()
291 dsi->dsc = &ctx->dsc; in novatek_nt37801_probe()
292 ctx->dsc.dsc_version_major = 1; in novatek_nt37801_probe()
293 ctx->dsc.dsc_version_minor = 1; in novatek_nt37801_probe()
294 ctx->dsc.slice_height = 40; in novatek_nt37801_probe()
295 ctx->dsc.slice_width = 720; in novatek_nt37801_probe()
296 ctx->dsc.slice_count = 1440 / ctx->dsc.slice_width; in novatek_nt37801_probe()
297 ctx->dsc.bits_per_component = 8; in novatek_nt37801_probe()
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| /linux/drivers/gpu/drm/msm/dsi/ |
| H A D | dsi_host.c | 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
168 struct drm_dsc_config *dsc; member
571 * @dsc: DRM DSC configuration for this DSI output
579 * - For VIDEO mode they are not compressed by DSC and are passed as is.
590 const struct drm_dsc_config *dsc, in dsi_adjust_pclk_for_compression() argument
605 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), in dsi_adjust_pclk_for_compression()
606 dsc->bits_per_component * 3); in dsi_adjust_pclk_for_compression()
617 const struct drm_dsc_config *dsc, bool is_bonded_dsi) in dsi_get_pclk_rate() argument
623 if (dsc) in dsi_get_pclk_rate()
624 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); in dsi_get_pclk_rate()
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| /linux/drivers/gpu/drm/amd/display/dc/link/ |
| H A D | link_dpms.c | 55 #include "dsc.h"
614 static void dsc_optc_config_log(struct display_stream_compressor *dsc, in dsc_optc_config_log() argument
621 DC_LOGGER_INIT(dsc->ctx->logger); in dsc_optc_config_log()
623 /* 7 fractional digits decimal precision for bytes per pixel is enough because DSC in dsc_optc_config_log()
663 /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first,
671 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; in link_set_dsc_on_stream() local
681 * with DSC such as 480p60Hz, the dispclk could be low enough to trigger in link_set_dsc_on_stream()
688 DC_LOGGER_INIT(dsc->ctx->logger); in link_set_dsc_on_stream()
698 /* Enable DSC hw block */ in link_set_dsc_on_stream()
711 dccg->funcs->set_dto_dscclk(dccg, dsc->inst, dsc_cfg.dc_dsc_cfg.num_slices_h); in link_set_dsc_on_stream()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_mst_types.c | 273 u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 in validate_dsc_caps_on_connector()
280 * because it only check the dsc/fec caps of the "port variable" and not the dock in validate_dsc_caps_on_connector()
282 * This case will return NULL: DSC capabe MST dock connected to a non fec/dsc capable display in validate_dsc_caps_on_connector()
933 params[i].timing->flags.DSC = 1; in set_dsc_configs_from_fairness_vars()
946 params[i].timing->flags.DSC = 0; in set_dsc_configs_from_fairness_vars()
959 DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", in set_dsc_configs_from_fairness_vars()
960 params[i].timing->flags.DSC, in set_dsc_configs_from_fairness_vars()
1154 DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); in try_disable_dsc()
1182 DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", in log_dsc_params()
1233 stream->timing.flags.DSC = 0; in compute_mst_dsc_configs_for_link()
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| H A D | amdgpu_dm_helpers.c | 840 "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
843 /* When DSC is enabled on previous boot and reboot with the hub, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
853 DRM_INFO("MST_DSC Send DSC enable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
857 * external monitor occur garbage while disable DSC, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
858 * Disable DSC only when entire link status turn to false, in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
862 DRM_INFO("MST_DSC Send DSC disable to synaptics\n"); in write_dsc_enable_synaptics_non_virtual_dpcd_mst()
904 "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
911 "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
919 "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
929 "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", in dm_helpers_dp_write_dsc_enable()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dc_dsc.h | 28 /* DP Extended DSC Capabilities */
72 const struct display_stream_compressor *dsc,
82 const struct display_stream_compressor *dsc,
98 void dc_dsc_dump_decoder_caps(const struct display_stream_compressor *dsc,
100 void dc_dsc_dump_encoder_caps(const struct display_stream_compressor *dsc,
103 /* TODO - Hardware/specs limitation should be owned by dc dsc and returned to DM,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1093 struct dcn20_dsc *dsc = in dcn20_dsc_create() local
1096 if (!dsc) { in dcn20_dsc_create()
1101 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); in dcn20_dsc_create()
1102 return &dsc->base; in dcn20_dsc_create()
1105 void dcn20_dsc_destroy(struct display_stream_compressor **dsc) in dcn20_dsc_destroy() argument
1107 kfree(container_of(*dsc, struct dcn20_dsc, base)); in dcn20_dsc_destroy()
1108 *dsc = NULL; in dcn20_dsc_destroy()
1364 struct display_stream_compressor **dsc, in dcn20_acquire_dsc() argument
1369 … display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc; in dcn20_acquire_dsc()
1371 ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */ in dcn20_acquire_dsc()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_hw_sequencer.c | 36 #include "dsc.h"
2285 struct display_stream_compressor *dsc = params->dsc_set_config_params.dsc; in hwss_dsc_set_config() local
2289 if (dsc && dsc->funcs->dsc_set_config) in hwss_dsc_set_config()
2290 dsc->funcs->dsc_set_config(dsc, dsc_cfg, dsc_optc_cfg); in hwss_dsc_set_config()
2295 struct display_stream_compressor *dsc = params->dsc_enable_params.dsc; in hwss_dsc_enable() local
2298 if (dsc && dsc->funcs->dsc_enable) in hwss_dsc_enable()
2299 dsc->funcs->dsc_enable(dsc, opp_inst); in hwss_dsc_enable()
2326 struct display_stream_compressor *dsc = params->dsc_disconnect_params.dsc; in hwss_dsc_disconnect() local
2328 if (dsc && dsc->funcs->dsc_disconnect) in hwss_dsc_disconnect()
2329 dsc->funcs->dsc_disconnect(dsc); in hwss_dsc_disconnect()
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| /linux/drivers/gpu/drm/tests/ |
| H A D | drm_dp_mst_helper_test.c | 18 const bool dsc; member
26 .dsc = false,
32 .dsc = false,
38 .dsc = false,
44 .dsc = true,
50 .dsc = true,
65 sprintf(desc, "Clock %d BPP %d DSC %s", t->clock, t->bpp, t->dsc ? "enabled" : "disabled"); in dp_mst_calc_pbn_mode_desc()
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| /linux/drivers/gpu/drm/amd/display/dc/hwss/dcn401/ |
| H A D | dcn401_hwseq.c | 27 #include "dsc.h"
1466 // old_otg_master to NULL to skip the DSC configuration. in update_dsc_for_odm_change()
1471 if (otg_master->stream_res.dsc) in update_dsc_for_odm_change()
1473 otg_master->stream->timing.flags.DSC); in update_dsc_for_odm_change()
1474 if (old_otg_master && old_otg_master->stream_res.dsc) { in update_dsc_for_odm_change()
1478 if (old_pipe->stream_res.dsc && !new_pipe->stream_res.dsc) in update_dsc_for_odm_change()
1479 old_pipe->stream_res.dsc->funcs->dsc_disconnect( in update_dsc_for_odm_change()
1480 old_pipe->stream_res.dsc); in update_dsc_for_odm_change()
1550 /* Process new DSC configuration if DSC is enabled */ in dcn401_add_dsc_sequence_for_odm_change()
1551 if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { in dcn401_add_dsc_sequence_for_odm_change()
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