Home
last modified time | relevance | path

Searched full:dpll (Results 1 – 25 of 141) sorted by relevance

123456

/linux/drivers/dpll/
H A Ddpll_netlink.c3 * Generic netlink for DPLL management framework
16 #include <uapi/linux/dpll.h>
34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) in dpll_msg_add_dev_handle() argument
36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) in dpll_msg_add_dev_handle()
63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, in dpll_pin_available()
69 static bool dpll_device_registered(struct dpll_device *dpll) in dpll_device_registered() argument
71 return dpll_device_ops(dpll); in dpll_device_registered()
80 if (dpll_device_registered(ref->dpll)) in dpll_pin_first_registered_ref()
115 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, in dpll_msg_add_mode() argument
118 const struct dpll_device_ops *ops = dpll_device_ops(dpll); in dpll_msg_add_mode()
[all …]
H A Ddpll_core.c3 * dpll_core.c - DPLL subsystem kernel-space interface implementation.
22 /* Mutex lock to protect DPLL subsystem devices and pins */
62 void dpll_device_notify(struct dpll_device *dpll, unsigned long action) in dpll_device_notify() argument
65 .dpll = dpll, in dpll_device_notify()
66 .id = dpll->id, in dpll_device_notify()
67 .idx = dpll->device_idx, in dpll_device_notify()
68 .clock_id = dpll->clock_id, in dpll_device_notify()
69 .type = dpll->type, in dpll_device_notify()
91 static void dpll_device_tracker_alloc(struct dpll_device *dpll, in dpll_device_tracker_alloc() argument
95 ref_tracker_alloc(&dpll->refcnt_tracker, tracker, GFP_KERNEL); in dpll_device_tracker_alloc()
[all …]
H A Ddpll_core.h10 #include <linux/dpll.h>
19 * struct dpll_device - stores DPLL device internal data
20 * @id: unique id number for device given by dpll subsystem
22 * @clock_id: unique identifier (clock_id) of a dpll
24 * @type: type of a dpll
25 * @pin_refs: stores pins registered within a dpll
28 * @registration_list: list of registered ops and priv data of dpll owners
43 * struct dpll_pin - structure for a dpll pin
44 * @id: unique id number for pin given by dpll subsystem
75 * struct dpll_pin_ref - structure for referencing either dpll or pins
[all …]
H A DMakefile3 # Makefile for DPLL drivers.
6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
[all …]
/linux/Documentation/netlink/specs/
H A Ddpll.yaml3 name: dpll
5 doc: DPLL subsystem.
12 working modes a dpll can support, differentiates if and how dpll selects
18 doc: input can be only selected by sending a request to dpll
22 doc: highest prio input pin auto selected by dpll
28 provides information of dpll device lock status, valid values for
34 dpll was not yet locked to any valid input (or forced by setting
40 dpll is locked to a valid signal, but no holdover available
44 dpll is locked and holdover acquired
48 dpll is in holdover state - lost a valid lock or was forced
[all …]
/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c3 * OMAP DPLL clock support
137 * _register_dpll - low level registration of a DPLL clock
141 * Finalizes DPLL registration process. In case a failure (clk-ref or
207 * Initializes a DPLL x 2 clock from device tree data.
264 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
265 * @node: device node containing the DPLL info
266 * @ops: ops for the DPLL
267 * @ddt: DPLL data template to use
269 * Initializes a DPLL clock from device tree data.
314 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.c8 #include <linux/dpll.h>
99 * for pin control. For E810 NIC with dpll there is additional MUX-related logic
100 * between SMA/U.FL pins/connectors and dpll device, best to give user access
196 * @dpll: pointer to dpll
197 * @dpll_priv: private data pointer passed on dpll registration
211 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_frequency_set() argument
235 * @dpll: pointer to dpll
236 * @dpll_priv: private data pointer passed on dpll registration
249 const struct dpll_device *dpll, void *dpll_priv, in ice_dpll_input_frequency_set() argument
252 return ice_dpll_frequency_set(pin, pin_priv, dpll, dpll_priv, frequency, in ice_dpll_input_frequency_set()
[all …]
/linux/include/uapi/linux/
H A Ddpll.h3 /* Documentation/netlink/specs/dpll.yaml */
10 #define DPLL_FAMILY_NAME "dpll"
14 * enum dpll_mode - working modes a dpll can support, differentiates if and how
15 * dpll selects one of its inputs to syntonize with it, valid values for
17 * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
18 * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
30 * enum dpll_lock_status - provides information of dpll device lock status,
32 * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
34 * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
36 * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
[all …]
/linux/Documentation/driver-api/
H A Ddpll.rst4 The Linux kernel dpll subsystem
7 DPLL chapter
14 DPLL - Digital Phase Locked Loop is an integrated circuit which in
17 DPLL's input and output may be configurable.
22 The main purpose of dpll subsystem is to provide general interface
32 Single dpll device object means single Digital PLL circuit and bunch of
38 Changing the configuration of dpll device is done with `do` request of
52 The number of pins per dpll vary, but usually multiple pins shall be
53 provided for a single dpll device.
73 on hardware capabilities and active dpll device work mode
[all …]
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
30 dpll-types:
31 description: List of DPLL channel types, one per DPLL instance.
38 description: DPLL input pins
49 $ref: /schemas/dpll/dpll-pin.yaml
[all …]
H A Dmicrochip,zl30731.yaml4 $id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
7 title: Microchip Azurite DPLL device
13 Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14 provides up to 5 independent DPLL channels, up to 10 differential or
42 - $ref: /schemas/dpll/dpll-device.yaml#
53 dpll@70 {
56 dpll-types = "pps", "eec";
97 dpll@70 {
102 dpll-types = "pps";
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
161 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
162 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
164 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
168 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
169 dpll |= in psb_intel_crtc_mode_set()
174 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
H A Dcdv_intel_display.c208 /* Unlike most Intel display engines, on Cedarview the DPLL registers
210 * DPLL reference clock is on in the DPLL control register, but before
211 * the DPLL is enabled in the DPLL control register.
262 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
679 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
681 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
682 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
/linux/include/linux/clk/
H A Dti.h29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47 * @max_rate: maximum clock rate for the DPLL
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/linux/drivers/dpll/zl3073x/
H A Ddpll.c9 #include <linux/dpll.h>
22 #include "dpll.h"
30 * struct zl3073x_dpll_pin - DPLL pin
31 * @list: this DPLL pin list entry
32 * @dpll: DPLL the pin is registered to
49 struct zl3073x_dpll *dpll; member
110 const struct dpll_device *dpll, void *dpll_priv, in zl3073x_dpll_pin_direction_get() argument
151 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_get() argument
190 const struct dpll_device *dpll, in zl3073x_dpll_input_pin_esync_set() argument
232 struct zl3073x_dpll *zldpll = pin->dpll; in zl3073x_dpll_input_pin_ref_sync_get()
[all …]
H A Ddpll.h6 #include <linux/dpll.h>
13 * struct zl3073x_dpll - ZL3073x DPLL sub-device structure
14 * @list: this DPLL list entry
16 * @id: DPLL index
19 * @ops: DPLL device operations for this instance
20 * @dpll_dev: pointer to registered DPLL device
22 * @lock: per-DPLL mutex serializing all operations
23 * @type: DPLL type (PPS or EEC)
24 * @lock_status: last saved DPLL lock status
H A Dchan.c14 * zl3073x_chan_state_update - update DPLL channel status from HW
16 * @index: DPLL channel index
72 * zl3073x_chan_nco_mode_set - switch DPLL channel to NCO mode
74 * @index: DPLL channel index
151 "Failed to read DPLL%u df_offset: %pe\n", in zl3073x_chan_nco_mode_set()
162 * zl3073x_chan_state_fetch - fetch DPLL channel state from hardware
164 * @index: DPLL channel index to fetch state for
167 * the given DPLL channel and stores the values for later use.
185 dev_dbg(zldev->dev, "DPLL%u mode: %u, ref: %u\n", index, in zl3073x_chan_state_fetch()
200 "DPLL%u lock_state: %u, ho: %u, sel_state: %u, sel_ref: %u\n", in zl3073x_chan_state_fetch()
[all …]
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
H A Dchan.h17 * struct zl3073x_chan - DPLL channel state
18 * @ctrl: DPLL control register value
75 * zl3073x_chan_mode_get - get DPLL channel operating mode
78 * Return: reference selection mode of the given DPLL channel
97 * zl3073x_chan_mode_set - set DPLL channel operating mode
165 * zl3073x_chan_lock_state_get - get DPLL channel lock state
168 * Return: lock state of the given DPLL channel
250 * Return: reference selection state of the given DPLL channel
261 * Return: reference selected by the DPLL in automatic mode
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";

123456