Home
last modified time | relevance | path

Searched full:dpll (Results 1 – 25 of 118) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
4 register-mapped DPLL with usually two selectable input clocks
10 for the actual DPLL clock.
16 "ti,omap3-dpll-clock",
17 "ti,omap3-dpll-core-clock",
18 "ti,omap3-dpll-per-clock",
19 "ti,omap3-dpll-per-j-type-clock",
20 "ti,omap4-dpll-clock",
21 "ti,omap4-dpll-x2-clock",
22 "ti,omap4-dpll-core-clock",
[all …]
/linux/drivers/clk/ti/
H A Ddpll3xxx.c3 * OMAP3/4 - specific DPLL control functions
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
129 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
130 * @clk: pointer to a DPLL struct clk
132 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
133 * readiness before returning. Will save and restore the DPLL's
134 * autoidle state across the enable, per the CDP code. If the DPLL
135 * locked successfully, return 0; if the DPLL did not lock in the time
145 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock()
[all …]
H A Dclkt_dpll.c3 * OMAP2/3/4 DPLL clock functions
25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
33 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
44 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
45 * From device data manual section 4.3 "DPLL and DLL Specifications".
57 * _dpll_test_fint - test whether an Fint value is valid for the DPLL
58 * @clk: DPLL struct clk to test
61 * Tests whether a particular divider @n will result in a valid DPLL
62 * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter
75 /* DPLL divider must result in a valid jitter correction val */ in _dpll_test_fint()
[all …]
H A Ddpll44xx.c3 * OMAP4-specific DPLL control functions
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
79 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
80 * @dd: pointer to the dpll data structure
104 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
106 * @parent_rate: clock rate of the DPLL parent
108 * Compute the output rate for the OMAP4 DPLL represented by @clk.
110 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
128 /* regm4xen adds a multiplier of 4 to DPLL calculations */ in omap4_dpll_regm4xen_recalc()
[all …]
H A Ddpll.c3 * OMAP DPLL clock support
137 * _register_dpll - low level registration of a DPLL clock
141 * Finalizes DPLL registration process. In case a failure (clk-ref or
207 * Initializes a DPLL x 2 clock from device tree data.
264 * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
265 * @node: device node containing the DPLL info
266 * @ops: ops for the DPLL
267 * @ddt: DPLL data template to use
269 * Initializes a DPLL clock from device tree data.
314 * Special case for OMAP2 DPLL, register order is different due to in of_ti_dpll_setup()
[all …]
/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
18 indicated by dpll-types property.
22 pattern: "^dpll(@.*)?$"
30 dpll-types:
31 description: List of DPLL channel types, one per DPLL instance.
38 description: DPLL input pins
49 $ref: /schemas/dpll/dpll-pin.yaml
[all …]
/linux/include/linux/clk/
H A Dti.h29 * struct dpll_data - DPLL registers and integration data
30 * @mult_div1_reg: register containing the DPLL M and N bitfields
31 * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32 * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35 * @control_reg: register containing the DPLL mode bitfield
36 * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47 * @max_rate: maximum clock rate for the DPLL
49 * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50 * @idlest_reg: register containing the DPLL idle status bitfield
51 * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c108 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
159 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
161 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
162 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
164 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
168 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
169 dpll |= in psb_intel_crtc_mode_set()
174 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
177 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
180 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
H A Dcdv_intel_display.c208 /* Unlike most Intel display engines, on Cedarview the DPLL registers
210 * DPLL reference clock is on in the DPLL control register, but before
211 * the DPLL is enabled in the DPLL control register.
262 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n"); in cdv_dpll_set_clock_cdv()
585 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
666 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
677 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
679 dpll |= DPLLB_MODE_LVDS; in cdv_intel_crtc_mode_set()
681 dpll |= DPLLB_MODE_DAC_SERIAL; */ in cdv_intel_crtc_mode_set()
682 /* dpll |= (2 << 11); */ in cdv_intel_crtc_mode_set()
[all …]
H A Dgma_display.c222 /* Enable the DPLL */ in gma_crtc_dpms()
223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
310 /* Disable DPLL */ in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
H A Doaktrail_hdmi.c286 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
295 /* Disable dpll if necessary */ in oaktrail_crtc_hdmi_mode_set()
296 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
297 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
298 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
307 /* program and enable dpll */ in oaktrail_crtc_hdmi_mode_set()
311 /* Set the DPLL */ in oaktrail_crtc_hdmi_mode_set()
312 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
314 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
[all …]
/linux/arch/arm/mach-omap2/
H A Dclkt2xxx_dpll.c3 * OMAP2-specific DPLL control functions
21 * _allow_idle - enable DPLL autoidle bits
22 * @clk: struct clk * of the DPLL to operate on
24 * Enable DPLL automatic idle control. The DPLL will enter low-power
26 * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
38 * _deny_idle - prevent DPLL from automatically idling
39 * @clk: struct clk * of the DPLL to operate on
41 * Disable DPLL automatic idle control. No return value.
H A Dsleep24xx.S35 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
44 * Post sleep we will shift back to using the DPLL. Apparently,
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
69 /* The DPLL has to be on before we take the DDR out of self refresh */
H A Dopp2xxx.h14 * respect to each other. These ratio sets are for a given voltage/DPLL
15 * setting. All configurations can be described by a DPLL setting and a ratio
45 unsigned long dpll_speed; /* dpll: out*xtal*M/(N-1)table_recalc */
65 * Voltage/DPLL ratios
218 * describe DPLL combinations to go along with a ratio.
230 * #5a (ratio1) baseport-target, target DPLL = 266*2 = 532MHz
247 /* #5b (ratio1) target DPLL = 200*2 = 400MHz */
265 * #4 (ratio2), DPLL = 399*2 = 798MHz, L3=133MHz
286 * #3 (ratio2) baseport-target, target DPLL = 330*2 = 660MHz
305 * #2 (ratio1) DPLL = 330*2 = 660MHz, L3=165MHz
[all …]
H A Dclkt2xxx_dpllcore.c3 * DPLL + CORE_CLK composite clock functions
15 * XXX The DPLL and CORE clocks should be split into two separate clock
47 * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz
81 if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ in omap2_dpllcore_round_rate()
84 } else { /* DPLL clockout x 2 */ in omap2_dpllcore_round_rate()
/linux/drivers/dpll/zl3073x/
H A Ddpll.h6 #include <linux/dpll.h>
12 * struct zl3073x_dpll - ZL3073x DPLL sub-device structure
13 * @list: this DPLL list entry
15 * @id: DPLL index
18 * @ops: DPLL device operations for this instance
19 * @dpll_dev: pointer to registered DPLL device
21 * @lock_status: last saved DPLL lock status
H A DKconfig4 tristate "Microchip Azurite DPLL/PTP/SyncE devices" if COMPILE_TEST
6 select DPLL
10 This driver supports Microchip Azurite family DPLL/PTP/SyncE
11 devices that support up to 5 independent DPLL channels,
23 This is I2C bus implementation for Microchip Azurite DPLL/PTP/SyncE
35 This is SPI bus implementation for Microchip Azurite DPLL/PTP/SyncE
H A Dprop.c113 /* Set package_label pointer in DPLL core properties to generated in zl3073x_prop_pin_package_label_set()
242 /* Look for pin type property and translate its value to DPLL in zl3073x_pin_props_get()
276 * DPLL core pin properties requires list of frequency ranges. in zl3073x_pin_props_get()
352 * zl3073x_prop_dpll_type_get - get DPLL channel type
354 * @index: DPLL channel index
356 * Return: DPLL type for given DPLL channel
364 /* Read dpll types property from firmware */ in zl3073x_prop_dpll_type_get()
365 count = device_property_read_string_array(zldev->dev, "dpll-types", in zl3073x_prop_dpll_type_get()
377 dev_info(zldev->dev, "Unknown DPLL type '%s', using default\n", in zl3073x_prop_dpll_type_get()
H A Dprop.h6 #include <linux/dpll.h>
15 * @dpll_props: DPLL core pin properties
/linux/drivers/dpll/
H A DMakefile3 # Makefile for DPLL drivers.
6 obj-$(CONFIG_DPLL) += dpll.o
7 dpll-y += dpll_core.o
8 dpll-y += dpll_netlink.o
9 dpll-y += dpll_nl.o
/linux/Documentation/devicetree/bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/linux/drivers/ata/
H A Dpata_hpt3x2n.c61 /* 66MHz DPLL clocks */
263 * We must use the DPLL for
299 /* See if we should use the DPLL */ in hpt3x2n_use_dpll()
312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
372 * hpt3xn_calibrate_dpll - Calibrate the DPLL loop
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
H A Dam33xx-clocks.dtsi191 compatible = "ti,am3-dpll-core-clock";
197 dpll_core_x2_ck: clock-dpll-core-x2 {
199 compatible = "ti,am3-dpll-x2-clock";
204 dpll_core_m4_ck: clock-dpll-core-m4@480 {
214 dpll_core_m5_ck: clock-dpll-core-m5@484 {
224 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
236 compatible = "ti,am3-dpll-clock";
242 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
254 compatible = "ti,am3-dpll-no-gate-clock";
260 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]

12345