| /linux/drivers/net/ethernet/synopsys/ |
| H A D | dwc-xlgmac.h | 5 * This program is dual-licensed; you may select either version 2 of
21 #include <linux/dma-mapping.h>
29 #define XLGMAC_DRV_NAME "dwc-xlgmac"
33 /* Descriptor related parameters */
47 #define XLGMAC_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
97 ((_ring)->desc_data_head + \
98 ((idx) & ((_ring)->dma_desc_count - 1))); \
104 ((var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
111 ((_var) & GENMASK(_pos + _len - 1, _pos)) >> (_pos); \
119 _val = (_val << _pos) & GENMASK(_pos + _len - 1, _pos); \
[all …]
|
| /linux/drivers/net/ethernet/amd/xgbe/ |
| H A D | xgbe.h | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
11 #include <linux/dma-mapping.h>
28 #define XGBE_DRV_NAME "amd-xgbe"
31 /* Descriptor related defines */
42 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
49 * - Maximum number of SKB frags
50 * - Maximum descriptors for contiguous TSO/GSO packet
51 * - Possible context descriptor
52 * - Possible TSO header descriptor
[all …]
|
| /linux/arch/sh/include/mach-dreamcast/mach/ |
| H A D | sysasic.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/dreamcast/sysasic.h
5 * Definitions for the Dreamcast System ASIC and related peripherals.
8 * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
17 /* Hardware events -
29 #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
30 #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
31 #define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
32 #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
35 #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
[all …]
|
| /linux/drivers/crypto/ccp/ |
| H A D | ccp-dev.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
19 #include <linux/dma-direction.h>
27 #include "sp-dev.h"
63 /* ------------------------ CCP Version 5 Specifics ------------------------ */
103 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
105 #define Q_PTR_MASK (2 << (QUEUE_SIZE_VAL + 5) - 1)
125 /* ------------------------ CCP Version 3 Specifics ------------------------ */
133 /****** REQ1 Related Values ******/
141 /* AES Related Values */
147 /* XTS-AES Related Values */
[all …]
|
| /linux/drivers/usb/gadget/udc/cdns2/ |
| H A D | cdns2-gadget.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * USBHS-DEV device controller driver header file
14 #include <linux/dma-direction.h>
22 * struct cdns2_ep0_regs - endpoint 0 related registers.
45 /* EP0CS - bitmasks. */
59 /* EP0FIFO - bitmasks. */
70 * struct cdns2_epx_base - base endpoint registers.
87 /* rxcon/txcon - endpoint control register bitmasks. */
88 /* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
106 /* rxcs/txcs - endpoint control and status bitmasks. */
[all …]
|
| /linux/include/uapi/linux/ |
| H A D | fpga-dfl.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
38 * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
47 * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
58 * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
61 * Userspace can do Port reset at any time, e.g. during DMA or PR. But
63 * (e.g. DMA or PR operation failure) and be recoverable from the failure.
64 * Return: 0 on success, -errno of failure
70 * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
75 * Return: 0 on success, -errno on failure.
[all …]
|
| /linux/drivers/net/ethernet/ti/icssg/ |
| H A D | icssg_prueth.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
34 #include <linux/dma-mapping.h>
35 #include <linux/dma/ti-cppi5.h>
36 #include <linux/dma/k3-udma-glue.h>
46 #define PRUETH_MAX_MTU (2000 - ETH_HLEN - ETH_FCS_LEN)
60 /* Number of ICSSG related stats */
63 #define ICSSG_NUM_ETHTOOL_STATS (ICSSG_NUM_STATS - ICSSG_NUM_STANDARD_STATS)
91 /* VLAN Filtering Related MACROs */
161 /* There are 4 Tx DMA channels, but the highest priority is CH3 (thread 3)
[all …]
|
| /linux/arch/x86/kernel/ |
| H A D | i8237.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * 8237A DMA controller suspend functions.
12 #include <asm/dma.h>
17 * 8237A DMA controller (used for ISA and LPC).
18 * Allocation is handled in kernel/dma.c and normal usage is
19 * in asm/dma.h.
34 /* DMA count is a bit weird so this is not 0 */ in i8237A_resume()
38 /* Enable cascade DMA or channel 0-3 won't work */ in i8237A_resume()
51 * From SKL PCH onwards, the legacy DMA device is removed in which the in i8237A_init_ops()
52 * I/O ports (81h-83h, 87h, 89h-8Bh, 8Fh) related to it are removed in i8237A_init_ops()
[all …]
|
| /linux/drivers/staging/media/deprecated/atmel/ |
| H A D | atmel-isc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
13 #include <linux/clk-provider.h>
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/videobuf2-dma-contig.h>
57 * struct isc_format - ISC media bus format information
97 * struct fmt_config - ISC format configuration and internal pipeline
109 * @dcfg_imode: Configuration of the input of the DMA module
110 * @dctrl_dview: Configuration of the output of the DMA module
[all …]
|
| /linux/Documentation/admin-guide/blockdev/ |
| H A D | floppy.rst | 19 Example: If your kernel is called linux-2.6.9, type the following line
22 linux-2.6.9 floppy=thinkpad
25 of linux-2.6.9::
29 Several floppy related options may be given, example::
31 linux-2.6.9 floppy=daring floppy=two_fdc
59 The floppy driver related options are:
91 Tells the floppy driver not to use Dma for data transfers.
93 DMA channel for the floppy driver. This option is also useful
94 if you frequently get "Unable to allocate DMA memory" messages.
95 Indeed, dma memory needs to be continuous in physical memory,
[all …]
|
| /linux/drivers/ntb/hw/idt/ |
| H A D | ntb_hw_idt.h | 7 * Copyright (C) 2016-2018 T-Platforms JSC All Rights Reserved.
36 * IDT PCIe-switch NTB Linux driver
39 * Serge Semin <fancer.lancer@gmail.com>, <Sergey.Semin@t-platforms.ru>
55 * the supported IDT PCIe-switches
66 * IDT PCIe-switches device IDs
78 * NT-function Configuration Space registers
79 * NOTE 1) The IDT PCIe-switch internal data is little-endian
83 * with byte-enables corresponding to their native size or
86 * So to simplify the driver code, there is only DWORD-sized read/write
107 /* IDT Proprietary NT-port-specific registers */
[all …]
|
| /linux/drivers/media/platform/microchip/ |
| H A D | microchip-isc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2016-2019 Microchip Technology, Inc.
13 #include <linux/clk-provider.h>
16 #include <media/v4l2-ctrls.h>
17 #include <media/v4l2-device.h>
18 #include <media/videobuf2-dma-contig.h>
57 * struct isc_format - ISC media bus format information
98 * struct fmt_config - ISC format configuration and internal pipeline
110 * @dcfg_imode: Configuration of the input of the DMA module
111 * @dctrl_dview: Configuration of the output of the DMA module
[all …]
|
| /linux/drivers/media/platform/samsung/s5p-mfc/ |
| H A D | s5p_mfc_opr.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.c
5 * Samsung MFC (Multi Function Codec - FIMV) driver
6 * This file contains hw related functions.
20 dev->mfc_ops = s5p_mfc_init_hw_ops_v6(); in s5p_mfc_init_hw_ops()
21 dev->warn_start = S5P_FIMV_ERR_WARNINGS_START_V6; in s5p_mfc_init_hw_ops()
23 dev->mfc_ops = s5p_mfc_init_hw_ops_v5(); in s5p_mfc_init_hw_ops()
24 dev->warn_start = S5P_FIMV_ERR_WARNINGS_START; in s5p_mfc_init_hw_ops()
31 dev->mfc_regs = s5p_mfc_init_regs_v6_plus(dev); in s5p_mfc_init_regs()
37 unsigned int bits = dev->mem_size >> PAGE_SHIFT; in s5p_mfc_alloc_priv_buf()
[all …]
|
| /linux/Documentation/devicetree/bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
[all …]
|
| /linux/Documentation/driver-api/ |
| H A D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /linux/drivers/net/ipa/ |
| H A D | ipa_table.c | 1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
10 #include <linux/dma-mapping.h>
27 * The IPA has tables defined in its local (IPA-resident) memory that define
29 * endian 64-bit "slot" that holds the address of a rule definition. (The
30 * size of these slots is 64 bits regardless of the host DMA address size.)
38 * an object (such as a route or filter table) in IPA-resident memory must
39 * 128-byte aligned. An object in system memory (such as a route or filter
40 * rule) must be at an 8-byte aligned address. We currently only place
[all …]
|
| /linux/Documentation/core-api/ |
| H A D | pin_user_pages.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 pin_user_pages() and related calls
35 In other words, use pin_user_pages*() for DMA-pinned pages, and
54 flags the caller provides. The caller is required to pass in a non-null struct
72 --------
79 but the caller passed in a non-null struct pages* array, then the function
84 --------
89 Tracking dma-pinned pages
92 Some of the key design constraints, and solutions, for tracking dma-pinned
98 * False positives (reporting that a page is dma-pinned, when in fact it is not)
[all …]
|
| /linux/include/ufs/ |
| H A D | ufshcd.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-m
[all...] |
| /linux/drivers/net/wireless/ath/ath5k/ |
| H A D | dma.c | 2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
20 * DMA and interrupt masking functions *
24 * DOC: DMA and interrupt masking functions
26 * Here we setup descriptor pointers (rxdp/txdp) start/stop dma engine and
44 * ath5k_hw_start_rx_dma() - Start DMA receive
55 * ath5k_hw_stop_rx_dma() - Stop DMA receive
66 * It may take some time to disable the DMA receive unit in ath5k_hw_stop_rx_dma()
70 i--) in ath5k_hw_stop_rx_dma()
75 "failed to stop RX DMA !\n"); in ath5k_hw_stop_rx_dma()
[all …]
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
[all …]
|
| /linux/Documentation/arch/x86/ |
| H A D | iommu.rst | 7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_3_…
13 -----------
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
26 - IVHD - AMD I/O Virtualization Hardware Definition
33 reserved in the e820 map. When we turn on DMA translation, DMA to those
[all …]
|
| /linux/drivers/gpu/host1x/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
15 The Tegra host1x module is the DMA engine for register access to
16 Tegra's graphics- and multimedia-related modules. The modules served
|
| /linux/drivers/dma-buf/ |
| H A D | dma-buf.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Many thanks to linaro-mm-sig list, and specially
16 #include <linux/dma-buf.h>
17 #include <linux/dma-fence.h>
18 #include <linux/dma-fence-unwrap.h>
28 #include <linux/dma-resv.h>
33 #include <uapi/linux/dma-buf.h>
36 #include "dma-buf-sysfs-stats.h"
46 list_add(&dmabuf->list_node, &dmabuf_list); in __dma_buf_list_add()
56 list_del(&dmabuf->list_node); in __dma_buf_list_del()
[all …]
|
| /linux/drivers/net/ethernet/intel/idpf/ |
| H A D | idpf_controlq_setup.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 * idpf_ctlq_alloc_desc_ring - Allocate Control Queue (CQ) rings
14 size_t size = cq->ring_size * sizeof(struct idpf_ctlq_desc); in idpf_ctlq_alloc_desc_ring()
16 cq->desc_ring.va = idpf_alloc_dma_mem(hw, &cq->desc_ring, size); in idpf_ctlq_alloc_desc_ring()
17 if (!cq->desc_ring.va) in idpf_ctlq_alloc_desc_ring()
18 return -ENOMEM; in idpf_ctlq_alloc_desc_ring()
24 * idpf_ctlq_alloc_bufs - Allocate Control Queue (CQ) buffers
29 * queue, allocate DMA buffers
36 /* Do not allocate DMA buffers for transmit queues */ in idpf_ctlq_alloc_bufs()
37 if (cq->cq_type == IDPF_CTLQ_TYPE_MAILBOX_TX) in idpf_ctlq_alloc_bufs()
[all …]
|
| /linux/drivers/accel/habanalabs/common/ |
| H A D | habanalabs.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
[all …]
|