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/linux/Documentation/gpu/amdgpu/
H A Ddgpu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
3 AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --
4 AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, --
5 AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --
6 AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE…
7 AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1
8 AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1
10 AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3
11 AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3
12 …on (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / …
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce112/
H A Ddce112_resource.c37 #include "dce/dce_mem_input.h"
38 #include "dce/dce_transform.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_audio.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_clock_source.h"
46 #include "dce/dce_hwseq.h"
48 #include "dce/dce_abm.h"
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce110/
H A Ddce110_resource.c34 #include "dce/dce_audio.h"
38 #include "dce/dce_link_encoder.h"
39 #include "dce/dce_stream_encoder.h"
40 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
45 #include "dce/dce_opp.h"
47 #include "dce/dce_clock_source.h"
48 #include "dce/dce_hwseq.h"
50 #include "dce/dce_aux.h"
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
H A Ddce110_clk_mgr.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
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/linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/
H A Ddcn301_dio_link_encoder.c124 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn301_link_encoder_construct()
129 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn301_link_encoder_construct()
130 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn301_link_encoder_construct()
131 * By this, adding DIGG should not hurt DCE 8.0. in dcn301_link_encoder_construct()
132 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn301_link_encoder_construct()
174 /* Override features with DCE-specific values */ in dcn301_link_encoder_construct()
/linux/include/uapi/linux/hdlc/
H A Dioctl.h10 #define CLOCK_INT 2 /* Internal TX and RX clock - DCE */
65 unsigned short dce; /* 1 for DCE (network side) operation */ member
83 unsigned short dce; /* 1 for DCE (network side) operation */ member
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.c156 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn201_link_encoder_construct()
161 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn201_link_encoder_construct()
162 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn201_link_encoder_construct()
163 * By this, adding DIGG should not hurt DCE 8.0. in dcn201_link_encoder_construct()
164 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn201_link_encoder_construct()
191 /* Override features with DCE-specific values */ in dcn201_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/resource/dce100/
H A Ddce100_resource.c37 #include "dce/dce_link_encoder.h"
38 #include "dce/dce_stream_encoder.h"
39 #include "dce/dce_mem_input.h"
40 #include "dce/dce_ipp.h"
41 #include "dce/dce_transform.h"
42 #include "dce/dce_opp.h"
43 #include "dce/dce_clock_source.h"
44 #include "dce/dce_audio.h"
45 #include "dce/dce_hwseq.h"
47 #include "dce/dce_panel_cntl.h"
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A DMakefile23 # Makefile for common 'dce' logic
29 DCE = dce_audio.o dce_stream_encoder.o dce_link_encoder.o \ macro
35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
H A Ddce_clk_mgr.c54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
202 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in get_max_pixel_clock_for_all_paths()
227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
464 * the dce clock manager. This operation will overwrite the existing dprefclk
619 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
621 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
623 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
627 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-led-trigger-tty29 DCE is ready to accept data from the DTE.
39 DCE is ready to receive and send data.
49 DTE is receiving a carrier from the DCE.
59 DCE has detected an incoming ring signal on the telephone
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_link_encoder.c135 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn30_link_encoder_construct()
140 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn30_link_encoder_construct()
141 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn30_link_encoder_construct()
142 * By this, adding DIGG should not hurt DCE 8.0. in dcn30_link_encoder_construct()
143 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn30_link_encoder_construct()
185 /* Override features with DCE-specific values */ in dcn30_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_link_encoder.c376 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn21_link_encoder_construct()
381 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn21_link_encoder_construct()
382 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn21_link_encoder_construct()
383 * By this, adding DIGG should not hurt DCE 8.0. in dcn21_link_encoder_construct()
384 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn21_link_encoder_construct()
426 /* Override features with DCE-specific values */ in dcn21_link_encoder_construct()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_v.c29 #include "dce/dce_11_0_d.h"
30 #include "dce/dce_11_0_sh_mask.h"
32 #include "dce/dce_opp.h"
/linux/drivers/gpu/drm/amd/display/dc/resource/dce80/
H A Ddce80_resource.c26 #include "dce/dce_8_0_d.h"
27 #include "dce/dce_8_0_sh_mask.h"
40 #include "dce/dce_mem_input.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_transform.h"
45 #include "dce/dce_opp.h"
46 #include "dce/dce_clock_source.h"
47 #include "dce/dce_audio.h"
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/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_resource.c28 #include "dce/dce_6_0_d.h"
29 #include "dce/dce_6_0_sh_mask.h"
42 #include "dce/dce_mem_input.h"
43 #include "dce/dce_link_encoder.h"
44 #include "dce/dce_stream_encoder.h"
45 #include "dce/dce_ipp.h"
46 #include "dce/dce_transform.h"
47 #include "dce/dce_opp.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c41 #include "dce/dce_opp.h"
42 #include "dce/dce_clock_source.h"
43 #include "dce/dce_ipp.h"
44 #include "dce/dce_mem_input.h"
45 #include "dce/dce_panel_cntl.h"
49 #include "dce/dce_transform.h"
51 #include "dce/dce_audio.h"
52 #include "dce/dce_link_encoder.h"
53 #include "dce/dce_stream_encoder.h"
54 #include "dce/dce_hwseq.h"
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/linux/drivers/gpu/drm/amd/display/dc/hwss/dce80/
H A Ddce80_hwseq.c31 #include "dce/dce_hwseq.h"
36 #include "dce/dce_8_0_d.h"
37 #include "dce/dce_8_0_sh_mask.h"
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
H A Ddce60_clk_mgr.c43 #include "dce/dce_6_0_d.h"
44 #include "dce/dce_6_0_sh_mask.h"
74 /* ClocksStateUltraLow - not expected to be used for DCE 6.0 */
126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
/linux/drivers/net/wan/
H A Dhdlc_fr.c11 DCE mode:
352 if (state(hdlc)->settings.dce) { in pvc_close()
462 int dce = state(hdlc)->settings.dce; in fr_lmi_send() local
468 if (dce && fullrep) { in fr_lmi_send()
489 data[i++] = dce ? LMI_STATUS : LMI_STATUS_ENQUIRY; in fr_lmi_send()
502 if (dce && fullrep) { in fr_lmi_send()
575 if (!state(hdlc)->settings.dce) in fr_set_link_state()
590 if (state(hdlc)->settings.dce) { in fr_timer()
615 if (state(hdlc)->settings.dce) { in fr_timer()
639 int dce = state(hdlc)->settings.dce; in fr_lmi_recv() local
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c43 #include "dce/dce_8_0_d.h"
44 #include "dce/dce_8_0_sh_mask.h"
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
183 /* raise clock state for HBR3/2 if required. Confirmed with HW DCE/DPCS in dce_get_max_pixel_clock_for_all_paths()
208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
403 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/
H A Ddcn20_link_encoder.c435 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. in dcn20_link_encoder_construct()
440 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design in dcn20_link_encoder_construct()
441 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. in dcn20_link_encoder_construct()
442 * By this, adding DIGG should not hurt DCE 8.0. in dcn20_link_encoder_construct()
443 * This will let DCE 8.1 share DCE 8.0 as much as possible in dcn20_link_encoder_construct()
485 /* Override features with DCE-specific values */ in dcn20_link_encoder_construct()
/linux/Documentation/filesystems/smb/
H A Dksmbd.rst15 performance in userspace. So, DCE/RPC management that has historically resulted
34 currently DCE/RPC commands are identified to be handled through the user space.
59 NetServerGetInfo. Complete DCE/RPC response is prepared from the user space
104 DCE/RPC support Partially Supported. a few calls(NetShareEnumAll,
110 DCE/RPC management calls (and future support
/linux/drivers/gpu/drm/amd/display/dc/hwss/dce120/
H A Ddce120_hwseq.c30 #include "dce/dce_hwseq.h"
34 #include "dce/dce_12_0_offset.h"
35 #include "dce/dce_12_0_sh_mask.h"
246 * @hws: DCE hardware sequencer object
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_helper.c693 return "DCE 8.0"; in dce_version_to_string()
695 return "DCE 8.1"; in dce_version_to_string()
697 return "DCE 8.3"; in dce_version_to_string()
699 return "DCE 10.0"; in dce_version_to_string()
701 return "DCE 11.0"; in dce_version_to_string()
703 return "DCE 11.2"; in dce_version_to_string()
705 return "DCE 11.22"; in dce_version_to_string()
707 return "DCE 12.0"; in dce_version_to_string()
709 return "DCE 12.1"; in dce_version_to_string()

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