| /linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_cyclone5_mercury_sa1.dtsi | 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
21 * Enclustra Arria10 and Cyclone5 SoMs.
|
| H A D | socfpga_cyclone5_mercury_sa2.dtsi | 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
21 * Enclustra Arria10 and Cyclone5 SoMs.
|
| H A D | socfpga_cyclone5_sockit.dts | 10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_pe3_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_pe3_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_pe1_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_st1_emmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_pe3_emmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_st1_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_pe1_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_arria10_mercury_aa1_pe1_emmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa1_st1_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_st1_sdmmc.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mercury_sa2_st1_qspi.dts | 15 "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_mcv.dtsi | 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_socrates.dts | 10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_de10nano.dts | 15 compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_chameleon96.dts | 14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
|
| H A D | socfpga_cyclone5_de0_nano_soc.dts | 10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
|
| /linux/Documentation/devicetree/bindings/net/ |
| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
151 On Cyclone5/Arria5, the register shift represents the PHY mode
|
| /linux/Documentation/devicetree/bindings/reset/ |
| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
|