| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | altera.yaml | 43 - altr,socfpga-cyclone5-socdk
51 - terasic,socfpga-cyclone5-sockit
52 - const: altr,socfpga-cyclone5
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | socfpga-dwmac.txt | 9 - compatible : For Cyclone5/Arria5 SoCs it should contain
16 On Cyclone5/Arria5, the register shift represents the PHY mode bits, while
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| H A D | altr,socfpga-stmmac.yaml | 14 Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
126 On Cyclone5/Arria5, the register shift represents the PHY mode
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| /freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/ |
| H A D | socfpga_cyclone5_socdk.dts | 10 compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_sockit.dts | 10 compatible = "terasic,socfpga-cyclone5-sockit", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_mcv.dtsi | 10 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_socrates.dts | 10 compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_mcvevk.dts | 10 compatible = "denx,mcvevk", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_de10nano.dts | 15 compatible = "terasic,de10-nano", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_chameleon96.dts | 14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_de0_nano_soc.dts | 10 compatible = "terasic,de0-atlas", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_sodia.dts | 12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
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| H A D | socfpga_cyclone5_vining_fpga.dts | 12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | socfpga-reset.txt | 4 - compatible : "altr,rst-mgr" for (Cyclone5/Arria5/Arria10)
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| H A D | altr,rst-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /freebsd/sys/contrib/device-tree/Bindings/soc/altera/ |
| H A D | altr,sys-mgr.yaml | 15 - description: Cyclone5/Arria5/Arria10
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| /freebsd/sys/dts/arm/ |
| H A D | socfpga_cyclone5_sockit_sdmmc.dts | 36 compatible = "altr,socfpga-cyclone5", "altr,socfpga";
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| /freebsd/sys/contrib/device-tree/Bindings/arm/altera/ |
| H A D | socfpga-clk-manager.yaml | 14 tree of clocks, pll's, and clock gates for the Cyclone5, Arria5 and Arria10
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | altr,pcie-root-port.yaml | 16 PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5
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| /freebsd/sys/contrib/device-tree/Bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 6 Cyclone5 and Arria5 ECC Manager
54 in a shared register instead of individual IRQs like the Cyclone5
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| H A D | altr,socfpga-ecc-manager.yaml | 15 ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
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