1*2e36db14SWarner Losh/*- 2*2e36db14SWarner Losh * Copyright (c) 2017 Ruslan Bukin <br@bsdpad.com> 3*2e36db14SWarner Losh * All rights reserved. 4*2e36db14SWarner Losh * 5*2e36db14SWarner Losh * This software was developed by SRI International and the University of 6*2e36db14SWarner Losh * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7*2e36db14SWarner Losh * ("CTSRD"), as part of the DARPA CRASH research programme. 8*2e36db14SWarner Losh * 9*2e36db14SWarner Losh * Redistribution and use in source and binary forms, with or without 10*2e36db14SWarner Losh * modification, are permitted provided that the following conditions 11*2e36db14SWarner Losh * are met: 12*2e36db14SWarner Losh * 1. Redistributions of source code must retain the above copyright 13*2e36db14SWarner Losh * notice, this list of conditions and the following disclaimer. 14*2e36db14SWarner Losh * 2. Redistributions in binary form must reproduce the above copyright 15*2e36db14SWarner Losh * notice, this list of conditions and the following disclaimer in the 16*2e36db14SWarner Losh * documentation and/or other materials provided with the distribution. 17*2e36db14SWarner Losh * 18*2e36db14SWarner Losh * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19*2e36db14SWarner Losh * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*2e36db14SWarner Losh * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*2e36db14SWarner Losh * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22*2e36db14SWarner Losh * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23*2e36db14SWarner Losh * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24*2e36db14SWarner Losh * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25*2e36db14SWarner Losh * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26*2e36db14SWarner Losh * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27*2e36db14SWarner Losh * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28*2e36db14SWarner Losh * SUCH DAMAGE. 29*2e36db14SWarner Losh */ 30*2e36db14SWarner Losh 31*2e36db14SWarner Losh/* /dts-v1/; */ 32*2e36db14SWarner Losh#include "socfpga_cyclone5_sockit.dts" 33*2e36db14SWarner Losh 34*2e36db14SWarner Losh/ { 35*2e36db14SWarner Losh model = "Terasic SoCkit"; 36*2e36db14SWarner Losh compatible = "altr,socfpga-cyclone5", "altr,socfpga"; 37*2e36db14SWarner Losh 38*2e36db14SWarner Losh /* Reserve first page for secondary CPU trampoline code */ 39*2e36db14SWarner Losh memreserve = < 0x00000000 0x1000 >; 40*2e36db14SWarner Losh 41*2e36db14SWarner Losh soc { 42*2e36db14SWarner Losh /* Local timer */ 43*2e36db14SWarner Losh timer@fffec600 { 44*2e36db14SWarner Losh clock-frequency = <200000000>; 45*2e36db14SWarner Losh }; 46*2e36db14SWarner Losh 47*2e36db14SWarner Losh /* Global timer */ 48*2e36db14SWarner Losh global_timer: timer@fffec200 { 49*2e36db14SWarner Losh compatible = "arm,cortex-a9-global-timer"; 50*2e36db14SWarner Losh reg = <0xfffec200 0x20>; 51*2e36db14SWarner Losh interrupts = <1 11 0xf04>; 52*2e36db14SWarner Losh clock-frequency = <200000000>; 53*2e36db14SWarner Losh }; 54*2e36db14SWarner Losh }; 55*2e36db14SWarner Losh 56*2e36db14SWarner Losh chosen { 57*2e36db14SWarner Losh stdin = "serial0"; 58*2e36db14SWarner Losh stdout = "serial0"; 59*2e36db14SWarner Losh }; 60*2e36db14SWarner Losh}; 61*2e36db14SWarner Losh 62*2e36db14SWarner Losh&mmc0 { 63*2e36db14SWarner Losh bus-frequency = <25000000>; 64*2e36db14SWarner Losh}; 65*2e36db14SWarner Losh 66*2e36db14SWarner Losh&uart0 { 67*2e36db14SWarner Losh clock-frequency = <100000000>; 68*2e36db14SWarner Losh}; 69*2e36db14SWarner Losh 70*2e36db14SWarner Losh&uart1 { 71*2e36db14SWarner Losh status = "disabled"; 72*2e36db14SWarner Losh}; 73