| /linux/drivers/cxl/ |
| H A D | Kconfig | 3 tristate "CXL (Compute Express Link) Devices Support"
12 CXL is a bus that is electrically compatible with PCI Express, but
13 layers three protocols on that signalling (CXL.io, CXL.cache, and
14 CXL.mem). The CXL.cache protocol allows devices to hold cachelines
15 locally, the CXL.mem protocol allows devices to be fully coherent
16 memory targets, the CXL.io protocol is equivalent to PCI Express.
27 The CXL specification defines a "CXL memory device" sub-class in the
33 Say 'y/m' to enable a driver that will attach to CXL memory expander
36 Type 3 CXL Device in the CXL 2.0 specification for more details.
44 Enable CXL RAW command interface.
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| H A D | cxl.h | 15 #include <cxl/cxl.h>
20 * DOC: cxl objects
22 * The CXL core objects like ports, decoders, and regions are shared
27 /* CXL 2.0 8.2.4 CXL Component Register Layout and Definition */
30 /* CXL 2.0 8.2.5 CXL.cache and CXL.mem Registers*/
46 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */
73 /* HDM decoder control register constants CXL 3.0 8.2.5.19.7 */
93 /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
102 /* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */
145 /* RAS Registers CXL 2.0 8.2.5.9 CXL RAS Capability Structure */
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| H A D | acpi.c | 12 #include "cxl.h"
33 * that nullifies any expectation of trusted parameters from the CXL in cxl_do_xormap_calc()
46 * In regions using XOR interleave arithmetic the CXL HPA may not in cxl_do_xormap_calc()
47 * be the same as the SPA. This helper performs the SPA->CXL HPA in cxl_do_xormap_calc()
48 * or the CXL HPA->SPA translation. Since XOR is self-inverting, in cxl_do_xormap_calc()
57 * XORALLBITS: The CXL spec (3.1 Table 9-22) defines XORALLBITS in cxl_do_xormap_calc()
111 /* Does this CXIMS entry apply to the given CXL Window? */ in cxl_parse_cxims()
347 res->name = kasprintf(GFP_KERNEL, "CXL Window %d", id); in alloc_cxl_resource()
384 * Currently there is only support cache_size == cxl_size. CXL in cxl_setup_extended_linear_cache()
390 "Extended Linear Cache size %pa != CXL size %pa. No Support!", in cxl_setup_extended_linear_cache()
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| /linux/Documentation/driver-api/cxl/ |
| H A D | theory-of-operation.rst | 8 A Compute Express Link Memory Device is a CXL component that implements the
9 CXL.mem protocol. It contains some amount of volatile memory, persistent memory,
17 The CXL Bus
20 logical device, the CXL subsystem is tasked to take PCIe and ACPI objects and
21 assemble them into a CXL.mem decode topology. The need for runtime configuration
22 of the CXL.mem topology is also similar to RAID in that different environments
26 and disable any striping in the CXL.mem topology.
28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
38 Here is a sample listing of a CXL topology defined by 'cxl_test'. The 'cxl_test'
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| /linux/Documentation/driver-api/cxl/linux/ |
| H A D | cxl-driver.rst | 4 CXL Driver Operation
9 /sys/bus/cxl/devices/
10 /dev/cxl/
12 The :code:`cxl-cli` library, maintained as part of the NDTCL project, may
17 The CXL driver is split into a number of drivers.
31 # ls /sys/bus/cxl/devices/
39 :alt: Digraph of CXL fabric describing host-bridge interleaving
40 :caption: Diagraph of CXL fabric with a host-bridge interleave memory region
68 Most devices in a CXL fabric are a `port` of some kind (because each
74 The `CXL Root` is logical object created by the `cxl_acpi` driver during
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| H A D | access-coordinates.rst | 5 CXL Access Coordinates Computation
13 not able to annotate those for CXL devices that are hot-plugged since they do
14 not exist during platform firmware initialization. The CXL driver can compute
19 would be the CXL hostbridge. Using this association, the performance
22 performance coordinates between a CPU and a Generic Port (CXL hostbridge).
25 the CXL device itself. That is the bandwidth and latency to access that device's
34 If there's a CXL switch in the topology, then the performance coordinates for the
53 In this example, there is a CXL switch between an endpoint and a root port.
79 See `CXL Memory Device SW Guide r1.0 <https://www.intel.com/content/www/us/en/content-details/64380…
83 or more memory partitions from each of the CXL device(s).
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| H A D | dax-driver.rst | 8 extended to support CXL Memory Devices, which provide user-configured
11 The CXL subsystem depends on the DAX subsystem to either:
14 - Engage the memory-hotplug interface to add CXL memory to page allocator.
17 A `dax_region` provides the translation between a CXL `memory_region` and
25 CXL capacity in the task's page tables.
27 Users wishing to manually handle allocation of CXL memory should use this
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| /linux/drivers/nvdimm/ |
| H A D | nd.h | 33 bool cxl; member
42 if (ndd->cxl) in nsl_ref_name()
43 return nd_label->cxl.name; in nsl_ref_name()
50 if (ndd->cxl) in nsl_get_name()
51 return memcpy(name, nd_label->cxl.name, NSLABEL_NAME_LEN); in nsl_get_name()
60 if (ndd->cxl) in nsl_set_name()
61 return memcpy(nd_label->cxl.name, name, NSLABEL_NAME_LEN); in nsl_set_name()
68 if (ndd->cxl) in nsl_get_slot()
69 return __le32_to_cpu(nd_label->cxl.slot); in nsl_get_slot()
76 if (ndd->cxl) in nsl_set_slot()
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| /linux/drivers/acpi/apei/ |
| H A D | einj-cxl.c | 3 * CXL Error INJection support. Used by CXL core to inject
4 * protocol errors into CXL ports.
12 #include <cxl/einj.h>
20 { ACPI_EINJ_CXL_CACHE_CORRECTABLE, "CXL.cache Protocol Correctable" },
21 { ACPI_EINJ_CXL_CACHE_UNCORRECTABLE, "CXL.cache Protocol Uncorrectable non-fatal" },
22 { ACPI_EINJ_CXL_CACHE_FATAL, "CXL.cache Protocol Uncorrectable fatal" },
23 { ACPI_EINJ_CXL_MEM_CORRECTABLE, "CXL.mem Protocol Correctable" },
24 { ACPI_EINJ_CXL_MEM_UNCORRECTABLE, "CXL.mem Protocol Uncorrectable non-fatal" },
25 { ACPI_EINJ_CXL_MEM_FATAL, "CXL.mem Protocol Uncorrectable fatal" },
48 EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, "CXL");
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| /linux/drivers/firmware/efi/ |
| H A D | cper_cxl.c | 3 * UEFI Common Platform Error Record (CPER) support for CXL Section.
11 #include <cxl/event.h>
14 "Restricted CXL Device",
15 "Restricted CXL Host Downstream Port",
16 "CXL Device",
17 "CXL Logical Device",
18 "CXL Fabric Manager managed Logical Device",
19 "CXL Root Port",
20 "CXL Downstream Switch Port",
21 "CXL Upstream Switch Port",
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| /linux/Documentation/edac/ |
| H A D | memory_repair.rst | 32 For example, a CXL memory device with DRAM components that support PPR
46 For example, for CXL memory devices, see CXL spec rev 3.1 [1]_ sections
68 For example, CXL memory devices can support various subclasses for sparing
77 See CXL spec 3.1 [1]_ section 8.2.9.7.1.4 Memory Sparing Maintenance
80 .. [1] https://computeexpresslink.org/cxl-specification/
90 2. When a CXL device detects an error in a memory component, it informs the
94 that requires repair. The kernel reports the corresponding CXL general
128 1. CXL memory sparing
135 Memory sparing maintenance operations may be supported by CXL devices that
136 implement CXL.mem protocol. A sparing maintenance operation requests the
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| H A D | scrub.rst | 52 identified, such as CXL memory device patrol scrub, CXL DDR5 ECS, ACPI
68 identified, including the CXL memory device patrol scrub, CXL DDR5 ECS,
73 control over patrol (background) scrubbing (e.g., ACPI RAS2, CXL) and/or
97 be a system-wide BIOS or similar control to manage scrub settings for a CXL
107 CXL Memory Scrubbing features
110 CXL spec r3.1 [1]_ section 8.2.9.9.11.1 describes the memory device patrol
113 userspace request to change CXL patrol scrubber's configurations.
118 scrub rate that the device is capable of. In the CXL driver, the
129 CXL spec r3.1 [1]_ section 8.2.9.9.11.2 describes Error Check Scrub (ECS)
190 .. [1] https://computeexpresslink.org/cxl-specification/
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| /linux/Documentation/admin-guide/perf/ |
| H A D | cxl.rst | 4 CXL Performance Monitoring Unit (CPMU)
7 The CXL rev 3.0 specification provides a definition of CXL Performance
10 CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
12 the devices. The specification provides event definitions for all CXL protocol
14 CXL devices (e.g. DRAM events).
19 The CPMU driver registers a perf PMU with the name pmu_mem<X>.<Y> on the CXL bus
22 /sys/bus/cxl/device/pmu_mem<X>.<Y>
28 In common with other CXL bus devices, the id has no specific meaning and the
29 relationship to specific CXL device should be established via the device parent
30 of the device on the CXL bus.
|
| /linux/Documentation/driver-api/cxl/linux/example-configurations/ |
| H A D | single-device.rst | 6 This cxl-cli configuration dump shows the following host configuration:
8 * A single socket system with one CXL root
9 * CXL Root has Four (4) CXL Host Bridges
10 * One CXL Host Bridges has a single CXL Memory Expander Attached
13 This output is generated by :code:`cxl list -v` and describes the relationships
14 between objects exposed in :code:`/sys/bus/cxl/devices/`.
21 "provider":"ACPI.CXL",
46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
79 This chunk shows the available downstream ports associated with the CXL Host
145 The next chunk shows the three CXL host bridges without attached endpoints.
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| H A D | hb-interleave.rst | 6 This cxl-cli configuration dump shows the following host configuration:
8 * A single socket system with one CXL root
9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a single CXL Memory Expander Attached
11 * The CXL root is configured to interleave across the two host bridges.
13 This output is generated by :code:`cxl list -v` and describes the relationships
14 between objects exposed in :code:`/sys/bus/cxl/devices/`.
21 "provider":"ACPI.CXL",
46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
79 This chunk shows the available downstream ports associated with the CXL Host
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| H A D | intra-hb-interleave.rst | 6 This cxl-cli configuration dump shows the following host configuration:
8 * A single socket system with one CXL root
9 * CXL Root has Four (4) CXL Host Bridges
10 * One (1) CXL Host Bridges has two CXL Memory Expanders Attached
13 This output is generated by :code:`cxl list -v` and describes the relationships
14 between objects exposed in :code:`/sys/bus/cxl/devices/`.
21 "provider":"ACPI.CXL",
46 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
79 This chunk shows the available downstream ports associated with the CXL Host
183 The next chunk shows the three CXL host bridges without attached endpoints.
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| H A D | multi-interleave.rst | 6 This cxl-cli configuration dump shows the following host configuration:
8 * A single socket system with one CXL root
9 * CXL Root has Four (4) CXL Host Bridges
10 * Two CXL Host Bridges have a two CXL Memory Expanders Attached each.
11 * The CXL root is configured to interleave across the two host bridges.
14 This output is generated by :code:`cxl list -v` and describes the relationships
15 between objects exposed in :code:`/sys/bus/cxl/devices/`.
22 "provider":"ACPI.CXL",
47 This chunk shows the CXL "bus" (root0) has 4 downstream ports attached to CXL
80 This chunk shows the available downstream ports associated with the CXL Host
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| /linux/drivers/cxl/core/ |
| H A D | pmem.c | 7 #include <cxl.h>
11 * DOC: cxl pmem
13 * The core CXL PMEM infrastructure supports persistent memory
14 * provisioning and serves as a bridge to the LIBNVDIMM subsystem. A CXL
15 * 'bridge' device is added at the root of a CXL device topology if
17 * CXL window. That root-level bridge corresponds to a LIBNVDIMM 'bus'
18 * device. Then for each cxl_memdev in the CXL device topology a bridge
20 * are registered native LIBNVDIMM uapis are translated to CXL
52 EXPORT_SYMBOL_NS_GPL(to_cxl_nvdimm_bridge, "CXL");
57 * root-cxl-port
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| H A D | port.c | 13 #include <cxl/einj.h>
16 #include <cxl.h>
20 * DOC: cxl core
22 * The CXL core provides a set of interfaces that can be consumed by CXL aware
24 * regions, memory devices, ports, and decoders. CXL aware drivers must register
25 * with the CXL core via these interfaces in order to be able to participate in
26 * cross-device interleave coordination. The CXL core also establishes and
29 * CXL core introduces sysfs hierarchy to control the devices that are
453 EXPORT_SYMBOL_NS_GPL(to_cxl_root_decoder, "CXL");
487 EXPORT_SYMBOL_NS_GPL(is_endpoint_decoder, "CXL");
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| /linux/Documentation/firmware-guide/acpi/apei/ |
| H A D | einj.rst | 35 ...and to (optionally) enable CXL protocol error injection set::
137 CXL error types are supported from ACPI 6.5 onwards (given a CXL port
138 is present). The EINJ user interface for CXL error types is at
139 <debugfs mount point>/cxl. The following files belong to it:
144 for CXL error types
148 Injects a CXL error type into the CXL port represented by $dport_dev,
149 where $dport_dev is the name of the CXL port (usually a PCIe device name).
150 Error injections targeting a CXL 2.0+ port can use the legacy interface
151 under <debugfs mount point>/apei/einj, while CXL 1.1/1.0 port injections
239 A CXL error injection example with $dport_dev=0000:e0:01.1::
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| /linux/Documentation/driver-api/cxl/allocation/ |
| H A D | hugepages.rst | 9 CXL Memory onlined as SystemRAM during early boot is eligible for use by CMA,
13 CXL Memory deferred to the CXL Driver for configuration cannot have its
23 All CXL capacity regardless of configuration time or memory zone is eligible
28 CXL capacity onlined in :code:`ZONE_NORMAL` is eligible for 1GB Gigantic Page
31 CXL capacity onlined in :code:`ZONE_MOVABLE` is not eligible for 1GB Gigantic
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| H A D | page-allocator.rst | 8 as :code:`kmalloc`. CXL configuration steps affect the behavior of the page
21 Generally, we expect to see local DRAM and CXL memory on separate NUMA nodes,
22 with the CXL memory being non-local. Technically, however, it is possible
23 for a compute node to have no local DRAM, and for CXL memory to be the
29 CXL capacity may be onlined in :code:`ZONE_NORMAL` or :code:`ZONE_MOVABLE`.
46 Finally, assuming CXL memory is reachable via the page allocation (i.e. onlined
53 prevent demotions of shared data to CXL memory (if demotions are enabled).
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| /linux/Documentation/driver-api/cxl/platform/example-configurations/ |
| H A D | flexible.rst | 6 This system has a single socket with two CXL host bridges. Each host bridge
7 has two CXL memory expanders with a 4GB of memory (32GB total).
23 Subtable Type : 00 [CXL Host Bridge Structure]
32 Subtable Type : 00 [CXL Host Bridge Structure]
41 Subtable Type : 01 [CXL Fixed Memory Window Structure]
56 Subtable Type : 01 [CXL Fixed Memory Window Structure]
70 Subtable Type : 01 [CXL Fixed Memory Window Structure]
84 Subtable Type : 01 [CXL Fixed Memory Window Structure]
98 Subtable Type : 01 [CXL Fixed Memory Window Structure]
112 Subtable Type : 01 [CXL Fixed Memory Window Structure]
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| /linux/include/uapi/cxl/ |
| H A D | features.h | 5 * These are definitions for the mailbox command interface of CXL subsystem.
33 * Get Supported Features (0x500h) CXL r3.2 8.2.9.6.1 command.
42 /* CXL spec r3.2 Table 8-87 command effects */
68 * CXL spec r3.2 Table 8-109
96 * CXL spec r3.2 Table 8-108
109 * Get Feature CXL spec r3.2 Spec 8.2.9.6.2
119 * CXL spec r3.2 section 8.2.9.6.2 Table 8-99
139 * Set Feature CXL spec r3.2 8.2.9.6.3
151 * CXL spec r3.2 section 8.2.9.6.3 Table 8-101
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| /linux/Documentation/driver-api/cxl/platform/ |
| H A D | cdat.rst | 8 as CXL accelerators, switches, or endpoints. The table formatting is
13 DPA - Device Physical Address, used by the CXL device to denote the address
29 attributes of the CXL device itself.
48 performance attributes of a CXL device. The DSLBIS contains latency
60 Entry : 010000000000 <- First byte used here, CXL LTC
70 Entry : 020000000000 <- First byte used here, CXL BW
80 The table is used by Linux to compute the performance coordinates of a CXL path
117 The CXL driver uses a combination of CDAT, HMAT, SRAT, and other data to
118 generate "whole path performance" data for a CXL device.
|