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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.h31 SRI2_DWB(WB_ENABLE, CNV, inst),\
32 SRI2_DWB(WB_EC_CONFIG, CNV, inst),\
33 SRI2_DWB(CNV_MODE, CNV, inst),\
34 SRI2_DWB(CNV_WINDOW_START, CNV, inst),\
35 SRI2_DWB(CNV_WINDOW_SIZE, CNV, inst),\
36 SRI2_DWB(CNV_UPDATE, CNV, inst),\
37 SRI2_DWB(CNV_SOURCE_SIZE, CNV, inst),\
38 SRI2_DWB(CNV_TEST_CNTL, CNV, inst),\
39 SRI2_DWB(CNV_TEST_CRC_RED, CNV, inst),\
40 SRI2_DWB(CNV_TEST_CRC_GREEN, CNV, inst),\
[all …]
H A Ddcn20_dwb.c95 /* Set CNV output pixel depth */ in dwb2_config_dwb_cnv()
120 /* Set CNV parameters */ in dwb2_enable()
140 /* disable CNV */ in dwb2_disable()
172 * Check if the caller has already locked CNV registers. in dwb2_update()
184 /* Set CNV parameters */ in dwb2_update()
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dadi,ad4030.yaml77 cnv-gpios:
79 The Convert Input (CNV). It initiates the sampling conversions.
95 description: PWM signal connected to the CNV pin.
114 - cnv-gpios
168 cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
188 cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
209 cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
H A Dadi,ad4851.yaml60 description: PWM connected to the CNV pin.
/linux/Documentation/admin-guide/blockdev/
H A Dzoned_loop.rst153 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000000
154 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000001
155 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000002
156 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000003
157 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000004
158 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000005
159 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000006
160 -rw-------. 1 root root 67108864 Jan 6 22:23 cnv-000007
/linux/fs/ocfs2/dlm/
H A Ddlmconvert.c433 struct dlm_convert_lock *cnv = (struct dlm_convert_lock *)msg->buf; in dlm_convert_lock_handler() local
450 if (cnv->namelen > DLM_LOCKID_NAME_MAX) { in dlm_convert_lock_handler()
456 flags = be32_to_cpu(cnv->flags); in dlm_convert_lock_handler()
469 res = dlm_lookup_lockres(dlm, cnv->name, cnv->namelen); in dlm_convert_lock_handler()
483 if (tmp_lock->ml.cookie == cnv->cookie && in dlm_convert_lock_handler()
484 tmp_lock->ml.node == cnv->node_idx) { in dlm_convert_lock_handler()
495 dlm_get_lock_cookie_node(be64_to_cpu(cnv->cookie)), in dlm_convert_lock_handler()
496 dlm_get_lock_cookie_seq(be64_to_cpu(cnv->cookie))); in dlm_convert_lock_handler()
508 memcpy(&lksb->lvb[0], &cnv->lvb[0], DLM_LVB_LEN); in dlm_convert_lock_handler()
521 cnv->requested_type, in dlm_convert_lock_handler()
/linux/Documentation/iio/
H A Dad4030.rst82 | CNV |<--------| CNV |
101 | CNV |<-----+--| GPIO |
116 In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required.
117 The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin.
122 nanoseconds after the rising edge of CNV for sample N + 1.
127 delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This
H A Dad4000.rst54 for these devices, comprises of connecting the controller CS line to device CNV
72 | | CNV | | |
97 | | CNV | | |
105 Alternatively, a GPIO may be connected to the device CNV pin. This is similar to
114 | | CNV | | |
126 pin and a GPIO is connected to the ADC CNV pin. This connection mode may better
127 suit scenarios where multiple ADCs can share one CNV trigger.
140 | | CNV | | |
206 controller CS line connected to the CNV pin.
/linux/drivers/iio/adc/
H A Dti-ads1018.c207 * @cnv: ADC Conversion value (optional)
217 static int ads1018_spi_read_exclusive(struct ads1018 *ads1018, __be16 *cnv, in ads1018_spi_read_exclusive() argument
228 if (cnv) in ads1018_spi_read_exclusive()
229 *cnv = ads1018->rx_buf[0]; in ads1018_spi_read_exclusive()
238 * @cnv: Conversion value
248 struct iio_chan_spec const *chan, u16 *cnv) in ads1018_single_shot() argument
285 *cnv = be16_to_cpu(ads1018->rx_buf[0]); in ads1018_single_shot()
299 u16 cnv; in ads1018_read_raw_direct_mode() local
304 ret = ads1018_single_shot(ads1018, chan, &cnv); in ads1018_read_raw_direct_mode()
308 cnv >>= chan->scan_type.shift; in ads1018_read_raw_direct_mode()
[all …]
H A Dad4000.c622 * In 4-wire mode, the CNV line is held high for the entire conversion in ad4000_convert_and_acquire()
623 * and acquisition process. In other modes, the CNV GPIO is optional in ad4000_convert_and_acquire()
624 * and, if provided, replaces controller CS. If CNV GPIO is not defined in ad4000_convert_and_acquire()
883 * device tree property is absent or set to "high". Also, the ADC CNV pin must
922 * connected to MOSI or to VIO and ADC CNV pin is connected either to a SPI
924 * AD4000 series of devices initiate conversions on the rising edge of CNV pin.
926 * If the CNV pin is connected to an SPI controller CS line (which is by default
932 * preparatory transfer to pulse the CS/CNV line.
966 * ADC SDI pin and a GPIO is connected to ADC CNV pin.
967 * The GPIO connected to ADC CNV pin is set outside of the SPI transfer.
[all …]
H A Dad4695.c139 /* currently PWM CNV only supported with SPI offload use */
143 /* offload also requires separate gpio to manually control CNV */
156 * CNV. Excluding the trigger xfer, every 2nd xfer only serves
158 * CNV rising edges.
552 * In this case, CNV is not connected to CS, so we don't need in ad4695_exit_conversion_mode()
977 /* Required delay between last SCLK and CNV/CS */ in ad4695_read_one_sample()
989 * If CNV is connected to CS, the previous function will have triggered in ad4695_read_one_sample()
1008 * If CNV is connected to CS, the previous function will have in ad4695_read_one_sample()
1698 "CNV GPIO is required for SPI offload\n"); in ad4695_probe_spi_offload()
1718 "failed to get CNV PWM\n"); in ad4695_probe_spi_offload()
[all …]
H A Dad7625.c75 * properties for the clk_gate and cnv PWMs
186 * the duty_cycle for ref_clk, cnv, and clk_gate in ad7625_set_sampling_freq()
196 * offset should mirror the CNV signal in ad7625_set_sampling_freq()
429 /* Disable cnv PWM if clk_gate setup failed */ in ad7625_buffer_preenable()
463 st->cnv_pwm = devm_pwm_get(dev, "cnv"); in devm_ad7625_pwm_get()
466 "failed to get cnv pwm\n"); in devm_ad7625_pwm_get()
H A Dad4691.c135 /* CNV burst mode channel — exposes oversampling ratio. */
187 * CNV burst offload configures ACC_DEPTH_IN per channel, so the
484 * CNV Burst Mode - a pre-built SPI message that clocks out 2*N
489 * max 16 + 1 NOOP (manual) or 2*16 + 1 state-reset (CNV burst).
493 * CNV burst: 16 AVG_IN addresses = 16. Manual: 16 channel cmds +
502 * CNV burst state-reset: 4-byte write [addr_hi, addr_lo,
1616 * CNV burst mode: only allow our own trigger (driven by DATA_READY IRQ).
1642 st->conv_trigger = devm_pwm_get(dev, "cnv"); in ad4691_pwm_setup()
1645 "Failed to get CNV PWM\n"); in ad4691_pwm_setup()
1755 * drives the CNV pin (CNV_BURST_MODE); otherwise CNV is tied to CS in ad4691_config()
[all …]
H A Dad4851.c176 struct pwm_device *cnv; member
221 ret = pwm_apply_might_sleep(st->cnv, &cnv_state); in ad4851_set_sampling_freq()
1217 st->cnv = devm_pwm_get(dev, NULL); in ad4851_probe()
1218 if (IS_ERR(st->cnv)) in ad4851_probe()
1219 return dev_err_probe(dev, PTR_ERR(st->cnv), in ad4851_probe()
1235 st->cnv); in ad4851_probe()
H A Dad4080.c767 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable"); in ad4080_properties_parse()
836 clk = devm_clk_get_enabled(&spi->dev, "cnv"); in ad4080_probe()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.h52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
/linux/Documentation/filesystems/
H A Dzonefs.rst88 For conventional zones, the sub-directory "cnv" is used. This directory is
92 such devices, the "cnv" sub-directory will not be created.
97 cannot create other directories and cannot rename nor delete the "cnv" and
108 of zones of a particular type. That is, both the "cnv" and "seq" directories
413 dr-xr-xr-x 2 root root 1 Nov 25 13:23 cnv
421 # ls -l /mnt/cnv
427 # mkfs.ext4 /mnt/cnv/0
428 # mount -o loop /mnt/cnv/0 /data
/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_cnv_dbgfs.c161 * cnv_err_stats_alloc() - Get CNV stats for the provided device.
164 * Allocates and populates table of CNV errors statistics for each non-admin AE
208 "Failed to get CNV stats for ae %ld, [%d].\n", in cnv_err_stats_alloc()
/linux/drivers/block/
H A Dzloop.c1102 zone->file = zloop_filp_open_fmt(oflags, 0600, "%s/%u/cnv-%06u", in zloop_init_zone()
1105 pr_err("Failed to open zone %u file %s/%u/cnv-%06u (err=%ld)", in zloop_init_zone()
1168 struct file *cnv, *seq; in zloop_dev_exists() local
1171 cnv = zloop_filp_open_fmt(O_RDONLY, 0600, "%s/%u/cnv-%06u", in zloop_dev_exists()
1175 exists = !IS_ERR(cnv) || !IS_ERR(seq); in zloop_dev_exists()
1177 if (!IS_ERR(cnv)) in zloop_dev_exists()
1178 fput(cnv); in zloop_dev_exists()
/linux/drivers/platform/x86/intel/telemetry/
H A Ddebugfs.c197 {"CNV", 16},
229 {"CNV", 21},
/linux/fs/zonefs/
H A Dsuper.c38 return "cnv"; in zonefs_zgroup_name()
720 * the "cnv" directory if we have conventional zones. in zonefs_get_dir_inode()
/linux/drivers/net/wireless/intel/iwlwifi/fw/
H A Dfile.h1098 #define IWL_FSEQ_MAGIC "INTEL-CNV-FSEQ\n\0"
/linux/drivers/bluetooth/
H A Dbtintel_pcie.c3039 /* CNV information (CNVi and CNVr) is in CSR */ in btintel_pcie_probe()
/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h10792 * CNV Enums