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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,spmi-clkdiv.txt1 Qualcomm Technologies, Inc. SPMI PMIC clock divider (clkdiv)
3 clkdiv configures the clock frequency of a set of outputs on the PMIC.
11 - compatible
14 Definition: must be "qcom,spmi-clkdiv".
16 - reg
18 Value type: <prop-encoded-array>
19 Definition: base address of CLKDIV peripherals.
21 - qcom,num-clkdivs
24 Definition: number of CLKDIV peripherals.
26 - clocks:
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H A Dqcom,spmi-clkdiv.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,spmi-clkdiv.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Stephen Boyd <sboyd@kernel.org>
20 const: qcom,spmi-clkdiv
27 - description: Board XO source
29 clock-names:
31 - const: xo
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H A Drenesas,emev2-smu.txt10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
24 - #clock-cells: Should be <0>
32 - compatible: Should be "renesas,emev2-smu-gclk"
33 - reg: Byte offset from SMU base and Bit position in the register
34 - clocks: Input clock as described in clock-bindings.txt
35 - #clock-cells: Should be <0>
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H A Dbaikal,bt1-ccu-div.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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H A Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
31 - compatible
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/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Demev2.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
33 compatible = "arm,cortex-a9";
35 clock-frequency = <533000000>;
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/freebsd/sys/arm/ti/
H A Dti_spi.c1 /*-
93 for (i = 0; i < sc->sc_numcs; i++) { in ti_spi_printr()
103 while (j-- > 0) in ti_spi_printr()
108 device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); in ti_spi_printr()
121 uint32_t clkdiv, conf, div, extclk, reg; in ti_spi_set_clock() local
123 clkdiv = TI_SPI_GCLK / freq; in ti_spi_set_clock()
124 if (clkdiv > MCSPI_EXTCLK_MSK) { in ti_spi_set_clock()
126 clkdiv = 0; in ti_spi_set_clock()
128 while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { in ti_spi_set_clock()
129 clkdiv++; in ti_spi_set_clock()
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H A Dti_sdhci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
90 * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x.
93 {"ti,am335-sdhci", 1},
94 {"ti,omap3-hsmmc", 1},
95 {"ti,omap4-hsmmc", 1},
105 * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far
129 /* Forward declarations, CAM-relataed */
138 return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); in ti_mmchs_read_4()
145 bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); in ti_mmchs_write_4()
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/freebsd/sys/dev/iicbus/controller/rockchip/
H A Drk_i2c.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
143 {"rockchip,rk3288-i2c", 1},
144 {"rockchip,rk3328-i2c", 1},
145 {"rockchip,rk3399-i2c", 1},
152 { -1, 0 }
159 #define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx)
160 #define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
161 #define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED)
162 #define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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/freebsd/sys/arm/ti/am335x/
H A Dam335x_ehrpwm.c1 /*-
53 * variable-duty-cycle PWM output.
62 #define PWM_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
63 #define PWM_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
64 #define PWM_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
65 #define PWM_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \
66 device_get_nameunit(_sc->sc_dev), "am335x_ehrpwm softc", MTX_DEF)
67 #define PWM_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
69 #define EPWM_READ2(_sc, reg) bus_read_2((_sc)->sc_mem_res, reg)
71 bus_write_2((_sc)->sc_mem_res, reg, value)
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/freebsd/sys/contrib/device-tree/Bindings/iio/frequency/
H A Dadf4350.txt4 - compatible: Should be one of
7 - reg: SPI chip select numbert for the device
8 - spi-max-frequency: Max SPI frequency to use (< 20000000)
9 - clocks: From common clock binding. Clock is phandle to clock for
13 - gpios: GPIO Lock detect - If set with a valid phandle and GPIO number,
15 - adi,channel-spacing: Channel spacing in Hz (influences MODULUS).
16 - adi,power-up-frequency: If set in Hz the PLL tunes to
18 - adi,reference-div-factor: If set the driver skips dynamic calculation
20 - adi,reference-doubler-enable: Enables reference doubler.
21 - adi,reference-div2-enable: Enables reference divider.
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H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
31 '#clock-cells':
34 clock-output-names:
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/freebsd/sys/contrib/device-tree/src/arc/
H A Dabilis_tb10x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
12 compatible = "abilis,arc-tb10x";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
28 compatible = "snps,arc-timer";
30 interrupt-parent = <&intc>;
36 compatible = "snps,arc-timer";
41 #address-cells = <1>;
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/freebsd/sys/arm/freescale/imx/
H A Dimx_i2c.c1 /*-
2 * Copyright (C) 2008-2009 Semihalf, Michal Hajduk
36 * This driver currently implements only master-mode operations.
38 * This driver supports multi-master i2c buses, by detecting bus arbitration
41 * transfer cycles resulting in arbitration loss in mid-transfer. The caller
112 struct clkdiv { struct
116 static struct clkdiv clkdiv_table[] = { argument
133 {"fsl,imx21-i2c", 1},
134 {"fsl,imx6q-i2c", 1},
135 {"fsl,imx-i2c", 1},
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
/freebsd/sys/dev/bhnd/cores/chipc/
H A Dchipcreg.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 2010-2015 Broadcom Corporation
10 * distributed with the Asus RT-N16 firmware source code release.
77 /* siba backplane configuration broadcast (siba-only) */
81 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */
97 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */
100 /* clock control registers (non-PMU devices) */
114 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* "slowclock" (rev 6-9) */
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/freebsd/tools/tools/cxgbtool/
H A Dreg_defs_t3.c5 /* This file is automatically generated --- do not edit */
1689 { "ClkDiv", 0, 12 },
1702 { "ClkDiv", 5, 8 },
1721 { "ClkDiv", 2, 8 },
H A Dreg_defs_t3b.c4 /* This file is automatically generated --- do not edit */
1759 { "ClkDiv", 0, 12 },
1772 { "ClkDiv", 5, 8 },
1791 { "ClkDiv", 2, 8 },
H A Dreg_defs_t3c.c4 /* This file is automatically generated --- do not edit */
2003 { "ClkDiv", 0, 12 },
2016 { "ClkDiv", 5, 8 },
2035 { "ClkDiv", 2, 8 },
/freebsd/sys/arm/ti/cpsw/
H A Dif_cpsw.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
39 * a 3-port store-and-forward switch connected to two independent
252 { -1, 0 }
331 if ((_sc)->debug) { \
341 mtx_assert(&(sc)->rx.lock, MA_NOTOWNED); \
342 mtx_lock(&(sc)->tx.lock); \
345 #define CPSW_TX_UNLOCK(sc) mtx_unlock(&(sc)->tx.lock)
346 #define CPSW_TX_LOCK_ASSERT(sc) mtx_assert(&(sc)->tx.lock, MA_OWNED)
349 mtx_assert(&(sc)->tx.lock, MA_NOTOWNED); \
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/freebsd/sys/dev/cxgb/common/
H A Dcxgb_t3_hw.c2 SPDX-License-Identifier: BSD-2-Clause
4 Copyright (c) 2007-2009, Chelsio Inc.
38 * t3_wait_op_done_val - wait until an operation is completed
41 * @mask: a single-bit field within @reg that indicates completion
50 * operation completes and -EAGAIN otherwise.
63 if (--attempts == 0) in t3_wait_op_done_val()
64 return -EAGAIN; in t3_wait_op_done_val()
71 * t3_write_regs - write a bunch of registers
84 while (n--) { in t3_write_regs()
85 t3_write_reg(adapter, p->reg_addr + offset, p->val); in t3_write_regs()
[all …]
/freebsd/usr.sbin/cxgbetool/
H A Dreg_defs_t4.c1 /* This file is automatically generated --- changes will be lost */
30708 { "ClkDiv", 5, 8 },
30730 { "ClkDiv", 0, 12 },
H A Dreg_defs_t6.c1 /* This file is automatically generated --- changes will be lost */
38780 { "ClkDiv", 5, 8 },
38802 { "ClkDiv", 0, 12 },
H A Dreg_defs_t5.c1 /* This file is automatically generated --- changes will be lost */
40527 { "ClkDiv", 5, 8 },
40549 { "ClkDiv", 0, 12 },