Lines Matching +full:clkdiv +full:- +full:-
10 - compatible: Should be "renesas,emev2-smu"
11 - reg: Address and Size of SMU registers
21 - compatible: Should be "renesas,emev2-smu-clkdiv"
22 - reg: Byte offset from SMU base and Bit position in the register
23 - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
24 - #clock-cells: Should be <0>
32 - compatible: Should be "renesas,emev2-smu-gclk"
33 - reg: Byte offset from SMU base and Bit position in the register
34 - clocks: Input clock as described in clock-bindings.txt
35 - #clock-cells: Should be <0>
40 compatible = "renesas,emev2-smu-clkdiv";
43 #clock-cells = <0>;
47 compatible = "renesas,emev2-smu-gclk";
50 #clock-cells = <0>;
56 compatible = "renesas,em-uart";
60 clock-names = "sclk";
63 Example of clock-tree description:
66 c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
69 compatible = "renesas,emev2-smu";
71 #address-cells = <2>;
72 #size-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <32768>;
77 #clock-cells = <0>;
80 compatible = "fixed-factor-clock";
82 clock-div = <1>;
83 clock-mult = <7000>;
84 #clock-cells = <0>;
87 compatible = "renesas,emev2-smu-clkdiv";
90 #clock-cells = <0>;
93 compatible = "renesas,emev2-smu-gclk";
96 #clock-cells = <0>;