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/linux/drivers/video/fbdev/via/
H A Daccel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
11 * Figure out an appropriate bytes-per-pixel setting.
13 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
31 printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp); in viafb_set_bpp()
32 return -EINVAL; in viafb_set_bpp()
34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
[all …]
H A Daccel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
30 /* Defines for 2D registers */
56 /* defines for VIA 2D registers for vt3353/3409 (M1 engine)*/
99 /* VIA_REG_GECMD(0x00): 2D Engine Command */
156 /* defines for VIA 3D registers */
163 /* VIA_REG_STATUS(0x400): Engine Status */
167 /* 2D Engine is busy */
169 /* 3D Engine is busy */
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_engine_cs.c1 // SPDX-License-Identifier: GPL-2.0
21 return *a - *b; in cmp_u32()
29 atomic_inc(&gt->rps.num_waiters); in perf_begin()
30 queue_work(gt->i915->unordered_wq, &gt->rps.work); in perf_begin()
31 flush_work(&gt->rps.work); in perf_begin()
38 atomic_dec(&gt->rps.num_waiters); in perf_end()
41 return igt_flush_test(gt->i915); in perf_end()
44 static i915_reg_t timestamp_reg(struct intel_engine_cs *engine) in timestamp_reg() argument
46 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
49 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
[all …]
H A Dselftest_engine_pm.c1 // SPDX-License-Identifier: GPL-2.0
25 return *a - *b; in cmp_u64()
31 return (a[1] + 2 * a[2] + a[3]) >> 2; in trifilter()
76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps() local
77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps()
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
[all …]
H A Dselftest_gt_pm.c1 // SPDX-License-Identifier: MIT
20 return -1; in cmp_u64()
32 return -1; in cmp_u32()
39 static u32 read_timestamp(struct intel_engine_cs *engine) in read_timestamp() argument
41 struct drm_i915_private *i915 = engine->i915; in read_timestamp()
44 ENGINE_READ_FW(engine, RING_TIMESTAMP); in read_timestamp()
47 return ENGINE_READ_FW(engine, RING_TIMESTAMP_UDW); in read_timestamp()
49 return ENGINE_READ_FW(engine, RING_TIMESTAMP); in read_timestamp()
52 static void measure_clocks(struct intel_engine_cs *engine, in measure_clocks() argument
61 cycles[i] = -read_timestamp(engine); in measure_clocks()
[all …]
H A Dselftest_slpc.c1 // SPDX-License-Identifier: MIT
56 struct intel_guc_slpc *slpc = &gt_to_guc(gt)->slpc; in slpc_set_freq()
110 return div_u64(x[1] + 2 * x[2] + x[3], 4); in slpc_measure_power()
120 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
121 *power = slpc_measure_power(&gt->rps, freq); in measure_power_at_freq()
134 step = (slpc->rp0_freq - slpc->min_freq) / NUM_STEPS; in vary_max_freq()
135 *max_act_freq = slpc->min_freq; in vary_max_freq()
136 for (max_freq = slpc->rp0_freq; max_freq > slpc->min_freq; in vary_max_freq()
137 max_freq -= step) { in vary_max_freq()
144 /* GuC requests freq in multiples of 50/3 MHz */ in vary_max_freq()
[all …]
H A Dintel_engine_cs.c1 // SPDX-License-Identifier: MIT
40 * on HSW) - so the final size, including the extra state required for the
52 #define MAX_MMIO_BASES 3
94 .instance = 3,
160 .instance = 3,
217 .instance = 3,
245 .instance = 3,
260 * intel_engine_context_size() - return the size of the context for an engine
262 * @class: engine class
264 * Each engine class may require a different amount of space for a context
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H A Dselftest_hangcheck.c1 // SPDX-License-Identifier: MIT
47 h->gt = gt; in hang_init()
49 h->ctx = kernel_context(gt->i915, NULL); in hang_init()
50 if (IS_ERR(h->ctx)) in hang_init()
51 return PTR_ERR(h->ctx); in hang_init()
53 GEM_BUG_ON(i915_gem_context_is_bannable(h->ctx)); in hang_init()
55 h->hws = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
56 if (IS_ERR(h->hws)) { in hang_init()
57 err = PTR_ERR(h->hws); in hang_init()
61 h->obj = i915_gem_object_create_internal(gt->i915, PAGE_SIZE); in hang_init()
[all …]
H A Dselftest_execlists.c1 // SPDX-License-Identifier: MIT
27 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4) argument
45 static int wait_for_submit(struct intel_engine_cs *engine, in wait_for_submit() argument
50 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
60 intel_engine_flush_submission(engine); in wait_for_submit()
61 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
65 return -ETIME; in wait_for_submit()
71 static int wait_for_reset(struct intel_engine_cs *engine, in wait_for_reset() argument
79 intel_engine_flush_submission(engine); in wait_for_reset()
81 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
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/linux/drivers/soc/qcom/
H A Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
88 #define QCOM_ICE_HWKM_RSP_FIFO_CLEAR_VAL BIT(3)
96 #define qcom_ice_writel(engine, val, reg) \ argument
97 writel((val), (engine)->base + (reg))
99 #define qcom_ice_readl(engine, reg) \ argument
100 readl((engine)->base + (reg))
124 struct device *dev = ice->dev; in qcom_ice_check_supported()
129 /* For now this driver only supports ICE version 3 and 4. */ in qcom_ice_check_supported()
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/linux/drivers/input/misc/
H A Diqs626a.c1 // SPDX-License-Identifier: GPL-2.0+
8 * inductive keys as well as Hall-effect switches, and one for a trackpad that
45 #define IQS626_SYS_SETTINGS_PWR_MODE_MAX 3
58 #define IQS626_MISC_A_ATI_LP_ONLY BIT(3)
63 #define IQS626_EVENT_MASK_GESTURE BIT(3)
76 #define IQS626_MISC_B_RESEED_UI_SEL_MAX 3
79 #define IQS626_MISC_B_TPx_SWIPE BIT(3)
90 #define IQS626_CHx_ENG_0_DUAL_DIR BIT(3)
93 #define IQS626_CHx_ENG_0_ATI_MODE_MAX 3
99 #define IQS626_CHx_ENG_1_PROJ_BIAS_MAX 3
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c33 * DMA engine. The programming model is very similar
34 * to the 3D engine (ring buffer, IBs, etc.), but the
36 * different form the PM4 format used by the 3D engine.
43 * r600_dma_get_rptr - get the current read pointer
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
78 * r600_dma_set_wptr - commit the write pointer
88 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
92 * r600_dma_stop - stop the async dma engine
[all …]
/linux/drivers/crypto/amlogic/
H A Damlogic-gxl-cipher.c1 // SPDX-License-Identifier: GPL-2.0
3 * amlogic-cipher.c - hardware cryptographic offloader for Amlogic GXL SoC
5 * Copyright (C) 2018-2019 Corentin LABBE <clabbe@baylibre.com>
16 #include <linux/dma-mapping.h>
18 #include "amlogic-gxl.h"
22 return atomic_inc_return(&mc->flow) % MAXFLOW; in get_engine_number()
27 struct scatterlist *src_sg = areq->src; in meson_cipher_need_fallback()
28 struct scatterlist *dst_sg = areq->dst; in meson_cipher_need_fallback()
30 if (areq->cryptlen == 0) in meson_cipher_need_fallback()
36 /* KEY/IV descriptors use 3 desc */ in meson_cipher_need_fallback()
[all …]
/linux/arch/powerpc/platforms/powernv/
H A Dopal-hmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
62 "Hypervisor Resource error - core check stop" }, in print_core_checkstop_reason()
74 if (!hmi_evt->u.xstop_error.xstop_reason) { in print_core_checkstop_reason()
80 be32_to_cpu(hmi_evt->u.xstop_error.u.pir)); in print_core_checkstop_reason()
82 if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) & in print_core_checkstop_reason()
84 printk("%s [Unit: %-3s] %s\n", level, in print_core_checkstop_reason()
94 { NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
96 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine", in print_nx_checkstop_reason()
98 { NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine", in print_nx_checkstop_reason()
100 { NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine", in print_nx_checkstop_reason()
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/linux/drivers/video/fbdev/sis/
H A Dsis_accel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * frame buffer driver for Linux kernels >= 2.4.14 and >=2.6.3
8 * 2D acceleration part
11 * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria
13 * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria
28 #define CRITBEGIN spin_lock_irqsave(&ivideo->lockaccel, critflags);
29 #define CRITEND spin_unlock_irqrestore(&ivideo->lockaccel, critflags);
37 /* Definitions for the SIS engine communication. */
43 /* SiS300 engine commands */
52 /* Additional engine commands for 315 */
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/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c24 * Brad Volkin <bradley.d.volkin@intel.com>
57 * some operations that would be noop'd by hardware, if the parser determines
76 * few specific commands on each engine (e.g. PIPE_CONTROL and MI_FLUSH_DW).
79 * Each engine maintains tables of commands and registers which the parser
80 * uses in scanning batch buffers submitted to that engine.
87 * implemented via a per-engine length decoding vfunc.
92 * in the per-engine command tables.
120 #define CMD_DESC_REGISTER (1<<3)
150 * A non-zero step value implies that the command may access multiple
160 #define MAX_CMD_DESC_BITMASKS 3
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dfalcon.c22 #include <engine/falcon.h>
27 #include <engine/fifo.h>
32 struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); in nvkm_falcon_oclass_get()
35 while (falcon->func->sclass[c].oclass) { in nvkm_falcon_oclass_get()
37 oclass->base = falcon->func->sclass[index]; in nvkm_falcon_oclass_get()
49 return nvkm_gpuobj_new(object->engine->subdev.device, 256, in nvkm_falcon_cclass_bind()
59 nvkm_falcon_intr(struct nvkm_engine *engine) in nvkm_falcon_intr() argument
61 struct nvkm_falcon *falcon = nvkm_falcon(engine); in nvkm_falcon_intr()
62 struct nvkm_subdev *subdev = &falcon->engine.subdev; in nvkm_falcon_intr()
63 struct nvkm_device *device = subdev->device; in nvkm_falcon_intr()
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
H A Dnv50.c49 struct nvkm_device *device = pior->disp->engine.subdev.device; in nv50_pior_clock()
58 int ret = nvkm_i2c_aux_lnk_ctl(aux, pior->dp.nr, pior->dp.bw, pior->dp.ef); in nv50_pior_dp_links()
82 struct nvkm_device *device = pior->disp->engine.subdev.device; in nv50_pior_power()
96 /* GF119 moves this information to per-head methods, which is in nv50_pior_depth()
99 if (state->head && state == &ior->asy) { in nv50_pior_depth()
100 struct nvkm_head *head = nvkm_head_find(ior->disp, __ffs(state->head)); in nv50_pior_depth()
103 struct nvkm_head_state *state = &head->asy; in nv50_pior_depth()
105 case 6: state->or.depth = 30; break; in nv50_pior_depth()
106 case 5: state->or.depth = 24; break; in nv50_pior_depth()
107 case 2: state->or.depth = 18; break; in nv50_pior_depth()
[all …]
H A Dgf119.c39 struct nvkm_device *device = ior->disp->engine.subdev.device; in gf119_sor_hda_device_entry()
48 struct nvkm_device *device = ior->disp->engine.subdev.device; in gf119_sor_hda_eld()
49 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_eld()
62 struct nvkm_device *device = ior->disp->engine.subdev.device; in gf119_sor_hda_hpd()
63 const u32 soff = 0x030 * ior->id + (head * 0x04); in gf119_sor_hda_hpd()
68 ior->func->hda->device_entry(ior, head); in gf119_sor_hda_hpd()
87 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_watermark()
96 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio_sym()
106 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_audio()
121 struct nvkm_device *device = sor->disp->engine.subdev.device; in gf119_sor_dp_vcpi()
[all …]
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
27 * NOTE: For engine-registers, GuC only needs the register offsets
28 * from the engine-mmio-base
81 { GEN8_RING_PDP_LDW(0, 3), 0, 0, "PDP3_LDW" }, \
82 { GEN8_RING_PDP_UDW(0, 3), 0, 0, "PDP3_UDW" }
95 { GEN12_SFC_DONE(3), 0, 0, "SFC_DONE[3]" }
104 /* XE_LP Render / Compute Per-Class */
110 /* GEN8+ Render / Compute Per-Engine-Instance */
115 /* GEN8+ Media Decode/Encode Per-Engine-Instance */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/
H A Dgk104.c31 struct nvkm_subdev *subdev = &top->subdev; in gk104_top_parse()
32 struct nvkm_device *device = subdev->device; in gk104_top_parse()
40 return -ENOMEM; in gk104_top_parse()
52 info->addr = (data & 0x00fff000); in gk104_top_parse()
54 info->fault = (data & 0x000003f8) >> 3; in gk104_top_parse()
58 info->engine = (data & 0x3c000000) >> 26; in gk104_top_parse()
60 info->runlist = (data & 0x01e00000) >> 21; in gk104_top_parse()
62 info->intr = (data & 0x000f8000) >> 15; in gk104_top_parse()
64 info->reset = (data & 0x00003e00) >> 9; in gk104_top_parse()
74 /* Translate engine type to NVKM engine identifier. */ in gk104_top_parse()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
H A Dfifo.c22 #include <engine/fifo/priv.h>
23 #include <engine/fifo/cgrp.h>
24 #include <engine/fifo/chan.h>
25 #include <engine/fifo/chid.h>
26 #include <engine/fifo/runl.h>
32 #include <engine/gr.h>
34 #include <rm/engine.h>
39 #include "nvrm/engine.h"
44 struct nvkm_gsp *gsp = chan->rm.object.client->gsp; in r535_chan_doorbell_handle()
46 return gsp->rm->gpu->fifo.chan.doorbell_handle(chan); in r535_chan_doorbell_handle()
[all …]
/linux/drivers/video/fbdev/aty/
H A Dmach64_accel.c1 // SPDX-License-Identifier: GPL-2.0
17 /* this is for DMA GUI engine! work in progress */
42 /* reset engine */ in aty_reset_engine()
46 /* enable engine */ in aty_reset_engine()
49 /* ensure engine is not locked up by clearing any FIFO or */ in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
73 pitch_value = info->fix.line_length / (info->var.bits_per_pixel / 8); in aty_init_engine()
74 vxres = info->var.xres_virtual; in aty_init_engine()
76 if (info->var.bits_per_pixel == 24) { in aty_init_engine()
77 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in aty_init_engine()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgf100.c37 #include <engine/fifo.h>
51 struct nvkm_device *device = gr->base.engine.subdev.device; in gf100_gr_zbc_clear_color()
52 if (gr->zbc_color[zbc].format) { in gf100_gr_zbc_clear_color()
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc; in gf100_gr_zbc_color_get()
68 int zbc = -ENOSPC, i; in gf100_gr_zbc_color_get()
[all …]
/linux/drivers/crypto/marvell/octeontx2/
H A Dotx2_cptpf_ucode.c1 // SPDX-License-Identifier: GPL-2.0-only
38 if (eng_grp->g->engs_num < 0 || in get_cores_bmap()
39 eng_grp->g->engs_num > OTX2_CPT_MAX_ENGINES) { in get_cores_bmap()
40 dev_err(dev, "unsupported number of engines %d on octeontx2\n", in get_cores_bmap()
41 eng_grp->g->engs_num); in get_cores_bmap()
46 if (eng_grp->engs[i].type) { in get_cores_bmap()
48 eng_grp->engs[i].bmap, in get_cores_bmap()
49 eng_grp->g->engs_num); in get_cores_bmap()
50 bmap.size = eng_grp->g->engs_num; in get_cores_bmap()
56 dev_err(dev, "No engines reserved for engine group %d\n", in get_cores_bmap()
[all …]

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