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/linux/drivers/infiniband/hw/irdma/
H A Ddefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2015 - 2021 Intel Corporation */
123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))
141 #define IRDMA_QP_WQE_MIN_SIZE 32
198 IRDMA_OP_MC_DESTROY = 32,
360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])
366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])
375 #define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)
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H A Duda_d.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2016 - 2021 Intel Corporation */
27 #define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32)
28 #define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
41 #define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0)
70 #define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32)
78 #define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32)
83 #define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48)
85 #define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48)
86 #define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32)
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/linux/drivers/staging/rtl8723bs/hal/
H A DHalHWImg8723B_RF.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */ in CheckPositive()
17 ((pDM_Odm->BoardType & BIT3) >> 3) << 1 | /* _GPA */ in CheckPositive()
18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */ in CheckPositive()
19 ((pDM_Odm->BoardType & BIT6) >> 6) << 3 | /* _APA */ in CheckPositive()
20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ in CheckPositive()
24 pDM_Odm->CutVersion << 24 | in CheckPositive()
25 pDM_Odm->SupportPlatform << 16 | in CheckPositive()
26 pDM_Odm->PackageType << 12 | in CheckPositive()
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pip-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
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H A Dcvmx-led-defs.h7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
88 uint64_t reserved_1_63:63;
92 uint64_t reserved_1_63:63;
101 uint64_t reserved_1_63:63;
105 uint64_t reserved_1_63:63;
114 uint64_t reserved_1_63:63;
118 uint64_t reserved_1_63:63;
179 uint64_t reserved_32_63:32;
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_npc_hash.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 (((hdr_ofs) << 32) | ((bytesm1) << 16) | \
104 GENMASK_ULL(63, 0),
105 GENMASK_ULL(63, 0),
108 GENMASK_ULL(63, 0),
109 GENMASK_ULL(63, 0),
115 GENMASK_ULL(63, 0),
116 GENMASK_ULL(63, 0),
119 GENMASK_ULL(63, 0),
120 GENMASK_ULL(63, 0),
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/linux/Documentation/translations/zh_CN/core-api/
H A Dpacking.rst1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8703b_tables.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
19 /* Regd: FCC -> 0, ETSI -> 2, MKK -> 1
20 * Band: 2.4G -> 0, 5G -> 1
21 * Bandwidth (bw): 20M -> 0, 40M -> 1, 80M -> 2, 160M -> 3
22 * Rate Section (rs): CCK -> 0, OFDM -> 1, HT -> 2, VHT -> 3
27 {1, 0, 0, 0, 1, 32},
30 {1, 0, 0, 0, 2, 32},
33 {1, 0, 0, 0, 3, 32},
36 {1, 0, 0, 0, 4, 32},
39 {1, 0, 0, 0, 5, 32},
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H A Drtw8821c_table.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
6026 { 0, 0, 0, 0, 2, 32, },
6029 { 3, 0, 0, 0, 2, 32, },
6032 { 6, 0, 0, 0, 2, 32, },
6034 { 8, 0, 0, 0, 2, 32, },
6038 { 0, 0, 0, 0, 3, 32, },
6041 { 3, 0, 0, 0, 3, 32, },
6044 { 6, 0, 0, 0, 3, 32, },
6046 { 8, 0, 0, 0, 3, 32, },
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dtable.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2010 Realtek Corporation.*/
2899 "ETSI", "2.4G", "20M", "CCK", "1T", "01", "32",
2900 "MKK", "2.4G", "20M", "CCK", "1T", "01", "32",
2902 "ETSI", "2.4G", "20M", "CCK", "1T", "02", "32",
2903 "MKK", "2.4G", "20M", "CCK", "1T", "02", "32",
2905 "ETSI", "2.4G", "20M", "CCK", "1T", "03", "32",
2906 "MKK", "2.4G", "20M", "CCK", "1T", "03", "32",
2908 "ETSI", "2.4G", "20M", "CCK", "1T", "04", "32",
2909 "MKK", "2.4G", "20M", "CCK", "1T", "04", "32",
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/linux/drivers/net/ethernet/ibm/ehea/
H A Dehea_phyp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 * Jan-Bernd Themann <themann@de.ibm.com>
23 while (((1U << ld) - 1) < queue_entries) in get_order_of_qentries()
25 return ld - 1; in get_order_of_qentries()
144 #define H_ALL_RES_QP_RES_TYP EHEA_BMASK_IBM(56, 63)
148 #define H_ALL_RES_QP_PD EHEA_BMASK_IBM(32, 63)
160 #define H_ALL_RES_QP_MAX_R3SGE EHEA_BMASK_IBM(61, 63)
165 #define H_ALL_RES_QP_PORT_NUM EHEA_BMASK_IBM(48, 63)
176 #define H_ALL_RES_QP_ACT_R2WQE EHEA_BMASK_IBM(32, 47)
177 #define H_ALL_RES_QP_ACT_R3WQE EHEA_BMASK_IBM(48, 63)
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/linux/drivers/net/ethernet/sfc/falcon/
H A Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * ef4_dword_t) to be little-endian.
34 #define EF4_DWORD_0_WIDTH 32
35 #define EF4_DWORD_1_LBN 32
36 #define EF4_DWORD_1_WIDTH 32
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/linux/drivers/net/ethernet/sfc/
H A Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * efx_dword_t) to be little-endian.
36 #define EFX_DWORD_0_WIDTH 32
37 #define EFX_DWORD_1_LBN 32
38 #define EFX_DWORD_1_WIDTH 32
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H A Def10_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2012-2017 Solarflare Communications Inc.
13 * E<type>_<min-rev><max-rev>_
18 * -------------------------------------------------------------
23 * <min-rev> is the first revision to which the definition applies:
28 * then <max-rev> is the last revision to which the definition applies;
42 #define ERF_DZ_HW_REV_ID_WIDTH 32
49 #define ERF_DZ_MC_SFT_STATUS_WIDTH 32
54 #define ERF_DZ_ISR_REG_WIDTH 32
59 #define ERF_DZ_MC_DOORBELL_L_WIDTH 32
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/linux/drivers/net/ethernet/sfc/siena/
H A Dbitfield.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
15 * wide. Since there is no native 128-bit datatype on most systems,
16 * and since 64-bit datatypes are inefficient on 32-bit systems and
20 * The NICs are PCI devices and therefore little-endian. Since most
23 * efx_dword_t) to be little-endian.
34 #define EFX_DWORD_0_WIDTH 32
35 #define EFX_DWORD_1_LBN 32
36 #define EFX_DWORD_1_WIDTH 32
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/linux/include/crypto/
H A Dgf128mul.h1 /* gf128mul.h - GF(2^128) multiplication functions
16 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
59 * http://csrc.nist.gov/groups/ST/toolkit/BCM/documents/proposedmodes/gcm/gcm-revised-spec.pdf
61 * The elements of GF(2^128) := GF(2)[X]/(X^128-X^7-X^2-X^1-1) can
73 * in every byte in little-endian order and the bytes themselves also in
74 * little endian order. I will call this lle (little-little-endian).
81 * bytes also. This is bbe (big-big-endian). Now the buffer above
86 * Both of the above formats are easy to implement on big-endian
94 * The common machine word-size is smaller than 128 bits, so to make
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/linux/arch/s390/include/asm/
H A Dnmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define MCIC_SUBCLASS_MASK (1ULL<<63 | 1ULL<<62 | 1ULL<<61 | \
22 #define MCCK_CODE_SYSTEM_DAMAGE BIT(63)
23 #define MCCK_CODE_EXT_DAMAGE BIT(63 - 5)
24 #define MCCK_CODE_CP BIT(63 - 9)
25 #define MCCK_CODE_STG_ERROR BIT(63 - 16)
26 #define MCCK_CODE_STG_KEY_ERROR BIT(63 - 18)
27 #define MCCK_CODE_STG_DEGRAD BIT(63 - 19)
28 #define MCCK_CODE_PSW_MWP_VALID BIT(63 - 20)
29 #define MCCK_CODE_PSW_IA_VALID BIT(63 - 23)
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/linux/include/linux/
H A Dcnt32_to_63.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Extend a 32-bit counter to 63 bits
31 * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
34 * Many hardware clock counters are only 32 bits wide and therefore have
35 * a relatively short period making wrap-arounds rather frequent. This
36 * is a problem when implementing sched_clock() for example, where a 64-bit
37 * non-wrapping monotonic value is expected to be returned.
39 * To overcome that limitation, let's extend a 32-bit counter to 63 bits
41 * by the hardware while bits 32 to 62 are stored in memory. The top bit in
42 * memory is used to synchronize with the hardware clock half-period. When
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/linux/arch/mips/include/asm/
H A Dmsc01_ic.h20 #define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
22 #define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
24 #define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
26 #define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
40 #define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
41 #define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
42 #define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
43 #define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
131 * Soc-it interrupts are configurable.
/linux/drivers/clk/xilinx/
H A Dxlnx_vcu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016 - 2017 Xilinx, Inc.
11 #include <linux/clk-provider.h>
16 #include <linux/mfd/syscon/xlnx-vcu.h>
22 #include <dt-bindings/clock/xlnx-vcu.h>
50 * struct xvcu_device - Xilinx VCU init device structure
73 .reg_bits = 32,
74 .val_bits = 32,
81 * struct xvcu_pll_cfg - Helper data
99 { 25, 3, 10, 3, 63, 1000 },
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/linux/drivers/staging/media/ipu3/
H A Dipu3-tables.c1 // SPDX-License-Identifier: GPL-2.0
4 #include "ipu3-tables.h"
10 /* Scale factor 32 / (32 + 0) = 1 */
22 /* Scale factor 32 / (32 + 1) = 0.969697 */
25 { 0, 0, 122, 7, 7, -1, 0 },
26 { 0, -3, 122, 7, 10, -1, 0 },
27 { 0, -5, 121, 7, 14, -2, 0 },
28 { 0, -7, 120, 7, 18, -3, 0 },
29 { 0, -9, 118, 7, 23, -4, 0 },
30 { 0, -11, 116, 7, 27, -4, 0 },
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/linux/drivers/staging/media/rkvdec/
H A Drkvdec-h264.c1 // SPDX-License-Identifier: GPL-2.0
9 * Jeffy Chen <jeffy.chen@rock-chips.com>
12 #include <media/v4l2-h264.h>
13 #include <media/v4l2-mem2mem.h>
16 #include "rkvdec-regs.h"
83 #define SCALING_LIST_ADDRESS PS_FIELD(184, 32)
86 #define DPB_OFFS(i, j) (288 + ((j) * 32 * 7) + ((i) * 7))
133 /* Table 9-12 – Values of variables m and n for ctxIdx from 0 to 10 */
134 CABAC_ENTRY(0, 20, -15, 20, -15, 20, -15, 20, -15),
137 CABAC_ENTRY(3, 20, -15, 20, -15, 20, -15, 20, -15),
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/linux/arch/x86/include/asm/
H A Damd-ibs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include <asm/msr-index.h>
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
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/linux/tools/arch/x86/include/asm/
H A Damd-ibs.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * 55898 Rev 0.35 - Feb 5, 2021
7 #include "msr-index.h"
33 __u64 fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
34 fetch_cnt:16, /* 16-31: instruction fetch count */
35 fetch_lat:16, /* 32-47: instruction fetch latency */
39 ic_miss:1, /* 51: i-cache miss */
41 l1tlb_pgsz:2, /* 53-54: i-cache L1TLB page size
43 l1tlb_miss:1, /* 55: i-cache fetch missed in L1TLB */
44 l2tlb_miss:1, /* 56: i-cache fetch missed in L2TLB */
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/linux/drivers/crypto/cavium/cpt/
H A Dcpt_hw_types.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
42 * Address must be 16-byte aligned.
43 * Bits <63:49> are ignored by hardware; software should use a
44 * sign-extended bit <48> for forward compatibility.
46 * grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
48 * For the SSO to not discard the add-work request, FPA_PF_MAP() must map
52 * tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
56 * work-queue entry that CPT submits work to SSO after all context,
59 * Bits <63:49> are ignored by hardware; software should
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