Lines Matching +full:32 +full:- +full:63
7 * Copyright (c) 2003-2012 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
74 #define CVMX_PIP_PRT_CFGBX(offset) (CVMX_ADD_IO_SEG(0x00011800A0008000ull) + ((offset) & 63) * 8)
75 #define CVMX_PIP_PRT_CFGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000200ull) + ((offset) & 63) * 8)
76 #define CVMX_PIP_PRT_TAGX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000400ull) + ((offset) & 63) * 8)
77 #define CVMX_PIP_QOS_DIFFX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000600ull) + ((offset) & 63) * 8)
82 #define CVMX_PIP_STAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000800ull) + ((offset) & 63) * 80)
83 #define CVMX_PIP_STAT0_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040000ull) + ((offset) & 63) * 128)
84 #define CVMX_PIP_STAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001480ull) + ((offset) & 63) * 16)
85 #define CVMX_PIP_STAT10_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040050ull) + ((offset) & 63) * 128)
86 #define CVMX_PIP_STAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001488ull) + ((offset) & 63) * 16)
87 #define CVMX_PIP_STAT11_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040058ull) + ((offset) & 63) * 128)
88 #define CVMX_PIP_STAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000808ull) + ((offset) & 63) * 80)
89 #define CVMX_PIP_STAT1_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040008ull) + ((offset) & 63) * 128)
90 #define CVMX_PIP_STAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000810ull) + ((offset) & 63) * 80)
91 #define CVMX_PIP_STAT2_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040010ull) + ((offset) & 63) * 128)
92 #define CVMX_PIP_STAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000818ull) + ((offset) & 63) * 80)
93 #define CVMX_PIP_STAT3_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040018ull) + ((offset) & 63) * 128)
94 #define CVMX_PIP_STAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000820ull) + ((offset) & 63) * 80)
95 #define CVMX_PIP_STAT4_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040020ull) + ((offset) & 63) * 128)
96 #define CVMX_PIP_STAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000828ull) + ((offset) & 63) * 80)
97 #define CVMX_PIP_STAT5_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040028ull) + ((offset) & 63) * 128)
98 #define CVMX_PIP_STAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000830ull) + ((offset) & 63) * 80)
99 #define CVMX_PIP_STAT6_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040030ull) + ((offset) & 63) * 128)
100 #define CVMX_PIP_STAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000838ull) + ((offset) & 63) * 80)
101 #define CVMX_PIP_STAT7_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040038ull) + ((offset) & 63) * 128)
102 #define CVMX_PIP_STAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000840ull) + ((offset) & 63) * 80)
103 #define CVMX_PIP_STAT8_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040040ull) + ((offset) & 63) * 128)
104 #define CVMX_PIP_STAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0000848ull) + ((offset) & 63) * 80)
105 #define CVMX_PIP_STAT9_X(offset) (CVMX_ADD_IO_SEG(0x00011800A0040048ull) + ((offset) & 63) * 128)
107 …ine CVMX_PIP_STAT_INB_ERRSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A10ull) + ((offset) & 63) * 32)
108 …VMX_PIP_STAT_INB_ERRS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020010ull) + ((offset) & 63) * 32)
109 …ine CVMX_PIP_STAT_INB_OCTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A08ull) + ((offset) & 63) * 32)
110 …VMX_PIP_STAT_INB_OCTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020008ull) + ((offset) & 63) * 32)
111 …ine CVMX_PIP_STAT_INB_PKTSX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001A00ull) + ((offset) & 63) * 32)
112 …VMX_PIP_STAT_INB_PKTS_PKNDX(offset) (CVMX_ADD_IO_SEG(0x00011800A0020000ull) + ((offset) & 63) * 32)
114 #define CVMX_PIP_TAG_INCX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001800ull) + ((offset) & 63) * 8)
119 …VMX_PIP_XSTAT0_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002000ull) + ((offset) & 63) * 80 - 80*40)
120 …MX_PIP_XSTAT10_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001700ull) + ((offset) & 63) * 16 - 16*40)
121 …MX_PIP_XSTAT11_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0001708ull) + ((offset) & 63) * 16 - 16*40)
122 …VMX_PIP_XSTAT1_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002008ull) + ((offset) & 63) * 80 - 80*40)
123 …VMX_PIP_XSTAT2_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002010ull) + ((offset) & 63) * 80 - 80*40)
124 …VMX_PIP_XSTAT3_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002018ull) + ((offset) & 63) * 80 - 80*40)
125 …VMX_PIP_XSTAT4_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002020ull) + ((offset) & 63) * 80 - 80*40)
126 …VMX_PIP_XSTAT5_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002028ull) + ((offset) & 63) * 80 - 80*40)
127 …VMX_PIP_XSTAT6_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002030ull) + ((offset) & 63) * 80 - 80*40)
128 …VMX_PIP_XSTAT7_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002038ull) + ((offset) & 63) * 80 - 80*40)
129 …VMX_PIP_XSTAT8_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002040ull) + ((offset) & 63) * 80 - 80*40)
130 …VMX_PIP_XSTAT9_PRTX(offset) (CVMX_ADD_IO_SEG(0x00011800A0002048ull) + ((offset) & 63) * 80 - 80*40)
354 uint64_t reserved_1_63:63;
358 uint64_t reserved_1_63:63;
382 uint64_t reserved_32_63:32;
383 uint64_t iv:32;
385 uint64_t iv:32;
386 uint64_t reserved_32_63:32;
494 uint64_t reserved_32_63:32;
500 uint64_t reserved_32_63:32;
1716 uint64_t reserved_0_31:32;
1718 uint64_t reserved_0_31:32;
2069 uint64_t reserved_1_63:63;
2073 uint64_t reserved_1_63:63;
2082 uint64_t drp_pkts:32;
2083 uint64_t drp_octs:32;
2085 uint64_t drp_octs:32;
2086 uint64_t drp_pkts:32;
2095 uint64_t drp_pkts:32;
2096 uint64_t drp_octs:32;
2098 uint64_t drp_octs:32;
2099 uint64_t drp_pkts:32;
2108 uint64_t bcast:32;
2109 uint64_t mcast:32;
2111 uint64_t mcast:32;
2112 uint64_t bcast:32;
2121 uint64_t bcast:32;
2122 uint64_t mcast:32;
2124 uint64_t mcast:32;
2125 uint64_t bcast:32;
2134 uint64_t bcast:32;
2135 uint64_t mcast:32;
2137 uint64_t mcast:32;
2138 uint64_t bcast:32;
2147 uint64_t bcast:32;
2148 uint64_t mcast:32;
2150 uint64_t mcast:32;
2151 uint64_t bcast:32;
2186 uint64_t pkts:32;
2187 uint64_t raw:32;
2189 uint64_t raw:32;
2190 uint64_t pkts:32;
2199 uint64_t pkts:32;
2200 uint64_t raw:32;
2202 uint64_t raw:32;
2203 uint64_t pkts:32;
2212 uint64_t bcst:32;
2213 uint64_t mcst:32;
2215 uint64_t mcst:32;
2216 uint64_t bcst:32;
2225 uint64_t bcst:32;
2226 uint64_t mcst:32;
2228 uint64_t mcst:32;
2229 uint64_t bcst:32;
2238 uint64_t h65to127:32;
2239 uint64_t h64:32;
2241 uint64_t h64:32;
2242 uint64_t h65to127:32;
2251 uint64_t h65to127:32;
2252 uint64_t h64:32;
2254 uint64_t h64:32;
2255 uint64_t h65to127:32;
2264 uint64_t h256to511:32;
2265 uint64_t h128to255:32;
2267 uint64_t h128to255:32;
2268 uint64_t h256to511:32;
2277 uint64_t h256to511:32;
2278 uint64_t h128to255:32;
2280 uint64_t h128to255:32;
2281 uint64_t h256to511:32;
2290 uint64_t h1024to1518:32;
2291 uint64_t h512to1023:32;
2293 uint64_t h512to1023:32;
2294 uint64_t h1024to1518:32;
2303 uint64_t h1024to1518:32;
2304 uint64_t h512to1023:32;
2306 uint64_t h512to1023:32;
2307 uint64_t h1024to1518:32;
2316 uint64_t fcs:32;
2317 uint64_t h1519:32;
2319 uint64_t h1519:32;
2320 uint64_t fcs:32;
2329 uint64_t fcs:32;
2330 uint64_t h1519:32;
2332 uint64_t h1519:32;
2333 uint64_t fcs:32;
2342 uint64_t frag:32;
2343 uint64_t undersz:32;
2345 uint64_t undersz:32;
2346 uint64_t frag:32;
2355 uint64_t frag:32;
2356 uint64_t undersz:32;
2358 uint64_t undersz:32;
2359 uint64_t frag:32;
2368 uint64_t jabber:32;
2369 uint64_t oversz:32;
2371 uint64_t oversz:32;
2372 uint64_t jabber:32;
2381 uint64_t jabber:32;
2382 uint64_t oversz:32;
2384 uint64_t oversz:32;
2385 uint64_t jabber:32;
2407 uint64_t reserved_1_63:63;
2411 uint64_t reserved_1_63:63;
2472 uint64_t reserved_32_63:32;
2473 uint64_t pkts:32;
2475 uint64_t pkts:32;
2476 uint64_t reserved_32_63:32;
2485 uint64_t reserved_32_63:32;
2486 uint64_t pkts:32;
2488 uint64_t pkts:32;
2489 uint64_t reserved_32_63:32;
2535 uint64_t reserved_32_63:32;
2541 uint64_t reserved_32_63:32;
2582 uint64_t drp_pkts:32;
2583 uint64_t drp_octs:32;
2585 uint64_t drp_octs:32;
2586 uint64_t drp_pkts:32;
2595 uint64_t bcast:32;
2596 uint64_t mcast:32;
2598 uint64_t mcast:32;
2599 uint64_t bcast:32;
2608 uint64_t bcast:32;
2609 uint64_t mcast:32;
2611 uint64_t mcast:32;
2612 uint64_t bcast:32;
2634 uint64_t pkts:32;
2635 uint64_t raw:32;
2637 uint64_t raw:32;
2638 uint64_t pkts:32;
2647 uint64_t bcst:32;
2648 uint64_t mcst:32;
2650 uint64_t mcst:32;
2651 uint64_t bcst:32;
2660 uint64_t h65to127:32;
2661 uint64_t h64:32;
2663 uint64_t h64:32;
2664 uint64_t h65to127:32;
2673 uint64_t h256to511:32;
2674 uint64_t h128to255:32;
2676 uint64_t h128to255:32;
2677 uint64_t h256to511:32;
2686 uint64_t h1024to1518:32;
2687 uint64_t h512to1023:32;
2689 uint64_t h512to1023:32;
2690 uint64_t h1024to1518:32;
2699 uint64_t fcs:32;
2700 uint64_t h1519:32;
2702 uint64_t h1519:32;
2703 uint64_t fcs:32;
2712 uint64_t frag:32;
2713 uint64_t undersz:32;
2715 uint64_t undersz:32;
2716 uint64_t frag:32;
2725 uint64_t jabber:32;
2726 uint64_t oversz:32;
2728 uint64_t oversz:32;
2729 uint64_t jabber:32;