1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-camcc.h> 7#include <dt-bindings/clock/qcom,glymur-dispcc.h> 8#include <dt-bindings/clock/qcom,glymur-evacc.h> 9#include <dt-bindings/clock/qcom,glymur-gcc.h> 10#include <dt-bindings/clock/qcom,glymur-gpucc.h> 11#include <dt-bindings/clock/qcom,glymur-tcsr.h> 12#include <dt-bindings/clock/qcom,glymur-videocc.h> 13#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29#include <dt-bindings/spmi/spmi.h> 30#include <dt-bindings/thermal/thermal.h> 31 32#include "glymur-ipcc.h" 33 34/ { 35 interrupt-parent = <&intc>; 36 #address-cells = <2>; 37 #size-cells = <2>; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu0: cpu@0 { 44 device_type = "cpu"; 45 compatible = "qcom,oryon-2-2"; 46 reg = <0x0 0x0>; 47 enable-method = "psci"; 48 capacity-dmips-mhz = <1024>; 49 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 50 power-domain-names = "psci", "perf"; 51 next-level-cache = <&l2_0>; 52 #cooling-cells = <2>; 53 54 l2_0: l2-cache { 55 compatible = "cache"; 56 cache-level = <2>; 57 cache-unified; 58 }; 59 }; 60 61 cpu1: cpu@100 { 62 device_type = "cpu"; 63 compatible = "qcom,oryon-2-2"; 64 reg = <0x0 0x100>; 65 enable-method = "psci"; 66 capacity-dmips-mhz = <1024>; 67 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 68 power-domain-names = "psci", "perf"; 69 next-level-cache = <&l2_0>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu2: cpu@200 { 74 device_type = "cpu"; 75 compatible = "qcom,oryon-2-2"; 76 reg = <0x0 0x200>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 80 power-domain-names = "psci", "perf"; 81 next-level-cache = <&l2_0>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu3: cpu@300 { 86 device_type = "cpu"; 87 compatible = "qcom,oryon-2-2"; 88 reg = <0x0 0x300>; 89 enable-method = "psci"; 90 capacity-dmips-mhz = <1024>; 91 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 92 power-domain-names = "psci", "perf"; 93 next-level-cache = <&l2_0>; 94 #cooling-cells = <2>; 95 }; 96 97 cpu4: cpu@400 { 98 device_type = "cpu"; 99 compatible = "qcom,oryon-2-2"; 100 reg = <0x0 0x400>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <1024>; 103 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 104 power-domain-names = "psci", "perf"; 105 next-level-cache = <&l2_0>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu5: cpu@500 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon-2-2"; 112 reg = <0x0 0x500>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <1024>; 115 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 116 power-domain-names = "psci", "perf"; 117 next-level-cache = <&l2_0>; 118 #cooling-cells = <2>; 119 }; 120 121 cpu6: cpu@10000 { 122 device_type = "cpu"; 123 compatible = "qcom,oryon-2-1"; 124 reg = <0x0 0x10000>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1372>; 127 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 128 power-domain-names = "psci", "perf"; 129 next-level-cache = <&l2_1>; 130 #cooling-cells = <2>; 131 132 l2_1: l2-cache { 133 compatible = "cache"; 134 cache-level = <2>; 135 cache-unified; 136 }; 137 }; 138 139 cpu7: cpu@10100 { 140 device_type = "cpu"; 141 compatible = "qcom,oryon-2-1"; 142 reg = <0x0 0x10100>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1372>; 145 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 146 power-domain-names = "psci", "perf"; 147 next-level-cache = <&l2_1>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu8: cpu@10200 { 152 device_type = "cpu"; 153 compatible = "qcom,oryon-2-1"; 154 reg = <0x0 0x10200>; 155 enable-method = "psci"; 156 capacity-dmips-mhz = <1372>; 157 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 158 power-domain-names = "psci", "perf"; 159 next-level-cache = <&l2_1>; 160 #cooling-cells = <2>; 161 }; 162 163 cpu9: cpu@10300 { 164 device_type = "cpu"; 165 compatible = "qcom,oryon-2-1"; 166 reg = <0x0 0x10300>; 167 enable-method = "psci"; 168 capacity-dmips-mhz = <1372>; 169 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 170 power-domain-names = "psci", "perf"; 171 next-level-cache = <&l2_1>; 172 #cooling-cells = <2>; 173 }; 174 175 cpu10: cpu@10400 { 176 device_type = "cpu"; 177 compatible = "qcom,oryon-2-1"; 178 reg = <0x0 0x10400>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1372>; 181 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 182 power-domain-names = "psci", "perf"; 183 next-level-cache = <&l2_1>; 184 #cooling-cells = <2>; 185 }; 186 187 cpu11: cpu@10500 { 188 device_type = "cpu"; 189 compatible = "qcom,oryon-2-1"; 190 reg = <0x0 0x10500>; 191 enable-method = "psci"; 192 capacity-dmips-mhz = <1372>; 193 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 194 power-domain-names = "psci", "perf"; 195 next-level-cache = <&l2_1>; 196 #cooling-cells = <2>; 197 }; 198 199 cpu12: cpu@20000 { 200 device_type = "cpu"; 201 compatible = "qcom,oryon-2-1"; 202 reg = <0x0 0x20000>; 203 enable-method = "psci"; 204 capacity-dmips-mhz = <1372>; 205 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 206 power-domain-names = "psci", "perf"; 207 next-level-cache = <&l2_2>; 208 #cooling-cells = <2>; 209 210 l2_2: l2-cache { 211 compatible = "cache"; 212 cache-level = <2>; 213 cache-unified; 214 }; 215 }; 216 217 cpu13: cpu@20100 { 218 device_type = "cpu"; 219 compatible = "qcom,oryon-2-1"; 220 reg = <0x0 0x20100>; 221 enable-method = "psci"; 222 capacity-dmips-mhz = <1372>; 223 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 224 power-domain-names = "psci", "perf"; 225 next-level-cache = <&l2_2>; 226 #cooling-cells = <2>; 227 }; 228 229 cpu14: cpu@20200 { 230 device_type = "cpu"; 231 compatible = "qcom,oryon-2-1"; 232 reg = <0x0 0x20200>; 233 enable-method = "psci"; 234 capacity-dmips-mhz = <1372>; 235 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 236 power-domain-names = "psci", "perf"; 237 next-level-cache = <&l2_2>; 238 #cooling-cells = <2>; 239 }; 240 241 cpu15: cpu@20300 { 242 device_type = "cpu"; 243 compatible = "qcom,oryon-2-1"; 244 reg = <0x0 0x20300>; 245 enable-method = "psci"; 246 capacity-dmips-mhz = <1372>; 247 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 248 power-domain-names = "psci", "perf"; 249 next-level-cache = <&l2_2>; 250 #cooling-cells = <2>; 251 }; 252 253 cpu16: cpu@20400 { 254 device_type = "cpu"; 255 compatible = "qcom,oryon-2-1"; 256 reg = <0x0 0x20400>; 257 enable-method = "psci"; 258 capacity-dmips-mhz = <1372>; 259 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 260 power-domain-names = "psci", "perf"; 261 next-level-cache = <&l2_2>; 262 #cooling-cells = <2>; 263 }; 264 265 cpu17: cpu@20500 { 266 device_type = "cpu"; 267 compatible = "qcom,oryon-2-1"; 268 reg = <0x0 0x20500>; 269 enable-method = "psci"; 270 capacity-dmips-mhz = <1372>; 271 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 272 power-domain-names = "psci", "perf"; 273 next-level-cache = <&l2_2>; 274 #cooling-cells = <2>; 275 }; 276 277 cpu-map { 278 cluster0 { 279 core0 { 280 cpu = <&cpu0>; 281 }; 282 283 core1 { 284 cpu = <&cpu1>; 285 }; 286 287 core2 { 288 cpu = <&cpu2>; 289 }; 290 291 core3 { 292 cpu = <&cpu3>; 293 }; 294 295 core4 { 296 cpu = <&cpu4>; 297 }; 298 299 core5 { 300 cpu = <&cpu5>; 301 }; 302 }; 303 304 cluster1 { 305 core0 { 306 cpu = <&cpu6>; 307 }; 308 309 core1 { 310 cpu = <&cpu7>; 311 }; 312 313 core2 { 314 cpu = <&cpu8>; 315 }; 316 317 core3 { 318 cpu = <&cpu9>; 319 }; 320 321 core4 { 322 cpu = <&cpu10>; 323 }; 324 325 core5 { 326 cpu = <&cpu11>; 327 }; 328 }; 329 330 cpu_map_cluster2: cluster2 { 331 core0 { 332 cpu = <&cpu12>; 333 }; 334 335 core1 { 336 cpu = <&cpu13>; 337 }; 338 339 core2 { 340 cpu = <&cpu14>; 341 }; 342 343 core3 { 344 cpu = <&cpu15>; 345 }; 346 347 core4 { 348 cpu = <&cpu16>; 349 }; 350 351 core5 { 352 cpu = <&cpu17>; 353 }; 354 }; 355 }; 356 357 idle-states { 358 entry-method = "psci"; 359 360 cpu_c4: cpu-sleep-0 { 361 compatible = "arm,idle-state"; 362 idle-state-name = "ret"; 363 arm,psci-suspend-param = <0x00000004>; 364 entry-latency-us = <180>; 365 exit-latency-us = <320>; 366 min-residency-us = <1000>; 367 }; 368 }; 369 370 domain-idle-states { 371 cluster_cl5: cluster-sleep-0 { 372 compatible = "domain-idle-state"; 373 arm,psci-suspend-param = <0x01000054>; 374 entry-latency-us = <2000>; 375 exit-latency-us = <2000>; 376 min-residency-us = <9000>; 377 }; 378 379 domain_ss3: domain-sleep-0 { 380 compatible = "domain-idle-state"; 381 arm,psci-suspend-param = <0x0200c354>; 382 entry-latency-us = <2800>; 383 exit-latency-us = <4400>; 384 min-residency-us = <10150>; 385 }; 386 }; 387 }; 388 389 dummy-sink { 390 compatible = "arm,coresight-dummy-sink"; 391 392 in-ports { 393 port { 394 eud_in: endpoint { 395 remote-endpoint = <&swao_rep_out1>; 396 }; 397 }; 398 }; 399 }; 400 401 firmware { 402 scm: scm { 403 compatible = "qcom,scm-glymur", "qcom,scm"; 404 qcom,dload-mode = <&tcsr 0x4000>; 405 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 406 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 407 }; 408 409 scmi { 410 compatible = "arm,scmi"; 411 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 412 mbox-names = "tx", "rx"; 413 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 414 415 #address-cells = <1>; 416 #size-cells = <0>; 417 418 scmi_perf: protocol@13 { 419 reg = <0x13>; 420 #power-domain-cells = <1>; 421 }; 422 }; 423 }; 424 425 clk_virt: interconnect-0 { 426 compatible = "qcom,glymur-clk-virt"; 427 #interconnect-cells = <2>; 428 qcom,bcm-voters = <&apps_bcm_voter>; 429 }; 430 431 mc_virt: interconnect-1 { 432 compatible = "qcom,glymur-mc-virt"; 433 #interconnect-cells = <2>; 434 qcom,bcm-voters = <&apps_bcm_voter>; 435 }; 436 437 pmu { 438 compatible = "arm,armv8-pmuv3"; 439 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 440 }; 441 442 psci { 443 compatible = "arm,psci-1.0"; 444 method = "smc"; 445 446 cpu_pd0: power-domain-cpu0 { 447 #power-domain-cells = <0>; 448 power-domains = <&cluster0_pd>; 449 domain-idle-states = <&cpu_c4>; 450 }; 451 452 cpu_pd1: power-domain-cpu1 { 453 #power-domain-cells = <0>; 454 power-domains = <&cluster0_pd>; 455 domain-idle-states = <&cpu_c4>; 456 }; 457 458 cpu_pd2: power-domain-cpu2 { 459 #power-domain-cells = <0>; 460 power-domains = <&cluster0_pd>; 461 domain-idle-states = <&cpu_c4>; 462 }; 463 464 cpu_pd3: power-domain-cpu3 { 465 #power-domain-cells = <0>; 466 power-domains = <&cluster0_pd>; 467 domain-idle-states = <&cpu_c4>; 468 }; 469 470 cpu_pd4: power-domain-cpu4 { 471 #power-domain-cells = <0>; 472 power-domains = <&cluster0_pd>; 473 domain-idle-states = <&cpu_c4>; 474 }; 475 476 cpu_pd5: power-domain-cpu5 { 477 #power-domain-cells = <0>; 478 power-domains = <&cluster0_pd>; 479 domain-idle-states = <&cpu_c4>; 480 }; 481 482 cpu_pd6: power-domain-cpu6 { 483 #power-domain-cells = <0>; 484 power-domains = <&cluster1_pd>; 485 domain-idle-states = <&cpu_c4>; 486 }; 487 488 cpu_pd7: power-domain-cpu7 { 489 #power-domain-cells = <0>; 490 power-domains = <&cluster1_pd>; 491 domain-idle-states = <&cpu_c4>; 492 }; 493 494 cpu_pd8: power-domain-cpu8 { 495 #power-domain-cells = <0>; 496 power-domains = <&cluster1_pd>; 497 domain-idle-states = <&cpu_c4>; 498 }; 499 500 cpu_pd9: power-domain-cpu9 { 501 #power-domain-cells = <0>; 502 power-domains = <&cluster1_pd>; 503 domain-idle-states = <&cpu_c4>; 504 }; 505 506 cpu_pd10: power-domain-cpu10 { 507 #power-domain-cells = <0>; 508 power-domains = <&cluster1_pd>; 509 domain-idle-states = <&cpu_c4>; 510 }; 511 512 cpu_pd11: power-domain-cpu11 { 513 #power-domain-cells = <0>; 514 power-domains = <&cluster1_pd>; 515 domain-idle-states = <&cpu_c4>; 516 }; 517 518 cpu_pd12: power-domain-cpu12 { 519 #power-domain-cells = <0>; 520 power-domains = <&cluster2_pd>; 521 domain-idle-states = <&cpu_c4>; 522 }; 523 524 cpu_pd13: power-domain-cpu13 { 525 #power-domain-cells = <0>; 526 power-domains = <&cluster2_pd>; 527 domain-idle-states = <&cpu_c4>; 528 }; 529 530 cpu_pd14: power-domain-cpu14 { 531 #power-domain-cells = <0>; 532 power-domains = <&cluster2_pd>; 533 domain-idle-states = <&cpu_c4>; 534 }; 535 536 cpu_pd15: power-domain-cpu15 { 537 #power-domain-cells = <0>; 538 power-domains = <&cluster2_pd>; 539 domain-idle-states = <&cpu_c4>; 540 }; 541 542 cpu_pd16: power-domain-cpu16 { 543 #power-domain-cells = <0>; 544 power-domains = <&cluster2_pd>; 545 domain-idle-states = <&cpu_c4>; 546 }; 547 548 cpu_pd17: power-domain-cpu17 { 549 #power-domain-cells = <0>; 550 power-domains = <&cluster2_pd>; 551 domain-idle-states = <&cpu_c4>; 552 }; 553 554 cluster0_pd: power-domain-cpu-cluster0 { 555 #power-domain-cells = <0>; 556 power-domains = <&system_pd>; 557 domain-idle-states = <&cluster_cl5>; 558 }; 559 560 cluster1_pd: power-domain-cpu-cluster1 { 561 #power-domain-cells = <0>; 562 power-domains = <&system_pd>; 563 domain-idle-states = <&cluster_cl5>; 564 }; 565 566 cluster2_pd: power-domain-cpu-cluster2 { 567 #power-domain-cells = <0>; 568 power-domains = <&system_pd>; 569 domain-idle-states = <&cluster_cl5>; 570 }; 571 572 system_pd: power-domain-system { 573 #power-domain-cells = <0>; 574 domain-idle-states = <&domain_ss3>; 575 }; 576 }; 577 578 reserved-memory { 579 #address-cells = <2>; 580 #size-cells = <2>; 581 ranges; 582 583 pdp_mem: pdp@81400000 { 584 reg = <0x0 0x81400000 0x0 0x100000>; 585 no-map; 586 }; 587 588 aop_cmd_db_mem: aop-cmd-db@81c60000 { 589 compatible = "qcom,cmd-db"; 590 reg = <0x0 0x81c60000 0x0 0x20000>; 591 no-map; 592 }; 593 594 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 595 reg = <0x0 0x81e00000 0x0 0x200000>; 596 no-map; 597 }; 598 599 oobdaretag_mem: oobdaretag@86e10000 { 600 reg = <0x0 0x86e10000 0x0 0x360000>; 601 no-map; 602 }; 603 604 oob_secure_mem: oob-secure@87170000 { 605 reg = <0x0 0x87170000 0x0 0xbc0000>; 606 no-map; 607 }; 608 609 oobdtbqc_mem: oobdtbqc@87d30000 { 610 reg = <0x0 0x87d30000 0x0 0x20000>; 611 no-map; 612 }; 613 614 oobdtboem_mem: oobdtboem@87d50000 { 615 reg = <0x0 0x87d50000 0x0 0x20000>; 616 no-map; 617 }; 618 619 oob_nonsecure_mem: oob-nonsecure@87e00000 { 620 reg = <0x0 0x87e00000 0x0 0xc00000>; 621 no-map; 622 }; 623 624 spss_region_mem: spss@88a00000 { 625 reg = <0x0 0x88a00000 0x0 0x400000>; 626 no-map; 627 }; 628 629 soccp_mem: soccp@88e00000 { 630 reg = <0x0 0x88e00000 0x0 0x400000>; 631 no-map; 632 }; 633 634 soccpdtb_mem: soccpdtb@89200000 { 635 reg = <0x0 0x89200000 0x0 0x20000>; 636 no-map; 637 }; 638 639 cvp_mem: cvp@89700000 { 640 reg = <0x0 0x89700000 0x0 0x700000>; 641 no-map; 642 }; 643 644 adspslpi_mem: adspslpi@89e00000 { 645 reg = <0x0 0x89e00000 0x0 0x3a00000>; 646 no-map; 647 }; 648 649 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 650 reg = <0x0 0x8d800000 0x0 0x80000>; 651 no-map; 652 }; 653 654 cdsp_mem: cdsp@8d900000 { 655 reg = <0x0 0x8d900000 0x0 0x4000000>; 656 no-map; 657 }; 658 659 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 660 reg = <0x0 0x91900000 0x0 0x80000>; 661 no-map; 662 }; 663 664 gpu_microcode_mem: gpu-microcode@919fe000 { 665 reg = <0x0 0x919fe000 0x0 0x2000>; 666 no-map; 667 }; 668 669 camera_mem: camera@91a00000 { 670 reg = <0x0 0x91a00000 0x0 0x800000>; 671 no-map; 672 }; 673 674 av1_encoder_mem: av1-encoder@92200000 { 675 reg = <0x0 0x92200000 0x0 0x700000>; 676 no-map; 677 }; 678 679 video_mem: video@92900000 { 680 reg = <0x0 0x92900000 0x0 0xc00000>; 681 no-map; 682 }; 683 684 smem_mem: smem@ffe00000 { 685 compatible = "qcom,smem"; 686 reg = <0x0 0xffe00000 0x0 0x200000>; 687 hwlocks = <&tcsr_mutex 3>; 688 no-map; 689 }; 690 691 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { 692 compatible = "shared-dma-pool"; 693 alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; 694 reusable; 695 alignment = <0x0 0x400000>; 696 size = <0x0 0x800000>; 697 }; 698 }; 699 700 smp2p-adsp { 701 compatible = "qcom,smp2p"; 702 703 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 704 IPCC_MPROC_SIGNAL_SMP2P 705 IRQ_TYPE_EDGE_RISING>; 706 707 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 708 709 qcom,smem = <443>, <429>; 710 qcom,local-pid = <0>; 711 qcom,remote-pid = <2>; 712 713 smp2p_adsp_out: master-kernel { 714 qcom,entry-name = "master-kernel"; 715 #qcom,smem-state-cells = <1>; 716 }; 717 718 smp2p_adsp_in: slave-kernel { 719 qcom,entry-name = "slave-kernel"; 720 interrupt-controller; 721 #interrupt-cells = <2>; 722 }; 723 }; 724 725 smp2p-cdsp { 726 compatible = "qcom,smp2p"; 727 728 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 729 IPCC_MPROC_SIGNAL_SMP2P 730 IRQ_TYPE_EDGE_RISING>; 731 732 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 733 734 qcom,smem = <94>, <432>; 735 qcom,local-pid = <0>; 736 qcom,remote-pid = <5>; 737 738 smp2p_cdsp_out: master-kernel { 739 qcom,entry-name = "master-kernel"; 740 #qcom,smem-state-cells = <1>; 741 }; 742 743 smp2p_cdsp_in: slave-kernel { 744 qcom,entry-name = "slave-kernel"; 745 interrupt-controller; 746 #interrupt-cells = <2>; 747 }; 748 }; 749 750 smp2p-soccp { 751 compatible = "qcom,smp2p"; 752 753 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 754 IPCC_MPROC_SIGNAL_SMP2P 755 IRQ_TYPE_EDGE_RISING>; 756 757 mboxes = <&ipcc IPCC_MPROC_SOCCP 758 IPCC_MPROC_SIGNAL_SMP2P>; 759 760 qcom,smem = <617>, <616>; 761 qcom,local-pid = <0>; 762 qcom,remote-pid = <19>; 763 764 soccp_smp2p_out: master-kernel { 765 qcom,entry-name = "master-kernel"; 766 #qcom,smem-state-cells = <1>; 767 }; 768 769 soccp_smp2p_in: slave-kernel { 770 qcom,entry-name = "slave-kernel"; 771 interrupt-controller; 772 #interrupt-cells = <2>; 773 }; 774 }; 775 776 soc: soc@0 { 777 compatible = "simple-bus"; 778 #address-cells = <2>; 779 #size-cells = <2>; 780 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 781 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 782 783 gcc: clock-controller@100000 { 784 compatible = "qcom,glymur-gcc"; 785 reg = <0x0 0x00100000 0x0 0x1f9000>; 786 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 787 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 788 <&sleep_clk>, /* Sleep */ 789 <0>, /* USB 0 Phy DP0 GMUX */ 790 <0>, /* USB 0 Phy DP1 GMUX */ 791 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 792 <0>, /* USB 0 Phy PIPEGMUX */ 793 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 794 <0>, /* USB 1 Phy DP0 GMUX 2 */ 795 <0>, /* USB 1 Phy DP1 GMUX 2 */ 796 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 797 <0>, /* USB 1 Phy PIPEGMUX */ 798 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 799 <0>, /* USB 2 Phy DP0 GMUX 2 */ 800 <0>, /* USB 2 Phy DP1 GMUX 2 */ 801 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 802 <0>, /* USB 2 Phy PIPEGMUX */ 803 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 804 <0>, /* PCIe 3a */ 805 <0>, /* PCIe 3b */ 806 <&pcie4_phy>, /* PCIe 4 */ 807 <&pcie5_phy>, /* PCIe 5 */ 808 <&pcie6_phy>, /* PCIe 6 */ 809 <0>, /* QUSB4 0 PHY RX 0 */ 810 <0>, /* QUSB4 0 PHY RX 1 */ 811 <0>, /* QUSB4 1 PHY RX 0 */ 812 <0>, /* QUSB4 1 PHY RX 1 */ 813 <0>, /* QUSB4 2 PHY RX 0 */ 814 <0>, /* QUSB4 2 PHY RX 1 */ 815 <0>, /* UFS PHY RX Symbol 0 */ 816 <0>, /* UFS PHY RX Symbol 1 */ 817 <0>, /* UFS PHY TX Symbol 0 */ 818 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 819 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 820 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 821 <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */ 822 <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */ 823 <0>, /* USB4 PHY 0 pcie pipe */ 824 <0>, /* USB4 PHY 0 Max pipe */ 825 <0>, /* USB4 PHY 1 pcie pipe */ 826 <0>, /* USB4 PHY 1 Max pipe */ 827 <0>, /* USB4 PHY 2 pcie */ 828 <0>; /* USB4 PHY 2 Max */ 829 #clock-cells = <1>; 830 #reset-cells = <1>; 831 #power-domain-cells = <1>; 832 power-domains = <&rpmhpd RPMHPD_CX>; 833 }; 834 835 gpi_dma2: dma-controller@800000 { 836 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 837 reg = <0x0 0x00800000 0x0 0x60000>; 838 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 854 dma-channels = <16>; 855 dma-channel-mask = <0x3f>; 856 #dma-cells = <3>; 857 iommus = <&apps_smmu 0xd76 0x0>; 858 }; 859 860 qupv3_2: geniqup@8c0000 { 861 compatible = "qcom,geni-se-qup"; 862 reg = <0x0 0x008c0000 0x0 0x3000>; 863 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 864 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 865 clock-names = "m-ahb", 866 "s-ahb"; 867 iommus = <&apps_smmu 0xd63 0x0>; 868 #address-cells = <2>; 869 #size-cells = <2>; 870 ranges; 871 872 i2c16: i2c@880000 { 873 compatible = "qcom,geni-i2c"; 874 reg = <0x0 0x00880000 0x0 0x4000>; 875 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 877 clock-names = "se"; 878 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 879 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 880 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 881 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 882 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 883 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 884 interconnect-names = "qup-core", 885 "qup-config", 886 "qup-memory"; 887 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 888 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 889 dma-names = "tx", 890 "rx"; 891 pinctrl-0 = <&qup_i2c16_data_clk>; 892 pinctrl-names = "default"; 893 #address-cells = <1>; 894 #size-cells = <0>; 895 896 status = "disabled"; 897 }; 898 899 spi16: spi@880000 { 900 compatible = "qcom,geni-spi"; 901 reg = <0x0 0x00880000 0x0 0x4000>; 902 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 904 clock-names = "se"; 905 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 906 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 907 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 908 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 909 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 910 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 911 interconnect-names = "qup-core", 912 "qup-config", 913 "qup-memory"; 914 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 915 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 916 dma-names = "tx", 917 "rx"; 918 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 919 pinctrl-names = "default"; 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 status = "disabled"; 924 }; 925 926 i2c17: i2c@884000 { 927 compatible = "qcom,geni-i2c"; 928 reg = <0x0 0x00884000 0x0 0x4000>; 929 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 931 clock-names = "se"; 932 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 933 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 934 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 935 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 936 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 937 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 938 interconnect-names = "qup-core", 939 "qup-config", 940 "qup-memory"; 941 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 942 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 943 dma-names = "tx", 944 "rx"; 945 pinctrl-0 = <&qup_i2c17_data_clk>; 946 pinctrl-names = "default"; 947 #address-cells = <1>; 948 #size-cells = <0>; 949 950 status = "disabled"; 951 }; 952 953 spi17: spi@884000 { 954 compatible = "qcom,geni-spi"; 955 reg = <0x0 0x00884000 0x0 0x4000>; 956 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 958 clock-names = "se"; 959 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 960 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 961 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 962 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 963 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 964 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 965 interconnect-names = "qup-core", 966 "qup-config", 967 "qup-memory"; 968 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 969 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 970 dma-names = "tx", 971 "rx"; 972 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 973 pinctrl-names = "default"; 974 #address-cells = <1>; 975 #size-cells = <0>; 976 977 status = "disabled"; 978 }; 979 980 i2c18: i2c@888000 { 981 compatible = "qcom,geni-i2c"; 982 reg = <0x0 0x00888000 0x0 0x4000>; 983 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 985 clock-names = "se"; 986 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 987 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 988 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 989 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 990 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 991 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 992 interconnect-names = "qup-core", 993 "qup-config", 994 "qup-memory"; 995 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 996 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 997 dma-names = "tx", 998 "rx"; 999 pinctrl-0 = <&qup_i2c18_data_clk>; 1000 pinctrl-names = "default"; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 1004 status = "disabled"; 1005 }; 1006 1007 spi18: spi@888000 { 1008 compatible = "qcom,geni-spi"; 1009 reg = <0x0 0x00888000 0x0 0x4000>; 1010 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1011 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1012 clock-names = "se"; 1013 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1014 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1015 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1016 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1017 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1018 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1019 interconnect-names = "qup-core", 1020 "qup-config", 1021 "qup-memory"; 1022 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1023 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1024 dma-names = "tx", 1025 "rx"; 1026 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1027 pinctrl-names = "default"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 1031 status = "disabled"; 1032 }; 1033 1034 i2c19: i2c@88c000 { 1035 compatible = "qcom,geni-i2c"; 1036 reg = <0x0 0x0088c000 0x0 0x4000>; 1037 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1038 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1039 clock-names = "se"; 1040 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1041 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1042 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1043 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1044 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1045 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1046 interconnect-names = "qup-core", 1047 "qup-config", 1048 "qup-memory"; 1049 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1050 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1051 dma-names = "tx", 1052 "rx"; 1053 pinctrl-0 = <&qup_i2c19_data_clk>; 1054 pinctrl-names = "default"; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 1058 status = "disabled"; 1059 }; 1060 1061 spi19: spi@88c000 { 1062 compatible = "qcom,geni-spi"; 1063 reg = <0x0 0x0088c000 0x0 0x4000>; 1064 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1066 clock-names = "se"; 1067 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1068 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1069 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1070 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1071 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1073 interconnect-names = "qup-core", 1074 "qup-config", 1075 "qup-memory"; 1076 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1077 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1078 dma-names = "tx", 1079 "rx"; 1080 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1081 pinctrl-names = "default"; 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 status = "disabled"; 1086 }; 1087 1088 uart19: serial@88c000 { 1089 compatible = "qcom,geni-uart"; 1090 reg = <0x0 0x0088c000 0x0 0x4000>; 1091 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1092 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1093 clock-names = "se"; 1094 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1096 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1097 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1098 interconnect-names = "qup-core", 1099 "qup-config"; 1100 pinctrl-0 = <&qup_uart19_default>; 1101 pinctrl-names = "default"; 1102 1103 status = "disabled"; 1104 }; 1105 1106 i2c20: i2c@890000 { 1107 compatible = "qcom,geni-i2c"; 1108 reg = <0x0 0x00890000 0x0 0x4000>; 1109 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1111 clock-names = "se"; 1112 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1113 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1114 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1115 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1116 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1117 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1118 interconnect-names = "qup-core", 1119 "qup-config", 1120 "qup-memory"; 1121 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1122 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1123 dma-names = "tx", 1124 "rx"; 1125 pinctrl-0 = <&qup_i2c20_data_clk>; 1126 pinctrl-names = "default"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 1130 status = "disabled"; 1131 }; 1132 1133 spi20: spi@890000 { 1134 compatible = "qcom,geni-spi"; 1135 reg = <0x0 0x00890000 0x0 0x4000>; 1136 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1138 clock-names = "se"; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1140 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1141 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1142 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1143 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1144 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1145 interconnect-names = "qup-core", 1146 "qup-config", 1147 "qup-memory"; 1148 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1149 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1150 dma-names = "tx", 1151 "rx"; 1152 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1153 pinctrl-names = "default"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 1157 status = "disabled"; 1158 }; 1159 1160 i2c21: i2c@894000 { 1161 compatible = "qcom,geni-i2c"; 1162 reg = <0x0 0x00894000 0x0 0x4000>; 1163 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1164 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1165 clock-names = "se"; 1166 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1167 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1168 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1169 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1170 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1172 interconnect-names = "qup-core", 1173 "qup-config", 1174 "qup-memory"; 1175 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1176 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1177 dma-names = "tx", 1178 "rx"; 1179 pinctrl-0 = <&qup_i2c21_data_clk>; 1180 pinctrl-names = "default"; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 1184 status = "disabled"; 1185 }; 1186 1187 spi21: spi@894000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0x0 0x00894000 0x0 0x4000>; 1190 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1191 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1192 clock-names = "se"; 1193 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1194 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1195 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1196 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1197 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1198 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1199 interconnect-names = "qup-core", 1200 "qup-config", 1201 "qup-memory"; 1202 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1203 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1204 dma-names = "tx", 1205 "rx"; 1206 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1207 pinctrl-names = "default"; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 1211 status = "disabled"; 1212 }; 1213 1214 uart21: serial@894000 { 1215 compatible = "qcom,geni-debug-uart"; 1216 reg = <0x0 0x00894000 0x0 0x4000>; 1217 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1218 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1219 clock-names = "se"; 1220 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1221 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1222 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1223 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1224 interconnect-names = "qup-core", 1225 "qup-config"; 1226 pinctrl-0 = <&qup_uart21_default>; 1227 pinctrl-names = "default"; 1228 }; 1229 1230 i2c22: i2c@898000 { 1231 compatible = "qcom,geni-i2c"; 1232 reg = <0x0 0x00898000 0x0 0x4000>; 1233 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1235 clock-names = "se"; 1236 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1238 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1240 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1241 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1242 interconnect-names = "qup-core", 1243 "qup-config", 1244 "qup-memory"; 1245 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1246 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1247 dma-names = "tx", 1248 "rx"; 1249 pinctrl-0 = <&qup_i2c22_data_clk>; 1250 pinctrl-names = "default"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 1254 status = "disabled"; 1255 }; 1256 1257 spi22: spi@898000 { 1258 compatible = "qcom,geni-spi"; 1259 reg = <0x0 0x00898000 0x0 0x4000>; 1260 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1262 clock-names = "se"; 1263 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1265 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1266 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1267 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1268 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1269 interconnect-names = "qup-core", 1270 "qup-config", 1271 "qup-memory"; 1272 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1273 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1274 dma-names = "tx", 1275 "rx"; 1276 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1277 pinctrl-names = "default"; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 1281 status = "disabled"; 1282 }; 1283 1284 uart22: serial@898000 { 1285 compatible = "qcom,geni-uart"; 1286 reg = <0x0 0x00898000 0x0 0x4000>; 1287 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1289 clock-names = "se"; 1290 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1291 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1292 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1293 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1294 interconnect-names = "qup-core", 1295 "qup-config"; 1296 pinctrl-0 = <&qup_uart22_default>; 1297 pinctrl-names = "default"; 1298 1299 status = "disabled"; 1300 }; 1301 1302 i2c23: i2c@89c000 { 1303 compatible = "qcom,geni-i2c"; 1304 reg = <0x0 0x0089c000 0x0 0x4000>; 1305 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1306 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1307 clock-names = "se"; 1308 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1309 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1310 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1311 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1312 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1313 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1314 interconnect-names = "qup-core", 1315 "qup-config", 1316 "qup-memory"; 1317 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1318 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1319 dma-names = "tx", 1320 "rx"; 1321 pinctrl-0 = <&qup_i2c23_data_clk>; 1322 pinctrl-names = "default"; 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 status = "disabled"; 1327 }; 1328 1329 spi23: spi@89c000 { 1330 compatible = "qcom,geni-spi"; 1331 reg = <0x0 0x0089c000 0x0 0x4000>; 1332 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1333 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1334 clock-names = "se"; 1335 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1336 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1337 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1338 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1339 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1340 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1341 interconnect-names = "qup-core", 1342 "qup-config", 1343 "qup-memory"; 1344 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1345 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1346 dma-names = "tx", 1347 "rx"; 1348 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1349 pinctrl-names = "default"; 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 status = "disabled"; 1354 }; 1355 }; 1356 1357 gpi_dma1: dma-controller@a00000 { 1358 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1359 reg = <0x0 0x00a00000 0x0 0x60000>; 1360 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1376 dma-channels = <16>; 1377 dma-channel-mask = <0x3f>; 1378 #dma-cells = <3>; 1379 iommus = <&apps_smmu 0xcb6 0x0>; 1380 }; 1381 1382 qupv3_1: geniqup@ac0000 { 1383 compatible = "qcom,geni-se-qup"; 1384 reg = <0x0 0x00ac0000 0x0 0x3000>; 1385 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1386 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1387 clock-names = "m-ahb", 1388 "s-ahb"; 1389 iommus = <&apps_smmu 0xca3 0x0>; 1390 #address-cells = <2>; 1391 #size-cells = <2>; 1392 ranges; 1393 1394 i2c8: i2c@a80000 { 1395 compatible = "qcom,geni-i2c"; 1396 reg = <0x0 0x00a80000 0x0 0x4000>; 1397 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1399 clock-names = "se"; 1400 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1401 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1402 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1403 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1404 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1405 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1406 interconnect-names = "qup-core", 1407 "qup-config", 1408 "qup-memory"; 1409 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1410 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1411 dma-names = "tx", 1412 "rx"; 1413 pinctrl-0 = <&qup_i2c8_data_clk>; 1414 pinctrl-names = "default"; 1415 #address-cells = <1>; 1416 #size-cells = <0>; 1417 1418 status = "disabled"; 1419 }; 1420 1421 spi8: spi@a80000 { 1422 compatible = "qcom,geni-spi"; 1423 reg = <0x0 0x00a80000 0x0 0x4000>; 1424 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1425 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1426 clock-names = "se"; 1427 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1428 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1429 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1430 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1431 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1432 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1433 interconnect-names = "qup-core", 1434 "qup-config", 1435 "qup-memory"; 1436 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1437 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1438 dma-names = "tx", 1439 "rx"; 1440 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1441 pinctrl-names = "default"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 1445 status = "disabled"; 1446 }; 1447 1448 i2c9: i2c@a84000 { 1449 compatible = "qcom,geni-i2c"; 1450 reg = <0x0 0x00a84000 0x0 0x4000>; 1451 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1453 clock-names = "se"; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1455 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1456 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1457 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1458 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1459 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1460 interconnect-names = "qup-core", 1461 "qup-config", 1462 "qup-memory"; 1463 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1464 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1465 dma-names = "tx", 1466 "rx"; 1467 pinctrl-0 = <&qup_i2c9_data_clk>; 1468 pinctrl-names = "default"; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 1472 status = "disabled"; 1473 }; 1474 1475 spi9: spi@a84000 { 1476 compatible = "qcom,geni-spi"; 1477 reg = <0x0 0x00a84000 0x0 0x4000>; 1478 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1479 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1480 clock-names = "se"; 1481 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1482 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1483 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1484 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1485 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1486 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1487 interconnect-names = "qup-core", 1488 "qup-config", 1489 "qup-memory"; 1490 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1491 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1492 dma-names = "tx", 1493 "rx"; 1494 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1495 pinctrl-names = "default"; 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 1499 status = "disabled"; 1500 }; 1501 1502 i2c10: i2c@a88000 { 1503 compatible = "qcom,geni-i2c"; 1504 reg = <0x0 0x00a88000 0x0 0x4000>; 1505 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1507 clock-names = "se"; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1510 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1511 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1512 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1513 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1514 interconnect-names = "qup-core", 1515 "qup-config", 1516 "qup-memory"; 1517 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1518 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1519 dma-names = "tx", 1520 "rx"; 1521 pinctrl-0 = <&qup_i2c10_data_clk>; 1522 pinctrl-names = "default"; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 1526 status = "disabled"; 1527 }; 1528 1529 spi10: spi@a88000 { 1530 compatible = "qcom,geni-spi"; 1531 reg = <0x0 0x00a88000 0x0 0x4000>; 1532 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1534 clock-names = "se"; 1535 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1536 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1537 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1538 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1539 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1540 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1541 interconnect-names = "qup-core", 1542 "qup-config", 1543 "qup-memory"; 1544 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1545 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1546 dma-names = "tx", 1547 "rx"; 1548 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1549 pinctrl-names = "default"; 1550 #address-cells = <1>; 1551 #size-cells = <0>; 1552 1553 status = "disabled"; 1554 }; 1555 1556 i2c11: i2c@a8c000 { 1557 compatible = "qcom,geni-i2c"; 1558 reg = <0x0 0x00a8c000 0x0 0x4000>; 1559 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1560 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1561 clock-names = "se"; 1562 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1563 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1564 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1565 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1566 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1567 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1568 interconnect-names = "qup-core", 1569 "qup-config", 1570 "qup-memory"; 1571 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1572 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1573 dma-names = "tx", 1574 "rx"; 1575 pinctrl-0 = <&qup_i2c11_data_clk>; 1576 pinctrl-names = "default"; 1577 #address-cells = <1>; 1578 #size-cells = <0>; 1579 1580 status = "disabled"; 1581 }; 1582 1583 spi11: spi@a8c000 { 1584 compatible = "qcom,geni-spi"; 1585 reg = <0x0 0x00a8c000 0x0 0x4000>; 1586 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1587 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1588 clock-names = "se"; 1589 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1590 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1591 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1592 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1593 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1594 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1595 interconnect-names = "qup-core", 1596 "qup-config", 1597 "qup-memory"; 1598 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1599 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1600 dma-names = "tx", 1601 "rx"; 1602 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1603 pinctrl-names = "default"; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 1607 status = "disabled"; 1608 }; 1609 1610 i2c12: i2c@a90000 { 1611 compatible = "qcom,geni-i2c"; 1612 reg = <0x0 0x00a90000 0x0 0x4000>; 1613 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1615 clock-names = "se"; 1616 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1617 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1618 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1619 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1620 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1622 interconnect-names = "qup-core", 1623 "qup-config", 1624 "qup-memory"; 1625 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1626 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1627 dma-names = "tx", 1628 "rx"; 1629 pinctrl-0 = <&qup_i2c12_data_clk>; 1630 pinctrl-names = "default"; 1631 #address-cells = <1>; 1632 #size-cells = <0>; 1633 1634 status = "disabled"; 1635 }; 1636 1637 spi12: spi@a90000 { 1638 compatible = "qcom,geni-spi"; 1639 reg = <0x0 0x00a90000 0x0 0x4000>; 1640 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1641 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1642 clock-names = "se"; 1643 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1644 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1645 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1646 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1647 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1649 interconnect-names = "qup-core", 1650 "qup-config", 1651 "qup-memory"; 1652 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1653 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1654 dma-names = "tx", 1655 "rx"; 1656 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1657 pinctrl-names = "default"; 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 1661 status = "disabled"; 1662 }; 1663 1664 i2c13: i2c@a94000 { 1665 compatible = "qcom,geni-i2c"; 1666 reg = <0x0 0x00a94000 0x0 0x4000>; 1667 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1669 clock-names = "se"; 1670 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1671 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1672 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1673 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1674 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1675 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1676 interconnect-names = "qup-core", 1677 "qup-config", 1678 "qup-memory"; 1679 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1680 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1681 dma-names = "tx", 1682 "rx"; 1683 pinctrl-0 = <&qup_i2c13_data_clk>; 1684 pinctrl-names = "default"; 1685 #address-cells = <1>; 1686 #size-cells = <0>; 1687 1688 status = "disabled"; 1689 }; 1690 1691 spi13: spi@a94000 { 1692 compatible = "qcom,geni-spi"; 1693 reg = <0x0 0x00a94000 0x0 0x4000>; 1694 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1695 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1696 clock-names = "se"; 1697 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1698 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1699 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1700 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1701 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1702 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1703 interconnect-names = "qup-core", 1704 "qup-config", 1705 "qup-memory"; 1706 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1707 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1708 dma-names = "tx", 1709 "rx"; 1710 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1711 pinctrl-names = "default"; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 status = "disabled"; 1716 }; 1717 1718 i2c14: i2c@a98000 { 1719 compatible = "qcom,geni-i2c"; 1720 reg = <0x0 0x00a98000 0x0 0x4000>; 1721 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1722 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1723 clock-names = "se"; 1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1725 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1726 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1727 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1728 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1729 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1730 interconnect-names = "qup-core", 1731 "qup-config", 1732 "qup-memory"; 1733 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1734 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1735 dma-names = "tx", 1736 "rx"; 1737 pinctrl-0 = <&qup_i2c14_data_clk>; 1738 pinctrl-names = "default"; 1739 #address-cells = <1>; 1740 #size-cells = <0>; 1741 1742 status = "disabled"; 1743 }; 1744 1745 spi14: spi@a98000 { 1746 compatible = "qcom,geni-spi"; 1747 reg = <0x0 0x00a98000 0x0 0x4000>; 1748 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1749 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1750 clock-names = "se"; 1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1752 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1753 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1754 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1755 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1756 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1757 interconnect-names = "qup-core", 1758 "qup-config", 1759 "qup-memory"; 1760 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1761 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1762 dma-names = "tx", 1763 "rx"; 1764 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1765 pinctrl-names = "default"; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 1769 status = "disabled"; 1770 }; 1771 1772 uart14: serial@a98000 { 1773 compatible = "qcom,geni-uart"; 1774 reg = <0x0 0x00a98000 0x0 0x4000>; 1775 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1776 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1777 clock-names = "se"; 1778 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1779 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1780 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1781 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1782 interconnect-names = "qup-core", 1783 "qup-config"; 1784 pinctrl-0 = <&qup_uart14_default>; 1785 pinctrl-names = "default"; 1786 1787 status = "disabled"; 1788 }; 1789 1790 i2c15: i2c@a9c000 { 1791 compatible = "qcom,geni-i2c"; 1792 reg = <0x0 0x00a9c000 0x0 0x4000>; 1793 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1794 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1795 clock-names = "se"; 1796 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1797 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1798 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1799 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1800 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1801 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1802 interconnect-names = "qup-core", 1803 "qup-config", 1804 "qup-memory"; 1805 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1806 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1807 dma-names = "tx", 1808 "rx"; 1809 pinctrl-0 = <&qup_i2c15_data_clk>; 1810 pinctrl-names = "default"; 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 1814 status = "disabled"; 1815 }; 1816 1817 spi15: spi@a9c000 { 1818 compatible = "qcom,geni-spi"; 1819 reg = <0x0 0x00a9c000 0x0 0x4000>; 1820 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1822 clock-names = "se"; 1823 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1824 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1825 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1826 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1827 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1828 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1829 interconnect-names = "qup-core", 1830 "qup-config", 1831 "qup-memory"; 1832 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1833 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1834 dma-names = "tx", 1835 "rx"; 1836 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1837 pinctrl-names = "default"; 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 1841 status = "disabled"; 1842 }; 1843 }; 1844 1845 gpi_dma0: dma-controller@b00000 { 1846 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1847 reg = <0x0 0x00b00000 0x0 0x60000>; 1848 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1863 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1864 dma-channels = <16>; 1865 dma-channel-mask = <0x3f>; 1866 #dma-cells = <3>; 1867 iommus = <&apps_smmu 0xd36 0x0>; 1868 }; 1869 1870 qupv3_0: geniqup@bc0000 { 1871 compatible = "qcom,geni-se-qup"; 1872 reg = <0x0 0x00bc0000 0x0 0x3000>; 1873 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1874 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1875 clock-names = "m-ahb", 1876 "s-ahb"; 1877 iommus = <&apps_smmu 0xd23 0x0>; 1878 #address-cells = <2>; 1879 #size-cells = <2>; 1880 ranges; 1881 1882 i2c0: i2c@b80000 { 1883 compatible = "qcom,geni-i2c"; 1884 reg = <0x0 0x00b80000 0x0 0x4000>; 1885 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1886 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1887 clock-names = "se"; 1888 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1889 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1890 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1891 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1892 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1893 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1894 interconnect-names = "qup-core", 1895 "qup-config", 1896 "qup-memory"; 1897 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1898 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1899 dma-names = "tx", 1900 "rx"; 1901 pinctrl-0 = <&qup_i2c0_data_clk>; 1902 pinctrl-names = "default"; 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 1906 status = "disabled"; 1907 }; 1908 1909 spi0: spi@b80000 { 1910 compatible = "qcom,geni-spi"; 1911 reg = <0x0 0x00b80000 0x0 0x4000>; 1912 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1913 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1914 clock-names = "se"; 1915 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1916 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1917 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1918 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1919 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1920 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1921 interconnect-names = "qup-core", 1922 "qup-config", 1923 "qup-memory"; 1924 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1925 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1926 dma-names = "tx", 1927 "rx"; 1928 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1929 pinctrl-names = "default"; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 1933 status = "disabled"; 1934 }; 1935 1936 i2c1: i2c@b84000 { 1937 compatible = "qcom,geni-i2c"; 1938 reg = <0x0 0x00b84000 0x0 0x4000>; 1939 interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1941 clock-names = "se"; 1942 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1943 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1944 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1945 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1946 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1947 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1948 interconnect-names = "qup-core", 1949 "qup-config", 1950 "qup-memory"; 1951 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1952 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1953 dma-names = "tx", 1954 "rx"; 1955 pinctrl-0 = <&qup_i2c1_data_clk>; 1956 pinctrl-names = "default"; 1957 #address-cells = <1>; 1958 #size-cells = <0>; 1959 1960 status = "disabled"; 1961 }; 1962 1963 spi1: spi@b84000 { 1964 compatible = "qcom,geni-spi"; 1965 reg = <0x0 0x00b84000 0x0 0x4000>; 1966 interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>; 1967 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1968 clock-names = "se"; 1969 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1970 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1971 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1972 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1973 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1974 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1975 interconnect-names = "qup-core", 1976 "qup-config", 1977 "qup-memory"; 1978 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1979 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1980 dma-names = "tx", 1981 "rx"; 1982 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1983 pinctrl-names = "default"; 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 1987 status = "disabled"; 1988 }; 1989 1990 i2c2: i2c@b88000 { 1991 compatible = "qcom,geni-i2c"; 1992 reg = <0x0 0x00b88000 0x0 0x4000>; 1993 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 1994 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1995 clock-names = "se"; 1996 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1997 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1998 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1999 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2000 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2001 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2002 interconnect-names = "qup-core", 2003 "qup-config", 2004 "qup-memory"; 2005 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2006 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2007 dma-names = "tx", 2008 "rx"; 2009 pinctrl-0 = <&qup_i2c2_data_clk>; 2010 pinctrl-names = "default"; 2011 #address-cells = <1>; 2012 #size-cells = <0>; 2013 2014 status = "disabled"; 2015 }; 2016 2017 spi2: spi@b88000 { 2018 compatible = "qcom,geni-spi"; 2019 reg = <0x0 0x00b88000 0x0 0x4000>; 2020 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 2021 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2022 clock-names = "se"; 2023 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2024 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2025 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2026 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2027 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2029 interconnect-names = "qup-core", 2030 "qup-config", 2031 "qup-memory"; 2032 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2033 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2034 dma-names = "tx", 2035 "rx"; 2036 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2037 pinctrl-names = "default"; 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 status = "disabled"; 2042 }; 2043 2044 uart2: serial@b88000 { 2045 compatible = "qcom,geni-uart"; 2046 reg = <0x0 0x00b88000 0x0 0x4000>; 2047 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 2048 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2049 clock-names = "se"; 2050 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2051 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2052 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2053 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2054 interconnect-names = "qup-core", 2055 "qup-config"; 2056 pinctrl-0 = <&qup_uart2_default>; 2057 pinctrl-names = "default"; 2058 2059 status = "disabled"; 2060 }; 2061 2062 i2c3: i2c@b8c000 { 2063 compatible = "qcom,geni-i2c"; 2064 reg = <0x0 0x00b8c000 0x0 0x4000>; 2065 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2066 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2067 clock-names = "se"; 2068 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2069 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2070 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2071 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2072 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2073 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2074 interconnect-names = "qup-core", 2075 "qup-config", 2076 "qup-memory"; 2077 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2078 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2079 dma-names = "tx", 2080 "rx"; 2081 pinctrl-0 = <&qup_i2c3_data_clk>; 2082 pinctrl-names = "default"; 2083 #address-cells = <1>; 2084 #size-cells = <0>; 2085 2086 status = "disabled"; 2087 }; 2088 2089 spi3: spi@b8c000 { 2090 compatible = "qcom,geni-spi"; 2091 reg = <0x0 0x00b8c000 0x0 0x4000>; 2092 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2093 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2094 clock-names = "se"; 2095 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2096 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2097 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2098 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2099 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2101 interconnect-names = "qup-core", 2102 "qup-config", 2103 "qup-memory"; 2104 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2105 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2106 dma-names = "tx", 2107 "rx"; 2108 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2109 pinctrl-names = "default"; 2110 #address-cells = <1>; 2111 #size-cells = <0>; 2112 2113 status = "disabled"; 2114 }; 2115 2116 i2c4: i2c@b90000 { 2117 compatible = "qcom,geni-i2c"; 2118 reg = <0x0 0x00b90000 0x0 0x4000>; 2119 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2120 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2121 clock-names = "se"; 2122 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2123 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2124 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2125 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2126 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2128 interconnect-names = "qup-core", 2129 "qup-config", 2130 "qup-memory"; 2131 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2132 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2133 dma-names = "tx", 2134 "rx"; 2135 pinctrl-0 = <&qup_i2c4_data_clk>; 2136 pinctrl-names = "default"; 2137 #address-cells = <1>; 2138 #size-cells = <0>; 2139 2140 status = "disabled"; 2141 }; 2142 2143 spi4: spi@b90000 { 2144 compatible = "qcom,geni-spi"; 2145 reg = <0x0 0x00b90000 0x0 0x4000>; 2146 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2147 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2148 clock-names = "se"; 2149 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2150 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2151 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2152 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2153 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2155 interconnect-names = "qup-core", 2156 "qup-config", 2157 "qup-memory"; 2158 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2159 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2160 dma-names = "tx", 2161 "rx"; 2162 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2163 pinctrl-names = "default"; 2164 #address-cells = <1>; 2165 #size-cells = <0>; 2166 2167 status = "disabled"; 2168 }; 2169 2170 i2c5: i2c@b94000 { 2171 compatible = "qcom,geni-i2c"; 2172 reg = <0x0 0x00b94000 0x0 0x4000>; 2173 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2174 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2175 clock-names = "se"; 2176 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2177 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2178 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2179 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2180 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2181 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2182 interconnect-names = "qup-core", 2183 "qup-config", 2184 "qup-memory"; 2185 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2186 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2187 dma-names = "tx", 2188 "rx"; 2189 pinctrl-0 = <&qup_i2c5_data_clk>; 2190 pinctrl-names = "default"; 2191 #address-cells = <1>; 2192 #size-cells = <0>; 2193 2194 status = "disabled"; 2195 }; 2196 2197 spi5: spi@b94000 { 2198 compatible = "qcom,geni-spi"; 2199 reg = <0x0 0x00b94000 0x0 0x4000>; 2200 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2201 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2202 clock-names = "se"; 2203 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2204 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2205 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2206 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2207 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2208 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2209 interconnect-names = "qup-core", 2210 "qup-config", 2211 "qup-memory"; 2212 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2213 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2214 dma-names = "tx", 2215 "rx"; 2216 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2217 pinctrl-names = "default"; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 2221 status = "disabled"; 2222 }; 2223 2224 i2c6: i2c@b98000 { 2225 compatible = "qcom,geni-i2c"; 2226 reg = <0x0 0x00b98000 0x0 0x4000>; 2227 interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>; 2228 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2229 clock-names = "se"; 2230 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2231 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2232 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2233 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2234 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2235 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2236 interconnect-names = "qup-core", 2237 "qup-config", 2238 "qup-memory"; 2239 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2240 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2241 dma-names = "tx", 2242 "rx"; 2243 pinctrl-0 = <&qup_i2c6_data_clk>; 2244 pinctrl-names = "default"; 2245 #address-cells = <1>; 2246 #size-cells = <0>; 2247 2248 status = "disabled"; 2249 }; 2250 2251 spi6: spi@b98000 { 2252 compatible = "qcom,geni-spi"; 2253 reg = <0x0 0x00b98000 0x0 0x4000>; 2254 interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>; 2255 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2256 clock-names = "se"; 2257 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2258 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2259 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2260 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2261 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2262 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2263 interconnect-names = "qup-core", 2264 "qup-config", 2265 "qup-memory"; 2266 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2267 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2268 dma-names = "tx", 2269 "rx"; 2270 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2271 pinctrl-names = "default"; 2272 #address-cells = <1>; 2273 #size-cells = <0>; 2274 2275 status = "disabled"; 2276 }; 2277 2278 i2c7: i2c@b9c000 { 2279 compatible = "qcom,geni-i2c"; 2280 reg = <0x0 0x00b9c000 0x0 0x4000>; 2281 interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>; 2282 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2283 clock-names = "se"; 2284 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2285 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2286 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2287 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2288 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2289 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2290 interconnect-names = "qup-core", 2291 "qup-config", 2292 "qup-memory"; 2293 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2294 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2295 dma-names = "tx", 2296 "rx"; 2297 pinctrl-0 = <&qup_i2c7_data_clk>; 2298 pinctrl-names = "default"; 2299 #address-cells = <1>; 2300 #size-cells = <0>; 2301 2302 status = "disabled"; 2303 }; 2304 2305 spi7: spi@b9c000 { 2306 compatible = "qcom,geni-spi"; 2307 reg = <0x0 0x00b9c000 0x0 0x4000>; 2308 interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>; 2309 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2310 clock-names = "se"; 2311 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2312 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2313 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2314 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2315 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2316 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2317 interconnect-names = "qup-core", 2318 "qup-config", 2319 "qup-memory"; 2320 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2321 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2322 dma-names = "tx", 2323 "rx"; 2324 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2325 pinctrl-names = "default"; 2326 #address-cells = <1>; 2327 #size-cells = <0>; 2328 2329 status = "disabled"; 2330 }; 2331 }; 2332 2333 remoteproc_soccp: remoteproc@d00000 { 2334 compatible = "qcom,glymur-soccp-pas"; 2335 reg = <0x0 0x00d00000 0x0 0x200000>; 2336 2337 interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 2338 <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2339 <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2340 <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2341 <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2342 <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; 2343 interrupt-names = "wdog", 2344 "fatal", 2345 "ready", 2346 "handover", 2347 "stop-ack", 2348 "pong"; 2349 2350 clocks = <&rpmhcc RPMH_CXO_CLK>; 2351 clock-names = "xo"; 2352 2353 power-domains = <&rpmhpd RPMHPD_CX>, 2354 <&rpmhpd RPMHPD_MX>; 2355 power-domain-names = "cx", 2356 "mx"; 2357 2358 memory-region = <&soccp_mem>, 2359 <&soccpdtb_mem>; 2360 2361 qcom,smem-states = <&soccp_smp2p_out 0>, 2362 <&soccp_smp2p_out 8>; 2363 qcom,smem-state-names = "stop", 2364 "ping"; 2365 2366 glink-edge { 2367 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 2368 IPCC_MPROC_SIGNAL_GLINK_QMP 2369 IRQ_TYPE_EDGE_RISING>; 2370 mboxes = <&ipcc IPCC_MPROC_SOCCP 2371 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2372 qcom,remote-pid = <19>; 2373 label = "soccp"; 2374 }; 2375 }; 2376 2377 usb_hs_phy: phy@fa0000 { 2378 compatible = "qcom,glymur-m31-eusb2-phy", 2379 "qcom,sm8750-m31-eusb2-phy"; 2380 reg = <0x0 0x00fa0000 0x0 0x154>; 2381 #phy-cells = <0>; 2382 2383 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2384 clock-names = "ref"; 2385 2386 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2387 2388 status = "disabled"; 2389 }; 2390 2391 usb_mp_hsphy0: phy@fa1000 { 2392 compatible = "qcom,glymur-m31-eusb2-phy", 2393 "qcom,sm8750-m31-eusb2-phy"; 2394 2395 reg = <0x0 0x00fa1000 0x0 0x29c>; 2396 #phy-cells = <0>; 2397 2398 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2399 clock-names = "ref"; 2400 2401 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2402 2403 status = "disabled"; 2404 }; 2405 2406 usb_mp_hsphy1: phy@fa2000 { 2407 compatible = "qcom,glymur-m31-eusb2-phy", 2408 "qcom,sm8750-m31-eusb2-phy"; 2409 2410 reg = <0x0 0x00fa2000 0x0 0x29c>; 2411 #phy-cells = <0>; 2412 2413 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2414 clock-names = "ref"; 2415 2416 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2417 2418 status = "disabled"; 2419 }; 2420 2421 usb_mp_qmpphy0: phy@fa3000 { 2422 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2423 reg = <0x0 0x00fa3000 0x0 0x2000>; 2424 2425 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2426 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2427 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2428 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2429 clock-names = "aux", 2430 "ref", 2431 "com_aux", 2432 "pipe"; 2433 2434 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2435 2436 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2437 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2438 reset-names = "phy", 2439 "phy_phy"; 2440 2441 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2442 #clock-cells = <0>; 2443 #phy-cells = <0>; 2444 2445 status = "disabled"; 2446 }; 2447 2448 usb_mp_qmpphy1: phy@fa5000 { 2449 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2450 reg = <0x0 0x00fa5000 0x0 0x2000>; 2451 2452 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2453 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2454 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2455 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2456 clock-names = "aux", 2457 "ref", 2458 "com_aux", 2459 "pipe"; 2460 2461 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2462 2463 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2464 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2465 reset-names = "phy", 2466 "phy_phy"; 2467 2468 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2469 2470 #clock-cells = <0>; 2471 #phy-cells = <0>; 2472 2473 status = "disabled"; 2474 }; 2475 2476 mdss_dp3_phy: phy@faac00 { 2477 compatible = "qcom,glymur-dp-phy"; 2478 reg = <0x0 0x00faac00 0x0 0x1d0>, 2479 <0x0 0x00faa400 0x0 0x128>, 2480 <0x0 0x00faa800 0x0 0x128>, 2481 <0x0 0x00faa000 0x0 0x358>; 2482 2483 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2484 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2485 <&tcsr TCSR_EDP_CLKREF_EN>; 2486 clock-names = "aux", 2487 "cfg_ahb", 2488 "ref"; 2489 2490 power-domains = <&rpmhpd RPMHPD_MX>; 2491 2492 #clock-cells = <1>; 2493 #phy-cells = <0>; 2494 2495 status = "disabled"; 2496 }; 2497 2498 usb_0_hsphy: phy@fd3000 { 2499 compatible = "qcom,glymur-m31-eusb2-phy", 2500 "qcom,sm8750-m31-eusb2-phy"; 2501 2502 reg = <0x0 0x00fd3000 0x0 0x29c>; 2503 #phy-cells = <0>; 2504 2505 clocks = <&rpmhcc RPMH_CXO_CLK>; 2506 clock-names = "ref"; 2507 2508 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2509 2510 status = "disabled"; 2511 }; 2512 2513 usb_0_qmpphy: phy@fd5000 { 2514 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2515 reg = <0x0 0x00fd5000 0x0 0x8000>; 2516 2517 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2518 <&rpmhcc RPMH_CXO_CLK>, 2519 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2520 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2521 clock-names = "aux", 2522 "ref", 2523 "com_aux", 2524 "usb3_pipe"; 2525 2526 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2527 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2528 2529 reset-names = "phy", 2530 "common"; 2531 2532 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2533 2534 #clock-cells = <1>; 2535 #phy-cells = <1>; 2536 2537 mode-switch; 2538 orientation-switch; 2539 2540 status = "disabled"; 2541 2542 ports { 2543 #address-cells = <1>; 2544 #size-cells = <0>; 2545 2546 port@0 { 2547 reg = <0>; 2548 2549 usb_0_qmpphy_out: endpoint { 2550 }; 2551 }; 2552 2553 port@1 { 2554 reg = <1>; 2555 2556 usb_0_qmpphy_usb_ss_in: endpoint { 2557 remote-endpoint = <&usb_0_dwc3_ss>; 2558 }; 2559 }; 2560 2561 port@2 { 2562 reg = <2>; 2563 2564 usb_dp_qmpphy_dp_in: endpoint { 2565 remote-endpoint = <&mdss_dp0_out>; 2566 }; 2567 }; 2568 }; 2569 }; 2570 2571 usb_1_hsphy: phy@fdd000 { 2572 compatible = "qcom,glymur-m31-eusb2-phy", 2573 "qcom,sm8750-m31-eusb2-phy"; 2574 2575 reg = <0x0 0x00fdd000 0x0 0x29c>; 2576 #phy-cells = <0>; 2577 2578 clocks = <&rpmhcc RPMH_CXO_CLK>; 2579 clock-names = "ref"; 2580 2581 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2582 2583 status = "disabled"; 2584 }; 2585 2586 usb_1_qmpphy: phy@fde000 { 2587 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2588 reg = <0x0 0x00fde000 0x0 0x8000>; 2589 2590 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2591 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2592 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2593 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2594 clock-names = "aux", 2595 "ref", 2596 "com_aux", 2597 "usb3_pipe"; 2598 2599 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2600 2601 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2602 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2603 reset-names = "phy", 2604 "common"; 2605 2606 #clock-cells = <1>; 2607 #phy-cells = <1>; 2608 2609 mode-switch; 2610 orientation-switch; 2611 2612 status = "disabled"; 2613 2614 ports { 2615 #address-cells = <1>; 2616 #size-cells = <0>; 2617 2618 port@0 { 2619 reg = <0>; 2620 2621 usb_1_qmpphy_out: endpoint { 2622 }; 2623 }; 2624 2625 port@1 { 2626 reg = <1>; 2627 2628 usb_1_qmpphy_usb_ss_in: endpoint { 2629 remote-endpoint = <&usb_1_dwc3_ss>; 2630 }; 2631 }; 2632 2633 port@2 { 2634 reg = <2>; 2635 2636 usb_1_qmpphy_dp_in: endpoint { 2637 remote-endpoint = <&mdss_dp1_out>; 2638 }; 2639 }; 2640 }; 2641 }; 2642 2643 2644 /* cluster0 */ 2645 bwmon_cluster0: pmu@100c400 { 2646 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2647 reg = <0x0 0x0100c400 0x0 0x600>; 2648 2649 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2650 2651 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2653 2654 operating-points-v2 = <&cpu_bwmon_opp_table>; 2655 2656 cpu_bwmon_opp_table: opp-table { 2657 compatible = "operating-points-v2"; 2658 2659 opp-0 { 2660 opp-peak-kBps = <800000>; 2661 }; 2662 2663 opp-1 { 2664 opp-peak-kBps = <2188800>; 2665 }; 2666 2667 opp-2 { 2668 opp-peak-kBps = <5414400>; 2669 }; 2670 2671 opp-3 { 2672 opp-peak-kBps = <6220800>; 2673 }; 2674 2675 opp-4 { 2676 opp-peak-kBps = <6835200>; 2677 }; 2678 2679 opp-5 { 2680 opp-peak-kBps = <8371200>; 2681 }; 2682 2683 opp-6 { 2684 opp-peak-kBps = <10944000>; 2685 }; 2686 2687 opp-7 { 2688 opp-peak-kBps = <12748800>; 2689 }; 2690 2691 opp-8 { 2692 opp-peak-kBps = <14745600>; 2693 }; 2694 2695 opp-9 { 2696 opp-peak-kBps = <16896000>; 2697 }; 2698 2699 opp-10 { 2700 opp-peak-kBps = <19046400>; 2701 }; 2702 2703 opp-11 { 2704 opp-peak-kBps = <21332000>; 2705 }; 2706 }; 2707 }; 2708 2709 /* cluster1 */ 2710 bwmon_cluster1: pmu@100d400 { 2711 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2712 reg = <0x0 0x0100d400 0x0 0x600>; 2713 2714 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2715 2716 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2717 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2718 2719 operating-points-v2 = <&cpu_bwmon_opp_table>; 2720 }; 2721 2722 /* cluster2 */ 2723 bwmon_cluster2: pmu@100e400 { 2724 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2725 reg = <0x0 0x0100e400 0x0 0x600>; 2726 2727 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2728 2729 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2730 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2731 2732 operating-points-v2 = <&cpu_bwmon_opp_table>; 2733 }; 2734 cnoc_main: interconnect@1500000 { 2735 compatible = "qcom,glymur-cnoc-main"; 2736 reg = <0x0 0x01500000 0x0 0x17080>; 2737 qcom,bcm-voters = <&apps_bcm_voter>; 2738 #interconnect-cells = <2>; 2739 }; 2740 2741 config_noc: interconnect@1600000 { 2742 compatible = "qcom,glymur-cnoc-cfg"; 2743 reg = <0x0 0x01600000 0x0 0x6600>; 2744 qcom,bcm-voters = <&apps_bcm_voter>; 2745 #interconnect-cells = <2>; 2746 }; 2747 2748 system_noc: interconnect@1680000 { 2749 compatible = "qcom,glymur-system-noc"; 2750 reg = <0x0 0x01680000 0x0 0x1c080>; 2751 qcom,bcm-voters = <&apps_bcm_voter>; 2752 #interconnect-cells = <2>; 2753 }; 2754 2755 pcie_west_anoc: interconnect@16c0000 { 2756 compatible = "qcom,glymur-pcie-west-anoc"; 2757 reg = <0x0 0x016c0000 0x0 0xf580>; 2758 qcom,bcm-voters = <&apps_bcm_voter>; 2759 #interconnect-cells = <2>; 2760 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2761 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2762 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2763 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2764 }; 2765 2766 pcie_east_anoc: interconnect@16d0000 { 2767 compatible = "qcom,glymur-pcie-east-anoc"; 2768 reg = <0x0 0x016d0000 0x0 0xf300>; 2769 qcom,bcm-voters = <&apps_bcm_voter>; 2770 #interconnect-cells = <2>; 2771 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2772 }; 2773 2774 aggre1_noc: interconnect@16e0000 { 2775 compatible = "qcom,glymur-aggre1-noc"; 2776 reg = <0x0 0x016e0000 0x0 0x14400>; 2777 qcom,bcm-voters = <&apps_bcm_voter>; 2778 #interconnect-cells = <2>; 2779 }; 2780 2781 aggre2_noc: interconnect@1720000 { 2782 compatible = "qcom,glymur-aggre2-noc"; 2783 reg = <0x0 0x01720000 0x0 0x14400>; 2784 qcom,bcm-voters = <&apps_bcm_voter>; 2785 #interconnect-cells = <2>; 2786 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2787 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2788 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2789 }; 2790 2791 aggre3_noc: interconnect@1700000 { 2792 compatible = "qcom,glymur-aggre3-noc"; 2793 reg = <0x0 0x01700000 0x0 0x1d400>; 2794 qcom,bcm-voters = <&apps_bcm_voter>; 2795 #interconnect-cells = <2>; 2796 }; 2797 2798 aggre4_noc: interconnect@1740000 { 2799 compatible = "qcom,glymur-aggre4-noc"; 2800 reg = <0x0 0x01740000 0x0 0x14400>; 2801 qcom,bcm-voters = <&apps_bcm_voter>; 2802 #interconnect-cells = <2>; 2803 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2804 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2805 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2806 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2807 }; 2808 2809 mmss_noc: interconnect@1780000 { 2810 compatible = "qcom,glymur-mmss-noc"; 2811 reg = <0x0 0x01780000 0x0 0x5b800>; 2812 qcom,bcm-voters = <&apps_bcm_voter>; 2813 #interconnect-cells = <2>; 2814 }; 2815 2816 pcie_east_slv_noc: interconnect@1900000 { 2817 compatible = "qcom,glymur-pcie-east-slv-noc"; 2818 reg = <0x0 0x01900000 0x0 0xe080>; 2819 qcom,bcm-voters = <&apps_bcm_voter>; 2820 #interconnect-cells = <2>; 2821 }; 2822 2823 pcie_west_slv_noc: interconnect@1920000 { 2824 compatible = "qcom,glymur-pcie-west-slv-noc"; 2825 reg = <0x0 0x01920000 0x0 0xf180>; 2826 qcom,bcm-voters = <&apps_bcm_voter>; 2827 #interconnect-cells = <2>; 2828 }; 2829 2830 pcie4: pcie@1bf0000 { 2831 device_type = "pci"; 2832 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2833 reg = <0x0 0x01bf0000 0x0 0x3000>, 2834 <0x0 0x78000000 0x0 0xf20>, 2835 <0x0 0x78000f40 0x0 0xa8>, 2836 <0x0 0x78001000 0x0 0x4000>, 2837 <0x0 0x78005000 0x0 0x100000>, 2838 <0x0 0x01bf3000 0x0 0x1000>; 2839 reg-names = "parf", 2840 "dbi", 2841 "elbi", 2842 "atu", 2843 "config", 2844 "mhi"; 2845 #address-cells = <3>; 2846 #size-cells = <2>; 2847 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2848 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2849 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2850 bus-range = <0x00 0xff>; 2851 2852 dma-coherent; 2853 2854 linux,pci-domain = <4>; 2855 num-lanes = <2>; 2856 2857 operating-points-v2 = <&pcie4_opp_table>; 2858 2859 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2860 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2861 2862 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2863 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2866 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2867 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2868 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2869 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2870 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2871 interrupt-names = "msi0", 2872 "msi1", 2873 "msi2", 2874 "msi3", 2875 "msi4", 2876 "msi5", 2877 "msi6", 2878 "msi7", 2879 "global"; 2880 2881 #interrupt-cells = <1>; 2882 interrupt-map-mask = <0 0 0 0x7>; 2883 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 2884 <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 2885 <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 2886 <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 2887 2888 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2889 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2890 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2891 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2892 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2893 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2894 clock-names = "aux", 2895 "cfg", 2896 "bus_master", 2897 "bus_slave", 2898 "slave_q2a", 2899 "noc_aggr"; 2900 2901 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2902 assigned-clock-rates = <19200000>; 2903 2904 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2905 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2906 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2907 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2908 interconnect-names = "pcie-mem", 2909 "cpu-pcie"; 2910 2911 resets = <&gcc GCC_PCIE_4_BCR>, 2912 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2913 reset-names = "pci", 2914 "link_down"; 2915 2916 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2917 2918 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2919 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2920 2921 status = "disabled"; 2922 2923 pcie4_opp_table: opp-table { 2924 compatible = "operating-points-v2"; 2925 2926 /* GEN 1 x1 */ 2927 opp-2500000-1 { 2928 opp-hz = /bits/ 64 <2500000>; 2929 required-opps = <&rpmhpd_opp_low_svs>; 2930 opp-peak-kBps = <250000 1>; 2931 opp-level = <1>; 2932 }; 2933 2934 /* GEN 1 x2 */ 2935 opp-5000000-1 { 2936 opp-hz = /bits/ 64 <5000000>; 2937 required-opps = <&rpmhpd_opp_low_svs>; 2938 opp-peak-kBps = <500000 1>; 2939 opp-level = <1>; 2940 }; 2941 2942 /* GEN 2 x1 */ 2943 opp-5000000-2 { 2944 opp-hz = /bits/ 64 <5000000>; 2945 required-opps = <&rpmhpd_opp_low_svs>; 2946 opp-peak-kBps = <500000 1>; 2947 opp-level = <2>; 2948 }; 2949 2950 /* GEN 2 x2 */ 2951 opp-10000000-2 { 2952 opp-hz = /bits/ 64 <10000000>; 2953 required-opps = <&rpmhpd_opp_low_svs>; 2954 opp-peak-kBps = <1000000 1>; 2955 opp-level = <2>; 2956 }; 2957 2958 /* GEN 3 x1 */ 2959 opp-8000000-3 { 2960 opp-hz = /bits/ 64 <8000000>; 2961 required-opps = <&rpmhpd_opp_low_svs>; 2962 opp-peak-kBps = <984500 1>; 2963 opp-level = <3>; 2964 }; 2965 2966 /* GEN 3 x2 */ 2967 opp-16000000-3 { 2968 opp-hz = /bits/ 64 <16000000>; 2969 required-opps = <&rpmhpd_opp_low_svs>; 2970 opp-peak-kBps = <1969000 1>; 2971 opp-level = <3>; 2972 }; 2973 2974 /* GEN 4 x1 */ 2975 opp-16000000-4 { 2976 opp-hz = /bits/ 64 <16000000>; 2977 required-opps = <&rpmhpd_opp_low_svs>; 2978 opp-peak-kBps = <1969000 1>; 2979 opp-level = <4>; 2980 }; 2981 2982 /* GEN 4 x2 */ 2983 opp-32000000-4 { 2984 opp-hz = /bits/ 64 <32000000>; 2985 required-opps = <&rpmhpd_opp_low_svs>; 2986 opp-peak-kBps = <3938000 1>; 2987 opp-level = <4>; 2988 }; 2989 2990 }; 2991 2992 pcie4_port0: pcie@0 { 2993 device_type = "pci"; 2994 compatible = "pciclass,0604"; 2995 reg = <0x0 0x0 0x0 0x0 0x0>; 2996 bus-range = <0x01 0xff>; 2997 2998 phys = <&pcie4_phy>; 2999 3000 #address-cells = <3>; 3001 #size-cells = <2>; 3002 ranges; 3003 3004 port { 3005 pcie4_port0_ep: endpoint { 3006 }; 3007 }; 3008 }; 3009 }; 3010 3011 pcie4_phy: phy@1bf6000 { 3012 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3013 reg = <0x0 0x01bf6000 0x0 0x2000>; 3014 3015 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 3016 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3017 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 3018 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3019 <&gcc GCC_PCIE_4_PIPE_CLK>, 3020 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 3021 clock-names = "aux", 3022 "cfg_ahb", 3023 "ref", 3024 "rchng", 3025 "pipe", 3026 "pipediv2"; 3027 3028 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3029 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3030 reset-names = "phy", 3031 "phy_nocsr"; 3032 3033 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3034 assigned-clock-rates = <100000000>; 3035 3036 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3037 3038 #clock-cells = <0>; 3039 clock-output-names = "pcie4_pipe_clk"; 3040 3041 #phy-cells = <0>; 3042 3043 status = "disabled"; 3044 }; 3045 3046 pcie5: pcie@1b40000 { 3047 device_type = "pci"; 3048 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3049 reg = <0x0 0x01b40000 0x0 0x3000>, 3050 <0x0 0x7a000000 0x0 0xf20>, 3051 <0x0 0x7a000f40 0x0 0xa8>, 3052 <0x0 0x7a001000 0x0 0x4000>, 3053 <0x0 0x7a100000 0x0 0x100000>, 3054 <0x0 0x01b43000 0x0 0x1000>; 3055 reg-names = "parf", 3056 "dbi", 3057 "elbi", 3058 "atu", 3059 "config", 3060 "mhi"; 3061 #address-cells = <3>; 3062 #size-cells = <2>; 3063 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 3064 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 3065 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 3066 bus-range = <0x00 0xff>; 3067 3068 dma-coherent; 3069 3070 linux,pci-domain = <5>; 3071 num-lanes = <4>; 3072 3073 operating-points-v2 = <&pcie5_opp_table>; 3074 3075 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 3076 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 3077 3078 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 3087 interrupt-names = "msi0", 3088 "msi1", 3089 "msi2", 3090 "msi3", 3091 "msi4", 3092 "msi5", 3093 "msi6", 3094 "msi7", 3095 "global"; 3096 3097 #interrupt-cells = <1>; 3098 interrupt-map-mask = <0 0 0 0x7>; 3099 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 3100 <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 3101 <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 3102 <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 3103 3104 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3105 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3106 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3107 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3108 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3109 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3110 clock-names = "aux", 3111 "cfg", 3112 "bus_master", 3113 "bus_slave", 3114 "slave_q2a", 3115 "noc_aggr"; 3116 3117 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3118 assigned-clock-rates = <19200000>; 3119 3120 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3122 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3123 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3124 interconnect-names = "pcie-mem", 3125 "cpu-pcie"; 3126 3127 resets = <&gcc GCC_PCIE_5_BCR>, 3128 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3129 reset-names = "pci", 3130 "link_down"; 3131 3132 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3133 3134 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3135 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3136 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3137 3138 status = "disabled"; 3139 3140 pcie5_opp_table: opp-table { 3141 compatible = "operating-points-v2"; 3142 3143 /* GEN 1 x1 */ 3144 opp-2500000-1 { 3145 opp-hz = /bits/ 64 <2500000>; 3146 required-opps = <&rpmhpd_opp_low_svs>; 3147 opp-peak-kBps = <250000 1>; 3148 opp-level = <1>; 3149 }; 3150 3151 /* GEN 1 x2 */ 3152 opp-5000000-1 { 3153 opp-hz = /bits/ 64 <5000000>; 3154 required-opps = <&rpmhpd_opp_low_svs>; 3155 opp-peak-kBps = <500000 1>; 3156 opp-level = <1>; 3157 }; 3158 3159 /* GEN 1 x4 */ 3160 opp-10000000-1 { 3161 opp-hz = /bits/ 64 <10000000>; 3162 required-opps = <&rpmhpd_opp_low_svs>; 3163 opp-peak-kBps = <1000000 1>; 3164 opp-level = <1>; 3165 }; 3166 3167 /* GEN 2 x1 */ 3168 opp-5000000-2 { 3169 opp-hz = /bits/ 64 <5000000>; 3170 required-opps = <&rpmhpd_opp_low_svs>; 3171 opp-peak-kBps = <500000 1>; 3172 opp-level = <2>; 3173 }; 3174 3175 /* GEN 2 x2 */ 3176 opp-10000000-2 { 3177 opp-hz = /bits/ 64 <10000000>; 3178 required-opps = <&rpmhpd_opp_low_svs>; 3179 opp-peak-kBps = <1000000 1>; 3180 opp-level = <2>; 3181 }; 3182 3183 /* GEN 2 x4 */ 3184 opp-20000000-2 { 3185 opp-hz = /bits/ 64 <20000000>; 3186 required-opps = <&rpmhpd_opp_low_svs>; 3187 opp-peak-kBps = <2000000 1>; 3188 opp-level = <2>; 3189 }; 3190 3191 /* GEN 3 x1 */ 3192 opp-8000000-3 { 3193 opp-hz = /bits/ 64 <8000000>; 3194 required-opps = <&rpmhpd_opp_low_svs>; 3195 opp-peak-kBps = <984500 1>; 3196 opp-level = <3>; 3197 }; 3198 3199 /* GEN 3 x2 */ 3200 opp-16000000-3 { 3201 opp-hz = /bits/ 64 <16000000>; 3202 required-opps = <&rpmhpd_opp_low_svs>; 3203 opp-peak-kBps = <1969000 1>; 3204 opp-level = <3>; 3205 }; 3206 3207 /* GEN 3 x4 */ 3208 opp-32000000-3 { 3209 opp-hz = /bits/ 64 <32000000>; 3210 required-opps = <&rpmhpd_opp_low_svs>; 3211 opp-peak-kBps = <3938000 1>; 3212 opp-level = <3>; 3213 }; 3214 3215 /* GEN 4 x1 */ 3216 opp-16000000-4 { 3217 opp-hz = /bits/ 64 <16000000>; 3218 required-opps = <&rpmhpd_opp_svs>; 3219 opp-peak-kBps = <1969000 1>; 3220 opp-level = <4>; 3221 }; 3222 3223 /* GEN 4 x2 */ 3224 opp-32000000-4 { 3225 opp-hz = /bits/ 64 <32000000>; 3226 required-opps = <&rpmhpd_opp_svs>; 3227 opp-peak-kBps = <3938000 1>; 3228 opp-level = <4>; 3229 }; 3230 3231 /* GEN 4 x4 */ 3232 opp-64000000-4 { 3233 opp-hz = /bits/ 64 <64000000>; 3234 required-opps = <&rpmhpd_opp_svs>; 3235 opp-peak-kBps = <7876000 1>; 3236 opp-level = <4>; 3237 }; 3238 3239 /* GEN 5 x1 */ 3240 opp-32000000-5 { 3241 opp-hz = /bits/ 64 <32000000>; 3242 required-opps = <&rpmhpd_opp_nom>; 3243 opp-peak-kBps = <3938000 1>; 3244 opp-level = <5>; 3245 }; 3246 3247 /* GEN 5 x2 */ 3248 opp-64000000-5 { 3249 opp-hz = /bits/ 64 <64000000>; 3250 required-opps = <&rpmhpd_opp_nom>; 3251 opp-peak-kBps = <7876000 1>; 3252 opp-level = <5>; 3253 }; 3254 3255 /* GEN 5 x4 */ 3256 opp-128000000-5 { 3257 opp-hz = /bits/ 64 <128000000>; 3258 required-opps = <&rpmhpd_opp_nom>; 3259 opp-peak-kBps = <15753000 1>; 3260 opp-level = <5>; 3261 }; 3262 }; 3263 3264 pcie5_port0: pcie@0 { 3265 device_type = "pci"; 3266 compatible = "pciclass,0604"; 3267 reg = <0x0 0x0 0x0 0x0 0x0>; 3268 bus-range = <0x01 0xff>; 3269 3270 phys = <&pcie5_phy>; 3271 3272 #address-cells = <3>; 3273 #size-cells = <2>; 3274 ranges; 3275 3276 port { 3277 pcie5_port0_ep: endpoint { 3278 }; 3279 }; 3280 }; 3281 }; 3282 3283 pcie5_phy: phy@1b50000 { 3284 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3285 reg = <0x0 0x01b50000 0x0 0x10000>; 3286 3287 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3288 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3289 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3290 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3291 <&gcc GCC_PCIE_5_PIPE_CLK>, 3292 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3293 clock-names = "aux", 3294 "cfg_ahb", 3295 "ref", 3296 "rchng", 3297 "pipe", 3298 "pipediv2"; 3299 3300 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3301 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3302 reset-names = "phy", 3303 "phy_nocsr"; 3304 3305 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3306 assigned-clock-rates = <100000000>; 3307 3308 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3309 3310 #clock-cells = <0>; 3311 clock-output-names = "pcie5_pipe_clk"; 3312 3313 #phy-cells = <0>; 3314 3315 status = "disabled"; 3316 }; 3317 3318 pcie6: pcie@1c00000 { 3319 device_type = "pci"; 3320 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3321 reg = <0x0 0x01c00000 0x0 0x3000>, 3322 <0x0 0x7e000000 0x0 0xf20>, 3323 <0x0 0x7e000f40 0x0 0xa8>, 3324 <0x0 0x7e001000 0x0 0x4000>, 3325 <0x0 0x7e100000 0x0 0x100000>, 3326 <0x0 0x01c03000 0x0 0x1000>; 3327 reg-names = "parf", 3328 "dbi", 3329 "elbi", 3330 "atu", 3331 "config", 3332 "mhi"; 3333 #address-cells = <3>; 3334 #size-cells = <2>; 3335 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3336 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3337 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3338 bus-range = <0x00 0xff>; 3339 3340 dma-coherent; 3341 3342 linux,pci-domain = <6>; 3343 num-lanes = <2>; 3344 3345 operating-points-v2 = <&pcie6_opp_table>; 3346 3347 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3348 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3349 3350 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3359 interrupt-names = "msi0", 3360 "msi1", 3361 "msi2", 3362 "msi3", 3363 "msi4", 3364 "msi5", 3365 "msi6", 3366 "msi7", 3367 "global"; 3368 3369 #interrupt-cells = <1>; 3370 interrupt-map-mask = <0 0 0 0x7>; 3371 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 3372 <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 3373 <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 3374 <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 3375 3376 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3377 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3378 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3379 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3380 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3381 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3382 clock-names = "aux", 3383 "cfg", 3384 "bus_master", 3385 "bus_slave", 3386 "slave_q2a", 3387 "noc_aggr"; 3388 3389 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3390 assigned-clock-rates = <19200000>; 3391 3392 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3394 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3395 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3396 interconnect-names = "pcie-mem", 3397 "cpu-pcie"; 3398 3399 resets = <&gcc GCC_PCIE_6_BCR>, 3400 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3401 reset-names = "pci", 3402 "link_down"; 3403 3404 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3405 3406 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3407 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3408 3409 status = "disabled"; 3410 3411 pcie6_opp_table: opp-table { 3412 compatible = "operating-points-v2"; 3413 3414 /* GEN 1 x1 */ 3415 opp-2500000-1 { 3416 opp-hz = /bits/ 64 <2500000>; 3417 required-opps = <&rpmhpd_opp_low_svs>; 3418 opp-peak-kBps = <250000 1>; 3419 opp-level = <1>; 3420 }; 3421 3422 /* GEN 1 x2 */ 3423 opp-5000000-1 { 3424 opp-hz = /bits/ 64 <5000000>; 3425 required-opps = <&rpmhpd_opp_low_svs>; 3426 opp-peak-kBps = <500000 1>; 3427 opp-level = <1>; 3428 }; 3429 3430 /* GEN 2 x1 */ 3431 opp-5000000-2 { 3432 opp-hz = /bits/ 64 <5000000>; 3433 required-opps = <&rpmhpd_opp_low_svs>; 3434 opp-peak-kBps = <500000 1>; 3435 opp-level = <2>; 3436 }; 3437 3438 /* GEN 2 x2 */ 3439 opp-10000000-2 { 3440 opp-hz = /bits/ 64 <10000000>; 3441 required-opps = <&rpmhpd_opp_low_svs>; 3442 opp-peak-kBps = <1000000 1>; 3443 opp-level = <2>; 3444 }; 3445 3446 /* GEN 3 x1 */ 3447 opp-8000000-3 { 3448 opp-hz = /bits/ 64 <8000000>; 3449 required-opps = <&rpmhpd_opp_low_svs>; 3450 opp-peak-kBps = <984500 1>; 3451 opp-level = <3>; 3452 }; 3453 3454 /* GEN 3 x2 */ 3455 opp-16000000-3 { 3456 opp-hz = /bits/ 64 <16000000>; 3457 required-opps = <&rpmhpd_opp_low_svs>; 3458 opp-peak-kBps = <1969000 1>; 3459 opp-level = <3>; 3460 }; 3461 3462 /* GEN 4 x1 */ 3463 opp-16000000-4 { 3464 opp-hz = /bits/ 64 <16000000>; 3465 required-opps = <&rpmhpd_opp_low_svs>; 3466 opp-peak-kBps = <1969000 1>; 3467 opp-level = <4>; 3468 }; 3469 3470 /* GEN 4 x2 */ 3471 opp-32000000-4 { 3472 opp-hz = /bits/ 64 <32000000>; 3473 required-opps = <&rpmhpd_opp_low_svs>; 3474 opp-peak-kBps = <3938000 1>; 3475 opp-level = <4>; 3476 }; 3477 3478 }; 3479 3480 pcie6_port0: pcie@0 { 3481 device_type = "pci"; 3482 compatible = "pciclass,0604"; 3483 reg = <0x0 0x0 0x0 0x0 0x0>; 3484 bus-range = <0x01 0xff>; 3485 3486 phys = <&pcie6_phy>; 3487 3488 #address-cells = <3>; 3489 #size-cells = <2>; 3490 ranges; 3491 3492 port { 3493 pcie6_port0_ep: endpoint { 3494 }; 3495 }; 3496 }; 3497 }; 3498 3499 pcie6_phy: phy@1c06000 { 3500 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3501 reg = <0x0 0x01c06000 0x0 0x2000>; 3502 3503 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3504 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3505 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3506 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3507 <&gcc GCC_PCIE_6_PIPE_CLK>, 3508 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3509 clock-names = "aux", 3510 "cfg_ahb", 3511 "ref", 3512 "rchng", 3513 "pipe", 3514 "pipediv2"; 3515 3516 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3517 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3518 reset-names = "phy", 3519 "phy_nocsr"; 3520 3521 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3522 assigned-clock-rates = <100000000>; 3523 3524 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3525 3526 #clock-cells = <0>; 3527 clock-output-names = "pcie6_pipe_clk"; 3528 3529 #phy-cells = <0>; 3530 3531 status = "disabled"; 3532 }; 3533 3534 pcie3b: pcie@1b80000 { 3535 device_type = "pci"; 3536 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3537 reg = <0x0 0x01b80000 0x0 0x3000>, 3538 <0x0 0x74000000 0x0 0xf20>, 3539 <0x0 0x74000f40 0x0 0xa8>, 3540 <0x0 0x74001000 0x0 0x4000>, 3541 <0x0 0x74100000 0x0 0x100000>, 3542 <0x0 0x01b83000 0x0 0x1000>; 3543 reg-names = "parf", 3544 "dbi", 3545 "elbi", 3546 "atu", 3547 "config", 3548 "mhi"; 3549 #address-cells = <3>; 3550 #size-cells = <2>; 3551 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3552 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3553 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3554 bus-range = <0x00 0xff>; 3555 3556 dma-coherent; 3557 3558 linux,pci-domain = <7>; 3559 num-lanes = <4>; 3560 3561 operating-points-v2 = <&pcie3b_opp_table>; 3562 3563 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3564 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3565 3566 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3567 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3568 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3569 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3570 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3571 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3572 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3573 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3574 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3575 interrupt-names = "msi0", 3576 "msi1", 3577 "msi2", 3578 "msi3", 3579 "msi4", 3580 "msi5", 3581 "msi6", 3582 "msi7", 3583 "global"; 3584 3585 #interrupt-cells = <1>; 3586 interrupt-map-mask = <0 0 0 0x7>; 3587 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, 3588 <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 3589 <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, 3590 <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 3591 3592 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3593 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3594 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3595 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3596 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3597 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3598 clock-names = "aux", 3599 "cfg", 3600 "bus_master", 3601 "bus_slave", 3602 "slave_q2a", 3603 "noc_aggr"; 3604 3605 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3606 assigned-clock-rates = <19200000>; 3607 3608 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3610 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3611 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3612 interconnect-names = "pcie-mem", 3613 "cpu-pcie"; 3614 3615 resets = <&gcc GCC_PCIE_3B_BCR>, 3616 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3617 reset-names = "pci", 3618 "link_down"; 3619 3620 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3621 3622 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3623 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3624 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3625 3626 status = "disabled"; 3627 3628 pcie3b_opp_table: opp-table { 3629 compatible = "operating-points-v2"; 3630 3631 /* GEN 1 x1 */ 3632 opp-2500000-1 { 3633 opp-hz = /bits/ 64 <2500000>; 3634 required-opps = <&rpmhpd_opp_low_svs>; 3635 opp-peak-kBps = <250000 1>; 3636 opp-level = <1>; 3637 }; 3638 3639 /* GEN 1 x2 */ 3640 opp-5000000-1 { 3641 opp-hz = /bits/ 64 <5000000>; 3642 required-opps = <&rpmhpd_opp_low_svs>; 3643 opp-peak-kBps = <500000 1>; 3644 opp-level = <1>; 3645 }; 3646 3647 /* GEN 1 x4 */ 3648 opp-10000000-1 { 3649 opp-hz = /bits/ 64 <10000000>; 3650 required-opps = <&rpmhpd_opp_low_svs>; 3651 opp-peak-kBps = <1000000 1>; 3652 opp-level = <1>; 3653 }; 3654 3655 /* GEN 2 x1 */ 3656 opp-5000000-2 { 3657 opp-hz = /bits/ 64 <5000000>; 3658 required-opps = <&rpmhpd_opp_low_svs>; 3659 opp-peak-kBps = <500000 1>; 3660 opp-level = <2>; 3661 }; 3662 3663 /* GEN 2 x2 */ 3664 opp-10000000-2 { 3665 opp-hz = /bits/ 64 <10000000>; 3666 required-opps = <&rpmhpd_opp_low_svs>; 3667 opp-peak-kBps = <1000000 1>; 3668 opp-level = <2>; 3669 }; 3670 3671 /* GEN 2 x4 */ 3672 opp-20000000-2 { 3673 opp-hz = /bits/ 64 <20000000>; 3674 required-opps = <&rpmhpd_opp_low_svs>; 3675 opp-peak-kBps = <2000000 1>; 3676 opp-level = <2>; 3677 }; 3678 3679 /* GEN 3 x1 */ 3680 opp-8000000-3 { 3681 opp-hz = /bits/ 64 <8000000>; 3682 required-opps = <&rpmhpd_opp_low_svs>; 3683 opp-peak-kBps = <984500 1>; 3684 opp-level = <3>; 3685 }; 3686 3687 /* GEN 3 x2 */ 3688 opp-16000000-3 { 3689 opp-hz = /bits/ 64 <16000000>; 3690 required-opps = <&rpmhpd_opp_low_svs>; 3691 opp-peak-kBps = <1969000 1>; 3692 opp-level = <3>; 3693 }; 3694 3695 /* GEN 3 x4 */ 3696 opp-32000000-3 { 3697 opp-hz = /bits/ 64 <32000000>; 3698 required-opps = <&rpmhpd_opp_low_svs>; 3699 opp-peak-kBps = <3938000 1>; 3700 opp-level = <3>; 3701 }; 3702 3703 /* GEN 4 x1 */ 3704 opp-16000000-4 { 3705 opp-hz = /bits/ 64 <16000000>; 3706 required-opps = <&rpmhpd_opp_svs>; 3707 opp-peak-kBps = <1969000 1>; 3708 opp-level = <4>; 3709 }; 3710 3711 /* GEN 4 x2 */ 3712 opp-32000000-4 { 3713 opp-hz = /bits/ 64 <32000000>; 3714 required-opps = <&rpmhpd_opp_svs>; 3715 opp-peak-kBps = <3938000 1>; 3716 opp-level = <4>; 3717 }; 3718 3719 /* GEN 4 x4 */ 3720 opp-64000000-4 { 3721 opp-hz = /bits/ 64 <64000000>; 3722 required-opps = <&rpmhpd_opp_svs>; 3723 opp-peak-kBps = <7876000 1>; 3724 opp-level = <4>; 3725 }; 3726 3727 /* GEN 5 x1 */ 3728 opp-32000000-5 { 3729 opp-hz = /bits/ 64 <32000000>; 3730 required-opps = <&rpmhpd_opp_nom>; 3731 opp-peak-kBps = <3938000 1>; 3732 opp-level = <5>; 3733 }; 3734 3735 /* GEN 5 x2 */ 3736 opp-64000000-5 { 3737 opp-hz = /bits/ 64 <64000000>; 3738 required-opps = <&rpmhpd_opp_nom>; 3739 opp-peak-kBps = <7876000 1>; 3740 opp-level = <5>; 3741 }; 3742 3743 /* GEN 5 x4 */ 3744 opp-128000000-5 { 3745 opp-hz = /bits/ 64 <128000000>; 3746 required-opps = <&rpmhpd_opp_nom>; 3747 opp-peak-kBps = <15753000 1>; 3748 opp-level = <5>; 3749 }; 3750 }; 3751 3752 pcie3b_port0: pcie@0 { 3753 device_type = "pci"; 3754 compatible = "pciclass,0604"; 3755 reg = <0x0 0x0 0x0 0x0 0x0>; 3756 bus-range = <0x01 0xff>; 3757 3758 #address-cells = <3>; 3759 #size-cells = <2>; 3760 ranges; 3761 3762 port { 3763 pcie3b_port0_ep: endpoint { 3764 }; 3765 }; 3766 }; 3767 }; 3768 3769 rng: rng@10c3000 { 3770 compatible = "qcom,glymur-trng", "qcom,trng"; 3771 reg = <0x0 0x010c3000 0x0 0x1000>; 3772 }; 3773 3774 cryptobam: dma-controller@1dc4000 { 3775 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 3776 reg = <0x0 0x01dc4000 0x0 0x28000>; 3777 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3778 #dma-cells = <1>; 3779 iommus = <&apps_smmu 0x80 0x0>, 3780 <&apps_smmu 0x81 0x0>; 3781 qcom,ee = <0>; 3782 qcom,controlled-remotely; 3783 num-channels = <20>; 3784 qcom,num-ees = <4>; 3785 }; 3786 3787 crypto: crypto@1dfa000 { 3788 compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; 3789 reg = <0x0 0x01dfa000 0x0 0x6000>; 3790 dmas = <&cryptobam 4>, <&cryptobam 5>; 3791 dma-names = "rx", 3792 "tx"; 3793 iommus = <&apps_smmu 0x80 0x0>, 3794 <&apps_smmu 0x81 0x0>; 3795 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 3796 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3797 interconnect-names = "memory"; 3798 }; 3799 3800 tcsr_mutex: hwlock@1f40000 { 3801 compatible = "qcom,tcsr-mutex"; 3802 reg = <0x0 0x01f40000 0x0 0x20000>; 3803 3804 #hwlock-cells = <1>; 3805 }; 3806 3807 tcsr: clock-controller@1fd5000 { 3808 compatible = "qcom,glymur-tcsr", 3809 "syscon"; 3810 reg = <0x0 0x1fd5000 0x0 0x21000>; 3811 clocks = <&rpmhcc RPMH_CXO_CLK>; 3812 #clock-cells = <1>; 3813 #reset-cells = <1>; 3814 }; 3815 3816 hsc_noc: interconnect@2000000 { 3817 compatible = "qcom,glymur-hscnoc"; 3818 reg = <0x0 0x02000000 0x0 0x93a080>; 3819 qcom,bcm-voters = <&apps_bcm_voter>; 3820 #interconnect-cells = <2>; 3821 }; 3822 3823 gpu: gpu@3d00000 { 3824 compatible = "qcom,adreno-44070001", "qcom,adreno"; 3825 reg = <0x0 0x03d00000 0x0 0x6c000>, 3826 <0x0 0x03d9e000 0x0 0x2000>; 3827 reg-names = "kgsl_3d0_reg_memory", 3828 "cx_mem"; 3829 3830 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3831 3832 iommus = <&adreno_smmu 0 0x0>, 3833 <&adreno_smmu 1 0x0>; 3834 3835 operating-points-v2 = <&gpu_opp_table>; 3836 3837 qcom,gmu = <&gmu>; 3838 #cooling-cells = <2>; 3839 3840 interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 3841 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 3842 interconnect-names = "gfx-mem"; 3843 3844 gpu_opp_table: opp-table { 3845 compatible = "operating-points-v2-adreno", 3846 "operating-points-v2"; 3847 3848 opp-310000000 { 3849 opp-hz = /bits/ 64 <310000000>; 3850 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3851 opp-peak-kBps = <2136719>; 3852 opp-supported-hw = <0xf>; 3853 /* ACD is disabled */ 3854 }; 3855 3856 opp-410000000 { 3857 opp-hz = /bits/ 64 <410000000>; 3858 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3859 opp-peak-kBps = <6074219>; 3860 opp-supported-hw = <0xf>; 3861 /* ACD is disabled */ 3862 }; 3863 3864 opp-572000000 { 3865 opp-hz = /bits/ 64 <572000000>; 3866 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3867 opp-peak-kBps = <12449219>; 3868 opp-supported-hw = <0xf>; 3869 qcom,opp-acd-level = <0xe02d5ffd>; 3870 }; 3871 3872 opp-760000000 { 3873 opp-hz = /bits/ 64 <760000000>; 3874 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3875 opp-peak-kBps = <12449219>; 3876 opp-supported-hw = <0xf>; 3877 qcom,opp-acd-level = <0xc0285ffd>; 3878 }; 3879 3880 opp-820000000 { 3881 opp-hz = /bits/ 64 <820000000>; 3882 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3883 opp-peak-kBps = <16500000>; 3884 opp-supported-hw = <0xf>; 3885 qcom,opp-acd-level = <0xa82e5ffd>; 3886 }; 3887 3888 opp-915000000 { 3889 opp-hz = /bits/ 64 <915000000>; 3890 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3891 opp-peak-kBps = <16500000>; 3892 opp-supported-hw = <0xf>; 3893 qcom,opp-acd-level = <0x882d5ffd>; 3894 }; 3895 3896 opp-1070000000 { 3897 opp-hz = /bits/ 64 <1070000000>; 3898 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3899 opp-peak-kBps = <16500000>; 3900 opp-supported-hw = <0xf>; 3901 qcom,opp-acd-level = <0x882b5ffd>; 3902 }; 3903 3904 opp-1185000000 { 3905 opp-hz = /bits/ 64 <1185000000>; 3906 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3907 opp-peak-kBps = <16500000>; 3908 opp-supported-hw = <0xf>; 3909 qcom,opp-acd-level = <0x882a5ffd>; 3910 }; 3911 3912 opp-1350000000 { 3913 opp-hz = /bits/ 64 <1350000000>; 3914 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3915 opp-peak-kBps = <18597657>; 3916 opp-supported-hw = <0xf>; 3917 qcom,opp-acd-level = <0x882a5ffd>; 3918 }; 3919 3920 opp-1550000000 { 3921 opp-hz = /bits/ 64 <1550000000>; 3922 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3923 opp-peak-kBps = <18597657>; 3924 opp-supported-hw = <0x7>; 3925 qcom,opp-acd-level = <0xa8295ffd>; 3926 }; 3927 3928 opp-1700000000 { 3929 opp-hz = /bits/ 64 <1700000000>; 3930 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3931 opp-peak-kBps = <18597657>; 3932 opp-supported-hw = <0x7>; 3933 qcom,opp-acd-level = <0x88295ffd>; 3934 }; 3935 3936 opp-1850000000 { 3937 opp-hz = /bits/ 64 <1850000000>; 3938 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 3939 opp-peak-kBps = <18597657>; 3940 opp-supported-hw = <0x3>; 3941 qcom,opp-acd-level = <0x88285ffd>; 3942 }; 3943 }; 3944 }; 3945 3946 gxclkctl: clock-controller@3d64000 { 3947 compatible = "qcom,glymur-gxclkctl"; 3948 reg = <0x0 0x03d64000 0x0 0x6000>; 3949 3950 power-domains = <&rpmhpd RPMHPD_GFX>, 3951 <&rpmhpd RPMHPD_GMXC>, 3952 <&gpucc GPU_CC_CX_GDSC>; 3953 3954 #power-domain-cells = <1>; 3955 }; 3956 3957 gmu: gmu@3d6c000 { 3958 compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; 3959 3960 reg = <0x0 0x03d6c000 0x0 0x32000>; 3961 reg-names = "gmu"; 3962 3963 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3964 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3965 interrupt-names = "hfi", 3966 "gmu"; 3967 3968 clocks = <&gpucc GPU_CC_AHB_CLK>, 3969 <&gpucc GPU_CC_CX_GMU_CLK>, 3970 <&gpucc GPU_CC_CXO_CLK>, 3971 <&gcc GCC_GPU_GEMNOC_GFX_CLK>, 3972 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3973 <&gpucc GPU_CC_RSCC_HUB_AON_CLK>; 3974 clock-names = "ahb", 3975 "gmu", 3976 "cxo", 3977 "memnoc", 3978 "hub", 3979 "rscc"; 3980 3981 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3982 <&gxclkctl GX_CLKCTL_GX_GDSC>; 3983 power-domain-names = "cx", 3984 "gx"; 3985 3986 iommus = <&adreno_smmu 5 0x0>; 3987 3988 qcom,qmp = <&aoss_qmp>; 3989 3990 operating-points-v2 = <&gmu_opp_table>; 3991 3992 gmu_opp_table: opp-table { 3993 compatible = "operating-points-v2"; 3994 3995 opp-575000000 { 3996 opp-hz = /bits/ 64 <575000000>; 3997 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3998 }; 3999 4000 opp-700000000 { 4001 opp-hz = /bits/ 64 <700000000>; 4002 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4003 }; 4004 4005 opp-725000000 { 4006 opp-hz = /bits/ 64 <725000000>; 4007 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4008 }; 4009 4010 opp-750000000 { 4011 opp-hz = /bits/ 64 <750000000>; 4012 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4013 }; 4014 }; 4015 }; 4016 4017 gpucc: clock-controller@3d90000 { 4018 compatible = "qcom,glymur-gpucc"; 4019 reg = <0x0 0x03d90000 0x0 0x9800>; 4020 clocks = <&rpmhcc RPMH_CXO_CLK>, 4021 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4022 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4023 4024 power-domains = <&rpmhpd RPMHPD_MX>, 4025 <&rpmhpd RPMHPD_CX>; 4026 required-opps = <&rpmhpd_opp_low_svs>, 4027 <&rpmhpd_opp_low_svs>; 4028 4029 #clock-cells = <1>; 4030 #reset-cells = <1>; 4031 #power-domain-cells = <1>; 4032 }; 4033 4034 adreno_smmu: iommu@3da0000 { 4035 compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", 4036 "qcom,smmu-500", "arm,mmu-500"; 4037 reg = <0x0 0x03da0000 0x0 0x40000>; 4038 #iommu-cells = <2>; 4039 #global-interrupts = <1>; 4040 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4066 clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; 4067 clock-names = "hlos"; 4068 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4069 dma-coherent; 4070 }; 4071 4072 ipcc: mailbox@3e04000 { 4073 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 4074 reg = <0x0 0x03e04000 0x0 0x1000>; 4075 4076 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 4077 interrupt-controller; 4078 #interrupt-cells = <3>; 4079 4080 #mbox-cells = <2>; 4081 }; 4082 4083 remoteproc_adsp: remoteproc@6800000 { 4084 compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; 4085 reg = <0x0 0x06800000 0x0 0x10000>; 4086 4087 iommus = <&apps_smmu 0x1000 0x0>; 4088 4089 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4090 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4091 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4092 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4093 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 4094 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 4095 interrupt-names = "wdog", 4096 "fatal", 4097 "ready", 4098 "handover", 4099 "stop-ack", 4100 "shutdown-ack"; 4101 4102 clocks = <&rpmhcc RPMH_CXO_CLK>; 4103 clock-names = "xo"; 4104 4105 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4106 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4107 4108 power-domains = <&rpmhpd RPMHPD_LCX>, 4109 <&rpmhpd RPMHPD_LMX>; 4110 power-domain-names = "lcx", 4111 "lmx"; 4112 4113 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4114 4115 qcom,qmp = <&aoss_qmp>; 4116 4117 qcom,smem-states = <&smp2p_adsp_out 0>; 4118 qcom,smem-state-names = "stop"; 4119 4120 status = "disabled"; 4121 4122 remoteproc_adsp_glink: glink-edge { 4123 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 4124 IPCC_MPROC_SIGNAL_GLINK_QMP 4125 IRQ_TYPE_EDGE_RISING>; 4126 4127 mboxes = <&ipcc IPCC_MPROC_LPASS 4128 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4129 4130 qcom,remote-pid = <2>; 4131 4132 label = "lpass"; 4133 4134 fastrpc { 4135 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 4136 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4137 label = "adsp"; 4138 memory-region = <&adsp_rpc_remote_heap_mem>; 4139 qcom,vmids = <QCOM_SCM_VMID_LPASS 4140 QCOM_SCM_VMID_ADSP_HEAP>; 4141 #address-cells = <1>; 4142 #size-cells = <0>; 4143 4144 compute-cb@3 { 4145 compatible = "qcom,fastrpc-compute-cb"; 4146 reg = <3>; 4147 4148 iommus = <&apps_smmu 0x1003 0x80>, 4149 <&apps_smmu 0x1063 0x20>; 4150 dma-coherent; 4151 }; 4152 4153 compute-cb@4 { 4154 compatible = "qcom,fastrpc-compute-cb"; 4155 reg = <4>; 4156 4157 iommus = <&apps_smmu 0x1004 0x80>, 4158 <&apps_smmu 0x1064 0x20>; 4159 dma-coherent; 4160 }; 4161 4162 compute-cb@5 { 4163 compatible = "qcom,fastrpc-compute-cb"; 4164 reg = <5>; 4165 4166 iommus = <&apps_smmu 0x1005 0x80>, 4167 <&apps_smmu 0x1065 0x20>; 4168 dma-coherent; 4169 }; 4170 4171 compute-cb@6 { 4172 compatible = "qcom,fastrpc-compute-cb"; 4173 reg = <6>; 4174 4175 iommus = <&apps_smmu 0x1006 0x80>, 4176 <&apps_smmu 0x1066 0x20>; 4177 dma-coherent; 4178 }; 4179 4180 compute-cb@7 { 4181 compatible = "qcom,fastrpc-compute-cb"; 4182 reg = <7>; 4183 4184 iommus = <&apps_smmu 0x1007 0x40>, 4185 <&apps_smmu 0x1067 0x0>, 4186 <&apps_smmu 0x1087 0x0>; 4187 dma-coherent; 4188 }; 4189 4190 compute-cb@8 { 4191 compatible = "qcom,fastrpc-compute-cb"; 4192 reg = <8>; 4193 4194 iommus = <&apps_smmu 0x1008 0x80>, 4195 <&apps_smmu 0x1068 0x20>; 4196 dma-coherent; 4197 }; 4198 }; 4199 4200 gpr { 4201 compatible = "qcom,gpr"; 4202 qcom,glink-channels = "adsp_apps"; 4203 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4204 qcom,intents = <512 20>; 4205 #address-cells = <1>; 4206 #size-cells = <0>; 4207 4208 q6apm: service@1 { 4209 compatible = "qcom,q6apm"; 4210 reg = <GPR_APM_MODULE_IID>; 4211 #sound-dai-cells = <0>; 4212 qcom,protection-domain = "avs/audio", 4213 "msm/adsp/audio_pd"; 4214 4215 q6apmbedai: bedais { 4216 compatible = "qcom,q6apm-lpass-dais"; 4217 #sound-dai-cells = <1>; 4218 }; 4219 4220 q6apmdai: dais { 4221 compatible = "qcom,q6apm-dais"; 4222 iommus = <&apps_smmu 0x1001 0x80>, 4223 <&apps_smmu 0x1061 0x20>; 4224 }; 4225 }; 4226 4227 q6prm: service@2 { 4228 compatible = "qcom,q6prm"; 4229 reg = <GPR_PRM_MODULE_IID>; 4230 qcom,protection-domain = "avs/audio", 4231 "msm/adsp/audio_pd"; 4232 4233 q6prmcc: clock-controller { 4234 compatible = "qcom,q6prm-lpass-clocks"; 4235 #clock-cells = <2>; 4236 }; 4237 }; 4238 }; 4239 }; 4240 }; 4241 4242 swr0: soundwire@6c80000 { 4243 compatible = "qcom,soundwire-v3.1.0"; 4244 reg = <0x0 0x06c80000 0x0 0x10000>; 4245 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4246 clocks = <&lpass_wsamacro>; 4247 clock-names = "iface"; 4248 label = "WSA"; 4249 4250 pinctrl-0 = <&wsa_swr_active>; 4251 pinctrl-names = "default"; 4252 4253 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; 4254 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; 4255 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; 4256 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4257 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; 4258 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; 4259 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; 4260 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4261 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4262 #address-cells = <2>; 4263 #size-cells = <0>; 4264 #sound-dai-cells = <1>; 4265 status = "disabled"; 4266 }; 4267 4268 lpass_wsamacro: codec@6c90000 { 4269 compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4270 reg = <0x0 0x06c90000 0x0 0x1000>; 4271 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4272 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4273 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4274 <&lpass_vamacro>; 4275 clock-names = "mclk", 4276 "macro", 4277 "dcodec", 4278 "fsgen"; 4279 4280 #clock-cells = <0>; 4281 clock-output-names = "mclk"; 4282 #sound-dai-cells = <1>; 4283 sound-name-prefix = "WSA"; 4284 }; 4285 4286 swr3: soundwire@6ca0000 { 4287 compatible = "qcom,soundwire-v3.1.0"; 4288 reg = <0x0 0x06ca0000 0x0 0x10000>; 4289 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4290 clocks = <&lpass_wsa2macro>; 4291 clock-names = "iface"; 4292 label = "WSA2"; 4293 4294 pinctrl-0 = <&wsa2_swr_active>; 4295 pinctrl-names = "default"; 4296 4297 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; 4298 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; 4299 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; 4300 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4301 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; 4302 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; 4303 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; 4304 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4305 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4306 4307 #address-cells = <2>; 4308 #size-cells = <0>; 4309 #sound-dai-cells = <1>; 4310 status = "disabled"; 4311 }; 4312 4313 lpass_wsa2macro: codec@6cb0000 { 4314 compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4315 reg = <0x0 0x06cb0000 0x0 0x1000>; 4316 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4317 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4318 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4319 <&lpass_vamacro>; 4320 clock-names = "mclk", 4321 "macro", 4322 "dcodec", 4323 "fsgen"; 4324 4325 #clock-cells = <0>; 4326 clock-output-names = "wsa2-mclk"; 4327 #sound-dai-cells = <1>; 4328 sound-name-prefix = "WSA2"; 4329 }; 4330 4331 lpass_lpiaon_noc: interconnect@7400000 { 4332 compatible = "qcom,glymur-lpass-lpiaon-noc"; 4333 reg = <0x0 0x07400000 0x0 0x19080>; 4334 qcom,bcm-voters = <&apps_bcm_voter>; 4335 #interconnect-cells = <2>; 4336 }; 4337 4338 lpass_lpicx_noc: interconnect@7420000 { 4339 compatible = "qcom,glymur-lpass-lpicx-noc"; 4340 reg = <0x0 0x07420000 0x0 0x44080>; 4341 qcom,bcm-voters = <&apps_bcm_voter>; 4342 #interconnect-cells = <2>; 4343 }; 4344 4345 lpass_vamacro: codec@7660000 { 4346 compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4347 reg = <0x0 0x07660000 0x0 0x2000>; 4348 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4349 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4350 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4351 clock-names = "mclk", 4352 "macro", 4353 "dcodec"; 4354 4355 #clock-cells = <0>; 4356 clock-output-names = "fsgen"; 4357 #sound-dai-cells = <1>; 4358 }; 4359 4360 lpass_tlmm: pinctrl@7760000 { 4361 compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl"; 4362 reg = <0x0 0x07760000 0x0 0x20000>; 4363 4364 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4365 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4366 clock-names = "core", "audio"; 4367 4368 gpio-controller; 4369 #gpio-cells = <2>; 4370 gpio-ranges = <&lpass_tlmm 0 0 23>; 4371 4372 tx_swr_active: tx-swr-active-state { 4373 clk-pins { 4374 pins = "gpio0"; 4375 function = "swr_tx_clk"; 4376 drive-strength = <2>; 4377 slew-rate = <1>; 4378 bias-disable; 4379 }; 4380 4381 data-pins { 4382 pins = "gpio1", "gpio2"; 4383 function = "swr_tx_data"; 4384 drive-strength = <2>; 4385 slew-rate = <1>; 4386 bias-bus-hold; 4387 }; 4388 }; 4389 4390 rx_swr_active: rx-swr-active-state { 4391 clk-pins { 4392 pins = "gpio3"; 4393 function = "swr_rx_clk"; 4394 drive-strength = <2>; 4395 slew-rate = <1>; 4396 bias-disable; 4397 }; 4398 4399 data-pins { 4400 pins = "gpio4", "gpio5"; 4401 function = "swr_rx_data"; 4402 drive-strength = <2>; 4403 slew-rate = <1>; 4404 bias-bus-hold; 4405 }; 4406 }; 4407 4408 dmic01_default: dmic01-default-state { 4409 clk-pins { 4410 pins = "gpio6"; 4411 function = "dmic1_clk"; 4412 drive-strength = <8>; 4413 output-high; 4414 }; 4415 4416 data-pins { 4417 pins = "gpio7"; 4418 function = "dmic1_data"; 4419 drive-strength = <8>; 4420 input-enable; 4421 }; 4422 }; 4423 4424 dmic23_default: dmic23-default-state { 4425 clk-pins { 4426 pins = "gpio8"; 4427 function = "dmic2_clk"; 4428 drive-strength = <8>; 4429 output-high; 4430 }; 4431 4432 data-pins { 4433 pins = "gpio9"; 4434 function = "dmic2_data"; 4435 drive-strength = <8>; 4436 input-enable; 4437 }; 4438 }; 4439 4440 wsa_swr_active: wsa-swr-active-state { 4441 clk-pins { 4442 pins = "gpio10"; 4443 function = "wsa_swr_clk"; 4444 drive-strength = <2>; 4445 slew-rate = <1>; 4446 bias-disable; 4447 }; 4448 4449 data-pins { 4450 pins = "gpio11"; 4451 function = "wsa_swr_data"; 4452 drive-strength = <2>; 4453 slew-rate = <1>; 4454 bias-bus-hold; 4455 }; 4456 }; 4457 4458 wsa2_swr_active: wsa2-swr-active-state { 4459 clk-pins { 4460 pins = "gpio15"; 4461 function = "wsa2_swr_clk"; 4462 drive-strength = <2>; 4463 slew-rate = <1>; 4464 bias-disable; 4465 }; 4466 4467 data-pins { 4468 pins = "gpio16"; 4469 function = "wsa2_swr_data"; 4470 drive-strength = <2>; 4471 slew-rate = <1>; 4472 bias-bus-hold; 4473 }; 4474 }; 4475 }; 4476 4477 lpass_ag_noc: interconnect@7e40000 { 4478 compatible = "qcom,glymur-lpass-ag-noc"; 4479 reg = <0x0 0x07e40000 0x0 0xe080>; 4480 qcom,bcm-voters = <&apps_bcm_voter>; 4481 #interconnect-cells = <2>; 4482 }; 4483 4484 usb_2_hsphy: phy@88e0000 { 4485 compatible = "qcom,glymur-m31-eusb2-phy", 4486 "qcom,sm8750-m31-eusb2-phy"; 4487 4488 reg = <0x0 0x088e0000 0x0 0x29c>; 4489 #phy-cells = <0>; 4490 4491 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 4492 clock-names = "ref"; 4493 4494 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 4495 4496 status = "disabled"; 4497 }; 4498 4499 usb_2_qmpphy: phy@88e1000 { 4500 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 4501 reg = <0x0 0x088e1000 0x0 0x8000>; 4502 4503 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 4504 <&tcsr TCSR_USB4_2_CLKREF_EN>, 4505 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 4506 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 4507 clock-names = "aux", 4508 "ref", 4509 "com_aux", 4510 "usb3_pipe"; 4511 4512 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 4513 4514 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 4515 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 4516 reset-names = "phy", 4517 "common"; 4518 4519 #clock-cells = <1>; 4520 #phy-cells = <1>; 4521 4522 mode-switch; 4523 orientation-switch; 4524 4525 status = "disabled"; 4526 4527 ports { 4528 #address-cells = <1>; 4529 #size-cells = <0>; 4530 4531 port@0 { 4532 reg = <0>; 4533 4534 usb_2_qmpphy_out: endpoint { 4535 }; 4536 }; 4537 4538 port@1 { 4539 reg = <1>; 4540 4541 usb_2_qmpphy_usb_ss_in: endpoint { 4542 remote-endpoint = <&usb_2_dwc3_ss>; 4543 }; 4544 }; 4545 4546 port@2 { 4547 reg = <2>; 4548 4549 usb_2_qmpphy_dp_in: endpoint { 4550 remote-endpoint = <&mdss_dp2_out>; 4551 }; 4552 }; 4553 }; 4554 }; 4555 4556 usb_0: usb@a600000 { 4557 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4558 reg = <0x0 0x0a600000 0x0 0xfc100>; 4559 4560 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4561 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4562 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4563 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4564 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4565 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4566 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4567 clock-names = "cfg_noc", 4568 "core", 4569 "iface", 4570 "sleep", 4571 "mock_utmi", 4572 "noc_aggr_north", 4573 "noc_aggr_south"; 4574 4575 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4576 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4577 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 4578 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4579 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 4580 interrupt-names = "dwc_usb3", 4581 "pwr_event", 4582 "dp_hs_phy_irq", 4583 "dm_hs_phy_irq", 4584 "ss_phy_irq"; 4585 4586 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4587 resets = <&gcc GCC_USB30_PRIM_BCR>; 4588 4589 iommus = <&apps_smmu 0x1420 0x0>; 4590 phys = <&usb_0_hsphy>, 4591 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4592 phy-names = "usb2-phy", 4593 "usb3-phy"; 4594 4595 snps,hird-threshold = /bits/ 8 <0x0>; 4596 snps,dis-u1-entry-quirk; 4597 snps,dis-u2-entry-quirk; 4598 snps,is-utmi-l1-suspend; 4599 snps,usb3_lpm_capable; 4600 snps,has-lpm-erratum; 4601 tx-fifo-resize; 4602 snps,dis_u2_susphy_quirk; 4603 snps,dis_enblslpm_quirk; 4604 4605 usb-role-switch; 4606 wakeup-source; 4607 4608 status = "disabled"; 4609 4610 ports { 4611 #address-cells = <1>; 4612 #size-cells = <0>; 4613 4614 port@0 { 4615 reg = <0>; 4616 4617 usb_0_dwc3_hs: endpoint { 4618 }; 4619 }; 4620 4621 port@1 { 4622 reg = <1>; 4623 4624 usb_0_dwc3_ss: endpoint { 4625 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 4626 }; 4627 }; 4628 }; 4629 }; 4630 4631 usb_1: usb@a800000 { 4632 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4633 reg = <0x0 0x0a800000 0x0 0xfc100>; 4634 4635 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4636 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4637 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4638 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4639 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4640 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4641 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4642 clock-names = "cfg_noc", 4643 "core", 4644 "iface", 4645 "sleep", 4646 "mock_utmi", 4647 "noc_aggr_north", 4648 "noc_aggr_south"; 4649 4650 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 4651 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 4652 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 4653 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 4654 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 4655 interrupt-names = "dwc_usb3", 4656 "pwr_event", 4657 "dp_hs_phy_irq", 4658 "dm_hs_phy_irq", 4659 "ss_phy_irq"; 4660 4661 resets = <&gcc GCC_USB30_SEC_BCR>; 4662 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4663 4664 iommus = <&apps_smmu 0x1460 0x0>; 4665 4666 phys = <&usb_1_hsphy>, 4667 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4668 phy-names = "usb2-phy", 4669 "usb3-phy"; 4670 4671 snps,hird-threshold = /bits/ 8 <0x0>; 4672 snps,dis-u1-entry-quirk; 4673 snps,dis-u2-entry-quirk; 4674 snps,is-utmi-l1-suspend; 4675 snps,usb3_lpm_capable; 4676 snps,has-lpm-erratum; 4677 tx-fifo-resize; 4678 snps,dis_u2_susphy_quirk; 4679 snps,dis_enblslpm_quirk; 4680 4681 usb-role-switch; 4682 wakeup-source; 4683 4684 status = "disabled"; 4685 4686 ports { 4687 #address-cells = <1>; 4688 #size-cells = <0>; 4689 4690 port@0 { 4691 reg = <0>; 4692 4693 usb_1_dwc3_hs: endpoint { 4694 }; 4695 }; 4696 4697 port@1 { 4698 reg = <1>; 4699 4700 usb_1_dwc3_ss: endpoint { 4701 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4702 }; 4703 }; 4704 }; 4705 }; 4706 4707 usb_2: usb@a000000 { 4708 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4709 reg = <0x0 0x0a000000 0x0 0xfc100>; 4710 4711 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 4712 <&gcc GCC_USB30_TERT_MASTER_CLK>, 4713 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 4714 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 4715 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 4716 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4717 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4718 clock-names = "cfg_noc", 4719 "core", 4720 "iface", 4721 "sleep", 4722 "mock_utmi", 4723 "noc_aggr_north", 4724 "noc_aggr_south"; 4725 4726 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 4727 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 4728 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 4729 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 4730 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 4731 interrupt-names = "dwc_usb3", 4732 "pwr_event", 4733 "dp_hs_phy_irq", 4734 "dm_hs_phy_irq", 4735 "ss_phy_irq"; 4736 4737 resets = <&gcc GCC_USB30_TERT_BCR>; 4738 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 4739 4740 iommus = <&apps_smmu 0x420 0x0>; 4741 4742 phys = <&usb_2_hsphy>, 4743 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 4744 phy-names = "usb2-phy", 4745 "usb3-phy"; 4746 4747 snps,hird-threshold = /bits/ 8 <0x0>; 4748 snps,dis-u1-entry-quirk; 4749 snps,dis-u2-entry-quirk; 4750 snps,is-utmi-l1-suspend; 4751 snps,usb3_lpm_capable; 4752 snps,has-lpm-erratum; 4753 tx-fifo-resize; 4754 snps,dis_u2_susphy_quirk; 4755 snps,dis_enblslpm_quirk; 4756 4757 usb-role-switch; 4758 wakeup-source; 4759 4760 status = "disabled"; 4761 4762 ports { 4763 #address-cells = <1>; 4764 #size-cells = <0>; 4765 4766 port@0 { 4767 reg = <0>; 4768 4769 usb_2_dwc3_hs: endpoint { 4770 }; 4771 }; 4772 4773 port@1 { 4774 reg = <1>; 4775 4776 usb_2_dwc3_ss: endpoint { 4777 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4778 }; 4779 }; 4780 }; 4781 }; 4782 4783 usb_hs: usb@a200000 { 4784 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4785 reg = <0x0 0x0a200000 0x0 0xfc100>; 4786 4787 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4788 <&gcc GCC_USB20_MASTER_CLK>, 4789 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4790 <&gcc GCC_USB20_SLEEP_CLK>, 4791 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4792 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4793 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4794 clock-names = "cfg_noc", 4795 "core", 4796 "iface", 4797 "sleep", 4798 "mock_utmi", 4799 "noc_aggr_north", 4800 "noc_aggr_south"; 4801 4802 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4803 <&gcc GCC_USB20_MASTER_CLK>; 4804 assigned-clock-rates = <19200000>, <200000000>; 4805 4806 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4807 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4808 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4809 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4810 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4811 interrupt-names = "dwc_usb3", 4812 "pwr_event", 4813 "dp_hs_phy_irq", 4814 "dm_hs_phy_irq", 4815 "hs_phy_irq"; 4816 4817 resets = <&gcc GCC_USB20_PRIM_BCR>; 4818 4819 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4820 required-opps = <&rpmhpd_opp_nom>; 4821 4822 iommus = <&apps_smmu 0x0ce0 0x0>; 4823 4824 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4825 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4826 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4827 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4828 interconnect-names = "usb-ddr", 4829 "apps-usb"; 4830 4831 phys = <&usb_hs_phy>; 4832 phy-names = "usb2-phy"; 4833 4834 snps,hird-threshold = /bits/ 8 <0x0>; 4835 snps,dis-u1-entry-quirk; 4836 snps,dis-u2-entry-quirk; 4837 snps,is-utmi-l1-suspend; 4838 snps,usb3_lpm_capable; 4839 snps,has-lpm-erratum; 4840 tx-fifo-resize; 4841 snps,dis_u2_susphy_quirk; 4842 snps,dis_enblslpm_quirk; 4843 4844 maximum-speed = "high-speed"; 4845 4846 qcom,select-utmi-as-pipe-clk; 4847 usb-role-switch; 4848 wakeup-source; 4849 4850 status = "disabled"; 4851 }; 4852 4853 usb_mp: usb@a400000 { 4854 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4855 reg = <0x0 0x0a400000 0x0 0xfc100>; 4856 4857 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4858 <&gcc GCC_USB30_MP_MASTER_CLK>, 4859 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4860 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4861 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4862 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4863 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4864 clock-names = "cfg_noc", 4865 "core", 4866 "iface", 4867 "sleep", 4868 "mock_utmi", 4869 "noc_aggr_north", 4870 "noc_aggr_south"; 4871 4872 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4873 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4874 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4875 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4876 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4877 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4878 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4879 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4880 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4881 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4882 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4883 interrupt-names = "dwc_usb3", 4884 "pwr_event_1", 4885 "pwr_event_2", 4886 "hs_phy_1", 4887 "hs_phy_2", 4888 "dp_hs_phy_1", 4889 "dm_hs_phy_1", 4890 "dp_hs_phy_2", 4891 "dm_hs_phy_2", 4892 "ss_phy_1", 4893 "ss_phy_2"; 4894 4895 resets = <&gcc GCC_USB30_MP_BCR>; 4896 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4897 4898 iommus = <&apps_smmu 0xda0 0x0>; 4899 4900 phys = <&usb_mp_hsphy0>, 4901 <&usb_mp_qmpphy0>, 4902 <&usb_mp_hsphy1>, 4903 <&usb_mp_qmpphy1>; 4904 phy-names = "usb2-0", 4905 "usb3-0", 4906 "usb2-1", 4907 "usb3-1"; 4908 4909 snps,hird-threshold = /bits/ 8 <0x0>; 4910 snps,dis-u1-entry-quirk; 4911 snps,dis-u2-entry-quirk; 4912 snps,is-utmi-l1-suspend; 4913 snps,usb3_lpm_capable; 4914 snps,has-lpm-erratum; 4915 tx-fifo-resize; 4916 snps,dis_u2_susphy_quirk; 4917 snps,dis_enblslpm_quirk; 4918 4919 dr_mode = "host"; 4920 wakeup-source; 4921 4922 status = "disabled"; 4923 }; 4924 4925 camcc: clock-controller@ade0000 { 4926 compatible = "qcom,glymur-camcc"; 4927 reg = <0x0 0x0ade0000 0x0 0x20000>; 4928 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4929 <&rpmhcc RPMH_CXO_CLK>, 4930 <&rpmhcc RPMH_CXO_CLK_A>, 4931 <&sleep_clk>; 4932 power-domains = <&rpmhpd RPMHPD_MXC>, 4933 <&rpmhpd RPMHPD_MMCX>; 4934 required-opps = <&rpmhpd_opp_low_svs>, 4935 <&rpmhpd_opp_low_svs>; 4936 #clock-cells = <1>; 4937 #reset-cells = <1>; 4938 #power-domain-cells = <1>; 4939 }; 4940 4941 mdss: display-subsystem@ae00000 { 4942 compatible = "qcom,glymur-mdss"; 4943 reg = <0x0 0x0ae00000 0x0 0x1000>; 4944 reg-names = "mdss"; 4945 4946 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4947 4948 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4949 <&gcc GCC_DISP_HF_AXI_CLK>, 4950 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4951 4952 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4953 4954 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4955 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4956 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4957 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4958 interconnect-names = "mdp0-mem", 4959 "cpu-cfg"; 4960 4961 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4962 4963 iommus = <&apps_smmu 0x1de0 0x2>; 4964 4965 interrupt-controller; 4966 #interrupt-cells = <1>; 4967 4968 #address-cells = <2>; 4969 #size-cells = <2>; 4970 ranges; 4971 4972 status = "disabled"; 4973 4974 mdss_mdp: display-controller@ae01000 { 4975 compatible = "qcom,glymur-dpu"; 4976 reg = <0x0 0x0ae01000 0x0 0x93000>, 4977 <0x0 0x0aeb0000 0x0 0x3000>; 4978 reg-names = "mdp", 4979 "vbif"; 4980 4981 interrupts-extended = <&mdss 0>; 4982 4983 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4984 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4985 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4986 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4987 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4988 clock-names = "nrt_bus", 4989 "iface", 4990 "lut", 4991 "core", 4992 "vsync"; 4993 4994 operating-points-v2 = <&mdp_opp_table>; 4995 4996 power-domains = <&rpmhpd RPMHPD_MMCX>; 4997 4998 ports { 4999 #address-cells = <1>; 5000 #size-cells = <0>; 5001 5002 port@0 { 5003 reg = <0>; 5004 5005 dpu_intf0_out: endpoint { 5006 remote-endpoint = <&mdss_dp0_in>; 5007 }; 5008 }; 5009 5010 port@4 { 5011 reg = <4>; 5012 5013 mdss_intf4_out: endpoint { 5014 remote-endpoint = <&mdss_dp1_in>; 5015 }; 5016 }; 5017 5018 port@5 { 5019 reg = <5>; 5020 5021 mdss_intf5_out: endpoint { 5022 remote-endpoint = <&mdss_dp3_in>; 5023 }; 5024 }; 5025 5026 port@6 { 5027 reg = <6>; 5028 5029 mdss_intf6_out: endpoint { 5030 remote-endpoint = <&mdss_dp2_in>; 5031 }; 5032 }; 5033 }; 5034 5035 mdp_opp_table: opp-table { 5036 compatible = "operating-points-v2"; 5037 5038 opp-156000000 { 5039 opp-hz = /bits/ 64 <156000000>; 5040 required-opps = <&rpmhpd_opp_low_svs_d1>; 5041 }; 5042 5043 opp-205000000 { 5044 opp-hz = /bits/ 64 <205000000>; 5045 required-opps = <&rpmhpd_opp_low_svs>; 5046 }; 5047 5048 opp-337000000 { 5049 opp-hz = /bits/ 64 <337000000>; 5050 required-opps = <&rpmhpd_opp_svs>; 5051 }; 5052 5053 opp-417000000 { 5054 opp-hz = /bits/ 64 <417000000>; 5055 required-opps = <&rpmhpd_opp_svs_l1>; 5056 }; 5057 5058 opp-532000000 { 5059 opp-hz = /bits/ 64 <532000000>; 5060 required-opps = <&rpmhpd_opp_nom>; 5061 }; 5062 5063 opp-600000000 { 5064 opp-hz = /bits/ 64 <600000000>; 5065 required-opps = <&rpmhpd_opp_nom_l1>; 5066 }; 5067 5068 opp-660000000 { 5069 opp-hz = /bits/ 64 <660000000>; 5070 required-opps = <&rpmhpd_opp_turbo>; 5071 }; 5072 5073 opp-717000000 { 5074 opp-hz = /bits/ 64 <717000000>; 5075 required-opps = <&rpmhpd_opp_turbo_l1>; 5076 }; 5077 }; 5078 }; 5079 5080 mdss_dp0: displayport-controller@af54000 { 5081 compatible = "qcom,glymur-dp"; 5082 reg = <0x0 0xaf54000 0x0 0x200>, 5083 <0x0 0xaf54200 0x0 0x200>, 5084 <0x0 0xaf55000 0x0 0xc00>, 5085 <0x0 0xaf56000 0x0 0x400>, 5086 <0x0 0xaf57000 0x0 0x400>, 5087 <0x0 0xaf58000 0x0 0x400>, 5088 <0x0 0xaf59000 0x0 0x400>, 5089 <0x0 0xaf5a000 0x0 0x600>, 5090 <0x0 0xaf5b000 0x0 0x600>; 5091 5092 interrupts-extended = <&mdss 12>; 5093 5094 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5095 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5096 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5097 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5098 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5099 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5100 clock-names = "core_iface", 5101 "core_aux", 5102 "ctrl_link", 5103 "ctrl_link_iface", 5104 "stream_pixel", 5105 "stream_1_pixel"; 5106 5107 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5108 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5109 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5110 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5111 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5112 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5113 5114 operating-points-v2 = <&mdss_dp0_opp_table>; 5115 5116 power-domains = <&rpmhpd RPMHPD_MMCX>; 5117 5118 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 5119 phy-names = "dp"; 5120 5121 #sound-dai-cells = <0>; 5122 5123 status = "disabled"; 5124 5125 ports { 5126 #address-cells = <1>; 5127 #size-cells = <0>; 5128 5129 port@0 { 5130 reg = <0>; 5131 5132 mdss_dp0_in: endpoint { 5133 remote-endpoint = <&dpu_intf0_out>; 5134 }; 5135 }; 5136 5137 port@1 { 5138 reg = <1>; 5139 5140 mdss_dp0_out: endpoint { 5141 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5142 }; 5143 }; 5144 }; 5145 5146 mdss_dp0_opp_table: opp-table { 5147 compatible = "operating-points-v2"; 5148 5149 opp-270000000 { 5150 opp-hz = /bits/ 64 <270000000>; 5151 required-opps = <&rpmhpd_opp_low_svs>; 5152 }; 5153 5154 opp-540000000 { 5155 opp-hz = /bits/ 64 <540000000>; 5156 required-opps = <&rpmhpd_opp_svs>; 5157 }; 5158 5159 opp-675000000 { 5160 opp-hz = /bits/ 64 <675000000>; 5161 required-opps = <&rpmhpd_opp_svs_l1>; 5162 }; 5163 5164 opp-810000000 { 5165 opp-hz = /bits/ 64 <810000000>; 5166 required-opps = <&rpmhpd_opp_nom>; 5167 }; 5168 }; 5169 }; 5170 5171 mdss_dp1: displayport-controller@af5c000 { 5172 compatible = "qcom,glymur-dp"; 5173 reg = <0x0 0xaf5c000 0x0 0x200>, 5174 <0x0 0xaf5c200 0x0 0x200>, 5175 <0x0 0xaf5d000 0x0 0xc00>, 5176 <0x0 0xaf5e000 0x0 0x400>, 5177 <0x0 0xaf5f000 0x0 0x400>, 5178 <0x0 0xaf60000 0x0 0x400>, 5179 <0x0 0xaf61000 0x0 0x400>, 5180 <0x0 0xaf62000 0x0 0x600>, 5181 <0x0 0xaf63000 0x0 0x600>; 5182 5183 interrupts-extended = <&mdss 13>; 5184 5185 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5186 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5187 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5188 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5189 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5190 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5191 clock-names = "core_iface", 5192 "core_aux", 5193 "ctrl_link", 5194 "ctrl_link_iface", 5195 "stream_pixel", 5196 "stream_1_pixel"; 5197 5198 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5199 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5200 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5201 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5202 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5203 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5204 5205 operating-points-v2 = <&mdss_dp0_opp_table>; 5206 5207 power-domains = <&rpmhpd RPMHPD_MMCX>; 5208 5209 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5210 phy-names = "dp"; 5211 5212 #sound-dai-cells = <0>; 5213 5214 status = "disabled"; 5215 5216 ports { 5217 #address-cells = <1>; 5218 #size-cells = <0>; 5219 5220 port@0 { 5221 reg = <0>; 5222 5223 mdss_dp1_in: endpoint { 5224 remote-endpoint = <&mdss_intf4_out>; 5225 }; 5226 }; 5227 5228 port@1 { 5229 reg = <1>; 5230 5231 mdss_dp1_out: endpoint { 5232 remote-endpoint = <&usb_1_qmpphy_dp_in>; 5233 }; 5234 }; 5235 }; 5236 }; 5237 5238 mdss_dp2: displayport-controller@af64000 { 5239 compatible = "qcom,glymur-dp"; 5240 reg = <0x0 0x0af64000 0x0 0x200>, 5241 <0x0 0x0af64200 0x0 0x200>, 5242 <0x0 0x0af65000 0x0 0xc00>, 5243 <0x0 0x0af66000 0x0 0x400>, 5244 <0x0 0x0af67000 0x0 0x400>, 5245 <0x0 0x0af68000 0x0 0x400>, 5246 <0x0 0x0af69000 0x0 0x400>, 5247 <0x0 0x0af6a000 0x0 0x600>, 5248 <0x0 0x0af6b000 0x0 0x600>; 5249 5250 interrupts-extended = <&mdss 14>; 5251 5252 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5253 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5254 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5255 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5256 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5257 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5258 clock-names = "core_iface", 5259 "core_aux", 5260 "ctrl_link", 5261 "ctrl_link_iface", 5262 "stream_pixel", 5263 "stream_1_pixel"; 5264 5265 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5266 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5267 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5268 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5269 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5270 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5271 5272 operating-points-v2 = <&mdss_dp0_opp_table>; 5273 5274 power-domains = <&rpmhpd RPMHPD_MMCX>; 5275 5276 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 5277 phy-names = "dp"; 5278 5279 #sound-dai-cells = <0>; 5280 5281 status = "disabled"; 5282 5283 ports { 5284 #address-cells = <1>; 5285 #size-cells = <0>; 5286 5287 port@0 { 5288 reg = <0>; 5289 mdss_dp2_in: endpoint { 5290 remote-endpoint = <&mdss_intf6_out>; 5291 }; 5292 }; 5293 5294 port@1 { 5295 reg = <1>; 5296 5297 mdss_dp2_out: endpoint { 5298 remote-endpoint = <&usb_2_qmpphy_dp_in>; 5299 }; 5300 }; 5301 }; 5302 }; 5303 5304 mdss_dp3: displayport-controller@af6c000 { 5305 compatible = "qcom,glymur-dp"; 5306 reg = <0x0 0x0af6c000 0x0 0x200>, 5307 <0x0 0x0af6c200 0x0 0x200>, 5308 <0x0 0x0af6d000 0x0 0xc00>, 5309 <0x0 0x0af6e000 0x0 0x400>, 5310 <0x0 0x0af6f000 0x0 0x400>, 5311 <0x0 0x0af70000 0x0 0x400>, 5312 <0x0 0x0af71000 0x0 0x400>, 5313 <0x0 0x0af72000 0x0 0x600>, 5314 <0x0 0x0af73000 0x0 0x600>; 5315 5316 interrupts-extended = <&mdss 15>; 5317 5318 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5319 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5320 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5321 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5322 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5323 clock-names = "core_iface", 5324 "core_aux", 5325 "ctrl_link", 5326 "ctrl_link_iface", 5327 "stream_pixel"; 5328 5329 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5330 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5331 assigned-clock-parents = <&mdss_dp3_phy 0>, 5332 <&mdss_dp3_phy 1>; 5333 5334 operating-points-v2 = <&mdss_dp0_opp_table>; 5335 5336 power-domains = <&rpmhpd RPMHPD_MMCX>; 5337 5338 phys = <&mdss_dp3_phy>; 5339 phy-names = "dp"; 5340 5341 #sound-dai-cells = <0>; 5342 5343 status = "disabled"; 5344 5345 ports { 5346 #address-cells = <1>; 5347 #size-cells = <0>; 5348 5349 port@0 { 5350 reg = <0>; 5351 5352 mdss_dp3_in: endpoint { 5353 remote-endpoint = <&mdss_intf5_out>; 5354 }; 5355 }; 5356 5357 port@1 { 5358 reg = <1>; 5359 5360 mdss_dp3_out: endpoint { 5361 }; 5362 }; 5363 }; 5364 }; 5365 }; 5366 5367 videocc: clock-controller@aaf0000 { 5368 compatible = "qcom,glymur-videocc"; 5369 reg = <0x0 0x0aaf0000 0x0 0x10000>; 5370 clocks = <&rpmhcc RPMH_CXO_CLK>, 5371 <&rpmhcc RPMH_CXO_CLK_A>; 5372 5373 power-domains = <&rpmhpd RPMHPD_MMCX>, 5374 <&rpmhpd RPMHPD_MXC>; 5375 required-opps = <&rpmhpd_opp_low_svs>, 5376 <&rpmhpd_opp_low_svs>; 5377 5378 #clock-cells = <1>; 5379 #reset-cells = <1>; 5380 #power-domain-cells = <1>; 5381 }; 5382 5383 evacc: clock-controller@abf0000 { 5384 compatible = "qcom,glymur-evacc"; 5385 reg = <0x0 0x0abf0000 0x0 0x10000>; 5386 clocks = <&gcc GCC_EVA_AHB_CLK>, 5387 <&rpmhcc RPMH_CXO_CLK>, 5388 <&sleep_clk>; 5389 5390 power-domains = <&rpmhpd RPMHPD_MMCX>, 5391 <&rpmhpd RPMHPD_MXC>; 5392 required-opps = <&rpmhpd_opp_low_svs>, 5393 <&rpmhpd_opp_low_svs>; 5394 5395 #clock-cells = <1>; 5396 #reset-cells = <1>; 5397 #power-domain-cells = <1>; 5398 }; 5399 5400 dispcc: clock-controller@af00000 { 5401 compatible = "qcom,glymur-dispcc"; 5402 reg = <0x0 0x0af00000 0x0 0x20000>; 5403 clocks = <&rpmhcc RPMH_CXO_CLK>, 5404 <&sleep_clk>, 5405 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5406 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5407 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5408 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5409 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5410 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5411 <&mdss_dp3_phy 0>, /* dp3 */ 5412 <&mdss_dp3_phy 1>, 5413 <0>, /* dsi0 */ 5414 <0>, 5415 <0>, /* dsi1 */ 5416 <0>, 5417 <0>, 5418 <0>, 5419 <0>, 5420 <0>; 5421 power-domains = <&rpmhpd RPMHPD_MMCX>; 5422 required-opps = <&rpmhpd_opp_low_svs>; 5423 #clock-cells = <1>; 5424 #reset-cells = <1>; 5425 #power-domain-cells = <1>; 5426 }; 5427 5428 pdc: interrupt-controller@b220000 { 5429 compatible = "qcom,glymur-pdc", "qcom,pdc"; 5430 reg = <0x0 0x0b220000 0x0 0x10000>; 5431 qcom,pdc-ranges = <0 745 38>, 5432 <40 785 11>, 5433 <51 527 4>, 5434 <57 533 10>, 5435 <70 546 4>, 5436 <75 551 18>, 5437 <108 619 22>, 5438 <130 717 12>, 5439 <142 251 5>, 5440 <147 796 16>, 5441 <171 4104 36>; 5442 #interrupt-cells = <2>; 5443 interrupt-parent = <&intc>; 5444 interrupt-controller; 5445 }; 5446 5447 tsens0: thermal-sensor@c22c000 { 5448 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5449 reg = <0x0 0x0c22c000 0x0 0x1000>, 5450 <0x0 0x0c222000 0x0 0x1000>; 5451 5452 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 5453 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 5454 interrupt-names = "uplow", 5455 "critical"; 5456 5457 #qcom,sensors = <13>; 5458 5459 #thermal-sensor-cells = <1>; 5460 }; 5461 5462 tsens1: thermal-sensor@c22d000 { 5463 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5464 reg = <0x0 0x0c22d000 0x0 0x1000>, 5465 <0x0 0x0c223000 0x0 0x1000>; 5466 5467 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 5468 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 5469 interrupt-names = "uplow", 5470 "critical"; 5471 5472 #qcom,sensors = <9>; 5473 5474 #thermal-sensor-cells = <1>; 5475 }; 5476 5477 tsens2: thermal-sensor@c22e000 { 5478 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5479 reg = <0x0 0x0c22e000 0x0 0x1000>, 5480 <0x0 0x0c224000 0x0 0x1000>; 5481 5482 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 5483 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 5484 interrupt-names = "uplow", 5485 "critical"; 5486 5487 #qcom,sensors = <13>; 5488 5489 #thermal-sensor-cells = <1>; 5490 }; 5491 5492 tsens3: thermal-sensor@c22f000 { 5493 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5494 reg = <0x0 0x0c22f000 0x0 0x1000>, 5495 <0x0 0x0c225000 0x0 0x1000>; 5496 5497 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 5498 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 5499 interrupt-names = "uplow", 5500 "critical"; 5501 5502 #qcom,sensors = <8>; 5503 5504 #thermal-sensor-cells = <1>; 5505 }; 5506 5507 tsens4: thermal-sensor@c230000 { 5508 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5509 reg = <0x0 0x0c230000 0x0 0x1000>, 5510 <0x0 0x0c226000 0x0 0x1000>; 5511 5512 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5514 interrupt-names = "uplow", 5515 "critical"; 5516 5517 #qcom,sensors = <13>; 5518 5519 #thermal-sensor-cells = <1>; 5520 }; 5521 5522 tsens5: thermal-sensor@c231000 { 5523 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5524 reg = <0x0 0x0c231000 0x0 0x1000>, 5525 <0x0 0x0c227000 0x0 0x1000>; 5526 5527 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 5529 interrupt-names = "uplow", 5530 "critical"; 5531 5532 #qcom,sensors = <8>; 5533 5534 #thermal-sensor-cells = <1>; 5535 }; 5536 5537 tsens6: thermal-sensor@c232000 { 5538 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5539 reg = <0x0 0x0c232000 0x0 0x1000>, 5540 <0x0 0x0c228000 0x0 0x1000>; 5541 5542 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 5543 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 5544 interrupt-names = "uplow", 5545 "critical"; 5546 5547 #qcom,sensors = <13>; 5548 5549 #thermal-sensor-cells = <1>; 5550 }; 5551 5552 tsens7: thermal-sensor@c233000 { 5553 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5554 reg = <0x0 0x0c233000 0x0 0x1000>, 5555 <0x0 0x0c229000 0x0 0x1000>; 5556 5557 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 5558 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 5559 interrupt-names = "uplow", 5560 "critical"; 5561 5562 #qcom,sensors = <15>; 5563 5564 #thermal-sensor-cells = <1>; 5565 }; 5566 5567 aoss_qmp: power-management@c300000 { 5568 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 5569 reg = <0x0 0x0c300000 0x0 0x400>; 5570 interrupt-parent = <&ipcc>; 5571 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 5572 IRQ_TYPE_EDGE_RISING>; 5573 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 5574 5575 #clock-cells = <0>; 5576 }; 5577 5578 sram@c30f000 { 5579 compatible = "qcom,rpmh-stats"; 5580 reg = <0x0 0x0c30f000 0x0 0x400>; 5581 }; 5582 5583 arbiter@c400000 { 5584 compatible = "qcom,glymur-spmi-pmic-arb"; 5585 reg = <0x0 0x0c400000 0x0 0x3000>, 5586 <0x0 0x0c900000 0x0 0x400000>, 5587 <0x0 0x0c4c0000 0x0 0x400000>, 5588 <0x0 0x0c403000 0x0 0x8000>; 5589 reg-names = "core", 5590 "chnls", 5591 "obsrvr", 5592 "chnl_map"; 5593 #address-cells = <2>; 5594 #size-cells = <2>; 5595 ranges; 5596 qcom,channel = <0>; 5597 qcom,ee = <0>; 5598 5599 spmi_bus0: spmi@c426000 { 5600 reg = <0x0 0x0c426000 0x0 0x4000>, 5601 <0x0 0x0c8c0000 0x0 0x10000>, 5602 <0x0 0x0c42a000 0x0 0x8000>; 5603 reg-names = "cnfg", 5604 "intr", 5605 "chnl_owner"; 5606 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5607 interrupt-names = "periph_irq"; 5608 interrupt-controller; 5609 #interrupt-cells = <4>; 5610 #address-cells = <2>; 5611 #size-cells = <0>; 5612 }; 5613 5614 spmi_bus1: spmi@c437000 { 5615 reg = <0x0 0x0c437000 0x0 0x4000>, 5616 <0x0 0x0c8d0000 0x0 0x10000>, 5617 <0x0 0x0c43b000 0x0 0x8000>; 5618 reg-names = "cnfg", 5619 "intr", 5620 "chnl_owner"; 5621 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 5622 interrupt-names = "periph_irq"; 5623 interrupt-controller; 5624 #interrupt-cells = <4>; 5625 #address-cells = <2>; 5626 #size-cells = <0>; 5627 }; 5628 5629 spmi_bus2: spmi@c448000 { 5630 reg = <0x0 0x0c448000 0x0 0x4000>, 5631 <0x0 0x0c8e0000 0x0 0x10000>, 5632 <0x0 0x0c44c000 0x0 0x8000>; 5633 reg-names = "cnfg", 5634 "intr", 5635 "chnl_owner"; 5636 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 5637 interrupt-names = "periph_irq"; 5638 interrupt-controller; 5639 #interrupt-cells = <4>; 5640 #address-cells = <2>; 5641 #size-cells = <0>; 5642 }; 5643 }; 5644 5645 tlmm: pinctrl@f100000 { 5646 compatible = "qcom,glymur-tlmm"; 5647 reg = <0x0 0x0f100000 0x0 0xf00000>; 5648 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5649 gpio-controller; 5650 #gpio-cells = <2>; 5651 interrupt-controller; 5652 #interrupt-cells = <2>; 5653 gpio-ranges = <&tlmm 0 0 249>; 5654 wakeup-parent = <&pdc>; 5655 5656 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5657 /* SDA, SCL */ 5658 pins = "gpio0", "gpio1"; 5659 function = "qup0_se0"; 5660 drive-strength = <2>; 5661 bias-pull-up = <2200>; 5662 }; 5663 5664 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5665 /* SDA, SCL */ 5666 pins = "gpio4", "gpio5"; 5667 function = "qup0_se1"; 5668 drive-strength = <2>; 5669 bias-pull-up = <2200>; 5670 }; 5671 5672 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5673 /* SDA, SCL */ 5674 pins = "gpio8", "gpio9"; 5675 function = "qup0_se2"; 5676 drive-strength = <2>; 5677 bias-pull-up = <2200>; 5678 }; 5679 5680 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 5681 /* SDA, SCL */ 5682 pins = "gpio12", "gpio13"; 5683 function = "qup0_se3"; 5684 drive-strength = <2>; 5685 bias-pull-up = <2200>; 5686 }; 5687 5688 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 5689 /* SDA, SCL */ 5690 pins = "gpio16", "gpio17"; 5691 function = "qup0_se4"; 5692 drive-strength = <2>; 5693 bias-pull-up = <2200>; 5694 }; 5695 5696 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 5697 /* SDA, SCL */ 5698 pins = "gpio20", "gpio21"; 5699 function = "qup0_se5"; 5700 drive-strength = <2>; 5701 bias-pull-up = <2200>; 5702 }; 5703 5704 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 5705 /* SDA, SCL */ 5706 pins = "gpio6", "gpio7"; 5707 function = "qup0_se6"; 5708 drive-strength = <2>; 5709 bias-pull-up = <2200>; 5710 }; 5711 5712 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 5713 /* SDA, SCL */ 5714 pins = "gpio14", "gpio15"; 5715 function = "qup0_se7"; 5716 drive-strength = <2>; 5717 bias-pull-up = <2200>; 5718 }; 5719 5720 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 5721 /* SDA, SCL */ 5722 pins = "gpio32", "gpio33"; 5723 function = "qup1_se0"; 5724 drive-strength = <2>; 5725 bias-pull-up = <2200>; 5726 }; 5727 5728 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 5729 /* SDA, SCL */ 5730 pins = "gpio36", "gpio37"; 5731 function = "qup1_se1"; 5732 drive-strength = <2>; 5733 bias-pull-up = <2200>; 5734 }; 5735 5736 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 5737 /* SDA, SCL */ 5738 pins = "gpio40", "gpio41"; 5739 function = "qup1_se2"; 5740 drive-strength = <2>; 5741 bias-pull-up = <2200>; 5742 }; 5743 5744 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 5745 /* SDA, SCL */ 5746 pins = "gpio44", "gpio45"; 5747 function = "qup1_se3"; 5748 drive-strength = <2>; 5749 bias-pull-up = <2200>; 5750 }; 5751 5752 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5753 /* SDA, SCL */ 5754 pins = "gpio48", "gpio49"; 5755 function = "qup1_se4"; 5756 drive-strength = <2>; 5757 bias-pull-up = <2200>; 5758 }; 5759 5760 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5761 /* SDA, SCL */ 5762 pins = "gpio52", "gpio53"; 5763 function = "qup1_se5"; 5764 drive-strength = <2>; 5765 bias-pull-up = <2200>; 5766 }; 5767 5768 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5769 /* SDA, SCL */ 5770 pins = "gpio56", "gpio57"; 5771 function = "qup1_se6"; 5772 drive-strength = <2>; 5773 bias-pull-up = <2200>; 5774 }; 5775 5776 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5777 /* SDA, SCL */ 5778 pins = "gpio54", "gpio55"; 5779 function = "qup1_se7"; 5780 drive-strength = <2>; 5781 bias-pull-up = <2200>; 5782 }; 5783 5784 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5785 /* SDA, SCL */ 5786 pins = "gpio64", "gpio65"; 5787 function = "qup2_se0"; 5788 drive-strength = <2>; 5789 bias-pull-up = <2200>; 5790 }; 5791 5792 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 5793 /* SDA, SCL */ 5794 pins = "gpio68", "gpio69"; 5795 function = "qup2_se1"; 5796 drive-strength = <2>; 5797 bias-pull-up = <2200>; 5798 }; 5799 5800 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 5801 /* SDA, SCL */ 5802 pins = "gpio72", "gpio73"; 5803 function = "qup2_se2"; 5804 drive-strength = <2>; 5805 bias-pull-up = <2200>; 5806 }; 5807 5808 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 5809 /* SDA, SCL */ 5810 pins = "gpio76", "gpio77"; 5811 function = "qup2_se3"; 5812 drive-strength = <2>; 5813 bias-pull-up = <2200>; 5814 }; 5815 5816 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 5817 /* SDA, SCL */ 5818 pins = "gpio80", "gpio81"; 5819 function = "qup2_se4"; 5820 drive-strength = <2>; 5821 bias-pull-up = <2200>; 5822 }; 5823 5824 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5825 /* SDA, SCL */ 5826 pins = "gpio84", "gpio85"; 5827 function = "qup2_se5"; 5828 drive-strength = <2>; 5829 bias-pull-up = <2200>; 5830 }; 5831 5832 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5833 /* SDA, SCL */ 5834 pins = "gpio88", "gpio89"; 5835 function = "qup2_se6"; 5836 drive-strength = <2>; 5837 bias-pull-up = <2200>; 5838 }; 5839 5840 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5841 /* SDA, SCL */ 5842 pins = "gpio80", "gpio81"; 5843 function = "qup2_se7"; 5844 drive-strength = <2>; 5845 bias-pull-up = <2200>; 5846 }; 5847 5848 qup_spi0_cs: qup-spi0-cs-state { 5849 pins = "gpio3"; 5850 function = "qup0_se0"; 5851 drive-strength = <6>; 5852 bias-disable; 5853 }; 5854 5855 qup_spi0_data_clk: qup-spi0-data-clk-state { 5856 /* MISO, MOSI, CLK */ 5857 pins = "gpio0", "gpio1", "gpio2"; 5858 function = "qup0_se0"; 5859 drive-strength = <6>; 5860 bias-disable; 5861 }; 5862 5863 qup_spi1_cs: qup-spi1-cs-state { 5864 pins = "gpio7"; 5865 function = "qup0_se1"; 5866 drive-strength = <6>; 5867 bias-disable; 5868 }; 5869 5870 qup_spi1_data_clk: qup-spi1-data-clk-state { 5871 /* MISO, MOSI, CLK */ 5872 pins = "gpio4", "gpio5", "gpio6"; 5873 function = "qup0_se1"; 5874 drive-strength = <6>; 5875 bias-disable; 5876 }; 5877 5878 qup_spi2_cs: qup-spi2-cs-state { 5879 pins = "gpio11"; 5880 function = "qup0_se2"; 5881 drive-strength = <6>; 5882 bias-disable; 5883 }; 5884 5885 qup_spi2_data_clk: qup-spi2-data-clk-state { 5886 /* MISO, MOSI, CLK */ 5887 pins = "gpio8", "gpio9", "gpio10"; 5888 function = "qup0_se2"; 5889 drive-strength = <6>; 5890 bias-disable; 5891 }; 5892 5893 qup_spi3_cs: qup-spi3-cs-state { 5894 pins = "gpio15"; 5895 function = "qup0_se3"; 5896 drive-strength = <6>; 5897 bias-disable; 5898 }; 5899 5900 qup_spi3_data_clk: qup-spi3-data-clk-state { 5901 /* MISO, MOSI, CLK */ 5902 pins = "gpio12", "gpio13", "gpio14"; 5903 function = "qup0_se3"; 5904 drive-strength = <6>; 5905 bias-disable; 5906 }; 5907 5908 qup_spi4_cs: qup-spi4-cs-state { 5909 pins = "gpio19"; 5910 function = "qup0_se4"; 5911 drive-strength = <6>; 5912 bias-disable; 5913 }; 5914 5915 qup_spi4_data_clk: qup-spi4-data-clk-state { 5916 /* MISO, MOSI, CLK */ 5917 pins = "gpio16", "gpio17", "gpio18"; 5918 function = "qup0_se4"; 5919 drive-strength = <6>; 5920 bias-disable; 5921 }; 5922 5923 qup_spi5_cs: qup-spi5-cs-state { 5924 pins = "gpio23"; 5925 function = "qup0_se5"; 5926 drive-strength = <6>; 5927 bias-disable; 5928 }; 5929 5930 qup_spi5_data_clk: qup-spi5-data-clk-state { 5931 /* MISO, MOSI, CLK */ 5932 pins = "gpio20", "gpio21", "gpio22"; 5933 function = "qup0_se5"; 5934 drive-strength = <6>; 5935 bias-disable; 5936 }; 5937 5938 qup_spi6_cs: qup-spi6-cs-state { 5939 pins = "gpio5"; 5940 function = "qup0_se6"; 5941 drive-strength = <6>; 5942 bias-disable; 5943 }; 5944 5945 qup_spi6_data_clk: qup-spi6-data-clk-state { 5946 /* MISO, MOSI, CLK */ 5947 pins = "gpio6", "gpio7", "gpio4"; 5948 function = "qup0_se6"; 5949 drive-strength = <6>; 5950 bias-disable; 5951 }; 5952 5953 qup_spi7_cs: qup-spi7-cs-state { 5954 pins = "gpio13"; 5955 function = "qup0_se7"; 5956 drive-strength = <6>; 5957 bias-disable; 5958 }; 5959 5960 qup_spi7_data_clk: qup-spi7-data-clk-state { 5961 /* MISO, MOSI, CLK */ 5962 pins = "gpio14", "gpio15", "gpio12"; 5963 function = "qup0_se7"; 5964 drive-strength = <6>; 5965 bias-disable; 5966 }; 5967 5968 qup_spi8_cs: qup-spi8-cs-state { 5969 pins = "gpio35"; 5970 function = "qup1_se0"; 5971 drive-strength = <6>; 5972 bias-disable; 5973 }; 5974 5975 qup_spi8_data_clk: qup-spi8-data-clk-state { 5976 /* MISO, MOSI, CLK */ 5977 pins = "gpio32", "gpio33", "gpio34"; 5978 function = "qup1_se0"; 5979 drive-strength = <6>; 5980 bias-disable; 5981 }; 5982 5983 qup_spi9_cs: qup-spi9-cs-state { 5984 pins = "gpio39"; 5985 function = "qup1_se1"; 5986 drive-strength = <6>; 5987 bias-disable; 5988 }; 5989 5990 qup_spi9_data_clk: qup-spi9-data-clk-state { 5991 /* MISO, MOSI, CLK */ 5992 pins = "gpio36", "gpio37", "gpio38"; 5993 function = "qup1_se1"; 5994 drive-strength = <6>; 5995 bias-disable; 5996 }; 5997 5998 qup_spi10_cs: qup-spi10-cs-state { 5999 pins = "gpio43"; 6000 function = "qup1_se2"; 6001 drive-strength = <6>; 6002 bias-disable; 6003 }; 6004 6005 qup_spi10_data_clk: qup-spi10-data-clk-state { 6006 /* MISO, MOSI, CLK */ 6007 pins = "gpio40", "gpio41", "gpio42"; 6008 function = "qup1_se2"; 6009 drive-strength = <6>; 6010 bias-disable; 6011 }; 6012 6013 qup_spi11_cs: qup-spi11-cs-state { 6014 pins = "gpio47"; 6015 function = "qup1_se3"; 6016 drive-strength = <6>; 6017 bias-disable; 6018 }; 6019 6020 qup_spi11_data_clk: qup-spi11-data-clk-state { 6021 pins = "gpio44", "gpio45", "gpio46"; 6022 function = "qup1_se3"; 6023 drive-strength = <6>; 6024 bias-disable; 6025 }; 6026 6027 qup_spi12_cs: qup-spi12-cs-state { 6028 pins = "gpio51"; 6029 function = "qup1_se4"; 6030 drive-strength = <6>; 6031 bias-disable; 6032 }; 6033 6034 qup_spi12_data_clk: qup-spi12-data-clk-state { 6035 /* MISO, MOSI, CLK */ 6036 pins = "gpio48", "gpio49", "gpio50"; 6037 function = "qup1_se4"; 6038 drive-strength = <6>; 6039 bias-disable; 6040 }; 6041 6042 qup_spi13_cs: qup-spi13-cs-state { 6043 pins = "gpio55"; 6044 function = "qup1_se5"; 6045 drive-strength = <6>; 6046 bias-disable; 6047 }; 6048 6049 qup_spi13_data_clk: qup-spi13-data-clk-state { 6050 /* MISO, MOSI, CLK */ 6051 pins = "gpio52", "gpio53", "gpio54"; 6052 function = "qup1_se5"; 6053 drive-strength = <6>; 6054 bias-disable; 6055 }; 6056 6057 qup_spi14_cs: qup-spi14-cs-state { 6058 pins = "gpio59"; 6059 function = "qup1_se6"; 6060 drive-strength = <6>; 6061 bias-disable; 6062 }; 6063 6064 qup_spi14_data_clk: qup-spi14-data-clk-state { 6065 /* MISO, MOSI, CLK */ 6066 pins = "gpio56", "gpio57", "gpio58"; 6067 function = "qup1_se6"; 6068 drive-strength = <6>; 6069 bias-disable; 6070 }; 6071 6072 qup_spi15_cs: qup-spi15-cs-state { 6073 pins = "gpio53"; 6074 function = "qup1_se7"; 6075 drive-strength = <6>; 6076 bias-disable; 6077 }; 6078 6079 qup_spi15_data_clk: qup-spi15-data-clk-state { 6080 /* MISO, MOSI, CLK */ 6081 pins = "gpio54", "gpio55", "gpio52"; 6082 function = "qup1_se7"; 6083 drive-strength = <6>; 6084 bias-disable; 6085 }; 6086 6087 qup_spi16_cs: qup-spi16-cs-state { 6088 pins = "gpio67"; 6089 function = "qup2_se0"; 6090 drive-strength = <6>; 6091 bias-disable; 6092 }; 6093 6094 qup_spi16_data_clk: qup-spi16-data-clk-state { 6095 /* MISO, MOSI, CLK */ 6096 pins = "gpio64", "gpio65", "gpio66"; 6097 function = "qup2_se0"; 6098 drive-strength = <6>; 6099 bias-disable; 6100 }; 6101 6102 qup_spi17_cs: qup-spi17-cs-state { 6103 pins = "gpio71"; 6104 function = "qup2_se1"; 6105 drive-strength = <6>; 6106 bias-disable; 6107 }; 6108 6109 qup_spi17_data_clk: qup-spi17-data-clk-state { 6110 /* MISO, MOSI, CLK */ 6111 pins = "gpio68", "gpio69", "gpio70"; 6112 function = "qup2_se1"; 6113 drive-strength = <6>; 6114 bias-disable; 6115 }; 6116 6117 qup_spi18_cs: qup-spi18-cs-state { 6118 pins = "gpio75"; 6119 function = "qup2_se2"; 6120 drive-strength = <6>; 6121 bias-disable; 6122 }; 6123 6124 qup_spi18_data_clk: qup-spi18-data-clk-state { 6125 /* MISO, MOSI, CLK */ 6126 pins = "gpio72", "gpio73", "gpio74"; 6127 function = "qup2_se2"; 6128 drive-strength = <6>; 6129 bias-disable; 6130 }; 6131 6132 qup_spi19_cs: qup-spi19-cs-state { 6133 pins = "gpio79"; 6134 function = "qup2_se3"; 6135 drive-strength = <6>; 6136 bias-disable; 6137 }; 6138 6139 qup_spi19_data_clk: qup-spi19-data-clk-state { 6140 /* MISO, MOSI, CLK */ 6141 pins = "gpio76", "gpio77", "gpio78"; 6142 function = "qup2_se3"; 6143 drive-strength = <6>; 6144 bias-disable; 6145 }; 6146 6147 qup_spi20_cs: qup-spi20-cs-state { 6148 pins = "gpio83"; 6149 function = "qup2_se4"; 6150 drive-strength = <6>; 6151 bias-disable; 6152 }; 6153 6154 qup_spi20_data_clk: qup-spi20-data-clk-state { 6155 /* MISO, MOSI, CLK */ 6156 pins = "gpio80", "gpio81", "gpio82"; 6157 function = "qup2_se4"; 6158 drive-strength = <6>; 6159 bias-disable; 6160 }; 6161 6162 qup_spi21_cs: qup-spi21-cs-state { 6163 pins = "gpio87"; 6164 function = "qup2_se5"; 6165 drive-strength = <6>; 6166 bias-disable; 6167 }; 6168 6169 qup_spi21_data_clk: qup-spi21-data-clk-state { 6170 /* MISO, MOSI, CLK */ 6171 pins = "gpio84", "gpio85", "gpio86"; 6172 function = "qup2_se5"; 6173 drive-strength = <6>; 6174 bias-disable; 6175 }; 6176 6177 qup_spi22_cs: qup-spi22-cs-state { 6178 pins = "gpio91"; 6179 function = "qup2_se6"; 6180 drive-strength = <6>; 6181 bias-disable; 6182 }; 6183 6184 qup_spi22_data_clk: qup-spi22-data-clk-state { 6185 /* MISO, MOSI, CLK */ 6186 pins = "gpio88", "gpio89", "gpio90"; 6187 function = "qup2_se6"; 6188 drive-strength = <6>; 6189 bias-disable; 6190 }; 6191 6192 qup_spi23_cs: qup-spi23-cs-state { 6193 pins = "gpio83"; 6194 function = "qup2_se7"; 6195 drive-strength = <6>; 6196 bias-disable; 6197 }; 6198 6199 qup_spi23_data_clk: qup-spi23-data-clk-state { 6200 /* MISO, MOSI, CLK */ 6201 pins = "gpio80", "gpio81", "gpio82"; 6202 function = "qup2_se7"; 6203 drive-strength = <6>; 6204 bias-disable; 6205 }; 6206 6207 qup_uart2_default: qup-uart2-default-state { 6208 tx-pins { 6209 pins = "gpio10"; 6210 function = "qup0_se2"; 6211 drive-strength = <2>; 6212 bias-disable; 6213 }; 6214 6215 rx-pins { 6216 pins = "gpio11"; 6217 function = "qup0_se2"; 6218 drive-strength = <2>; 6219 bias-disable; 6220 }; 6221 }; 6222 6223 qup_uart14_default: qup-uart14-default-state { 6224 cts-pins { 6225 pins = "gpio56"; 6226 function = "qup1_se6"; 6227 drive-strength = <2>; 6228 bias-disable; 6229 }; 6230 6231 rts-pins { 6232 pins = "gpio57"; 6233 function = "qup1_se6"; 6234 drive-strength = <2>; 6235 bias-disable; 6236 }; 6237 6238 tx-pins { 6239 pins = "gpio58"; 6240 function = "qup1_se6"; 6241 drive-strength = <2>; 6242 bias-disable; 6243 }; 6244 6245 rx-pins { 6246 pins = "gpio59"; 6247 function = "qup1_se6"; 6248 drive-strength = <2>; 6249 bias-disable; 6250 }; 6251 }; 6252 6253 qup_uart19_default: qup-uart19-default-state { 6254 cts-pins { 6255 pins = "gpio76"; 6256 function = "qup2_se3"; 6257 drive-strength = <2>; 6258 bias-disable; 6259 }; 6260 6261 rts-pins { 6262 pins = "gpio77"; 6263 function = "qup2_se3"; 6264 drive-strength = <2>; 6265 bias-disable; 6266 }; 6267 6268 tx-pins { 6269 pins = "gpio78"; 6270 function = "qup2_se3"; 6271 drive-strength = <2>; 6272 bias-disable; 6273 }; 6274 6275 rx-pins { 6276 pins = "gpio79"; 6277 function = "qup2_se3"; 6278 drive-strength = <2>; 6279 bias-disable; 6280 }; 6281 }; 6282 6283 qup_uart21_default: qup-uart21-default-state { 6284 tx-pins { 6285 pins = "gpio86"; 6286 function = "qup2_se5"; 6287 drive-strength = <2>; 6288 bias-disable; 6289 }; 6290 6291 rx-pins { 6292 pins = "gpio87"; 6293 function = "qup2_se5"; 6294 drive-strength = <2>; 6295 bias-disable; 6296 }; 6297 }; 6298 6299 qup_uart22_default: qup-uart22-default-state { 6300 tx-pins { 6301 pins = "gpio90"; 6302 function = "qup2_se6"; 6303 drive-strength = <2>; 6304 bias-disable; 6305 }; 6306 6307 rx-pins { 6308 pins = "gpio91"; 6309 function = "qup2_se6"; 6310 drive-strength = <2>; 6311 bias-disable; 6312 }; 6313 }; 6314 }; 6315 6316 ctcu@10001000 { 6317 compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu"; 6318 reg = <0x0 0x10001000 0x0 0x1000>; 6319 6320 clocks = <&aoss_qmp>; 6321 clock-names = "apb"; 6322 6323 in-ports { 6324 #address-cells = <1>; 6325 #size-cells = <0>; 6326 6327 port@0 { 6328 reg = <0>; 6329 6330 ctcu_in0: endpoint { 6331 remote-endpoint = <&etr0_out>; 6332 }; 6333 }; 6334 6335 port@1 { 6336 reg = <1>; 6337 6338 ctcu_in1: endpoint { 6339 remote-endpoint = <&etr1_out>; 6340 }; 6341 }; 6342 }; 6343 }; 6344 6345 stm: stm@10002000 { 6346 compatible = "arm,coresight-stm", "arm,primecell"; 6347 reg = <0x0 0x10002000 0x0 0x1000>, 6348 <0x0 0x16280000 0x0 0x180000>; 6349 reg-names = "stm-base", 6350 "stm-stimulus-base"; 6351 6352 clocks = <&aoss_qmp>; 6353 clock-names = "apb_pclk"; 6354 6355 out-ports { 6356 port { 6357 stm_out: endpoint { 6358 remote-endpoint = <&funnel0_in7>; 6359 }; 6360 }; 6361 }; 6362 }; 6363 6364 tpda@10004000 { 6365 compatible = "qcom,coresight-tpda", "arm,primecell"; 6366 reg = <0x0 0x10004000 0x0 0x1000>; 6367 6368 clocks = <&aoss_qmp>; 6369 clock-names = "apb_pclk"; 6370 6371 in-ports { 6372 #address-cells = <1>; 6373 #size-cells = <0>; 6374 6375 port@1 { 6376 reg = <1>; 6377 6378 qdss_tpda_in1: endpoint { 6379 remote-endpoint = <&spdm_tpdm_out>; 6380 }; 6381 }; 6382 }; 6383 6384 out-ports { 6385 port { 6386 qdss_tpda_out: endpoint { 6387 remote-endpoint = <&funnel0_in6>; 6388 }; 6389 }; 6390 }; 6391 }; 6392 6393 tpdm@1000f000 { 6394 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6395 reg = <0x0 0x1000f000 0x0 0x1000>; 6396 6397 clocks = <&aoss_qmp>; 6398 clock-names = "apb_pclk"; 6399 label = "tpdm_spdm"; 6400 6401 qcom,cmb-element-bits = <32>; 6402 qcom,cmb-msrs-num = <32>; 6403 6404 out-ports { 6405 port { 6406 spdm_tpdm_out: endpoint { 6407 remote-endpoint = <&qdss_tpda_in1>; 6408 }; 6409 }; 6410 }; 6411 }; 6412 6413 funnel@10041000 { 6414 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6415 reg = <0x0 0x10041000 0x0 0x1000>; 6416 6417 clocks = <&aoss_qmp>; 6418 clock-names = "apb_pclk"; 6419 6420 in-ports { 6421 #address-cells = <1>; 6422 #size-cells = <0>; 6423 6424 port@0 { 6425 reg = <0>; 6426 6427 funnel0_in0: endpoint { 6428 remote-endpoint = <&tn_ag_out>; 6429 }; 6430 }; 6431 6432 port@6 { 6433 reg = <6>; 6434 6435 funnel0_in6: endpoint { 6436 remote-endpoint = <&qdss_tpda_out>; 6437 }; 6438 }; 6439 6440 port@7 { 6441 reg = <7>; 6442 6443 funnel0_in7: endpoint { 6444 remote-endpoint = <&stm_out>; 6445 }; 6446 }; 6447 }; 6448 6449 out-ports { 6450 port { 6451 funnel0_out: endpoint { 6452 remote-endpoint = <&aoss_funnel_in6>; 6453 }; 6454 }; 6455 }; 6456 }; 6457 6458 replicator@10046000 { 6459 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6460 reg = <0x0 0x10046000 0x0 0x1000>; 6461 6462 clocks = <&aoss_qmp>; 6463 clock-names = "apb_pclk"; 6464 6465 in-ports { 6466 port { 6467 qdss_rep_in: endpoint { 6468 remote-endpoint = <&swao_rep_out0>; 6469 }; 6470 }; 6471 }; 6472 6473 out-ports { 6474 port { 6475 qdss_rep_out0: endpoint { 6476 remote-endpoint = <&etr_rep_in>; 6477 }; 6478 }; 6479 }; 6480 }; 6481 6482 tmc@10048000 { 6483 compatible = "arm,coresight-tmc", "arm,primecell"; 6484 reg = <0x0 0x10048000 0x0 0x1000>; 6485 6486 clocks = <&aoss_qmp>; 6487 clock-names = "apb_pclk"; 6488 6489 iommus = <&apps_smmu 0x00e0 0x0000>; 6490 arm,scatter-gather; 6491 6492 in-ports { 6493 port { 6494 etr0_in: endpoint { 6495 remote-endpoint = <&etr_rep_out0>; 6496 }; 6497 }; 6498 }; 6499 6500 out-ports { 6501 port { 6502 etr0_out: endpoint { 6503 remote-endpoint = <&ctcu_in0>; 6504 }; 6505 }; 6506 }; 6507 }; 6508 6509 replicator@1004e000 { 6510 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6511 reg = <0x0 0x1004e000 0x0 0x1000>; 6512 6513 clocks = <&aoss_qmp>; 6514 clock-names = "apb_pclk"; 6515 6516 in-ports { 6517 port { 6518 etr_rep_in: endpoint { 6519 remote-endpoint = <&qdss_rep_out0>; 6520 }; 6521 }; 6522 }; 6523 6524 out-ports { 6525 #address-cells = <1>; 6526 #size-cells = <0>; 6527 6528 port@0 { 6529 reg = <0>; 6530 6531 etr_rep_out0: endpoint { 6532 remote-endpoint = <&etr0_in>; 6533 }; 6534 }; 6535 6536 port@1 { 6537 reg = <1>; 6538 6539 etr_rep_out1: endpoint { 6540 remote-endpoint = <&etr1_in>; 6541 }; 6542 }; 6543 }; 6544 }; 6545 6546 tmc@1004f000 { 6547 compatible = "arm,coresight-tmc", "arm,primecell"; 6548 reg = <0x0 0x1004f000 0x0 0x1000>; 6549 6550 clocks = <&aoss_qmp>; 6551 clock-names = "apb_pclk"; 6552 6553 iommus = <&apps_smmu 0x0100 0x0000>; 6554 arm,scatter-gather; 6555 6556 in-ports { 6557 port { 6558 etr1_in: endpoint { 6559 remote-endpoint = <&etr_rep_out1>; 6560 }; 6561 }; 6562 }; 6563 6564 out-ports { 6565 port { 6566 etr1_out: endpoint { 6567 remote-endpoint = <&ctcu_in1>; 6568 }; 6569 }; 6570 }; 6571 }; 6572 6573 tpdm@1102c000 { 6574 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6575 reg = <0x0 0x1102c000 0x0 0x1000>; 6576 6577 clocks = <&aoss_qmp>; 6578 clock-names = "apb_pclk"; 6579 label = "tpdm_gcc"; 6580 6581 qcom,dsb-msrs-num = <32>; 6582 6583 out-ports { 6584 port { 6585 gcc_tpdm_out: endpoint { 6586 remote-endpoint = <&tn_ag_in36>; 6587 }; 6588 }; 6589 }; 6590 }; 6591 6592 tpdm@11180000 { 6593 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6594 reg = <0x0 0x11180000 0x0 0x1000>; 6595 6596 clocks = <&aoss_qmp>; 6597 clock-names = "apb_pclk"; 6598 label = "tpdm_cdsp"; 6599 6600 qcom,dsb-element-bits = <32>; 6601 qcom,dsb-msrs-num = <32>; 6602 6603 out-ports { 6604 port { 6605 cdsp_tpdm_out: endpoint { 6606 remote-endpoint = <&cdsp_tpda_in0>; 6607 }; 6608 }; 6609 }; 6610 }; 6611 6612 tpdm@11185000 { 6613 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6614 reg = <0x0 0x11185000 0x0 0x1000>; 6615 6616 clocks = <&aoss_qmp>; 6617 clock-names = "apb_pclk"; 6618 label = "tpdm_cdsp_dpm_1"; 6619 6620 qcom,cmb-element-bits = <64>; 6621 qcom,cmb-msrs-num = <32>; 6622 6623 out-ports { 6624 port { 6625 cdsp_dpm1_tpdm_out: endpoint { 6626 remote-endpoint = <&cdsp_tpda_in5>; 6627 }; 6628 }; 6629 }; 6630 }; 6631 6632 tpdm@11186000 { 6633 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6634 reg = <0x0 0x11186000 0x0 0x1000>; 6635 6636 clocks = <&aoss_qmp>; 6637 clock-names = "apb_pclk"; 6638 label = "tpdm_cdsp_dpm_2"; 6639 6640 qcom,cmb-element-bits = <64>; 6641 qcom,cmb-msrs-num = <32>; 6642 6643 out-ports { 6644 port { 6645 cdsp_dpm2_tpdm_out: endpoint { 6646 remote-endpoint = <&cdsp_tpda_in6>; 6647 }; 6648 }; 6649 }; 6650 }; 6651 6652 tpda@11188000 { 6653 compatible = "qcom,coresight-tpda", "arm,primecell"; 6654 reg = <0x0 0x11188000 0x0 0x1000>; 6655 6656 clocks = <&aoss_qmp>; 6657 clock-names = "apb_pclk"; 6658 6659 in-ports { 6660 #address-cells = <1>; 6661 #size-cells = <0>; 6662 6663 port@0 { 6664 reg = <0>; 6665 6666 cdsp_tpda_in0: endpoint { 6667 remote-endpoint = <&cdsp_tpdm_out>; 6668 }; 6669 }; 6670 6671 port@1 { 6672 reg = <1>; 6673 6674 cdsp_tpda_in1: endpoint { 6675 remote-endpoint = <&cdsp_llm_tpdm_out>; 6676 }; 6677 }; 6678 6679 port@2 { 6680 reg = <2>; 6681 6682 cdsp_tpda_in2: endpoint { 6683 remote-endpoint = <&cdsp_llm2_tpdm_out>; 6684 }; 6685 }; 6686 6687 port@3 { 6688 reg = <3>; 6689 6690 cdsp_tpda_in3: endpoint { 6691 remote-endpoint = <&cdsp_cmsr_tpdm_out>; 6692 }; 6693 }; 6694 6695 port@4 { 6696 reg = <4>; 6697 6698 cdsp_tpda_in4: endpoint { 6699 remote-endpoint = <&cdsp_cmsr2_tpdm_out>; 6700 }; 6701 }; 6702 6703 port@5 { 6704 reg = <5>; 6705 6706 cdsp_tpda_in5: endpoint { 6707 remote-endpoint = <&cdsp_dpm1_tpdm_out>; 6708 }; 6709 }; 6710 6711 port@6 { 6712 reg = <6>; 6713 6714 cdsp_tpda_in6: endpoint { 6715 remote-endpoint = <&cdsp_dpm2_tpdm_out>; 6716 }; 6717 }; 6718 }; 6719 6720 out-ports { 6721 port { 6722 cdsp_tpda_out: endpoint { 6723 remote-endpoint = <&cdsp_funnel_in0>; 6724 }; 6725 }; 6726 }; 6727 }; 6728 6729 funnel@11189000 { 6730 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6731 reg = <0x0 0x11189000 0x0 0x1000>; 6732 6733 clocks = <&aoss_qmp>; 6734 clock-names = "apb_pclk"; 6735 6736 in-ports { 6737 port { 6738 cdsp_funnel_in0: endpoint { 6739 remote-endpoint = <&cdsp_tpda_out>; 6740 }; 6741 }; 6742 }; 6743 6744 out-ports { 6745 port { 6746 cdsp_funnel_out: endpoint { 6747 remote-endpoint = <&tn_ag_in53>; 6748 }; 6749 }; 6750 }; 6751 }; 6752 6753 cti@11193000 { 6754 compatible = "arm,coresight-cti", "arm,primecell"; 6755 reg = <0x0 0x11193000 0x0 0x1000>; 6756 6757 clocks = <&aoss_qmp>; 6758 clock-names = "apb_pclk"; 6759 label = "cti_cdsp"; 6760 }; 6761 6762 cti_wpss: cti@111ab000 { 6763 compatible = "arm,coresight-cti", "arm,primecell"; 6764 reg = <0x0 0x111ab000 0x0 0x1000>; 6765 6766 clocks = <&aoss_qmp>; 6767 clock-names = "apb_pclk"; 6768 label = "cti_wpss"; 6769 }; 6770 6771 tpdm@111d0000 { 6772 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6773 reg = <0x0 0x111d0000 0x0 0x1000>; 6774 6775 clocks = <&aoss_qmp>; 6776 clock-names = "apb_pclk"; 6777 label = "tpdm_qm"; 6778 6779 qcom,dsb-msrs-num = <32>; 6780 6781 out-ports { 6782 port { 6783 qm_tpdm_out: endpoint { 6784 remote-endpoint = <&tn_ag_in35>; 6785 }; 6786 }; 6787 }; 6788 }; 6789 6790 itnoc@11200000 { 6791 compatible = "qcom,coresight-itnoc"; 6792 reg = <0x0 0x11200000 0x0 0x3c00>; 6793 6794 clocks = <&aoss_qmp>; 6795 clock-names = "apb"; 6796 6797 in-ports { 6798 #address-cells = <1>; 6799 #size-cells = <0>; 6800 6801 port@6 { 6802 reg = <6>; 6803 6804 tn_ag_in6: endpoint { 6805 remote-endpoint = <&mm_dsb_tpdm_out>; 6806 }; 6807 }; 6808 6809 port@10 { 6810 reg = <0x10>; 6811 6812 tn_ag_in16: endpoint { 6813 remote-endpoint = <&east_dsb_tpdm_out>; 6814 }; 6815 }; 6816 6817 port@21 { 6818 reg = <0x21>; 6819 6820 tn_ag_in33: endpoint { 6821 remote-endpoint = <&west_dsb_tpdm_out>; 6822 }; 6823 }; 6824 6825 port@23 { 6826 reg = <0x23>; 6827 6828 tn_ag_in35: endpoint { 6829 remote-endpoint = <&qm_tpdm_out>; 6830 }; 6831 }; 6832 6833 port@24 { 6834 reg = <0x24>; 6835 6836 tn_ag_in36: endpoint { 6837 remote-endpoint = <&gcc_tpdm_out>; 6838 }; 6839 }; 6840 6841 port@32 { 6842 reg = <0x32>; 6843 6844 tn_ag_in50: endpoint { 6845 remote-endpoint = <&pcie_rscc_tpda_out>; 6846 }; 6847 }; 6848 6849 port@35 { 6850 reg = <0x35>; 6851 6852 tn_ag_in53: endpoint { 6853 remote-endpoint = <&cdsp_funnel_out>; 6854 }; 6855 }; 6856 6857 port@3f { 6858 reg = <0x3f>; 6859 6860 tn_ag_in63: endpoint { 6861 remote-endpoint = <¢er_dsb_tpdm_out>; 6862 }; 6863 }; 6864 6865 port@40 { 6866 reg = <0x40>; 6867 6868 tn_ag_in64: endpoint { 6869 remote-endpoint = <&ipcc_cmb_tpdm_out>; 6870 }; 6871 }; 6872 6873 port@41 { 6874 reg = <0x41>; 6875 6876 tn_ag_in65: endpoint { 6877 remote-endpoint = <&qrng_tpdm_out>; 6878 }; 6879 }; 6880 6881 port@42 { 6882 reg = <0x42>; 6883 6884 tn_ag_in66: endpoint { 6885 remote-endpoint = <&pmu_tpdm_out>; 6886 }; 6887 }; 6888 6889 port@43 { 6890 reg = <0x43>; 6891 6892 tn_ag_in67: endpoint { 6893 remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; 6894 }; 6895 }; 6896 6897 port@44 { 6898 reg = <0x44>; 6899 6900 tn_ag_in68: endpoint { 6901 remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; 6902 }; 6903 }; 6904 6905 port@45 { 6906 reg = <0x45>; 6907 6908 tn_ag_in69: endpoint { 6909 remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; 6910 }; 6911 }; 6912 6913 port@4b { 6914 reg = <0x4b>; 6915 6916 tn_ag_in75: endpoint { 6917 remote-endpoint = <&south_dsb2_tpdm_out>; 6918 }; 6919 }; 6920 6921 port@52 { 6922 reg = <0x52>; 6923 6924 tn_ag_in82: endpoint { 6925 remote-endpoint = <&south_dsb_tpdm_out>; 6926 }; 6927 }; 6928 6929 port@53 { 6930 reg = <0x53>; 6931 6932 tn_ag_in83: endpoint { 6933 remote-endpoint = <¢er_dsb1_tpdm_out>; 6934 }; 6935 }; 6936 }; 6937 6938 out-ports { 6939 port { 6940 tn_ag_out: endpoint { 6941 remote-endpoint = <&funnel0_in0>; 6942 }; 6943 }; 6944 }; 6945 }; 6946 6947 tpdm@11207000 { 6948 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6949 reg = <0x0 0x11207000 0x0 0x1000>; 6950 6951 clocks = <&aoss_qmp>; 6952 clock-names = "apb_pclk"; 6953 label = "tpdm_mm_dsb"; 6954 6955 qcom,dsb-msrs-num = <32>; 6956 6957 out-ports { 6958 port { 6959 mm_dsb_tpdm_out: endpoint { 6960 remote-endpoint = <&tn_ag_in6>; 6961 }; 6962 }; 6963 }; 6964 }; 6965 6966 tpdm@1120b000 { 6967 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6968 reg = <0x0 0x1120b000 0x0 0x1000>; 6969 6970 clocks = <&aoss_qmp>; 6971 clock-names = "apb_pclk"; 6972 label = "tpdm_east_dsb"; 6973 6974 qcom,dsb-msrs-num = <32>; 6975 6976 out-ports { 6977 port { 6978 east_dsb_tpdm_out: endpoint { 6979 remote-endpoint = <&tn_ag_in16>; 6980 }; 6981 }; 6982 }; 6983 }; 6984 6985 tpdm@11213000 { 6986 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6987 reg = <0x0 0x11213000 0x0 0x1000>; 6988 6989 clocks = <&aoss_qmp>; 6990 clock-names = "apb_pclk"; 6991 label = "tpdm_west_dsb"; 6992 6993 qcom,dsb-msrs-num = <32>; 6994 6995 out-ports { 6996 port { 6997 west_dsb_tpdm_out: endpoint { 6998 remote-endpoint = <&tn_ag_in33>; 6999 }; 7000 }; 7001 }; 7002 }; 7003 7004 tpdm@11219000 { 7005 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7006 reg = <0x0 0x11219000 0x0 0x1000>; 7007 7008 clocks = <&aoss_qmp>; 7009 clock-names = "apb_pclk"; 7010 label = "tpdm_center_dsb"; 7011 7012 qcom,dsb-msrs-num = <32>; 7013 7014 out-ports { 7015 port { 7016 center_dsb_tpdm_out: endpoint { 7017 remote-endpoint = <&tn_ag_in63>; 7018 }; 7019 }; 7020 }; 7021 }; 7022 7023 tpdm@1121a000 { 7024 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7025 reg = <0x0 0x1121a000 0x0 0x1000>; 7026 7027 clocks = <&aoss_qmp>; 7028 clock-names = "apb_pclk"; 7029 label = "tpdm_ipcc"; 7030 7031 qcom,cmb-msrs-num = <32>; 7032 7033 out-ports { 7034 port { 7035 ipcc_cmb_tpdm_out: endpoint { 7036 remote-endpoint = <&tn_ag_in64>; 7037 }; 7038 }; 7039 }; 7040 }; 7041 7042 tpdm@1121b000 { 7043 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7044 reg = <0x0 0x1121b000 0x0 0x1000>; 7045 7046 clocks = <&aoss_qmp>; 7047 clock-names = "apb_pclk"; 7048 label = "tpdm_qrng"; 7049 7050 qcom,cmb-msrs-num = <32>; 7051 7052 out-ports { 7053 port { 7054 qrng_tpdm_out: endpoint { 7055 remote-endpoint = <&tn_ag_in65>; 7056 }; 7057 }; 7058 }; 7059 }; 7060 7061 tpdm@1121c000 { 7062 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7063 reg = <0x0 0x1121c000 0x0 0x1000>; 7064 7065 clocks = <&aoss_qmp>; 7066 clock-names = "apb_pclk"; 7067 label = "tpdm_pmu"; 7068 7069 qcom,dsb-msrs-num = <32>; 7070 7071 out-ports { 7072 port { 7073 pmu_tpdm_out: endpoint { 7074 remote-endpoint = <&tn_ag_in66>; 7075 }; 7076 }; 7077 }; 7078 }; 7079 7080 tpdm@1121d000 { 7081 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7082 reg = <0x0 0x1121d000 0x0 0x1000>; 7083 7084 clocks = <&aoss_qmp>; 7085 clock-names = "apb_pclk"; 7086 label = "tpdm_rdpm_cx"; 7087 7088 qcom,cmb-msrs-num = <32>; 7089 7090 out-ports { 7091 port { 7092 rdpm_west_cmb0_tpdm_out: endpoint { 7093 remote-endpoint = <&tn_ag_in67>; 7094 }; 7095 }; 7096 }; 7097 }; 7098 7099 tpdm@1121e000 { 7100 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7101 reg = <0x0 0x1121e000 0x0 0x1000>; 7102 7103 clocks = <&aoss_qmp>; 7104 clock-names = "apb_pclk"; 7105 label = "tpdm_rdpm_mxc"; 7106 7107 qcom,cmb-msrs-num = <32>; 7108 7109 out-ports { 7110 port { 7111 rdpm_west_cmb1_tpdm_out: endpoint { 7112 remote-endpoint = <&tn_ag_in68>; 7113 }; 7114 }; 7115 }; 7116 }; 7117 7118 tpdm@1121f000 { 7119 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7120 reg = <0x0 0x1121f000 0x0 0x1000>; 7121 7122 clocks = <&aoss_qmp>; 7123 clock-names = "apb_pclk"; 7124 label = "tpdm_rdpm_mxa"; 7125 7126 qcom,cmb-msrs-num = <32>; 7127 7128 out-ports { 7129 port { 7130 rdpm_west_cmb2_tpdm_out: endpoint { 7131 remote-endpoint = <&tn_ag_in69>; 7132 }; 7133 }; 7134 }; 7135 }; 7136 7137 tpdm@11220000 { 7138 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7139 reg = <0x0 0x11220000 0x0 0x1000>; 7140 7141 clocks = <&aoss_qmp>; 7142 clock-names = "apb_pclk"; 7143 label = "tpdm_center_dsb_1"; 7144 7145 qcom,dsb-msrs-num = <32>; 7146 7147 out-ports { 7148 port { 7149 center_dsb1_tpdm_out: endpoint { 7150 remote-endpoint = <&tn_ag_in83>; 7151 }; 7152 }; 7153 }; 7154 }; 7155 7156 tpdm@11224000 { 7157 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7158 reg = <0x0 0x11224000 0x0 0x1000>; 7159 7160 clocks = <&aoss_qmp>; 7161 clock-names = "apb_pclk"; 7162 label = "tpdm_south2_dsb"; 7163 7164 qcom,dsb-msrs-num = <32>; 7165 7166 out-ports { 7167 port { 7168 south_dsb2_tpdm_out: endpoint { 7169 remote-endpoint = <&tn_ag_in75>; 7170 }; 7171 }; 7172 }; 7173 }; 7174 7175 tpdm@11228000 { 7176 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7177 reg = <0x0 0x11228000 0x0 0x1000>; 7178 7179 clocks = <&aoss_qmp>; 7180 clock-names = "apb_pclk"; 7181 label = "tpdm_south_dsb"; 7182 7183 qcom,dsb-msrs-num = <32>; 7184 7185 out-ports { 7186 port { 7187 south_dsb_tpdm_out: endpoint { 7188 remote-endpoint = <&tn_ag_in82>; 7189 }; 7190 }; 7191 }; 7192 }; 7193 7194 tpdm@11470000 { 7195 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7196 reg = <0x0 0x11470000 0x0 0x1000>; 7197 7198 clocks = <&aoss_qmp>; 7199 clock-names = "apb_pclk"; 7200 label = "tpdm_pcie_rscc"; 7201 7202 qcom,cmb-element-bits = <32>; 7203 qcom,cmb-msrs-num = <32>; 7204 7205 out-ports { 7206 port { 7207 pcie_rscc_tpdm_out: endpoint { 7208 remote-endpoint = <&pcie_rscc_tpda_in0>; 7209 }; 7210 }; 7211 }; 7212 }; 7213 7214 tpda@11471000 { 7215 compatible = "qcom,coresight-tpda", "arm,primecell"; 7216 reg = <0x0 0x11471000 0x0 0x1000>; 7217 7218 clocks = <&aoss_qmp>; 7219 clock-names = "apb_pclk"; 7220 7221 in-ports { 7222 port { 7223 pcie_rscc_tpda_in0: endpoint { 7224 remote-endpoint = <&pcie_rscc_tpdm_out>; 7225 }; 7226 }; 7227 }; 7228 7229 out-ports { 7230 port { 7231 pcie_rscc_tpda_out: endpoint { 7232 remote-endpoint = <&tn_ag_in50>; 7233 }; 7234 }; 7235 }; 7236 }; 7237 7238 tpdm@11c03000 { 7239 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7240 reg = <0x0 0x11c03000 0x0 0x1000>; 7241 7242 clocks = <&aoss_qmp>; 7243 clock-names = "apb_pclk"; 7244 label = "tpdm_swao_prio_4"; 7245 7246 qcom,cmb-element-bits = <64>; 7247 qcom,cmb-msrs-num = <32>; 7248 7249 out-ports { 7250 port { 7251 swao_prio4_tpdm_out: endpoint { 7252 remote-endpoint = <&aoss_tpda_in4>; 7253 }; 7254 }; 7255 }; 7256 }; 7257 7258 funnel@11c04000 { 7259 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7260 reg = <0x0 0x11c04000 0x0 0x1000>; 7261 7262 clocks = <&aoss_qmp>; 7263 clock-names = "apb_pclk"; 7264 7265 in-ports { 7266 #address-cells = <1>; 7267 #size-cells = <0>; 7268 7269 port@5 { 7270 reg = <5>; 7271 7272 aoss_funnel_in5: endpoint { 7273 remote-endpoint = <&aoss_tpda_out>; 7274 }; 7275 }; 7276 7277 port@6 { 7278 reg = <6>; 7279 7280 aoss_funnel_in6: endpoint { 7281 remote-endpoint = <&funnel0_out>; 7282 }; 7283 }; 7284 }; 7285 7286 out-ports { 7287 port { 7288 aoss_funnel_out: endpoint { 7289 remote-endpoint = <&etf0_in>; 7290 }; 7291 }; 7292 }; 7293 }; 7294 7295 tmc_etf: tmc@11c05000 { 7296 compatible = "arm,coresight-tmc", "arm,primecell"; 7297 reg = <0x0 0x11c05000 0x0 0x1000>; 7298 7299 clocks = <&aoss_qmp>; 7300 clock-names = "apb_pclk"; 7301 7302 in-ports { 7303 port { 7304 etf0_in: endpoint { 7305 remote-endpoint = <&aoss_funnel_out>; 7306 }; 7307 }; 7308 }; 7309 7310 out-ports { 7311 port { 7312 etf0_out: endpoint { 7313 remote-endpoint = <&swao_rep_in>; 7314 }; 7315 }; 7316 }; 7317 }; 7318 7319 replicator@11c06000 { 7320 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7321 reg = <0x0 0x11c06000 0x0 0x1000>; 7322 7323 clocks = <&aoss_qmp>; 7324 clock-names = "apb_pclk"; 7325 7326 in-ports { 7327 port { 7328 swao_rep_in: endpoint { 7329 remote-endpoint = <&etf0_out>; 7330 }; 7331 }; 7332 }; 7333 7334 out-ports { 7335 #address-cells = <1>; 7336 #size-cells = <0>; 7337 7338 port@0 { 7339 reg = <0>; 7340 7341 swao_rep_out0: endpoint { 7342 remote-endpoint = <&qdss_rep_in>; 7343 }; 7344 }; 7345 7346 port@1 { 7347 reg = <1>; 7348 7349 swao_rep_out1: endpoint { 7350 remote-endpoint = <&eud_in>; 7351 }; 7352 }; 7353 }; 7354 }; 7355 7356 tpda@11c08000 { 7357 compatible = "qcom,coresight-tpda", "arm,primecell"; 7358 reg = <0x0 0x11c08000 0x0 0x1000>; 7359 7360 clocks = <&aoss_qmp>; 7361 clock-names = "apb_pclk"; 7362 7363 in-ports { 7364 #address-cells = <1>; 7365 #size-cells = <0>; 7366 7367 port@0 { 7368 reg = <0>; 7369 7370 aoss_tpda_in0: endpoint { 7371 remote-endpoint = <&swao_prio0_tpdm_out>; 7372 }; 7373 }; 7374 7375 port@1 { 7376 reg = <1>; 7377 7378 aoss_tpda_in1: endpoint { 7379 remote-endpoint = <&swao_prio1_tpdm_out>; 7380 }; 7381 }; 7382 7383 port@2 { 7384 reg = <2>; 7385 7386 aoss_tpda_in2: endpoint { 7387 remote-endpoint = <&swao_prio2_tpdm_out>; 7388 }; 7389 }; 7390 7391 port@3 { 7392 reg = <3>; 7393 7394 aoss_tpda_in3: endpoint { 7395 remote-endpoint = <&swao_prio3_tpdm_out>; 7396 }; 7397 }; 7398 7399 port@4 { 7400 reg = <4>; 7401 7402 aoss_tpda_in4: endpoint { 7403 remote-endpoint = <&swao_prio4_tpdm_out>; 7404 }; 7405 }; 7406 7407 port@5 { 7408 reg = <5>; 7409 7410 aoss_tpda_in5: endpoint { 7411 remote-endpoint = <&swao_tpdm_out>; 7412 }; 7413 }; 7414 }; 7415 7416 out-ports { 7417 port { 7418 aoss_tpda_out: endpoint { 7419 remote-endpoint = <&aoss_funnel_in5>; 7420 }; 7421 }; 7422 }; 7423 }; 7424 7425 tpdm@11c09000 { 7426 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7427 reg = <0x0 0x11c09000 0x0 0x1000>; 7428 7429 clocks = <&aoss_qmp>; 7430 clock-names = "apb_pclk"; 7431 label = "tpdm_swao_prio_0"; 7432 7433 qcom,cmb-element-bits = <64>; 7434 qcom,cmb-msrs-num = <32>; 7435 7436 out-ports { 7437 port { 7438 swao_prio0_tpdm_out: endpoint { 7439 remote-endpoint = <&aoss_tpda_in0>; 7440 }; 7441 }; 7442 }; 7443 }; 7444 7445 tpdm@11c0a000 { 7446 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7447 reg = <0x0 0x11c0a000 0x0 0x1000>; 7448 7449 clocks = <&aoss_qmp>; 7450 clock-names = "apb_pclk"; 7451 label = "tpdm_swao_prio_1"; 7452 7453 qcom,cmb-element-bits = <64>; 7454 qcom,cmb-msrs-num = <32>; 7455 7456 out-ports { 7457 port { 7458 swao_prio1_tpdm_out: endpoint { 7459 remote-endpoint = <&aoss_tpda_in1>; 7460 }; 7461 }; 7462 }; 7463 }; 7464 7465 tpdm@11c0b000 { 7466 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7467 reg = <0x0 0x11c0b000 0x0 0x1000>; 7468 7469 clocks = <&aoss_qmp>; 7470 clock-names = "apb_pclk"; 7471 label = "tpdm_swao_prio_2"; 7472 7473 qcom,cmb-element-bits = <64>; 7474 qcom,cmb-msrs-num = <32>; 7475 7476 out-ports { 7477 port { 7478 swao_prio2_tpdm_out: endpoint { 7479 remote-endpoint = <&aoss_tpda_in2>; 7480 }; 7481 }; 7482 }; 7483 }; 7484 7485 tpdm@11c0c000 { 7486 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7487 reg = <0x0 0x11c0c000 0x0 0x1000>; 7488 7489 clocks = <&aoss_qmp>; 7490 clock-names = "apb_pclk"; 7491 label = "tpdm_swao_prio_3"; 7492 7493 qcom,cmb-element-bits = <64>; 7494 qcom,cmb-msrs-num = <32>; 7495 7496 out-ports { 7497 port { 7498 swao_prio3_tpdm_out: endpoint { 7499 remote-endpoint = <&aoss_tpda_in3>; 7500 }; 7501 }; 7502 }; 7503 }; 7504 7505 tpdm@11c0d000 { 7506 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7507 reg = <0x0 0x11c0d000 0x0 0x1000>; 7508 7509 clocks = <&aoss_qmp>; 7510 clock-names = "apb_pclk"; 7511 label = "tpdm_swao"; 7512 7513 qcom,dsb-element-bits = <32>; 7514 qcom,dsb-msrs-num = <32>; 7515 7516 out-ports { 7517 port { 7518 swao_tpdm_out: endpoint { 7519 remote-endpoint = <&aoss_tpda_in5>; 7520 }; 7521 }; 7522 }; 7523 }; 7524 7525 sram@14680000 { 7526 compatible = "qcom,glymur-imem", "mmio-sram"; 7527 reg = <0x0 0x14680000 0x0 0x2c000>; 7528 ranges = <0 0 0x14680000 0x2c000>; 7529 7530 no-memory-wc; 7531 7532 #address-cells = <1>; 7533 #size-cells = <1>; 7534 7535 pil-sram@94c { 7536 compatible = "qcom,pil-reloc-info"; 7537 reg = <0x94c 0xc8>; 7538 }; 7539 }; 7540 7541 apps_smmu: iommu@15000000 { 7542 compatible = "qcom,glymur-smmu-500", 7543 "qcom,smmu-500", 7544 "arm,mmu-500"; 7545 reg = <0x0 0x15000000 0x0 0x100000>; 7546 7547 #iommu-cells = <2>; 7548 #global-interrupts = <1>; 7549 7550 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 7551 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 7552 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7553 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7554 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7555 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7556 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7557 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7558 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7559 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7560 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7561 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7562 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7563 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7564 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7565 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7566 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7567 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7568 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7569 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7570 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7571 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7572 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7573 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7574 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7575 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7576 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7577 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7578 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7579 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7580 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7581 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7582 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7583 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7584 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7585 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7586 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7587 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7588 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7589 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7590 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7591 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7592 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7593 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7594 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7595 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7596 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7597 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7598 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7599 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7600 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7601 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7602 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7603 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7604 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7605 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7606 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7607 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7608 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7609 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7610 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7611 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7612 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7613 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7614 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7615 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7616 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7617 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7618 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7619 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7620 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7621 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7622 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7623 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7624 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7625 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7626 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7627 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7628 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7629 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7630 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7631 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7632 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7633 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7634 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7635 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7636 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7637 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7638 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7639 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7640 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7641 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7642 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7643 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7644 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7645 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7646 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 7647 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 7648 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 7649 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 7650 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 7651 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 7652 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 7653 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 7654 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 7655 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 7656 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 7657 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 7658 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 7659 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 7660 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 7661 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 7662 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 7663 7664 dma-coherent; 7665 }; 7666 7667 pcie_smmu: iommu@15480000 { 7668 compatible = "arm,smmu-v3"; 7669 reg = <0x0 0x15480000 0x0 0x20000>; 7670 interrupts = <GIC_ESPI 4 IRQ_TYPE_LEVEL_HIGH>, 7671 <GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>, 7672 <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>; 7673 interrupt-names = "eventq", "cmdq-sync", "gerror"; 7674 dma-coherent; 7675 #iommu-cells = <1>; 7676 }; 7677 7678 intc: interrupt-controller@17000000 { 7679 compatible = "arm,gic-v3"; 7680 reg = <0x0 0x17000000 0x0 0x10000>, 7681 <0x0 0x17080000 0x0 0x480000>; 7682 7683 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7684 7685 #interrupt-cells = <3>; 7686 interrupt-controller; 7687 7688 #address-cells = <2>; 7689 #size-cells = <2>; 7690 ranges; 7691 7692 gic_its: msi-controller@17040000 { 7693 compatible = "arm,gic-v3-its"; 7694 reg = <0x0 0x17040000 0x0 0x40000>; 7695 7696 msi-controller; 7697 #msi-cells = <1>; 7698 }; 7699 }; 7700 7701 watchdog@17600000 { 7702 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 7703 reg = <0x0 0x17600000 0x0 0x1000>; 7704 clocks = <&sleep_clk>; 7705 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7706 }; 7707 7708 pdp0_mbox: mailbox@17610000 { 7709 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 7710 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 7711 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 7712 #mbox-cells = <1>; 7713 }; 7714 7715 timer@17810000 { 7716 compatible = "arm,armv7-timer-mem"; 7717 reg = <0x0 0x17810000 0x0 0x1000>; 7718 #address-cells = <2>; 7719 #size-cells = <1>; 7720 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 7721 7722 frame@17811000 { 7723 reg = <0x0 0x17811000 0x1000>, 7724 <0x0 0x17812000 0x1000>; 7725 7726 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7727 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7728 7729 frame-number = <0>; 7730 }; 7731 7732 frame@17813000 { 7733 reg = <0x0 0x17813000 0x1000>; 7734 7735 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7736 7737 frame-number = <1>; 7738 7739 status = "disabled"; 7740 }; 7741 7742 frame@17815000 { 7743 reg = <0x0 0x17815000 0x1000>; 7744 7745 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7746 7747 frame-number = <2>; 7748 7749 status = "disabled"; 7750 }; 7751 7752 frame@17817000 { 7753 reg = <0x0 0x17817000 0x1000>; 7754 7755 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7756 7757 frame-number = <3>; 7758 7759 status = "disabled"; 7760 }; 7761 7762 frame@17819000 { 7763 reg = <0x0 0x17819000 0x1000>; 7764 7765 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7766 7767 frame-number = <4>; 7768 7769 status = "disabled"; 7770 }; 7771 7772 frame@1781b000 { 7773 reg = <0x0 0x1781b000 0x1000>; 7774 7775 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7776 7777 frame-number = <5>; 7778 7779 status = "disabled"; 7780 }; 7781 7782 frame@1781d000 { 7783 reg = <0x0 0x1781d000 0x1000>; 7784 7785 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7786 7787 frame-number = <6>; 7788 7789 status = "disabled"; 7790 }; 7791 }; 7792 7793 apps_rsc: rsc@18900000 { 7794 compatible = "qcom,rpmh-rsc"; 7795 label = "apps_rsc"; 7796 reg = <0x0 0x18900000 0x0 0x10000>, 7797 <0x0 0x18910000 0x0 0x10000>, 7798 <0x0 0x18920000 0x0 0x10000>; 7799 reg-names = "drv-0", 7800 "drv-1", 7801 "drv-2"; 7802 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7803 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7804 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7805 qcom,tcs-offset = <0xd00>; 7806 qcom,drv-id = <2>; 7807 qcom,tcs-config = <ACTIVE_TCS 2>, 7808 <SLEEP_TCS 3>, 7809 <WAKE_TCS 3>, 7810 <CONTROL_TCS 0>; 7811 power-domains = <&system_pd>; 7812 7813 apps_bcm_voter: bcm-voter { 7814 compatible = "qcom,bcm-voter"; 7815 }; 7816 7817 rpmhcc: clock-controller { 7818 compatible = "qcom,glymur-rpmh-clk"; 7819 7820 clocks = <&xo_board>; 7821 clock-names = "xo"; 7822 7823 #clock-cells = <1>; 7824 }; 7825 7826 rpmhpd: power-controller { 7827 compatible = "qcom,glymur-rpmhpd"; 7828 7829 operating-points-v2 = <&rpmhpd_opp_table>; 7830 7831 #power-domain-cells = <1>; 7832 7833 rpmhpd_opp_table: opp-table { 7834 compatible = "operating-points-v2"; 7835 7836 rpmhpd_opp_ret: opp-16 { 7837 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7838 }; 7839 7840 rpmhpd_opp_min_svs: opp-48 { 7841 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7842 }; 7843 7844 rpmhpd_opp_low_svs_d2: opp-52 { 7845 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 7846 }; 7847 7848 rpmhpd_opp_low_svs_d1: opp-56 { 7849 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 7850 }; 7851 7852 rpmhpd_opp_low_svs_d0: opp-60 { 7853 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 7854 }; 7855 7856 rpmhpd_opp_low_svs: opp-64 { 7857 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7858 }; 7859 7860 rpmhpd_opp_low_svs_l1: opp-80 { 7861 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 7862 }; 7863 7864 rpmhpd_opp_svs: opp-128 { 7865 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7866 }; 7867 7868 rpmhpd_opp_svs_l0: opp-144 { 7869 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 7870 }; 7871 7872 rpmhpd_opp_svs_l1: opp-192 { 7873 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7874 }; 7875 7876 rpmhpd_opp_nom: opp-256 { 7877 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7878 }; 7879 7880 rpmhpd_opp_nom_l1: opp-320 { 7881 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7882 }; 7883 7884 rpmhpd_opp_nom_l2: opp-336 { 7885 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7886 }; 7887 7888 rpmhpd_opp_turbo: opp-384 { 7889 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7890 }; 7891 7892 rpmhpd_opp_turbo_l1: opp-416 { 7893 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7894 }; 7895 }; 7896 }; 7897 }; 7898 7899 nsi_noc: interconnect@1d600000 { 7900 compatible = "qcom,glymur-nsinoc"; 7901 reg = <0x0 0x1d600000 0x0 0x14080>; 7902 qcom,bcm-voters = <&apps_bcm_voter>; 7903 #interconnect-cells = <2>; 7904 }; 7905 7906 oobm_ss_noc: interconnect@1f300000 { 7907 compatible = "qcom,glymur-oobm-ss-noc"; 7908 reg = <0x0 0x1f300000 0x0 0x49a00>; 7909 qcom,bcm-voters = <&apps_bcm_voter>; 7910 #interconnect-cells = <2>; 7911 }; 7912 7913 system-cache-controller@21800000 { 7914 compatible = "qcom,glymur-llcc"; 7915 reg = <0x0 0x21800000 0x0 0x100000>, 7916 <0x0 0x21a00000 0x0 0x100000>, 7917 <0x0 0x21c00000 0x0 0x100000>, 7918 <0x0 0x21e00000 0x0 0x100000>, 7919 <0x0 0x22800000 0x0 0x100000>, 7920 <0x0 0x22a00000 0x0 0x100000>, 7921 <0x0 0x22c00000 0x0 0x100000>, 7922 <0x0 0x22e00000 0x0 0x100000>, 7923 <0x0 0x23800000 0x0 0x100000>, 7924 <0x0 0x23a00000 0x0 0x100000>, 7925 <0x0 0x23c00000 0x0 0x100000>, 7926 <0x0 0x23e00000 0x0 0x100000>, 7927 <0x0 0x20400000 0x0 0x100000>, 7928 <0x0 0x20600000 0x0 0x100000>; 7929 reg-names = "llcc0_base", 7930 "llcc1_base", 7931 "llcc2_base", 7932 "llcc3_base", 7933 "llcc4_base", 7934 "llcc5_base", 7935 "llcc6_base", 7936 "llcc7_base", 7937 "llcc8_base", 7938 "llcc9_base", 7939 "llcc10_base", 7940 "llcc11_base", 7941 "llcc_broadcast_base", 7942 "llcc_broadcast_and_base"; 7943 7944 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 7945 }; 7946 7947 remoteproc_cdsp: remoteproc@32300000 { 7948 compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; 7949 reg = <0x0 0x32300000 0x0 0x10000>; 7950 7951 iommus = <&apps_smmu 0x2400 0x400>; 7952 7953 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7954 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7955 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7956 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7957 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 7958 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 7959 interrupt-names = "wdog", 7960 "fatal", 7961 "ready", 7962 "handover", 7963 "stop-ack", 7964 "shutdown-ack"; 7965 7966 clocks = <&rpmhcc RPMH_CXO_CLK>; 7967 clock-names = "xo"; 7968 7969 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7970 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7971 7972 power-domains = <&rpmhpd RPMHPD_CX>, 7973 <&rpmhpd RPMHPD_MXC>, 7974 <&rpmhpd RPMHPD_NSP>; 7975 power-domain-names = "cx", 7976 "mxc", 7977 "nsp"; 7978 7979 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 7980 qcom,qmp = <&aoss_qmp>; 7981 qcom,smem-states = <&smp2p_cdsp_out 0>; 7982 qcom,smem-state-names = "stop"; 7983 7984 status = "disabled"; 7985 7986 glink-edge { 7987 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 7988 IPCC_MPROC_SIGNAL_GLINK_QMP 7989 IRQ_TYPE_EDGE_RISING>; 7990 mboxes = <&ipcc IPCC_MPROC_CDSP 7991 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7992 qcom,remote-pid = <5>; 7993 label = "cdsp"; 7994 7995 fastrpc { 7996 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 7997 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7998 label = "cdsp"; 7999 #address-cells = <1>; 8000 #size-cells = <0>; 8001 8002 compute-cb@1 { 8003 compatible = "qcom,fastrpc-compute-cb"; 8004 reg = <1>; 8005 8006 iommus = <&apps_smmu 0x2401 0x440>, 8007 <&apps_smmu 0x1961 0x0>, 8008 <&apps_smmu 0x19c1 0x0>; 8009 dma-coherent; 8010 }; 8011 8012 compute-cb@2 { 8013 compatible = "qcom,fastrpc-compute-cb"; 8014 reg = <2>; 8015 8016 iommus = <&apps_smmu 0x2402 0x440>, 8017 <&apps_smmu 0x1962 0x0>, 8018 <&apps_smmu 0x19c2 0x0>; 8019 dma-coherent; 8020 }; 8021 8022 compute-cb@3 { 8023 compatible = "qcom,fastrpc-compute-cb"; 8024 reg = <3>; 8025 8026 iommus = <&apps_smmu 0x2403 0x440>, 8027 <&apps_smmu 0x1963 0x0>, 8028 <&apps_smmu 0x19c3 0x0>; 8029 dma-coherent; 8030 }; 8031 8032 compute-cb@4 { 8033 compatible = "qcom,fastrpc-compute-cb"; 8034 reg = <4>; 8035 8036 iommus = <&apps_smmu 0x2404 0x440>, 8037 <&apps_smmu 0x1964 0x0>, 8038 <&apps_smmu 0x19c4 0x0>; 8039 dma-coherent; 8040 }; 8041 8042 compute-cb@5 { 8043 compatible = "qcom,fastrpc-compute-cb"; 8044 reg = <5>; 8045 8046 iommus = <&apps_smmu 0x2405 0x440>, 8047 <&apps_smmu 0x1965 0x0>, 8048 <&apps_smmu 0x19c5 0x0>; 8049 dma-coherent; 8050 }; 8051 8052 compute-cb@6 { 8053 compatible = "qcom,fastrpc-compute-cb"; 8054 reg = <6>; 8055 8056 iommus = <&apps_smmu 0x2406 0x440>, 8057 <&apps_smmu 0x1966 0x0>, 8058 <&apps_smmu 0x19c6 0x0>; 8059 dma-coherent; 8060 }; 8061 8062 compute-cb@7 { 8063 compatible = "qcom,fastrpc-compute-cb"; 8064 reg = <7>; 8065 8066 iommus = <&apps_smmu 0x2407 0x440>, 8067 <&apps_smmu 0x1967 0x0>, 8068 <&apps_smmu 0x19c7 0x0>; 8069 dma-coherent; 8070 }; 8071 8072 compute-cb@8 { 8073 compatible = "qcom,fastrpc-compute-cb"; 8074 reg = <8>; 8075 8076 iommus = <&apps_smmu 0x2408 0x440>, 8077 <&apps_smmu 0x1968 0x0>, 8078 <&apps_smmu 0x19c8 0x0>; 8079 dma-coherent; 8080 }; 8081 8082 /* note: compute-cb@9 is secure */ 8083 8084 compute-cb@10 { 8085 compatible = "qcom,fastrpc-compute-cb"; 8086 reg = <10>; 8087 8088 iommus = <&apps_smmu 0x240c 0x440>, 8089 <&apps_smmu 0x196c 0x0>, 8090 <&apps_smmu 0x19cc 0x0>; 8091 dma-coherent; 8092 }; 8093 8094 compute-cb@11 { 8095 compatible = "qcom,fastrpc-compute-cb"; 8096 reg = <11>; 8097 8098 iommus = <&apps_smmu 0x240d 0x440>, 8099 <&apps_smmu 0x196d 0x0>, 8100 <&apps_smmu 0x19cd 0x0>; 8101 dma-coherent; 8102 }; 8103 8104 compute-cb@12 { 8105 compatible = "qcom,fastrpc-compute-cb"; 8106 reg = <12>; 8107 8108 iommus = <&apps_smmu 0x240e 0x440>, 8109 <&apps_smmu 0x196e 0x0>, 8110 <&apps_smmu 0x19ce 0x0>; 8111 dma-coherent; 8112 }; 8113 }; 8114 }; 8115 }; 8116 8117 nsp_noc: interconnect@320c0000 { 8118 compatible = "qcom,glymur-nsp-noc"; 8119 reg = <0x0 0x320c0000 0x0 0x21280>; 8120 qcom,bcm-voters = <&apps_bcm_voter>; 8121 #interconnect-cells = <2>; 8122 }; 8123 8124 qfprom: efuse@361c8000 { 8125 compatible = "qcom,glymur-qfprom", "qcom,qfprom"; 8126 reg = <0x0 0x361c8000 0x0 0x1000>; 8127 #address-cells = <1>; 8128 #size-cells = <1>; 8129 8130 gpu_speed_bin: gpu-speed-bin@138 { 8131 reg = <0x138 0x2>; 8132 bits = <0 9>; 8133 }; 8134 }; 8135 8136 imem: sram@81e08600 { 8137 compatible = "mmio-sram"; 8138 reg = <0x0 0x81e08600 0x0 0x300>; 8139 8140 #address-cells = <1>; 8141 #size-cells = <1>; 8142 ranges = <0x0 0x0 0x81e08600 0x300>; 8143 8144 cpu_scp_lpri0: scp-sram-section@0 { 8145 compatible = "arm,scmi-shmem"; 8146 reg = <0x0 0x180>; 8147 }; 8148 8149 cpu_scp_lpri1: scp-sram-section@180 { 8150 compatible = "arm,scmi-shmem"; 8151 reg = <0x180 0x180>; 8152 }; 8153 }; 8154 }; 8155 8156 timer { 8157 compatible = "arm,armv8-timer"; 8158 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8159 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8160 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8161 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 8162 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 8163 }; 8164 8165 thermal_zones: thermal-zones { 8166 aoss-0-thermal { 8167 thermal-sensors = <&tsens0 0>; 8168 8169 trips { 8170 aoss-0-critical { 8171 temperature = <115000>; 8172 hysteresis = <1000>; 8173 type = "critical"; 8174 }; 8175 }; 8176 }; 8177 8178 cpu-0-0-0-thermal { 8179 thermal-sensors = <&tsens0 1>; 8180 8181 trips { 8182 cpu-0-0-0-critical { 8183 temperature = <115000>; 8184 hysteresis = <1000>; 8185 type = "critical"; 8186 }; 8187 }; 8188 }; 8189 8190 cpu-0-0-1-thermal { 8191 thermal-sensors = <&tsens0 2>; 8192 8193 trips { 8194 cpu-0-0-1-critical { 8195 temperature = <115000>; 8196 hysteresis = <1000>; 8197 type = "critical"; 8198 }; 8199 }; 8200 }; 8201 8202 cpu-0-1-0-thermal { 8203 thermal-sensors = <&tsens0 3>; 8204 8205 trips { 8206 cpu-0-1-0-critical { 8207 temperature = <115000>; 8208 hysteresis = <1000>; 8209 type = "critical"; 8210 }; 8211 }; 8212 }; 8213 8214 cpu-0-1-1-thermal { 8215 thermal-sensors = <&tsens0 4>; 8216 8217 trips { 8218 cpu-0-1-1-critical { 8219 temperature = <115000>; 8220 hysteresis = <1000>; 8221 type = "critical"; 8222 }; 8223 }; 8224 }; 8225 8226 cpu-0-2-0-thermal { 8227 thermal-sensors = <&tsens0 5>; 8228 8229 trips { 8230 cpu-0-2-0-critical { 8231 temperature = <115000>; 8232 hysteresis = <1000>; 8233 type = "critical"; 8234 }; 8235 }; 8236 }; 8237 8238 cpu-0-2-1-thermal { 8239 thermal-sensors = <&tsens0 6>; 8240 8241 trips { 8242 cpu-0-2-1-critical { 8243 temperature = <115000>; 8244 hysteresis = <1000>; 8245 type = "critical"; 8246 }; 8247 }; 8248 }; 8249 8250 cpu-0-3-0-thermal { 8251 thermal-sensors = <&tsens0 7>; 8252 8253 trips { 8254 cpu-0-3-0-critical { 8255 temperature = <115000>; 8256 hysteresis = <1000>; 8257 type = "critical"; 8258 }; 8259 }; 8260 }; 8261 8262 cpu-0-3-1-thermal { 8263 thermal-sensors = <&tsens0 8>; 8264 8265 trips { 8266 cpu-0-3-1-critical { 8267 temperature = <115000>; 8268 hysteresis = <1000>; 8269 type = "critical"; 8270 }; 8271 }; 8272 }; 8273 8274 cpu-0-4-0-thermal { 8275 thermal-sensors = <&tsens0 9>; 8276 8277 trips { 8278 cpu-0-4-0-critical { 8279 temperature = <115000>; 8280 hysteresis = <1000>; 8281 type = "critical"; 8282 }; 8283 }; 8284 }; 8285 8286 cpu-0-4-1-thermal { 8287 thermal-sensors = <&tsens0 10>; 8288 8289 trips { 8290 cpu-0-4-1-critical { 8291 temperature = <115000>; 8292 hysteresis = <1000>; 8293 type = "critical"; 8294 }; 8295 }; 8296 }; 8297 8298 cpu-0-5-0-thermal { 8299 thermal-sensors = <&tsens0 11>; 8300 8301 trips { 8302 cpu-0-5-0-critical { 8303 temperature = <115000>; 8304 hysteresis = <1000>; 8305 type = "critical"; 8306 }; 8307 }; 8308 }; 8309 8310 cpu-0-5-1-thermal { 8311 thermal-sensors = <&tsens0 12>; 8312 8313 trips { 8314 cpu-0-5-1-critical { 8315 temperature = <115000>; 8316 hysteresis = <1000>; 8317 type = "critical"; 8318 }; 8319 }; 8320 }; 8321 8322 aoss-1-thermal { 8323 thermal-sensors = <&tsens1 0>; 8324 8325 trips { 8326 aoss-1-critical { 8327 temperature = <115000>; 8328 hysteresis = <1000>; 8329 type = "critical"; 8330 }; 8331 }; 8332 }; 8333 8334 cpullc-0-0-thermal { 8335 thermal-sensors = <&tsens1 1>; 8336 8337 trips { 8338 cpullc-0-0-critical { 8339 temperature = <115000>; 8340 hysteresis = <1000>; 8341 type = "critical"; 8342 }; 8343 }; 8344 }; 8345 8346 cpullc-0-1-thermal { 8347 thermal-sensors = <&tsens1 2>; 8348 8349 trips { 8350 cpullc-0-1-critical { 8351 temperature = <115000>; 8352 hysteresis = <1000>; 8353 type = "critical"; 8354 }; 8355 }; 8356 }; 8357 8358 qmx-0-0-thermal { 8359 thermal-sensors = <&tsens1 3>; 8360 8361 trips { 8362 qmx-0-0-critical { 8363 temperature = <115000>; 8364 hysteresis = <1000>; 8365 type = "critical"; 8366 }; 8367 }; 8368 }; 8369 8370 qmx-0-1-thermal { 8371 thermal-sensors = <&tsens1 4>; 8372 8373 trips { 8374 qmx-0-1-critical { 8375 temperature = <115000>; 8376 hysteresis = <1000>; 8377 type = "critical"; 8378 }; 8379 }; 8380 }; 8381 8382 qmx-0-2-thermal { 8383 thermal-sensors = <&tsens1 5>; 8384 8385 trips { 8386 qmx-0-2-critical { 8387 temperature = <115000>; 8388 hysteresis = <1000>; 8389 type = "critical"; 8390 }; 8391 }; 8392 }; 8393 8394 ddr-0-thermal { 8395 thermal-sensors = <&tsens1 6>; 8396 8397 trips { 8398 ddr-0-critical { 8399 temperature = <115000>; 8400 hysteresis = <1000>; 8401 type = "critical"; 8402 }; 8403 }; 8404 }; 8405 8406 thermal_video_0: video-0-thermal { 8407 thermal-sensors = <&tsens1 7>; 8408 8409 trips { 8410 video-0-critical { 8411 temperature = <115000>; 8412 hysteresis = <1000>; 8413 type = "critical"; 8414 }; 8415 }; 8416 }; 8417 8418 thermal_video_1: video-1-thermal { 8419 thermal-sensors = <&tsens1 8>; 8420 8421 trips { 8422 video-1-critical { 8423 temperature = <115000>; 8424 hysteresis = <1000>; 8425 type = "critical"; 8426 }; 8427 }; 8428 }; 8429 8430 aoss-2-thermal { 8431 thermal-sensors = <&tsens2 0>; 8432 8433 trips { 8434 aoss-2-critical { 8435 temperature = <115000>; 8436 hysteresis = <1000>; 8437 type = "critical"; 8438 }; 8439 }; 8440 }; 8441 8442 cpu-1-0-0-thermal { 8443 thermal-sensors = <&tsens2 1>; 8444 8445 trips { 8446 cpu-1-0-0-critical { 8447 temperature = <115000>; 8448 hysteresis = <1000>; 8449 type = "critical"; 8450 }; 8451 }; 8452 }; 8453 8454 cpu-1-0-1-thermal { 8455 thermal-sensors = <&tsens2 2>; 8456 8457 trips { 8458 cpu-1-0-1-critical { 8459 temperature = <115000>; 8460 hysteresis = <1000>; 8461 type = "critical"; 8462 }; 8463 }; 8464 }; 8465 8466 cpu-1-1-0-thermal { 8467 thermal-sensors = <&tsens2 3>; 8468 8469 trips { 8470 cpu-1-1-0-critical { 8471 temperature = <115000>; 8472 hysteresis = <1000>; 8473 type = "critical"; 8474 }; 8475 }; 8476 }; 8477 8478 cpu-1-1-1-thermal { 8479 thermal-sensors = <&tsens2 4>; 8480 8481 trips { 8482 cpu-1-1-1-critical { 8483 temperature = <115000>; 8484 hysteresis = <1000>; 8485 type = "critical"; 8486 }; 8487 }; 8488 }; 8489 8490 cpu-1-2-0-thermal { 8491 thermal-sensors = <&tsens2 5>; 8492 8493 trips { 8494 cpu-1-2-0-critical { 8495 temperature = <115000>; 8496 hysteresis = <1000>; 8497 type = "critical"; 8498 }; 8499 }; 8500 }; 8501 8502 cpu-1-2-1-thermal { 8503 thermal-sensors = <&tsens2 6>; 8504 8505 trips { 8506 cpu-1-2-1-critical { 8507 temperature = <115000>; 8508 hysteresis = <1000>; 8509 type = "critical"; 8510 }; 8511 }; 8512 }; 8513 8514 cpu-1-3-0-thermal { 8515 thermal-sensors = <&tsens2 7>; 8516 8517 trips { 8518 cpu-1-3-0-critical { 8519 temperature = <115000>; 8520 hysteresis = <1000>; 8521 type = "critical"; 8522 }; 8523 }; 8524 }; 8525 8526 cpu-1-3-1-thermal { 8527 thermal-sensors = <&tsens2 8>; 8528 8529 trips { 8530 cpu-1-3-1-critical { 8531 temperature = <115000>; 8532 hysteresis = <1000>; 8533 type = "critical"; 8534 }; 8535 }; 8536 }; 8537 8538 cpu-1-4-0-thermal { 8539 thermal-sensors = <&tsens2 9>; 8540 8541 trips { 8542 cpu-1-4-0-critical { 8543 temperature = <115000>; 8544 hysteresis = <1000>; 8545 type = "critical"; 8546 }; 8547 }; 8548 }; 8549 8550 cpu-1-4-1-thermal { 8551 thermal-sensors = <&tsens2 10>; 8552 8553 trips { 8554 cpu-1-4-1-critical { 8555 temperature = <115000>; 8556 hysteresis = <1000>; 8557 type = "critical"; 8558 }; 8559 }; 8560 }; 8561 8562 cpu-1-5-0-thermal { 8563 thermal-sensors = <&tsens2 11>; 8564 8565 trips { 8566 cpu-1-5-0-critical { 8567 temperature = <115000>; 8568 hysteresis = <1000>; 8569 type = "critical"; 8570 }; 8571 }; 8572 }; 8573 8574 cpu-1-5-1-thermal { 8575 thermal-sensors = <&tsens2 12>; 8576 8577 trips { 8578 cpu-1-5-1-critical { 8579 temperature = <115000>; 8580 hysteresis = <1000>; 8581 type = "critical"; 8582 }; 8583 }; 8584 }; 8585 8586 aoss-3-thermal { 8587 thermal-sensors = <&tsens3 0>; 8588 8589 trips { 8590 aoss-3-critical { 8591 temperature = <115000>; 8592 hysteresis = <1000>; 8593 type = "critical"; 8594 }; 8595 }; 8596 }; 8597 8598 cpullc-1-0-thermal { 8599 thermal-sensors = <&tsens3 1>; 8600 8601 trips { 8602 cpullc-1-0-critical { 8603 temperature = <115000>; 8604 hysteresis = <1000>; 8605 type = "critical"; 8606 }; 8607 }; 8608 }; 8609 8610 cpullc-1-1-thermal { 8611 thermal-sensors = <&tsens3 2>; 8612 8613 trips { 8614 cpullc-1-1-critical { 8615 temperature = <115000>; 8616 hysteresis = <1000>; 8617 type = "critical"; 8618 }; 8619 }; 8620 }; 8621 8622 qmx-1-0-thermal { 8623 thermal-sensors = <&tsens3 3>; 8624 8625 trips { 8626 qmx-1-0-critical { 8627 temperature = <115000>; 8628 hysteresis = <1000>; 8629 type = "critical"; 8630 }; 8631 }; 8632 }; 8633 8634 qmx-1-1-thermal { 8635 thermal-sensors = <&tsens3 4>; 8636 8637 trips { 8638 qmx-1-1-critical { 8639 temperature = <115000>; 8640 hysteresis = <1000>; 8641 type = "critical"; 8642 }; 8643 }; 8644 }; 8645 8646 qmx-1-2-thermal { 8647 thermal-sensors = <&tsens3 5>; 8648 8649 trips { 8650 qmx-1-2-critical { 8651 temperature = <115000>; 8652 hysteresis = <1000>; 8653 type = "critical"; 8654 }; 8655 }; 8656 }; 8657 8658 qmx-1-3-thermal { 8659 thermal-sensors = <&tsens3 6>; 8660 8661 trips { 8662 qmx-1-3-critical { 8663 temperature = <115000>; 8664 hysteresis = <1000>; 8665 type = "critical"; 8666 }; 8667 }; 8668 }; 8669 8670 qmx-1-4-thermal { 8671 thermal-sensors = <&tsens3 7>; 8672 8673 trips { 8674 qmx-1-4-critical { 8675 temperature = <115000>; 8676 hysteresis = <1000>; 8677 type = "critical"; 8678 }; 8679 }; 8680 }; 8681 8682 aoss-4-thermal { 8683 thermal-sensors = <&tsens4 0>; 8684 8685 trips { 8686 aoss-4-critical { 8687 temperature = <115000>; 8688 hysteresis = <1000>; 8689 type = "critical"; 8690 }; 8691 }; 8692 }; 8693 8694 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 8695 thermal-sensors = <&tsens4 1>; 8696 8697 trips { 8698 cpu-2-0-0-critical { 8699 temperature = <115000>; 8700 hysteresis = <1000>; 8701 type = "critical"; 8702 }; 8703 }; 8704 }; 8705 8706 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 8707 thermal-sensors = <&tsens4 2>; 8708 8709 trips { 8710 cpu-2-0-1-critical { 8711 temperature = <115000>; 8712 hysteresis = <1000>; 8713 type = "critical"; 8714 }; 8715 }; 8716 }; 8717 8718 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 8719 thermal-sensors = <&tsens4 3>; 8720 8721 trips { 8722 cpu-2-1-0-critical { 8723 temperature = <115000>; 8724 hysteresis = <1000>; 8725 type = "critical"; 8726 }; 8727 }; 8728 }; 8729 8730 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 8731 thermal-sensors = <&tsens4 4>; 8732 8733 trips { 8734 cpu-2-1-1-critical { 8735 temperature = <115000>; 8736 hysteresis = <1000>; 8737 type = "critical"; 8738 }; 8739 }; 8740 }; 8741 8742 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 8743 thermal-sensors = <&tsens4 5>; 8744 8745 trips { 8746 cpu-2-2-0-critical { 8747 temperature = <115000>; 8748 hysteresis = <1000>; 8749 type = "critical"; 8750 }; 8751 }; 8752 }; 8753 8754 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 8755 thermal-sensors = <&tsens4 6>; 8756 8757 trips { 8758 cpu-2-2-1-critical { 8759 temperature = <115000>; 8760 hysteresis = <1000>; 8761 type = "critical"; 8762 }; 8763 }; 8764 }; 8765 8766 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 8767 thermal-sensors = <&tsens4 7>; 8768 8769 trips { 8770 cpu-2-3-0-critical { 8771 temperature = <115000>; 8772 hysteresis = <1000>; 8773 type = "critical"; 8774 }; 8775 }; 8776 }; 8777 8778 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 8779 thermal-sensors = <&tsens4 8>; 8780 8781 trips { 8782 cpu-2-3-1-critical { 8783 temperature = <115000>; 8784 hysteresis = <1000>; 8785 type = "critical"; 8786 }; 8787 }; 8788 }; 8789 8790 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 8791 thermal-sensors = <&tsens4 9>; 8792 8793 trips { 8794 cpu-2-4-0-critical { 8795 temperature = <115000>; 8796 hysteresis = <1000>; 8797 type = "critical"; 8798 }; 8799 }; 8800 }; 8801 8802 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 8803 thermal-sensors = <&tsens4 10>; 8804 8805 trips { 8806 cpu-2-4-1-critical { 8807 temperature = <115000>; 8808 hysteresis = <1000>; 8809 type = "critical"; 8810 }; 8811 }; 8812 }; 8813 8814 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 8815 thermal-sensors = <&tsens4 11>; 8816 8817 trips { 8818 cpu-2-5-0-critical { 8819 temperature = <115000>; 8820 hysteresis = <1000>; 8821 type = "critical"; 8822 }; 8823 }; 8824 }; 8825 8826 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 8827 thermal-sensors = <&tsens4 12>; 8828 8829 trips { 8830 cpu-2-5-1-critical { 8831 temperature = <115000>; 8832 hysteresis = <1000>; 8833 type = "critical"; 8834 }; 8835 }; 8836 }; 8837 8838 aoss-5-thermal { 8839 thermal-sensors = <&tsens5 0>; 8840 8841 trips { 8842 aoss-5-critical { 8843 temperature = <115000>; 8844 hysteresis = <1000>; 8845 type = "critical"; 8846 }; 8847 }; 8848 }; 8849 8850 thermal_cpullc_2_0: cpullc-2-0-thermal { 8851 thermal-sensors = <&tsens5 1>; 8852 8853 trips { 8854 cpullc-2-0-critical { 8855 temperature = <115000>; 8856 hysteresis = <1000>; 8857 type = "critical"; 8858 }; 8859 }; 8860 }; 8861 8862 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 8863 thermal-sensors = <&tsens5 2>; 8864 8865 trips { 8866 cpullc-2-1-critical { 8867 temperature = <115000>; 8868 hysteresis = <1000>; 8869 type = "critical"; 8870 }; 8871 }; 8872 }; 8873 8874 thermal_qmx_2_0: qmx-2-0-thermal { 8875 thermal-sensors = <&tsens5 3>; 8876 8877 trips { 8878 qmx-2-0-critical { 8879 temperature = <115000>; 8880 hysteresis = <1000>; 8881 type = "critical"; 8882 }; 8883 }; 8884 }; 8885 8886 thermal_qmx_2_1: qmx-2-1-thermal { 8887 thermal-sensors = <&tsens5 4>; 8888 8889 trips { 8890 qmx-2-1-critical { 8891 temperature = <115000>; 8892 hysteresis = <1000>; 8893 type = "critical"; 8894 }; 8895 }; 8896 }; 8897 8898 thermal_qmx_2_2: qmx-2-2-thermal { 8899 thermal-sensors = <&tsens5 5>; 8900 8901 trips { 8902 qmx-2-2-critical { 8903 temperature = <115000>; 8904 hysteresis = <1000>; 8905 type = "critical"; 8906 }; 8907 }; 8908 }; 8909 8910 thermal_qmx_2_3: qmx-2-3-thermal { 8911 thermal-sensors = <&tsens5 6>; 8912 8913 trips { 8914 qmx-2-3-critical { 8915 temperature = <115000>; 8916 hysteresis = <1000>; 8917 type = "critical"; 8918 }; 8919 }; 8920 }; 8921 8922 thermal_qmx_2_4: qmx-2-4-thermal { 8923 thermal-sensors = <&tsens5 7>; 8924 8925 trips { 8926 qmx-2-4-critical { 8927 temperature = <115000>; 8928 hysteresis = <1000>; 8929 type = "critical"; 8930 }; 8931 }; 8932 }; 8933 8934 thermal_aoss_6: aoss-6-thermal { 8935 thermal-sensors = <&tsens6 0>; 8936 8937 trips { 8938 aoss-6-critical { 8939 temperature = <115000>; 8940 hysteresis = <1000>; 8941 type = "critical"; 8942 }; 8943 }; 8944 }; 8945 8946 thermal_nsphvx_0: nsphvx-0-thermal { 8947 thermal-sensors = <&tsens6 1>; 8948 8949 trips { 8950 nsphvx-0-critical { 8951 temperature = <115000>; 8952 hysteresis = <1000>; 8953 type = "critical"; 8954 }; 8955 }; 8956 }; 8957 8958 thermal_nsphvx_1: nsphvx-1-thermal { 8959 thermal-sensors = <&tsens6 2>; 8960 8961 trips { 8962 nsphvx-1-critical { 8963 temperature = <115000>; 8964 hysteresis = <1000>; 8965 type = "critical"; 8966 }; 8967 }; 8968 }; 8969 8970 thermal_nsphvx_2: nsphvx-2-thermal { 8971 thermal-sensors = <&tsens6 3>; 8972 8973 trips { 8974 nsphvx-2-critical { 8975 temperature = <115000>; 8976 hysteresis = <1000>; 8977 type = "critical"; 8978 }; 8979 }; 8980 }; 8981 8982 thermal_nsphvx_3: nsphvx-3-thermal { 8983 thermal-sensors = <&tsens6 4>; 8984 8985 trips { 8986 nsphvx-3-critical { 8987 temperature = <115000>; 8988 hysteresis = <1000>; 8989 type = "critical"; 8990 }; 8991 }; 8992 }; 8993 8994 thermal_nsphmx_0: nsphmx-0-thermal { 8995 thermal-sensors = <&tsens6 5>; 8996 8997 trips { 8998 nsphmx-0-critical { 8999 temperature = <115000>; 9000 hysteresis = <1000>; 9001 type = "critical"; 9002 }; 9003 }; 9004 }; 9005 9006 thermal_nsphmx_1: nsphmx-1-thermal { 9007 thermal-sensors = <&tsens6 6>; 9008 9009 trips { 9010 nsphmx-1-critical { 9011 temperature = <115000>; 9012 hysteresis = <1000>; 9013 type = "critical"; 9014 }; 9015 }; 9016 }; 9017 9018 thermal_nsphmx_2: nsphmx-2-thermal { 9019 thermal-sensors = <&tsens6 7>; 9020 9021 trips { 9022 nsphmx-2-critical { 9023 temperature = <115000>; 9024 hysteresis = <1000>; 9025 type = "critical"; 9026 }; 9027 }; 9028 }; 9029 9030 thermal_nsphmx_3: nsphmx-3-thermal { 9031 thermal-sensors = <&tsens6 8>; 9032 9033 trips { 9034 nsphmx-3-critical { 9035 temperature = <115000>; 9036 hysteresis = <1000>; 9037 type = "critical"; 9038 }; 9039 }; 9040 }; 9041 9042 thermal_camera_0: camera-0-thermal { 9043 thermal-sensors = <&tsens6 9>; 9044 9045 trips { 9046 camera-0-critical { 9047 temperature = <115000>; 9048 hysteresis = <1000>; 9049 type = "critical"; 9050 }; 9051 }; 9052 }; 9053 9054 thermal_camera_1: camera-1-thermal { 9055 thermal-sensors = <&tsens6 10>; 9056 9057 trips { 9058 camera-1-critical { 9059 temperature = <115000>; 9060 hysteresis = <1000>; 9061 type = "critical"; 9062 }; 9063 }; 9064 }; 9065 9066 thermal_ddr_1: ddr-1-thermal { 9067 thermal-sensors = <&tsens6 11>; 9068 9069 trips { 9070 ddr-1-critical { 9071 temperature = <115000>; 9072 hysteresis = <1000>; 9073 type = "critical"; 9074 }; 9075 }; 9076 }; 9077 9078 thermal_ddr_2: ddr-2-thermal { 9079 thermal-sensors = <&tsens6 12>; 9080 9081 trips { 9082 ddr-2-critical { 9083 temperature = <115000>; 9084 hysteresis = <1000>; 9085 type = "critical"; 9086 }; 9087 }; 9088 }; 9089 9090 thermal_aoss_7: aoss-7-thermal { 9091 thermal-sensors = <&tsens7 0>; 9092 9093 trips { 9094 aoss-7-critical { 9095 temperature = <115000>; 9096 hysteresis = <1000>; 9097 type = "critical"; 9098 }; 9099 }; 9100 }; 9101 9102 thermal_gpu_0_0: gpu-0-0-thermal { 9103 polling-delay-passive = <100>; 9104 9105 thermal-sensors = <&tsens7 1>; 9106 9107 cooling-maps { 9108 map0 { 9109 trip = <&gpu00_alert0>; 9110 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9111 }; 9112 }; 9113 9114 trips { 9115 gpu00_alert0: trip-point0 { 9116 temperature = <95000>; 9117 hysteresis = <1000>; 9118 type = "passive"; 9119 }; 9120 9121 gpu-0-0-critical { 9122 temperature = <115000>; 9123 hysteresis = <1000>; 9124 type = "critical"; 9125 }; 9126 }; 9127 9128 }; 9129 9130 thermal_gpu_0_1: gpu-0-1-thermal { 9131 polling-delay-passive = <100>; 9132 9133 thermal-sensors = <&tsens7 2>; 9134 9135 cooling-maps { 9136 map0 { 9137 trip = <&gpu01_alert0>; 9138 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9139 }; 9140 }; 9141 9142 trips { 9143 gpu01_alert0: trip-point0 { 9144 temperature = <95000>; 9145 hysteresis = <1000>; 9146 type = "passive"; 9147 }; 9148 9149 gpu-0-1-critical { 9150 temperature = <115000>; 9151 hysteresis = <1000>; 9152 type = "critical"; 9153 }; 9154 }; 9155 }; 9156 9157 thermal_gpu_0_2: gpu-0-2-thermal { 9158 polling-delay-passive = <100>; 9159 9160 thermal-sensors = <&tsens7 3>; 9161 9162 cooling-maps { 9163 map0 { 9164 trip = <&gpu02_alert0>; 9165 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9166 }; 9167 }; 9168 9169 trips { 9170 gpu02_alert0: trip-point0 { 9171 temperature = <95000>; 9172 hysteresis = <1000>; 9173 type = "passive"; 9174 }; 9175 9176 gpu-0-2-critical { 9177 temperature = <115000>; 9178 hysteresis = <1000>; 9179 type = "critical"; 9180 }; 9181 }; 9182 }; 9183 9184 thermal_gpu_1_0: gpu-1-0-thermal { 9185 polling-delay-passive = <100>; 9186 9187 thermal-sensors = <&tsens7 4>; 9188 9189 cooling-maps { 9190 map0 { 9191 trip = <&gpu10_alert0>; 9192 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9193 }; 9194 }; 9195 9196 trips { 9197 gpu10_alert0: trip-point0 { 9198 temperature = <95000>; 9199 hysteresis = <1000>; 9200 type = "passive"; 9201 }; 9202 9203 gpu-1-0-critical { 9204 temperature = <115000>; 9205 hysteresis = <1000>; 9206 type = "critical"; 9207 }; 9208 }; 9209 }; 9210 9211 thermal_gpu_1_1: gpu-1-1-thermal { 9212 polling-delay-passive = <100>; 9213 9214 thermal-sensors = <&tsens7 5>; 9215 9216 cooling-maps { 9217 map0 { 9218 trip = <&gpu11_alert0>; 9219 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9220 }; 9221 }; 9222 9223 trips { 9224 gpu11_alert0: trip-point0 { 9225 temperature = <95000>; 9226 hysteresis = <1000>; 9227 type = "passive"; 9228 }; 9229 9230 gpu-1-1-critical { 9231 temperature = <115000>; 9232 hysteresis = <1000>; 9233 type = "critical"; 9234 }; 9235 }; 9236 }; 9237 9238 thermal_gpu_1_2: gpu-1-2-thermal { 9239 polling-delay-passive = <100>; 9240 9241 thermal-sensors = <&tsens7 6>; 9242 9243 cooling-maps { 9244 map0 { 9245 trip = <&gpu12_alert0>; 9246 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9247 }; 9248 }; 9249 9250 trips { 9251 gpu12_alert0: trip-point0 { 9252 temperature = <95000>; 9253 hysteresis = <1000>; 9254 type = "passive"; 9255 }; 9256 9257 gpu-1-2-critical { 9258 temperature = <115000>; 9259 hysteresis = <1000>; 9260 type = "critical"; 9261 }; 9262 }; 9263 }; 9264 9265 thermal_gpu_2_0: gpu-2-0-thermal { 9266 polling-delay-passive = <100>; 9267 9268 thermal-sensors = <&tsens7 7>; 9269 9270 cooling-maps { 9271 map0 { 9272 trip = <&gpu20_alert0>; 9273 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9274 }; 9275 }; 9276 9277 trips { 9278 gpu20_alert0: trip-point0 { 9279 temperature = <95000>; 9280 hysteresis = <1000>; 9281 type = "passive"; 9282 }; 9283 9284 gpu-2-0-critical { 9285 temperature = <115000>; 9286 hysteresis = <1000>; 9287 type = "critical"; 9288 }; 9289 }; 9290 }; 9291 9292 thermal_gpu_2_1: gpu-2-1-thermal { 9293 polling-delay-passive = <100>; 9294 9295 thermal-sensors = <&tsens7 8>; 9296 9297 cooling-maps { 9298 map0 { 9299 trip = <&gpu21_alert0>; 9300 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9301 }; 9302 }; 9303 9304 trips { 9305 gpu21_alert0: trip-point0 { 9306 temperature = <95000>; 9307 hysteresis = <1000>; 9308 type = "passive"; 9309 }; 9310 9311 gpu-2-1-critical { 9312 temperature = <115000>; 9313 hysteresis = <1000>; 9314 type = "critical"; 9315 }; 9316 }; 9317 }; 9318 9319 thermal_gpu_2_2: gpu-2-2-thermal { 9320 polling-delay-passive = <100>; 9321 9322 thermal-sensors = <&tsens7 9>; 9323 9324 cooling-maps { 9325 map0 { 9326 trip = <&gpu22_alert0>; 9327 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9328 }; 9329 }; 9330 9331 trips { 9332 gpu22_alert0: trip-point0 { 9333 temperature = <95000>; 9334 hysteresis = <1000>; 9335 type = "passive"; 9336 }; 9337 9338 gpu-2-2-critical { 9339 temperature = <115000>; 9340 hysteresis = <1000>; 9341 type = "critical"; 9342 }; 9343 }; 9344 }; 9345 9346 thermal_gpu_3_0: gpu-3-0-thermal { 9347 polling-delay-passive = <100>; 9348 9349 thermal-sensors = <&tsens7 10>; 9350 9351 cooling-maps { 9352 map0 { 9353 trip = <&gpu30_alert0>; 9354 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9355 }; 9356 }; 9357 9358 trips { 9359 gpu30_alert0: trip-point0 { 9360 temperature = <95000>; 9361 hysteresis = <1000>; 9362 type = "passive"; 9363 }; 9364 9365 gpu-3-0-critical { 9366 temperature = <115000>; 9367 hysteresis = <1000>; 9368 type = "critical"; 9369 }; 9370 }; 9371 }; 9372 9373 thermal_gpu_3_1: gpu-3-1-thermal { 9374 polling-delay-passive = <100>; 9375 9376 thermal-sensors = <&tsens7 11>; 9377 9378 cooling-maps { 9379 map0 { 9380 trip = <&gpu31_alert0>; 9381 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9382 }; 9383 }; 9384 9385 trips { 9386 gpu31_alert0: trip-point0 { 9387 temperature = <95000>; 9388 hysteresis = <1000>; 9389 type = "passive"; 9390 }; 9391 9392 gpu-3-1-critical { 9393 temperature = <115000>; 9394 hysteresis = <1000>; 9395 type = "critical"; 9396 }; 9397 }; 9398 }; 9399 9400 thermal_gpu_3_2: gpu-3-2-thermal { 9401 polling-delay-passive = <100>; 9402 9403 thermal-sensors = <&tsens7 12>; 9404 9405 cooling-maps { 9406 map0 { 9407 trip = <&gpu32_alert0>; 9408 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9409 }; 9410 }; 9411 9412 trips { 9413 gpu32_alert0: trip-point0 { 9414 temperature = <95000>; 9415 hysteresis = <1000>; 9416 type = "passive"; 9417 }; 9418 9419 gpu-3-2-critical { 9420 temperature = <115000>; 9421 hysteresis = <1000>; 9422 type = "critical"; 9423 }; 9424 }; 9425 }; 9426 9427 thermal_gpuss_0: gpuss-0-thermal { 9428 polling-delay-passive = <100>; 9429 9430 thermal-sensors = <&tsens7 13>; 9431 9432 cooling-maps { 9433 map0 { 9434 trip = <&gpuss0_alert0>; 9435 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9436 }; 9437 }; 9438 9439 trips { 9440 gpuss0_alert0: trip-point0 { 9441 temperature = <95000>; 9442 hysteresis = <1000>; 9443 type = "passive"; 9444 }; 9445 9446 gpuss-0-critical { 9447 temperature = <115000>; 9448 hysteresis = <1000>; 9449 type = "critical"; 9450 }; 9451 }; 9452 }; 9453 9454 thermal_gpuss_1: gpuss-1-thermal { 9455 polling-delay-passive = <100>; 9456 9457 thermal-sensors = <&tsens7 14>; 9458 9459 cooling-maps { 9460 map0 { 9461 trip = <&gpuss1_alert0>; 9462 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9463 }; 9464 }; 9465 9466 trips { 9467 gpuss1_alert0: trip-point0 { 9468 temperature = <95000>; 9469 hysteresis = <1000>; 9470 type = "passive"; 9471 }; 9472 9473 gpuss-1-critical { 9474 temperature = <115000>; 9475 hysteresis = <1000>; 9476 type = "critical"; 9477 }; 9478 }; 9479 }; 9480 }; 9481 9482 tpdm-cdsp-llm { 9483 compatible = "qcom,coresight-static-tpdm"; 9484 qcom,cmb-element-bits = <32>; 9485 9486 out-ports { 9487 port { 9488 cdsp_llm_tpdm_out: endpoint { 9489 remote-endpoint = <&cdsp_tpda_in1>; 9490 }; 9491 }; 9492 }; 9493 }; 9494 9495 tpdm-cdsp-llm2 { 9496 compatible = "qcom,coresight-static-tpdm"; 9497 qcom,cmb-element-bits = <32>; 9498 9499 out-ports { 9500 port { 9501 cdsp_llm2_tpdm_out: endpoint { 9502 remote-endpoint = <&cdsp_tpda_in2>; 9503 }; 9504 }; 9505 }; 9506 }; 9507 9508 tpdm-cdsp-cmsr { 9509 compatible = "qcom,coresight-static-tpdm"; 9510 9511 qcom,cmb-element-bits = <32>; 9512 qcom,dsb-element-bits = <32>; 9513 9514 out-ports { 9515 port { 9516 cdsp_cmsr_tpdm_out: endpoint { 9517 remote-endpoint = <&cdsp_tpda_in3>; 9518 }; 9519 }; 9520 }; 9521 }; 9522 9523 tpdm-cdsp-cmsr2 { 9524 compatible = "qcom,coresight-static-tpdm"; 9525 9526 qcom,cmb-element-bits = <32>; 9527 qcom,dsb-element-bits = <32>; 9528 9529 out-ports { 9530 port { 9531 cdsp_cmsr2_tpdm_out: endpoint { 9532 remote-endpoint = <&cdsp_tpda_in4>; 9533 }; 9534 }; 9535 }; 9536 }; 9537}; 9538