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/linux/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
H A Dg84.c37 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_bind()
39 nvkm_wr32(device, 0x002600 + (chan->id * 4), chan->ramfc->addr >> 8); in g84_chan_bind()
45 struct nvkm_device *device = chan->cgrp->runl->fifo->engine.subdev.device; in g84_chan_ramfc_write()
49 ret = nvkm_gpuobj_new(device, 0x0200, 0, true, chan->inst, &chan->eng); in g84_chan_ramfc_write()
53 ret = nvkm_gpuobj_new(device, 0x4000, 0, false, chan->inst, &chan->pgd); in g84_chan_ramfc_write()
57 ret = nvkm_gpuobj_new(device, 0x1000, 0x400, true, chan->inst, &chan->cache); in g84_chan_ramfc_write()
61 ret = nvkm_gpuobj_new(device, 0x100, 0x100, true, chan->inst, &chan->ramfc); in g84_chan_ramfc_write()
65 ret = nvkm_ramht_new(device, 0x8000, 16, chan->inst, &chan->ramht); in g84_chan_ramfc_write()
69 nvkm_kmap(chan->ramfc); in g84_chan_ramfc_write()
70 nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); in g84_chan_ramfc_write()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c43 struct gk104_clk_info eng[16]; member
52 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
62 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
77 sclk = device->crystal; in read_pll()
78 P = 1; in read_pll()
82 P = (coef & 0x10000000) ? 2 : 1; in read_pll()
99 P = 1; in read_pll()
108 struct nvkm_device *device = clk->base.subdev.device; in read_div()
115 return device->crystal; in read_div()
135 struct nvkm_device *device = clk->base.subdev.device; in read_mem()
[all …]
H A Dgf100.c43 struct gf100_clk_info eng[16]; member
51 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); in read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); in read_vco()
61 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
75 sclk = device->crystal; in read_pll()
76 P = 1; in read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); in read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); in read_pll()
100 struct nvkm_device *device = clk->base.subdev.device; in read_div()
[all …]
H A Dgt215.c36 struct gt215_clk_info eng[nv_clk_src_max]; member
45 struct nvkm_device *device = clk->base.subdev.device; in read_vco()
50 return device->crystal; in read_vco()
63 struct nvkm_device *device = clk->base.subdev.device; in read_clk()
68 if (device->chipset == 0xaf) { in read_clk()
73 return device->crystal; in read_clk()
88 return device->crystal; in read_clk()
110 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll()
122 /* no post-divider on these.. in read_pll()
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v12_0.c67 if (!adev->in_s0ix) in gmc_v12_0_vm_fault_interrupt_state()
79 if (!adev->in_s0ix) in gmc_v12_0_vm_fault_interrupt_state()
97 addr = (u64)entry->src_data[0] << 12; in gmc_v12_0_process_interrupt()
98 addr |= ((u64)entry->src_data[1] & 0xf) << 44; in gmc_v12_0_process_interrupt()
100 if (entry->client_id == SOC21_IH_CLIENTID_VMC) in gmc_v12_0_process_interrupt()
101 hub = &adev->vmhub[AMDGPU_MMHUB0(0)]; in gmc_v12_0_process_interrupt()
103 hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; in gmc_v12_0_process_interrupt()
111 if (entry->vmid_src == AMDGPU_GFXHUB(0)) in gmc_v12_0_process_interrupt()
112 RREG32(hub->vm_l2_pro_fault_status); in gmc_v12_0_process_interrupt()
114 status = RREG32(hub->vm_l2_pro_fault_status); in gmc_v12_0_process_interrupt()
[all …]
/linux/include/linux/
H A Dvia-core.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 1998-2009 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
5 * Copyright 2009-2010 Jonathan Corbet <corbet@lwn.net>
112 #define VDE_I_DMA1DDONE 0x00000040 /* DMA 1 descr done */
113 #define VDE_I_DMA1TDONE 0x00000080 /* DMA 1 transfer done */
114 #define VDE_I_C1AV 0x00000100 /* Cap Eng 1 act vid end */
118 #define VDE_I_C0AV 0x00001000 /* Cap Eng 0 act vid end */
119 #define VDE_I_C0VBI 0x00002000 /* Cap Eng 0 VBI end */
120 #define VDE_I_C1VBI 0x00004000 /* Cap Eng 1 VBI end */
[all …]
/linux/drivers/cpufreq/
H A Dsti-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Match running platform with pre-defined OPP values for CPUFreq
24 #define HW_INFO_INDEX 1
25 #define MAJOR_ID_INDEX 1
43 * struct sti_cpufreq_ddata - ST CPUFreq Driver Data
56 struct device_node *np = ddata.cpu->of_node; in sti_cpufreq_fetch_major()
77 return ((socid >> VERSION_SHIFT) & 0xf) + 1; in sti_cpufreq_fetch_major()
83 struct device_node *np = dev->of_node; in sti_cpufreq_fetch_minor()
88 ret = of_property_read_u32_index(np, "st,syscfg-eng", in sti_cpufreq_fetch_minor()
154 struct device_node *np = dev->of_node; in sti_cpufreq_set_opp_info()
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/linux/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c1 // SPDX-License-Identifier: MIT
3 * Copyright © 2021-2022 Intel Corporation
27 * NOTE: For engine-registers, GuC only needs the register offsets
28 * from the engine-mmio-base
77 { GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW" }, \
78 { GEN8_RING_PDP_UDW(0, 1), 0, 0, "PDP1_UDW" }, \
93 { GEN12_SFC_DONE(1), 0, 0, "SFC_DONE[1]" }, \
104 /* XE_LP Render / Compute Per-Class */
110 /* GEN8+ Render / Compute Per-Engine-Instance */
115 /* GEN8+ Media Decode/Encode Per-Engine-Instance */
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_cpt.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #define CPT_CTX_ILEN 1ULL
37 busy_sts |= 1ULL << i; \
40 free_sts |= 1ULL << i; \
42 (_rsp)->busy_sts_##etype = busy_sts; \
43 (_rsp)->free_sts_##etype = free_sts; \
73 dev_warn_once(rvu->dev, "flt_vecs:%d exceeds the max vectors:%d\n", in cpt_10k_flt_nvecs_get()
84 struct rvu *rvu = block->rvu; in cpt_af_flt_intr_handler()
85 int blkaddr = block->addr; in cpt_af_flt_intr_handler()
87 int i, eng; in cpt_af_flt_intr_handler() local
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/linux/drivers/infiniband/hw/hfi1/
H A Dsdma.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright(c) 2015 - 2018 Intel Corporation.
22 #define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)
25 #define SDMA_MAP_SINGLE 1
48 #define SDMA_AHG_COPY 1
61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)
67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)
74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)
80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)
86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)
[all …]
/linux/drivers/net/ethernet/cavium/liquidio/
H A Dcn23xx_pf_regs.h7 * Copyright (c) 2003-2016 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
74 /* 2 scatch registers (64-bit) */
80 /* 1 registers (64-bit) - SLI_CTL_STATUS */
117 /* 4 registers (64-bit) for mapping IOQs to MACs(PEMs)-
118 * SLI_PKT_MAC(0..3)_PF(0..1)_RINFO
122 /*1 register (64-bit) to determine whether IOQs are in reset. */
125 /* Each Input Queue register is at a 16-byte Offset in BAR0 */
152 /* 64 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
155 /* 64 registers for Input Queues Start Addr - SLI_PKT0_INSTR_BADDR */
[all …]
/linux/Documentation/devicetree/bindings/iio/accel/
H A Dmemsensing,msa311.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MEMSensing digital 3-Axis accelerometer
10 - Dmitry Rokosov <ddrokosov@sberdevices.ru>
13 MSA311 is a tri-axial, low-g accelerometer with I2C digital output for
15 scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements
16 with output data rates from 1Hz to 1000Hz.
18 https://cdn-shop.adafruit.com/product-files/5309/MSA311-V1.1-ENG.pdf
25 maxItems: 1
[all …]
/linux/drivers/soc/tegra/fuse/
H A Dspeedo-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
53 int sku = sku_info->sku_id; in rev_sku_to_speedo_ids()
56 sku_info->cpu_speedo_id = 0; in rev_sku_to_speedo_ids()
57 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
58 sku_info->gpu_speedo_id = 0; in rev_sku_to_speedo_ids()
62 case 0x00: /* Eng sku */ in rev_sku_to_speedo_ids()
68 sku_info->cpu_speedo_id = 2; in rev_sku_to_speedo_ids()
74 sku_info->cpu_speedo_id = 2; in rev_sku_to_speedo_ids()
75 sku_info->soc_speedo_id = 0; in rev_sku_to_speedo_ids()
[all …]
/linux/arch/sparc/include/uapi/asm/
H A Denvctrl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
8 * Copyright (C) 2000 Vinh Truong (vinh.truong@eng.sun.com)
9 * VT - Add all ioctl commands and environment status definitions
10 * VT - Add application note
13 #define _SPARC64_ENVCTRL_H 1
79 * if (read(fd, rslt, 1) <= 0) {
/linux/Documentation/fb/
H A Dsh7760fb.rst6 -----------
8 supports (in theory) resolutions ranging from 1x1 to 1024x1024,
9 with color depths ranging from 1 to 16 bits, on STN, DSTN and TFT Panels.
29 - drivers/video/sh7760fb.c
30 - include/asm-sh/sh7760fb.h
31 - Documentation/fb/sh7760fb.rst
33 1. Platform setup
34 -----------------
47 --------------------
53 (http://documentation.renesas.com/eng/products/mpumcu/e602291_sh7760.pdf)
[all …]
/linux/include/uapi/linux/spi/
H A Dspidev.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
6 * Andrea Paterniani <a.paterniani@swapp-eng.it>
35 * struct spi_ioc_transfer - describes a single SPI transfer
52 * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
53 * Zero-initialize the structure, including currently unused fields, to
65 * in a 16-bit word), the next could read a block of 8-bit data before
67 * could send a different nine bit command (re-selecting the chip), and the
94 /* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
96 ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
102 #define SPI_IOC_RD_MODE _IOR(SPI_IOC_MAGIC, 1, __u8)
[all …]
/linux/drivers/net/ethernet/qlogic/qed/
H A Dqed_dev.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
11 #include <linux/dma-mapping.h>
72 db_entry->db_addr, in qed_db_recovery_dp_entry()
73 db_entry->db_data, in qed_db_recovery_dp_entry()
74 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", in qed_db_recovery_dp_entry()
75 db_entry->db_space == DB_REC_USER ? "user" : "kernel", in qed_db_recovery_dp_entry()
76 db_entry->hwfn_idx); in qed_db_recovery_dp_entry()
88 if (db_addr < cdev->doorbells || in qed_db_rec_sanity()
[all …]
H A Dqed_rdma.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
11 #include <linux/dma-mapping.h>
43 bmap->max_count = max_count; in qed_rdma_bmap_alloc()
45 bmap->bitmap = bitmap_zalloc(max_count, GFP_KERNEL); in qed_rdma_bmap_alloc()
46 if (!bmap->bitmap) in qed_rdma_bmap_alloc()
47 return -ENOMEM; in qed_rdma_bmap_alloc()
49 snprintf(bmap->name, QED_RDMA_MAX_BMAP_NAME, "%s", name); in qed_rdma_bmap_alloc()
58 *id_num = find_first_zero_bit(bmap->bitmap, bmap->max_count); in qed_rdma_bmap_alloc_id()
[all …]
/linux/tools/memory-model/Documentation/
H A Dreferences.txt18 o Intel Corporation (Ed.). 2002. "Intel 64 and IA-32 Architectures
22 and Magnus O. Myreen. 2010. "x86-TSO: A Rigorous and Usable
24 (July, 2010), 89-97. http://doi.acm.org/10.1145/1785414.1785443
42 Implementation (PLDI '12). ACM, New York, NY, USA, 311-322.
45 for ARMv8-A architecture profile)". ARM Ltd.
48 For Programmers, Volume II-A: The MIPS64(R) Instruction,
55 SIGPLAN-SIGACT Symposium on Principles of Programming Languages
60 Sewell. 2017. "Mixed-size Concurrency: ARM, POWER, C/C++11,
67 multicopy-atomic axiomatic and operational models for ARMv8". In
72 Linux-kernel memory model
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/linux/drivers/crypto/marvell/octeontx/
H A Dotx_cptpf_mbox.c1 // SPDX-License-Identifier: GPL-2.0
67 get_mbox_opcode_str(mbox_msg->msg), vf_id, in dump_mbox_msg()
71 get_mbox_opcode_str(mbox_msg->msg), raw_data_str); in dump_mbox_msg()
78 writeq(mbx->data, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 1)); in otx_cpt_send_msg_to_vf()
79 writeq(mbx->msg, cpt->reg_base + OTX_CPT_PF_VFX_MBOXX(vf, 0)); in otx_cpt_send_msg_to_vf()
89 mbx->data = 0ull; in otx_cpt_mbox_send_ack()
90 mbx->msg = OTX_CPT_MSG_ACK; in otx_cpt_mbox_send_ack()
98 mbx->data = 0ull; in otx_cptpf_mbox_send_nack()
99 mbx->msg = OTX_CPT_MSG_NACK; in otx_cptpf_mbox_send_nack()
106 writeq(1ull << vf, cpt->reg_base + OTX_CPT_PF_MBOX_INTX(0)); in otx_cpt_clear_mbox_intr()
[all …]
/linux/drivers/spi/
H A Dspi-qpic-snand.c2 * SPDX-License-Identifier: GPL-2.0
15 #include <linux/dma-mapping.h>
22 #include <linux/mtd/nand-qpic-common.h>
40 #define QPIC_QSPI_NUM_CS 1
60 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng) argument
131 snandc->regs->read_location0 = locreg_val; in qcom_spi_set_read_loc_first()
133 snandc->regs->read_location1 = locreg_val; in qcom_spi_set_read_loc_first()
135 snandc->regs->read_location2 = locreg_val; in qcom_spi_set_read_loc_first()
137 snandc->regs->read_location3 = locreg_val; in qcom_spi_set_read_loc_first()
152 snandc->regs->read_location_last0 = locreg_val; in qcom_spi_set_read_loc_last()
[all …]
H A Dspidev.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Andrea Paterniani <a.paterniani@swapp-eng.it>
54 * - CS_HIGH ... this device will be active when it shouldn't be
55 * - 3WIRE ... when active, it won't behave as it should
56 * - NO_CS ... there will be no explicit message boundaries; this
58 * - READY ... transfers may proceed when they shouldn't.
91 /*-------------------------------------------------------------------------*/
100 status = message->actual_length; in spidev_sync_unlocked()
111 mutex_lock(&spidev->spi_lock); in spidev_sync()
112 spi = spidev->spi; in spidev_sync()
[all …]
/linux/drivers/dma/idxd/
H A Ddevice.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/io-64-nonatomic-lo-hi.h>
25 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_unmask_error_interrupts()
26 genctrl.softerr_int_en = 1; in idxd_unmask_error_interrupts()
27 genctrl.halt_int_en = 1; in idxd_unmask_error_interrupts()
28 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_unmask_error_interrupts()
35 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_mask_error_interrupts()
38 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); in idxd_mask_error_interrupts()
45 for (i = 0; i < wq->num_descs; i++) in free_hw_descs()
46 kfree(wq->hw_descs[i]); in free_hw_descs()
[all …]
H A Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0 */
35 u64 block_on_fault:1;
36 u64 overlap_copy:1;
37 u64 cache_control_mem:1;
38 u64 cache_control_cache:1;
39 u64 cmd_cap:1;
41 u64 dest_readback:1;
42 u64 drain_readback:1;
45 u64 batch_continuation:1;
49 u64 config_en:1;
[all …]
H A Dperfmon.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/io-64-nonatomic-lo-hi.h>
13 DEFINE_PERFMON_FORMAT_ATTR(event_category, "config:0-3");
14 DEFINE_PERFMON_FORMAT_ATTR(event, "config:4-31");
20 DEFINE_PERFMON_FORMAT_ATTR(filter_wq, "config1:0-31");
21 DEFINE_PERFMON_FORMAT_ATTR(filter_tc, "config1:32-39");
22 DEFINE_PERFMON_FORMAT_ATTR(filter_pgsz, "config1:40-43");
23 DEFINE_PERFMON_FORMAT_ATTR(filter_sz, "config1:44-51");
24 DEFINE_PERFMON_FORMAT_ATTR(filter_eng, "config1:52-59");
52 return &idxd_pmu->pmu == event->pmu; in is_idxd_event()
[all …]

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