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/linux/tools/testing/selftests/arm64/fp/
H A Dfp-ptrace-asm.S25 stp x11, x12, [sp, #-0x10]!
28 ldr x7, =v_in
29 ldp q0, q1, [x7]
30 ldp q2, q3, [x7, #16 * 2]
31 ldp q4, q5, [x7, #16 * 4]
32 ldp q6, q7, [x7, #16 * 6]
33 ldp q8, q9, [x7, #16 * 8]
34 ldp q10, q11, [x7, #16 * 10]
35 ldp q12, q13, [x7, #16 * 12]
36 ldp q14, q15, [x7, #16 * 14]
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8ulp-pinfunc.h13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6sx-pinfunc.h13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
[all …]
H A Dimx35-pinfunc.h13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0
14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0
15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0
16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0
17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0
18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0
19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0
20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0
21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0
22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0
[all …]
/linux/arch/x86/crypto/
H A Daria-aesni-avx-asm_64.S19 ( (((a0) & 1) << 0) | \
29 ( ((l7) << (0 * 8)) | \
172 x4, x5, x6, x7, \ argument
176 vmovdqu (0 * 16)(rio), x0; \
183 vmovdqu (7 * 16)(rio), x7; \
195 x4, x5, x6, x7, \ argument
200 x4, x5, x6, x7, \
205 vmovdqu x0, 0 * 16(mem_ab); \
212 vmovdqu x7, 7 * 16(mem_ab); \
213 vmovdqu y0, 0 * 16(mem_cd); \
[all …]
H A Daria-aesni-avx2-asm_64.S35 ( (((a0) & 1) << 0) | \
45 ( ((l7) << (0 * 8)) | \
188 x4, x5, x6, x7, \ argument
192 vmovdqu (0 * 32)(rio), x0; \
199 vmovdqu (7 * 32)(rio), x7; \
211 x4, x5, x6, x7, \ argument
216 x4, x5, x6, x7, \
221 vmovdqu x0, 0 * 32(mem_ab); \
228 vmovdqu x7, 7 * 32(mem_ab); \
229 vmovdqu y0, 0 * 32(mem_cd); \
[all …]
/linux/sound/soc/fsl/
H A Dfsl_asrc.c50 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
56 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0x
[all...]
/linux/drivers/pinctrl/
H A Dpinctrl-keembay.c22 #define KEEMBAY_GPIO_DATA_OUT 0x000
23 #define KEEMBAY_GPIO_DATA_IN 0x020
24 #define KEEMBAY_GPIO_DATA_IN_RAW 0x040
25 #define KEEMBAY_GPIO_DATA_HIGH 0x060
26 #define KEEMBAY_GPIO_DATA_LOW 0x080
29 #define KEEMBAY_GPIO_INT_CFG 0x000
30 #define KEEMBAY_GPIO_MODE 0x070
36 #define KEEMBAY_GPIO_MODE_SELECT_MASK GENMASK(2, 0)
43 #define KEEMBAY_GPIO_MODE_DEFAULT 0x7
44 #define KEEMBAY_GPIO_MODE_INV_VAL 0x3
[all …]
/linux/drivers/pinctrl/nuvoton/
H A Dpinctrl-ma35d1.c21 MA35_PIN(0, PA0, 0x80, 0x0,
22 MA35_MUX(0x0, "GPA0"),
23 MA35_MUX(0x2, "UART1_nCTS"),
24 MA35_MUX(0x3, "UART16_RXD"),
25 MA35_MUX(0x6, "NAND_DATA0"),
26 MA35_MUX(0x7, "EBI_AD0"),
27 MA35_MUX(0x9, "EBI_ADR0")),
28 MA35_PIN(1, PA1, 0x80, 0x4,
29 MA35_MUX(0x0, "GPA1"),
30 MA35_MUX(0x2, "UART1_nRTS"),
[all …]
/linux/sound/soc/codecs/
H A Dmt6359.h11 #define MT6359_TOP0_ID 0x0
12 #define MT6359_SMT_CON1 0x32
13 #define MT6359_DRV_CON2 0x3c
14 #define MT6359_DRV_CON3 0x3e
15 #define MT6359_DRV_CON4 0x40
16 #define MT6359_TOP_CKPDN_CON0 0x10c
17 #define MT6359_TOP_CKPDN_CON0_SET 0x10e
18 #define MT6359_TOP_CKPDN_CON0_CLR 0x110
19 #define MT6359_AUXADC_RQST0 0x1108
20 #define MT6359_AUXADC_CON10 0x11a0
[all …]
H A Dmt6358.h21 #define RG_VOW13M_CK_PDN_MASK 0x1
22 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
24 #define RG_VOW32K_CK_PDN_MASK 0x1
25 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
27 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
28 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
30 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
31 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
33 #define RG_AUDNCP_CK_PDN_MASK 0x1
34 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
[all …]
H A Drt1318.h36 #define RT1318_PLL_N_MAX 0x1ff
37 #define RT1318_PLL_K_MAX 0x1f
38 #define RT1318_PLL_M_MAX 0x1f
47 #define RT1318_CLK1 0xc001
48 #define RT1318_CLK2 0xc003
49 #define RT1318_CLK3 0xc004
50 #define RT1318_CLK4 0xc005
51 #define RT1318_CLK5 0xc006
52 #define RT1318_CLK6 0xc007
53 #define RT1318_CLK7 0xc008
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
H A Dbif_4_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2
36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h14 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
17 #define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */
18 #define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */
19 #define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */
20 #define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */
21 #define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */
22 #define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */
23 #define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */
24 #define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */
25 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_4_2_3_sh_mask.h31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0
44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL
49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0
50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL
[all …]
/linux/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_msg_arm64.h31 #define VMWARE_HYPERVISOR_PORT 0x5658
32 #define VMWARE_HYPERVISOR_PORT_HB 0x5659
34 #define VMWARE_HYPERVISOR_HB BIT(0)
37 #define VMWARE_HYPERVISOR_MAGIC 0x564D5868
39 #define X86_IO_MAGIC 0x86
41 #define X86_IO_W7_SIZE_SHIFT 0
42 #define X86_IO_W7_SIZE_MASK (0x3 << X86_IO_W7_SIZE_SHIFT)
48 #define X86_IO_W7_IMM_MASK (0xff << X86_IO_W7_IMM_SHIFT)
57 register u64 x7 asm("x7") = ((u64)X86_IO_MAGIC << 32) | in vmware_hypercall1()
65 : "r" (x1), "r" (x2), "r" (x3), "r" (x7) in vmware_hypercall1()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_vdec0_brdg_ctrl_masks.h24 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
[all …]
H A Dpcie_vdec0_brdg_ctrl_masks.h24 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0
25 #define PCIE_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1
28 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0
29 #define PCIE_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7
32 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0
33 #define PCIE_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF
36 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0
37 #define PCIE_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF
40 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0
41 #define PCIE_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1
[all …]
/linux/tools/perf/pmu-events/arch/x86/skylakex/
H A Duncore-io.json4 "Counter": "0,1",
5 "EventCode": "0x83",
7 "FCMask": "0x07",
8 "Filter": "ch_mask=0x1f",
12 "PortMask": "0x01",
13 … device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supp…
15 "UMask": "0x4",
20 "Counter": "0,1",
21 "EventCode": "0x83",
23 "FCMask": "0x07",
[all …]

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