Lines Matching +full:0 +full:x7
11 #define MT6359_TOP0_ID 0x0
12 #define MT6359_SMT_CON1 0x32
13 #define MT6359_DRV_CON2 0x3c
14 #define MT6359_DRV_CON3 0x3e
15 #define MT6359_DRV_CON4 0x40
16 #define MT6359_TOP_CKPDN_CON0 0x10c
17 #define MT6359_TOP_CKPDN_CON0_SET 0x10e
18 #define MT6359_TOP_CKPDN_CON0_CLR 0x110
19 #define MT6359_AUXADC_RQST0 0x1108
20 #define MT6359_AUXADC_CON10 0x11a0
21 #define MT6359_AUXADC_ACCDET 0x11ba
22 #define MT6359_LDO_VUSB_OP_EN 0x1d0c
23 #define MT6359_LDO_VUSB_OP_EN_SET 0x1d0e
24 #define MT6359_LDO_VUSB_OP_EN_CLR 0x1d10
25 #define MT6359_AUD_TOP_CKPDN_CON0 0x230c
26 #define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e
27 #define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310
28 #define MT6359_AUD_TOP_RST_CON0 0x2320
29 #define MT6359_AUD_TOP_RST_CON0_SET 0x2322
30 #define MT6359_AUD_TOP_RST_CON0_CLR 0x2324
31 #define MT6359_AUD_TOP_INT_CON0 0x2328
32 #define MT6359_AUD_TOP_INT_CON0_SET 0x232a
33 #define MT6359_AUD_TOP_INT_CON0_CLR 0x232c
34 #define MT6359_AUD_TOP_INT_MASK_CON0 0x232e
35 #define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330
36 #define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332
37 #define MT6359_AUD_TOP_INT_STATUS0 0x2334
38 #define MT6359_AFE_NCP_CFG2 0x24e2
39 #define MT6359_AUDENC_DSN_ID 0x2500
40 #define MT6359_AUDENC_DSN_REV0 0x2502
41 #define MT6359_AUDENC_DSN_DBI 0x2504
42 #define MT6359_AUDENC_DSN_FPI 0x2506
43 #define MT6359_AUDENC_ANA_CON0 0x2508
44 #define MT6359_AUDENC_ANA_CON1 0x250a
45 #define MT6359_AUDENC_ANA_CON2 0x250c
46 #define MT6359_AUDENC_ANA_CON3 0x250e
47 #define MT6359_AUDENC_ANA_CON4 0x2510
48 #define MT6359_AUDENC_ANA_CON5 0x2512
49 #define MT6359_AUDENC_ANA_CON6 0x2514
50 #define MT6359_AUDENC_ANA_CON7 0x2516
51 #define MT6359_AUDENC_ANA_CON8 0x2518
52 #define MT6359_AUDENC_ANA_CON9 0x251a
53 #define MT6359_AUDENC_ANA_CON10 0x251c
54 #define MT6359_AUDENC_ANA_CON11 0x251e
55 #define MT6359_AUDENC_ANA_CON12 0x2520
56 #define MT6359_AUDENC_ANA_CON13 0x2522
57 #define MT6359_AUDENC_ANA_CON14 0x2524
58 #define MT6359_AUDENC_ANA_CON15 0x2526
59 #define MT6359_AUDENC_ANA_CON16 0x2528
60 #define MT6359_AUDENC_ANA_CON17 0x252a
61 #define MT6359_AUDENC_ANA_CON18 0x252c
62 #define MT6359_AUDENC_ANA_CON19 0x252e
63 #define MT6359_AUDENC_ANA_CON20 0x2530
64 #define MT6359_AUDENC_ANA_CON21 0x2532
65 #define MT6359_AUDENC_ANA_CON22 0x2534
66 #define MT6359_AUDENC_ANA_CON23 0x2536
67 #define MT6359_AUDDEC_DSN_ID 0x2580
68 #define MT6359_AUDDEC_DSN_REV0 0x2582
69 #define MT6359_AUDDEC_DSN_DBI 0x2584
70 #define MT6359_AUDDEC_DSN_FPI 0x2586
71 #define MT6359_AUDDEC_ANA_CON0 0x2588
72 #define MT6359_AUDDEC_ANA_CON1 0x258a
73 #define MT6359_AUDDEC_ANA_CON2 0x258c
74 #define MT6359_AUDDEC_ANA_CON3 0x258e
75 #define MT6359_AUDDEC_ANA_CON4 0x2590
76 #define MT6359_AUDDEC_ANA_CON5 0x2592
77 #define MT6359_AUDDEC_ANA_CON6 0x2594
78 #define MT6359_AUDDEC_ANA_CON7 0x2596
79 #define MT6359_AUDDEC_ANA_CON8 0x2598
80 #define MT6359_AUDDEC_ANA_CON9 0x259a
81 #define MT6359_AUDDEC_ANA_CON10 0x259c
82 #define MT6359_AUDDEC_ANA_CON11 0x259e
83 #define MT6359_AUDDEC_ANA_CON12 0x25a0
84 #define MT6359_AUDDEC_ANA_CON13 0x25a2
85 #define MT6359_AUDDEC_ANA_CON14 0x25a4
86 #define MT6359_ACCDET_DSN_DIG_ID 0x2680
87 #define MT6359_ACCDET_DSN_DIG_REV0 0x2682
88 #define MT6359_ACCDET_DSN_DBI 0x2684
89 #define MT6359_ACCDET_DSN_FPI 0x2686
90 #define MT6359_ACCDET_CON0 0x2688
91 #define MT6359_ACCDET_CON1 0x268a
92 #define MT6359_ACCDET_CON2 0x268c
93 #define MT6359_ACCDET_CON3 0x268e
94 #define MT6359_ACCDET_CON4 0x2690
95 #define MT6359_ACCDET_CON5 0x2692
96 #define MT6359_ACCDET_CON6 0x2694
97 #define MT6359_ACCDET_CON7 0x2696
98 #define MT6359_ACCDET_CON8 0x2698
99 #define MT6359_ACCDET_CON9 0x269a
100 #define MT6359_ACCDET_CON10 0x269c
101 #define MT6359_ACCDET_CON11 0x269e
102 #define MT6359_ACCDET_CON12 0x26a0
103 #define MT6359_ACCDET_CON13 0x26a2
104 #define MT6359_ACCDET_CON14 0x26a4
105 #define MT6359_ACCDET_CON15 0x26a6
106 #define MT6359_ACCDET_CON16 0x26a8
107 #define MT6359_ACCDET_CON17 0x26aa
108 #define MT6359_ACCDET_CON18 0x26ac
109 #define MT6359_ACCDET_CON19 0x26ae
110 #define MT6359_ACCDET_CON20 0x26b0
111 #define MT6359_ACCDET_CON21 0x26b2
112 #define MT6359_ACCDET_CON22 0x26b4
113 #define MT6359_ACCDET_CON23 0x26b6
114 #define MT6359_ACCDET_CON24 0x26b8
115 #define MT6359_ACCDET_CON25 0x26ba
116 #define MT6359_ACCDET_CON26 0x26bc
117 #define MT6359_ACCDET_CON27 0x26be
118 #define MT6359_ACCDET_CON28 0x26c0
119 #define MT6359_ACCDET_CON29 0x26c2
120 #define MT6359_ACCDET_CON30 0x26c4
121 #define MT6359_ACCDET_CON31 0x26c6
122 #define MT6359_ACCDET_CON32 0x26c8
123 #define MT6359_ACCDET_CON33 0x26ca
124 #define MT6359_ACCDET_CON34 0x26cc
125 #define MT6359_ACCDET_CON35 0x26ce
126 #define MT6359_ACCDET_CON36 0x26d0
127 #define MT6359_ACCDET_CON37 0x26d2
128 #define MT6359_ACCDET_CON38 0x26d4
129 #define MT6359_ACCDET_CON39 0x26d6
130 #define MT6359_ACCDET_CON40 0x26d8
134 #define TOP0_ANA_ID_SFT 0
135 #define TOP0_ANA_ID_MASK 0xFF
136 #define TOP0_ANA_ID_MASK_SFT (0xFF << 0)
139 #define AUXADC_RQST_CH0_SFT 0
140 #define AUXADC_RQST_CH0_MASK 0x1
141 #define AUXADC_RQST_CH0_MASK_SFT (0x1 << 0)
145 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK 0x1
146 #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT (0x1 << 6)
150 #define AUXADC_ACCDET_AUTO_SPL_SFT 0
151 #define AUXADC_ACCDET_AUTO_SPL_MASK 0x1
152 #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT (0x1 << 0)
156 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
157 #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT (0x1 << 1)
161 #define AUXADC_ACCDET_DIG1_RSV0_MASK 0x3F
162 #define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT (0x3F << 2)
166 #define AUXADC_ACCDET_DIG0_RSV0_MASK 0xFF
167 #define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT (0xFF << 8)
171 #define RG_ACCDET_CK_PDN_SFT 0
172 #define RG_ACCDET_CK_PDN_MASK 0x1
173 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
178 #define RG_ACCDET_RST_MASK 0x1
179 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
182 #define BANK_ACCDET_SWRST_SFT 0
183 #define BANK_ACCDET_SWRST_MASK 0x1
184 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
189 #define RG_INT_EN_ACCDET_MASK 0x1
190 #define RG_INT_EN_ACCDET_MASK_SFT (0x1 << 5)
194 #define RG_INT_EN_ACCDET_EINT0_MASK 0x1
195 #define RG_INT_EN_ACCDET_EINT0_MASK_SFT (0x1 << 6)
199 #define RG_INT_EN_ACCDET_EINT1_MASK 0x1
200 #define RG_INT_EN_ACCDET_EINT1_MASK_SFT (0x1 << 7)
205 #define RG_INT_MASK_ACCDET_MASK 0x1
206 #define RG_INT_MASK_ACCDET_MASK_SFT (0x1 << 5)
210 #define RG_INT_MASK_ACCDET_EINT0_MASK 0x1
211 #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT (0x1 << 6)
215 #define RG_INT_MASK_ACCDET_EINT1_MASK 0x1
216 #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT (0x1 << 7)
221 #define RG_INT_STATUS_ACCDET_MASK 0x1
222 #define RG_INT_STATUS_ACCDET_MASK_SFT (0x1 << 5)
226 #define RG_INT_STATUS_ACCDET_EINT0_MASK 0x1
227 #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
231 #define RG_INT_STATUS_ACCDET_EINT1_MASK 0x1
232 #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
237 #define RG_INT_RAW_STATUS_ACCDET_MASK 0x1
238 #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT (0x1 << 5)
242 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK 0x1
243 #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT (0x1 << 6)
247 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK 0x1
248 #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT (0x1 << 7)
252 #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
253 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
254 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
258 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
259 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
263 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
264 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
268 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
269 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
273 #define RG_AUDACCDETVTHACAL_MASK 0x1
274 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
278 #define RG_AUDACCDETVTHBCAL_MASK 0x1
279 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
283 #define RG_AUDACCDETTVDET_MASK 0x1
284 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
288 #define RG_ACCDETSEL_MASK 0x1
289 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
293 #define RG_AUDPWDBMICBIAS1_SFT 0
294 #define RG_AUDPWDBMICBIAS1_MASK 0x1
295 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
299 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
300 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
304 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
305 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
309 #define RG_AUDMICBIAS1VREF_MASK 0x7
310 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
314 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
315 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
319 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
320 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
324 #define RG_BANDGAPGEN_MASK 0x1
325 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
329 #define RG_AUDMICBIAS1HVEN_MASK 0x1
330 #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
334 #define RG_AUDMICBIAS1HVVREF_MASK 0x1
335 #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
340 #define RG_EINT0NOHYS_MASK 0x1
341 #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
345 #define RG_EINT0CONFIGACCDET_MASK 0x1
346 #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
350 #define RG_EINT0HIRENB_MASK 0x1
351 #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
355 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
356 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
360 #define RG_ACCDET2AUXSWEN_MASK 0x1
361 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
365 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
366 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
369 #define RG_EINT1CONFIGACCDET_SFT 0
370 #define RG_EINT1CONFIGACCDET_MASK 0x1
371 #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
375 #define RG_EINT1HIRENB_MASK 0x1
376 #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
380 #define RG_EINT1NOHYS_MASK 0x1
381 #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
387 #define RG_MTEST_EN_MASK 0x1
388 #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
392 #define RG_MTEST_SEL_MASK 0x1
393 #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
397 #define RG_MTEST_CURRENT_MASK 0x1
398 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
402 #define RG_ANALOGFDEN_MASK 0x1
403 #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
407 #define RG_FDVIN1PPULLLOW_MASK 0x1
408 #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
412 #define RG_FDEINT0TYPE_MASK 0x1
413 #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
417 #define RG_FDEINT1TYPE_MASK 0x1
418 #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
421 #define RG_EINT0CMPEN_SFT 0
422 #define RG_EINT0CMPEN_MASK 0x1
423 #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
427 #define RG_EINT0CMPMEN_MASK 0x1
428 #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
432 #define RG_EINT0EN_MASK 0x1
433 #define RG_EINT0EN_MASK_SFT (0x1 << 2)
437 #define RG_EINT0CEN_MASK 0x1
438 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
442 #define RG_EINT0INVEN_MASK 0x1
443 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
447 #define RG_EINT0CTURBO_MASK 0x7
448 #define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
452 #define RG_EINT1CMPEN_MASK 0x1
453 #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
457 #define RG_EINT1CMPMEN_MASK 0x1
458 #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
462 #define RG_EINT1EN_MASK 0x1
463 #define RG_EINT1EN_MASK_SFT (0x1 << 10)
467 #define RG_EINT1CEN_MASK 0x1
468 #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
472 #define RG_EINT1INVEN_MASK 0x1
473 #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
477 #define RG_EINT1CTURBO_MASK 0x7
478 #define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
484 #define ACCDET_ANA_ID_SFT 0
485 #define ACCDET_ANA_ID_MASK 0xFF
486 #define ACCDET_ANA_ID_MASK_SFT (0xFF << 0)
490 #define ACCDET_DIG_ID_MASK 0xFF
491 #define ACCDET_DIG_ID_MASK_SFT (0xFF << 8)
494 #define ACCDET_ANA_MINOR_REV_SFT 0
495 #define ACCDET_ANA_MINOR_REV_MASK 0xF
496 #define ACCDET_ANA_MINOR_REV_MASK_SFT (0xF << 0)
500 #define ACCDET_ANA_MAJOR_REV_MASK 0xF
501 #define ACCDET_ANA_MAJOR_REV_MASK_SFT (0xF << 4)
505 #define ACCDET_DIG_MINOR_REV_MASK 0xF
506 #define ACCDET_DIG_MINOR_REV_MASK_SFT (0xF << 8)
510 #define ACCDET_DIG_MAJOR_REV_MASK 0xF
511 #define ACCDET_DIG_MAJOR_REV_MASK_SFT (0xF << 12)
514 #define ACCDET_DSN_CBS_SFT 0
515 #define ACCDET_DSN_CBS_MASK 0x3
516 #define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
520 #define ACCDET_DSN_BIX_MASK 0x3
521 #define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)
525 #define ACCDET_ESP_MASK 0xFF
526 #define ACCDET_ESP_MASK_SFT (0xFF << 8)
529 #define ACCDET_DSN_FPI_SFT 0
530 #define ACCDET_DSN_FPI_MASK 0xFF
531 #define ACCDET_DSN_FPI_MASK_SFT (0xFF << 0)
534 #define ACCDET_AUXADC_SEL_SFT 0
535 #define ACCDET_AUXADC_SEL_MASK 0x1
536 #define ACCDET_AUXADC_SEL_MASK_SFT (0x1 << 0)
540 #define ACCDET_AUXADC_SW_MASK 0x1
541 #define ACCDET_AUXADC_SW_MASK_SFT (0x1 << 1)
545 #define ACCDET_TEST_AUXADC_MASK 0x1
546 #define ACCDET_TEST_AUXADC_MASK_SFT (0x1 << 2)
550 #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK 0x1
551 #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT (0x1 << 8)
555 #define AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
556 #define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT (0x1 << 9)
560 #define AUDACCDETAUXADCSWCTRL_SW_MASK 0x1
561 #define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT (0x1 << 10)
565 #define ACCDET_TEST_ANA_MASK 0x1
566 #define ACCDET_TEST_ANA_MASK_SFT (0x1 << 11)
570 #define RG_AUDACCDETRSV_MASK 0x3
571 #define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)
574 #define ACCDET_SW_EN_SFT 0
575 #define ACCDET_SW_EN_MASK 0x1
576 #define ACCDET_SW_EN_MASK_SFT (0x1 << 0)
580 #define ACCDET_SEQ_INIT_MASK 0x1
581 #define ACCDET_SEQ_INIT_MASK_SFT (0x1 << 1)
585 #define ACCDET_EINT0_SW_EN_MASK 0x1
586 #define ACCDET_EINT0_SW_EN_MASK_SFT (0x1 << 2)
590 #define ACCDET_EINT0_SEQ_INIT_MASK 0x1
591 #define ACCDET_EINT0_SEQ_INIT_MASK_SFT (0x1 << 3)
595 #define ACCDET_EINT1_SW_EN_MASK 0x1
596 #define ACCDET_EINT1_SW_EN_MASK_SFT (0x1 << 4)
600 #define ACCDET_EINT1_SEQ_INIT_MASK 0x1
601 #define ACCDET_EINT1_SEQ_INIT_MASK_SFT (0x1 << 5)
605 #define ACCDET_EINT0_INVERTER_SW_EN_MASK 0x1
606 #define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT (0x1 << 6)
610 #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK 0x1
611 #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 7)
615 #define ACCDET_EINT1_INVERTER_SW_EN_MASK 0x1
616 #define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT (0x1 << 8)
620 #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK 0x1
621 #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT (0x1 << 9)
625 #define ACCDET_EINT0_M_SW_EN_MASK 0x1
626 #define ACCDET_EINT0_M_SW_EN_MASK_SFT (0x1 << 10)
630 #define ACCDET_EINT1_M_SW_EN_MASK 0x1
631 #define ACCDET_EINT1_M_SW_EN_MASK_SFT (0x1 << 11)
635 #define ACCDET_EINT_M_DETECT_EN_MASK 0x1
636 #define ACCDET_EINT_M_DETECT_EN_MASK_SFT (0x1 << 12)
639 #define ACCDET_CMP_PWM_EN_SFT 0
640 #define ACCDET_CMP_PWM_EN_MASK 0x1
641 #define ACCDET_CMP_PWM_EN_MASK_SFT (0x1 << 0)
645 #define ACCDET_VTH_PWM_EN_MASK 0x1
646 #define ACCDET_VTH_PWM_EN_MASK_SFT (0x1 << 1)
650 #define ACCDET_MBIAS_PWM_EN_MASK 0x1
651 #define ACCDET_MBIAS_PWM_EN_MASK_SFT (0x1 << 2)
655 #define ACCDET_EINT_EN_PWM_EN_MASK 0x1
656 #define ACCDET_EINT_EN_PWM_EN_MASK_SFT (0x1 << 3)
660 #define ACCDET_EINT_CMPEN_PWM_EN_MASK 0x1
661 #define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT (0x1 << 4)
665 #define ACCDET_EINT_CMPMEN_PWM_EN_MASK 0x1
666 #define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT (0x1 << 5)
670 #define ACCDET_EINT_CTURBO_PWM_EN_MASK 0x1
671 #define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT (0x1 << 6)
675 #define ACCDET_CMP_PWM_IDLE_MASK 0x1
676 #define ACCDET_CMP_PWM_IDLE_MASK_SFT (0x1 << 8)
680 #define ACCDET_VTH_PWM_IDLE_MASK 0x1
681 #define ACCDET_VTH_PWM_IDLE_MASK_SFT (0x1 << 9)
685 #define ACCDET_MBIAS_PWM_IDLE_MASK 0x1
686 #define ACCDET_MBIAS_PWM_IDLE_MASK_SFT (0x1 << 10)
690 #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK 0x1
691 #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 11)
695 #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK 0x1
696 #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT (0x1 << 12)
700 #define ACCDET_PWM_EN_SW_MASK 0x1
701 #define ACCDET_PWM_EN_SW_MASK_SFT (0x1 << 13)
705 #define ACCDET_PWM_EN_SEL_MASK 0x3
706 #define ACCDET_PWM_EN_SEL_MASK_SFT (0x3 << 14)
709 #define ACCDET_PWM_WIDTH_SFT 0
710 #define ACCDET_PWM_WIDTH_MASK 0xFFFF
711 #define ACCDET_PWM_WIDTH_MASK_SFT (0xFFFF << 0)
714 #define ACCDET_PWM_THRESH_SFT 0
715 #define ACCDET_PWM_THRESH_MASK 0xFFFF
716 #define ACCDET_PWM_THRESH_MASK_SFT (0xFFFF << 0)
719 #define ACCDET_RISE_DELAY_SFT 0
720 #define ACCDET_RISE_DELAY_MASK 0x7FFF
721 #define ACCDET_RISE_DELAY_MASK_SFT (0x7FFF << 0)
725 #define ACCDET_FALL_DELAY_MASK 0x1
726 #define ACCDET_FALL_DELAY_MASK_SFT (0x1 << 15)
729 #define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT 0
730 #define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK 0x7
731 #define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT (0x7 << 0)
735 #define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK 0x7
736 #define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT (0x7 << 4)
739 #define ACCDET_EINT_EN_PWM_THRESH_SFT 0
740 #define ACCDET_EINT_EN_PWM_THRESH_MASK 0x7
741 #define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT (0x7 << 0)
745 #define ACCDET_EINT_EN_PWM_WIDTH_MASK 0x3
746 #define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT (0x3 << 4)
750 #define ACCDET_EINT_CMPEN_PWM_THRESH_MASK 0x7
751 #define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT (0x7 << 8)
755 #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK 0x3
756 #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT (0x3 << 12)
759 #define ACCDET_DEBOUNCE0_SFT 0
760 #define ACCDET_DEBOUNCE0_MASK 0xFFFF
761 #define ACCDET_DEBOUNCE0_MASK_SFT (0xFFFF << 0)
764 #define ACCDET_DEBOUNCE1_SFT 0
765 #define ACCDET_DEBOUNCE1_MASK 0xFFFF
766 #define ACCDET_DEBOUNCE1_MASK_SFT (0xFFFF << 0)
769 #define ACCDET_DEBOUNCE2_SFT 0
770 #define ACCDET_DEBOUNCE2_MASK 0xFFFF
771 #define ACCDET_DEBOUNCE2_MASK_SFT (0xFFFF << 0)
774 #define ACCDET_DEBOUNCE3_SFT 0
775 #define ACCDET_DEBOUNCE3_MASK 0xFFFF
776 #define ACCDET_DEBOUNCE3_MASK_SFT (0xFFFF << 0)
779 #define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT 0
780 #define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK 0xFFFF
781 #define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT (0xFFFF << 0)
784 #define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT 0
785 #define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK 0xFFFF
786 #define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT (0xFFFF << 0)
789 #define ACCDET_EINT_DEBOUNCE0_SFT 0
790 #define ACCDET_EINT_DEBOUNCE0_MASK 0xF
791 #define ACCDET_EINT_DEBOUNCE0_MASK_SFT (0xF << 0)
795 #define ACCDET_EINT_DEBOUNCE1_MASK 0xF
796 #define ACCDET_EINT_DEBOUNCE1_MASK_SFT (0xF << 4)
800 #define ACCDET_EINT_DEBOUNCE2_MASK 0xF
801 #define ACCDET_EINT_DEBOUNCE2_MASK_SFT (0xF << 8)
805 #define ACCDET_EINT_DEBOUNCE3_MASK 0xF
806 #define ACCDET_EINT_DEBOUNCE3_MASK_SFT (0xF << 12)
809 #define ACCDET_EINT_INVERTER_DEBOUNCE_SFT 0
810 #define ACCDET_EINT_INVERTER_DEBOUNCE_MASK 0xF
811 #define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT (0xF << 0)
814 #define ACCDET_IVAL_CUR_IN_SFT 0
815 #define ACCDET_IVAL_CUR_IN_MASK 0x3
816 #define ACCDET_IVAL_CUR_IN_MASK_SFT (0x3 << 0)
820 #define ACCDET_IVAL_SAM_IN_MASK 0x3
821 #define ACCDET_IVAL_SAM_IN_MASK_SFT (0x3 << 2)
825 #define ACCDET_IVAL_MEM_IN_MASK 0x3
826 #define ACCDET_IVAL_MEM_IN_MASK_SFT (0x3 << 4)
830 #define ACCDET_EINT_IVAL_CUR_IN_MASK 0x3
831 #define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT (0x3 << 6)
835 #define ACCDET_EINT_IVAL_SAM_IN_MASK 0x3
836 #define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT (0x3 << 8)
840 #define ACCDET_EINT_IVAL_MEM_IN_MASK 0x3
841 #define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT (0x3 << 10)
845 #define ACCDET_IVAL_SEL_MASK 0x1
846 #define ACCDET_IVAL_SEL_MASK_SFT (0x1 << 12)
850 #define ACCDET_EINT_IVAL_SEL_MASK 0x1
851 #define ACCDET_EINT_IVAL_SEL_MASK_SFT (0x1 << 13)
854 #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT 0
855 #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK 0x1
856 #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT (0x1 << 0)
860 #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK 0x1
861 #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT (0x1 << 1)
865 #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK 0x1
866 #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT (0x1 << 2)
870 #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK 0x1
871 #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT (0x1 << 3)
874 #define ACCDET_IRQ_SFT 0
875 #define ACCDET_IRQ_MASK 0x1
876 #define ACCDET_IRQ_MASK_SFT (0x1 << 0)
880 #define ACCDET_EINT0_IRQ_MASK 0x1
881 #define ACCDET_EINT0_IRQ_MASK_SFT (0x1 << 2)
885 #define ACCDET_EINT1_IRQ_MASK 0x1
886 #define ACCDET_EINT1_IRQ_MASK_SFT (0x1 << 3)
890 #define ACCDET_EINT_IN_INVERSE_MASK 0x1
891 #define ACCDET_EINT_IN_INVERSE_MASK_SFT (0x1 << 4)
895 #define ACCDET_IRQ_CLR_MASK 0x1
896 #define ACCDET_IRQ_CLR_MASK_SFT (0x1 << 8)
900 #define ACCDET_EINT0_IRQ_CLR_MASK 0x1
901 #define ACCDET_EINT0_IRQ_CLR_MASK_SFT (0x1 << 10)
905 #define ACCDET_EINT1_IRQ_CLR_MASK 0x1
906 #define ACCDET_EINT1_IRQ_CLR_MASK_SFT (0x1 << 11)
910 #define ACCDET_EINT_M_PLUG_IN_NUM_MASK 0x7
911 #define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT (0x7 << 12)
914 #define ACCDET_DA_STABLE_SFT 0
915 #define ACCDET_DA_STABLE_MASK 0x1
916 #define ACCDET_DA_STABLE_MASK_SFT (0x1 << 0)
920 #define ACCDET_EINT0_EN_STABLE_MASK 0x1
921 #define ACCDET_EINT0_EN_STABLE_MASK_SFT (0x1 << 1)
925 #define ACCDET_EINT0_CMPEN_STABLE_MASK 0x1
926 #define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT (0x1 << 2)
930 #define ACCDET_EINT0_CMPMEN_STABLE_MASK 0x1
931 #define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT (0x1 << 3)
935 #define ACCDET_EINT0_CTURBO_STABLE_MASK 0x1
936 #define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT (0x1 << 4)
940 #define ACCDET_EINT0_CEN_STABLE_MASK 0x1
941 #define ACCDET_EINT0_CEN_STABLE_MASK_SFT (0x1 << 5)
945 #define ACCDET_EINT1_EN_STABLE_MASK 0x1
946 #define ACCDET_EINT1_EN_STABLE_MASK_SFT (0x1 << 6)
950 #define ACCDET_EINT1_CMPEN_STABLE_MASK 0x1
951 #define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT (0x1 << 7)
955 #define ACCDET_EINT1_CMPMEN_STABLE_MASK 0x1
956 #define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT (0x1 << 8)
960 #define ACCDET_EINT1_CTURBO_STABLE_MASK 0x1
961 #define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT (0x1 << 9)
965 #define ACCDET_EINT1_CEN_STABLE_MASK 0x1
966 #define ACCDET_EINT1_CEN_STABLE_MASK_SFT (0x1 << 10)
969 #define ACCDET_HWMODE_EN_SFT 0
970 #define ACCDET_HWMODE_EN_MASK 0x1
971 #define ACCDET_HWMODE_EN_MASK_SFT (0x1 << 0)
975 #define ACCDET_HWMODE_SEL_MASK 0x3
976 #define ACCDET_HWMODE_SEL_MASK_SFT (0x3 << 1)
980 #define ACCDET_PLUG_OUT_DETECT_MASK 0x1
981 #define ACCDET_PLUG_OUT_DETECT_MASK_SFT (0x1 << 3)
985 #define ACCDET_EINT0_REVERSE_MASK 0x1
986 #define ACCDET_EINT0_REVERSE_MASK_SFT (0x1 << 4)
990 #define ACCDET_EINT1_REVERSE_MASK 0x1
991 #define ACCDET_EINT1_REVERSE_MASK_SFT (0x1 << 5)
995 #define ACCDET_EINT_HWMODE_EN_MASK 0x1
996 #define ACCDET_EINT_HWMODE_EN_MASK_SFT (0x1 << 8)
1000 #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK 0x1
1001 #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT (0x1 << 9)
1005 #define ACCDET_EINT_M_PLUG_IN_EN_MASK 0x1
1006 #define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT (0x1 << 10)
1010 #define ACCDET_EINT_M_HWMODE_EN_MASK 0x1
1011 #define ACCDET_EINT_M_HWMODE_EN_MASK_SFT (0x1 << 11)
1014 #define ACCDET_TEST_CMPEN_SFT 0
1015 #define ACCDET_TEST_CMPEN_MASK 0x1
1016 #define ACCDET_TEST_CMPEN_MASK_SFT (0x1 << 0)
1020 #define ACCDET_TEST_VTHEN_MASK 0x1
1021 #define ACCDET_TEST_VTHEN_MASK_SFT (0x1 << 1)
1025 #define ACCDET_TEST_MBIASEN_MASK 0x1
1026 #define ACCDET_TEST_MBIASEN_MASK_SFT (0x1 << 2)
1030 #define ACCDET_EINT_TEST_EN_MASK 0x1
1031 #define ACCDET_EINT_TEST_EN_MASK_SFT (0x1 << 3)
1035 #define ACCDET_EINT_TEST_INVEN_MASK 0x1
1036 #define ACCDET_EINT_TEST_INVEN_MASK_SFT (0x1 << 4)
1040 #define ACCDET_EINT_TEST_CMPEN_MASK 0x1
1041 #define ACCDET_EINT_TEST_CMPEN_MASK_SFT (0x1 << 5)
1045 #define ACCDET_EINT_TEST_CMPMEN_MASK 0x1
1046 #define ACCDET_EINT_TEST_CMPMEN_MASK_SFT (0x1 << 6)
1050 #define ACCDET_EINT_TEST_CTURBO_MASK 0x1
1051 #define ACCDET_EINT_TEST_CTURBO_MASK_SFT (0x1 << 7)
1055 #define ACCDET_EINT_TEST_CEN_MASK 0x1
1056 #define ACCDET_EINT_TEST_CEN_MASK_SFT (0x1 << 8)
1060 #define ACCDET_TEST_B_MASK 0x1
1061 #define ACCDET_TEST_B_MASK_SFT (0x1 << 9)
1065 #define ACCDET_TEST_A_MASK 0x1
1066 #define ACCDET_TEST_A_MASK_SFT (0x1 << 10)
1070 #define ACCDET_EINT_TEST_CMPOUT_MASK 0x1
1071 #define ACCDET_EINT_TEST_CMPOUT_MASK_SFT (0x1 << 11)
1075 #define ACCDET_EINT_TEST_CMPMOUT_MASK 0x1
1076 #define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT (0x1 << 12)
1080 #define ACCDET_EINT_TEST_INVOUT_MASK 0x1
1081 #define ACCDET_EINT_TEST_INVOUT_MASK_SFT (0x1 << 13)
1084 #define ACCDET_CMPEN_SEL_SFT 0
1085 #define ACCDET_CMPEN_SEL_MASK 0x1
1086 #define ACCDET_CMPEN_SEL_MASK_SFT (0x1 << 0)
1090 #define ACCDET_VTHEN_SEL_MASK 0x1
1091 #define ACCDET_VTHEN_SEL_MASK_SFT (0x1 << 1)
1095 #define ACCDET_MBIASEN_SEL_MASK 0x1
1096 #define ACCDET_MBIASEN_SEL_MASK_SFT (0x1 << 2)
1100 #define ACCDET_EINT_EN_SEL_MASK 0x1
1101 #define ACCDET_EINT_EN_SEL_MASK_SFT (0x1 << 3)
1105 #define ACCDET_EINT_INVEN_SEL_MASK 0x1
1106 #define ACCDET_EINT_INVEN_SEL_MASK_SFT (0x1 << 4)
1110 #define ACCDET_EINT_CMPEN_SEL_MASK 0x1
1111 #define ACCDET_EINT_CMPEN_SEL_MASK_SFT (0x1 << 5)
1115 #define ACCDET_EINT_CMPMEN_SEL_MASK 0x1
1116 #define ACCDET_EINT_CMPMEN_SEL_MASK_SFT (0x1 << 6)
1120 #define ACCDET_EINT_CTURBO_SEL_MASK 0x1
1121 #define ACCDET_EINT_CTURBO_SEL_MASK_SFT (0x1 << 7)
1125 #define ACCDET_B_SEL_MASK 0x1
1126 #define ACCDET_B_SEL_MASK_SFT (0x1 << 9)
1130 #define ACCDET_A_SEL_MASK 0x1
1131 #define ACCDET_A_SEL_MASK_SFT (0x1 << 10)
1135 #define ACCDET_EINT_CMPOUT_SEL_MASK 0x1
1136 #define ACCDET_EINT_CMPOUT_SEL_MASK_SFT (0x1 << 11)
1140 #define ACCDET_EINT_CMPMOUT_SEL_MASK 0x1
1141 #define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT (0x1 << 12)
1145 #define ACCDET_EINT_INVOUT_SEL_MASK 0x1
1146 #define ACCDET_EINT_INVOUT_SEL_MASK_SFT (0x1 << 13)
1149 #define ACCDET_CMPEN_SW_SFT 0
1150 #define ACCDET_CMPEN_SW_MASK 0x1
1151 #define ACCDET_CMPEN_SW_MASK_SFT (0x1 << 0)
1155 #define ACCDET_VTHEN_SW_MASK 0x1
1156 #define ACCDET_VTHEN_SW_MASK_SFT (0x1 << 1)
1160 #define ACCDET_MBIASEN_SW_MASK 0x1
1161 #define ACCDET_MBIASEN_SW_MASK_SFT (0x1 << 2)
1165 #define ACCDET_EINT0_EN_SW_MASK 0x1
1166 #define ACCDET_EINT0_EN_SW_MASK_SFT (0x1 << 3)
1170 #define ACCDET_EINT0_INVEN_SW_MASK 0x1
1171 #define ACCDET_EINT0_INVEN_SW_MASK_SFT (0x1 << 4)
1175 #define ACCDET_EINT0_CMPEN_SW_MASK 0x1
1176 #define ACCDET_EINT0_CMPEN_SW_MASK_SFT (0x1 << 5)
1180 #define ACCDET_EINT0_CMPMEN_SW_MASK 0x1
1181 #define ACCDET_EINT0_CMPMEN_SW_MASK_SFT (0x1 << 6)
1185 #define ACCDET_EINT0_CTURBO_SW_MASK 0x1
1186 #define ACCDET_EINT0_CTURBO_SW_MASK_SFT (0x1 << 7)
1190 #define ACCDET_EINT1_EN_SW_MASK 0x1
1191 #define ACCDET_EINT1_EN_SW_MASK_SFT (0x1 << 8)
1195 #define ACCDET_EINT1_INVEN_SW_MASK 0x1
1196 #define ACCDET_EINT1_INVEN_SW_MASK_SFT (0x1 << 9)
1200 #define ACCDET_EINT1_CMPEN_SW_MASK 0x1
1201 #define ACCDET_EINT1_CMPEN_SW_MASK_SFT (0x1 << 10)
1205 #define ACCDET_EINT1_CMPMEN_SW_MASK 0x1
1206 #define ACCDET_EINT1_CMPMEN_SW_MASK_SFT (0x1 << 11)
1210 #define ACCDET_EINT1_CTURBO_SW_MASK 0x1
1211 #define ACCDET_EINT1_CTURBO_SW_MASK_SFT (0x1 << 12)
1214 #define ACCDET_B_SW_SFT 0
1215 #define ACCDET_B_SW_MASK 0x1
1216 #define ACCDET_B_SW_MASK_SFT (0x1 << 0)
1220 #define ACCDET_A_SW_MASK 0x1
1221 #define ACCDET_A_SW_MASK_SFT (0x1 << 1)
1225 #define ACCDET_EINT0_CMPOUT_SW_MASK 0x1
1226 #define ACCDET_EINT0_CMPOUT_SW_MASK_SFT (0x1 << 2)
1230 #define ACCDET_EINT0_CMPMOUT_SW_MASK 0x1
1231 #define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT (0x1 << 3)
1235 #define ACCDET_EINT0_INVOUT_SW_MASK 0x1
1236 #define ACCDET_EINT0_INVOUT_SW_MASK_SFT (0x1 << 4)
1240 #define ACCDET_EINT1_CMPOUT_SW_MASK 0x1
1241 #define ACCDET_EINT1_CMPOUT_SW_MASK_SFT (0x1 << 5)
1245 #define ACCDET_EINT1_CMPMOUT_SW_MASK 0x1
1246 #define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT (0x1 << 6)
1250 #define ACCDET_EINT1_INVOUT_SW_MASK 0x1
1251 #define ACCDET_EINT1_INVOUT_SW_MASK_SFT (0x1 << 7)
1254 #define AD_AUDACCDETCMPOB_SFT 0
1255 #define AD_AUDACCDETCMPOB_MASK 0x1
1256 #define AD_AUDACCDETCMPOB_MASK_SFT (0x1 << 0)
1260 #define AD_AUDACCDETCMPOA_MASK 0x1
1261 #define AD_AUDACCDETCMPOA_MASK_SFT (0x1 << 1)
1265 #define ACCDET_CUR_IN_MASK 0x3
1266 #define ACCDET_CUR_IN_MASK_SFT (0x3 << 2)
1270 #define ACCDET_SAM_IN_MASK 0x3
1271 #define ACCDET_SAM_IN_MASK_SFT (0x3 << 4)
1275 #define ACCDET_MEM_IN_MASK 0x3
1276 #define ACCDET_MEM_IN_MASK_SFT (0x3 << 6)
1280 #define ACCDET_STATE_MASK 0x7
1281 #define ACCDET_STATE_MASK_SFT (0x7 << 8)
1285 #define DA_AUDACCDETMBIASCLK_MASK 0x1
1286 #define DA_AUDACCDETMBIASCLK_MASK_SFT (0x1 << 12)
1290 #define DA_AUDACCDETVTHCLK_MASK 0x1
1291 #define DA_AUDACCDETVTHCLK_MASK_SFT (0x1 << 13)
1295 #define DA_AUDACCDETCMPCLK_MASK 0x1
1296 #define DA_AUDACCDETCMPCLK_MASK_SFT (0x1 << 14)
1300 #define DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
1301 #define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT (0x1 << 15)
1304 #define AD_EINT0CMPMOUT_SFT 0
1305 #define AD_EINT0CMPMOUT_MASK 0x1
1306 #define AD_EINT0CMPMOUT_MASK_SFT (0x1 << 0)
1310 #define AD_EINT0CMPOUT_MASK 0x1
1311 #define AD_EINT0CMPOUT_MASK_SFT (0x1 << 1)
1315 #define ACCDET_EINT0_CUR_IN_MASK 0x3
1316 #define ACCDET_EINT0_CUR_IN_MASK_SFT (0x3 << 2)
1320 #define ACCDET_EINT0_SAM_IN_MASK 0x3
1321 #define ACCDET_EINT0_SAM_IN_MASK_SFT (0x3 << 4)
1325 #define ACCDET_EINT0_MEM_IN_MASK 0x3
1326 #define ACCDET_EINT0_MEM_IN_MASK_SFT (0x3 << 6)
1330 #define ACCDET_EINT0_STATE_MASK 0x7
1331 #define ACCDET_EINT0_STATE_MASK_SFT (0x7 << 8)
1335 #define DA_EINT0CMPEN_MASK 0x1
1336 #define DA_EINT0CMPEN_MASK_SFT (0x1 << 13)
1340 #define DA_EINT0CMPMEN_MASK 0x1
1341 #define DA_EINT0CMPMEN_MASK_SFT (0x1 << 14)
1345 #define DA_EINT0CTURBO_MASK 0x1
1346 #define DA_EINT0CTURBO_MASK_SFT (0x1 << 15)
1349 #define AD_EINT1CMPMOUT_SFT 0
1350 #define AD_EINT1CMPMOUT_MASK 0x1
1351 #define AD_EINT1CMPMOUT_MASK_SFT (0x1 << 0)
1355 #define AD_EINT1CMPOUT_MASK 0x1
1356 #define AD_EINT1CMPOUT_MASK_SFT (0x1 << 1)
1360 #define ACCDET_EINT1_CUR_IN_MASK 0x3
1361 #define ACCDET_EINT1_CUR_IN_MASK_SFT (0x3 << 2)
1365 #define ACCDET_EINT1_SAM_IN_MASK 0x3
1366 #define ACCDET_EINT1_SAM_IN_MASK_SFT (0x3 << 4)
1370 #define ACCDET_EINT1_MEM_IN_MASK 0x3
1371 #define ACCDET_EINT1_MEM_IN_MASK_SFT (0x3 << 6)
1375 #define ACCDET_EINT1_STATE_MASK 0x7
1376 #define ACCDET_EINT1_STATE_MASK_SFT (0x7 << 8)
1380 #define DA_EINT1CMPEN_MASK 0x1
1381 #define DA_EINT1CMPEN_MASK_SFT (0x1 << 13)
1385 #define DA_EINT1CMPMEN_MASK 0x1
1386 #define DA_EINT1CMPMEN_MASK_SFT (0x1 << 14)
1390 #define DA_EINT1CTURBO_MASK 0x1
1391 #define DA_EINT1CTURBO_MASK_SFT (0x1 << 15)
1394 #define AD_EINT0INVOUT_SFT 0
1395 #define AD_EINT0INVOUT_MASK 0x1
1396 #define AD_EINT0INVOUT_MASK_SFT (0x1 << 0)
1400 #define ACCDET_EINT0_INVERTER_CUR_IN_MASK 0x1
1401 #define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1405 #define ACCDET_EINT0_INVERTER_SAM_IN_MASK 0x1
1406 #define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1410 #define ACCDET_EINT0_INVERTER_MEM_IN_MASK 0x1
1411 #define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1415 #define ACCDET_EINT0_INVERTER_STATE_MASK 0x7
1416 #define ACCDET_EINT0_INVERTER_STATE_MASK_SFT (0x7 << 8)
1420 #define DA_EINT0EN_MASK 0x1
1421 #define DA_EINT0EN_MASK_SFT (0x1 << 12)
1425 #define DA_EINT0INVEN_MASK 0x1
1426 #define DA_EINT0INVEN_MASK_SFT (0x1 << 13)
1430 #define DA_EINT0CEN_MASK 0x1
1431 #define DA_EINT0CEN_MASK_SFT (0x1 << 14)
1434 #define AD_EINT1INVOUT_SFT 0
1435 #define AD_EINT1INVOUT_MASK 0x1
1436 #define AD_EINT1INVOUT_MASK_SFT (0x1 << 0)
1440 #define ACCDET_EINT1_INVERTER_CUR_IN_MASK 0x1
1441 #define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT (0x1 << 1)
1445 #define ACCDET_EINT1_INVERTER_SAM_IN_MASK 0x1
1446 #define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT (0x1 << 2)
1450 #define ACCDET_EINT1_INVERTER_MEM_IN_MASK 0x1
1451 #define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT (0x1 << 3)
1455 #define ACCDET_EINT1_INVERTER_STATE_MASK 0x7
1456 #define ACCDET_EINT1_INVERTER_STATE_MASK_SFT (0x7 << 8)
1460 #define DA_EINT1EN_MASK 0x1
1461 #define DA_EINT1EN_MASK_SFT (0x1 << 12)
1465 #define DA_EINT1INVEN_MASK 0x1
1466 #define DA_EINT1INVEN_MASK_SFT (0x1 << 13)
1470 #define DA_EINT1CEN_MASK 0x1
1471 #define DA_EINT1CEN_MASK_SFT (0x1 << 14)
1474 #define ACCDET_EN_SFT 0
1475 #define ACCDET_EN_MASK 0x1
1476 #define ACCDET_EN_MASK_SFT (0x1 << 0)
1480 #define ACCDET_EINT0_EN_MASK 0x1
1481 #define ACCDET_EINT0_EN_MASK_SFT (0x1 << 1)
1485 #define ACCDET_EINT1_EN_MASK 0x1
1486 #define ACCDET_EINT1_EN_MASK_SFT (0x1 << 2)
1490 #define ACCDET_EINT0_M_EN_MASK 0x1
1491 #define ACCDET_EINT0_M_EN_MASK_SFT (0x1 << 3)
1495 #define ACCDET_EINT0_DETECT_MOISTURE_MASK 0x1
1496 #define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT (0x1 << 4)
1500 #define ACCDET_EINT0_PLUG_IN_MASK 0x1
1501 #define ACCDET_EINT0_PLUG_IN_MASK_SFT (0x1 << 5)
1505 #define ACCDET_EINT0_M_PLUG_IN_MASK 0x1
1506 #define ACCDET_EINT0_M_PLUG_IN_MASK_SFT (0x1 << 6)
1510 #define ACCDET_EINT1_M_EN_MASK 0x1
1511 #define ACCDET_EINT1_M_EN_MASK_SFT (0x1 << 7)
1515 #define ACCDET_EINT1_DETECT_MOISTURE_MASK 0x1
1516 #define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT (0x1 << 8)
1520 #define ACCDET_EINT1_PLUG_IN_MASK 0x1
1521 #define ACCDET_EINT1_PLUG_IN_MASK_SFT (0x1 << 9)
1525 #define ACCDET_EINT1_M_PLUG_IN_MASK 0x1
1526 #define ACCDET_EINT1_M_PLUG_IN_MASK_SFT (0x1 << 10)
1529 #define ACCDET_CUR_DEB_SFT 0
1530 #define ACCDET_CUR_DEB_MASK 0xFFFF
1531 #define ACCDET_CUR_DEB_MASK_SFT (0xFFFF << 0)
1534 #define ACCDET_EINT0_CUR_DEB_SFT 0
1535 #define ACCDET_EINT0_CUR_DEB_MASK 0x7FFF
1536 #define ACCDET_EINT0_CUR_DEB_MASK_SFT (0x7FFF << 0)
1539 #define ACCDET_EINT1_CUR_DEB_SFT 0
1540 #define ACCDET_EINT1_CUR_DEB_MASK 0x7FFF
1541 #define ACCDET_EINT1_CUR_DEB_MASK_SFT (0x7FFF << 0)
1544 #define ACCDET_EINT0_INVERTER_CUR_DEB_SFT 0
1545 #define ACCDET_EINT0_INVERTER_CUR_DEB_MASK 0x7FFF
1546 #define ACCDET_EINT0_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)
1549 #define ACCDET_EINT1_INVERTER_CUR_DEB_SFT 0
1550 #define ACCDET_EINT1_INVERTER_CUR_DEB_MASK 0x7FFF
1551 #define ACCDET_EINT1_INVERTER_CUR_DEB_MASK_SFT (0x7FFF << 0)
1554 #define AD_AUDACCDETCMPOB_MON_SFT 0
1555 #define AD_AUDACCDETCMPOB_MON_MASK 0x1
1556 #define AD_AUDACCDETCMPOB_MON_MASK_SFT (0x1 << 0)
1560 #define AD_AUDACCDETCMPOA_MON_MASK 0x1
1561 #define AD_AUDACCDETCMPOA_MON_MASK_SFT (0x1 << 1)
1565 #define AD_EINT0CMPMOUT_MON_MASK 0x1
1566 #define AD_EINT0CMPMOUT_MON_MASK_SFT (0x1 << 2)
1570 #define AD_EINT0CMPOUT_MON_MASK 0x1
1571 #define AD_EINT0CMPOUT_MON_MASK_SFT (0x1 << 3)
1575 #define AD_EINT0INVOUT_MON_MASK 0x1
1576 #define AD_EINT0INVOUT_MON_MASK_SFT (0x1 << 4)
1580 #define AD_EINT1CMPMOUT_MON_MASK 0x1
1581 #define AD_EINT1CMPMOUT_MON_MASK_SFT (0x1 << 5)
1585 #define AD_EINT1CMPOUT_MON_MASK 0x1
1586 #define AD_EINT1CMPOUT_MON_MASK_SFT (0x1 << 6)
1590 #define AD_EINT1INVOUT_MON_MASK 0x1
1591 #define AD_EINT1INVOUT_MON_MASK_SFT (0x1 << 7)
1594 #define DA_AUDACCDETCMPCLK_MON_SFT 0
1595 #define DA_AUDACCDETCMPCLK_MON_MASK 0x1
1596 #define DA_AUDACCDETCMPCLK_MON_MASK_SFT (0x1 << 0)
1600 #define DA_AUDACCDETVTHCLK_MON_MASK 0x1
1601 #define DA_AUDACCDETVTHCLK_MON_MASK_SFT (0x1 << 1)
1605 #define DA_AUDACCDETMBIASCLK_MON_MASK 0x1
1606 #define DA_AUDACCDETMBIASCLK_MON_MASK_SFT (0x1 << 2)
1610 #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK 0x1
1611 #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT (0x1 << 3)
1614 #define DA_EINT0CTURBO_MON_SFT 0
1615 #define DA_EINT0CTURBO_MON_MASK 0x1
1616 #define DA_EINT0CTURBO_MON_MASK_SFT (0x1 << 0)
1620 #define DA_EINT0CMPMEN_MON_MASK 0x1
1621 #define DA_EINT0CMPMEN_MON_MASK_SFT (0x1 << 1)
1625 #define DA_EINT0CMPEN_MON_MASK 0x1
1626 #define DA_EINT0CMPEN_MON_MASK_SFT (0x1 << 2)
1630 #define DA_EINT0INVEN_MON_MASK 0x1
1631 #define DA_EINT0INVEN_MON_MASK_SFT (0x1 << 3)
1635 #define DA_EINT0CEN_MON_MASK 0x1
1636 #define DA_EINT0CEN_MON_MASK_SFT (0x1 << 4)
1640 #define DA_EINT0EN_MON_MASK 0x1
1641 #define DA_EINT0EN_MON_MASK_SFT (0x1 << 5)
1645 #define DA_EINT1CTURBO_MON_MASK 0x1
1646 #define DA_EINT1CTURBO_MON_MASK_SFT (0x1 << 8)
1650 #define DA_EINT1CMPMEN_MON_MASK 0x1
1651 #define DA_EINT1CMPMEN_MON_MASK_SFT (0x1 << 9)
1655 #define DA_EINT1CMPEN_MON_MASK 0x1
1656 #define DA_EINT1CMPEN_MON_MASK_SFT (0x1 << 10)
1660 #define DA_EINT1INVEN_MON_MASK 0x1
1661 #define DA_EINT1INVEN_MON_MASK_SFT (0x1 << 11)
1665 #define DA_EINT1CEN_MON_MASK 0x1
1666 #define DA_EINT1CEN_MON_MASK_SFT (0x1 << 12)
1670 #define DA_EINT1EN_MON_MASK 0x1
1671 #define DA_EINT1EN_MON_MASK_SFT (0x1 << 13)
1674 #define ACCDET_EINT0_M_PLUG_IN_COUNT_SFT 0
1675 #define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK 0x7
1676 #define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 0)
1680 #define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK 0x7
1681 #define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK_SFT (0x7 << 4)
1684 #define ACCDET_MON_FLAG_EN_SFT 0
1685 #define ACCDET_MON_FLAG_EN_MASK 0x1
1686 #define ACCDET_MON_FLAG_EN_MASK_SFT (0x1 << 0)
1690 #define ACCDET_MON_FLAG_SEL_MASK 0xF
1691 #define ACCDET_MON_FLAG_SEL_MASK_SFT (0xF << 4)
1695 #define RG_AUDPWDBMICBIAS0_SFT 0
1696 #define RG_AUDPWDBMICBIAS0_MASK 0x1
1697 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
1700 #define RG_AUDPREAMPLON_SFT 0
1701 #define RG_AUDPREAMPLON_MASK 0x1
1702 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
1705 #define RG_CLKSQ_EN_SFT 0
1706 #define RG_CLKSQ_EN_MASK 0x1
1707 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
1711 #define RG_RTC32K_CK_PDN_MASK 0x1
1712 #define RG_RTC32K_CK_PDN_MASK_SFT (0x1 << 15)
1715 #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0
1716 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
1717 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
1721 #define AUXADC_RQST_CH5_MASK 0x1
1722 #define AUXADC_RQST_CH5_MASK_SFT (0x1 << 5)
1725 #define RG_LDO_VUSB_HW0_OP_EN_SFT 0
1726 #define RG_LDO_VUSB_HW0_OP_EN_MASK 0x1
1727 #define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT (0x1 << 0)
1731 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
1732 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
1735 #define RG_NCP_PDDIS_EN_SFT 0
1736 #define RG_NCP_PDDIS_EN_MASK 0x1
1737 #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
1740 #define RG_SCK32K_CK_PDN_SFT 0
1741 #define RG_SCK32K_CK_PDN_MASK 0x1
1742 #define RG_SCK32K_CK_PDN_MASK_SFT (0x1 << 0)
1744 #define RG_ACCDET_MODE_ANA11_MODE1 (0x000F)
1745 #define RG_ACCDET_MODE_ANA11_MODE2 (0x008F)
1746 #define RG_ACCDET_MODE_ANA11_MODE6 (0x008F)
1751 #define AUXADC_DATA_MASK (0x0FFF)
1753 /* AUXADC_RQST0_SET: Auxadc CH5 request, relevant 0x07EC */
1755 /* AUXADC_RQST0_CLR: Auxadc CH5 request, relevant 0x07EC */
1758 #define ACCDET_CALI_MASK0 (0xFF)
1759 #define ACCDET_CALI_MASK1 (0xFF << 8)
1760 #define ACCDET_CALI_MASK2 (0xFF)
1761 #define ACCDET_CALI_MASK3 (0xFF << 8)
1762 #define ACCDET_CALI_MASK4 (0xFF)
1764 #define ACCDET_EINT_IRQ_B2_B3 (0x03 << ACCDET_EINT0_IRQ_SFT)
1768 #define ACCDET_STATE_AB_MASK (0x03)
1769 #define ACCDET_STATE_AB_00 (0x00)
1770 #define ACCDET_STATE_AB_01 (0x01)
1771 #define ACCDET_STATE_AB_10 (0x02)
1772 #define ACCDET_STATE_AB_11 (0x03)
1790 #define RG_VOW13M_CK_PDN_MASK 0x1
1791 #define RG_VOW13M_CK_PDN_MASK_SFT (0x1 << 13)
1793 #define RG_VOW32K_CK_PDN_MASK 0x1
1794 #define RG_VOW32K_CK_PDN_MASK_SFT (0x1 << 12)
1796 #define RG_AUD_INTRP_CK_PDN_MASK 0x1
1797 #define RG_AUD_INTRP_CK_PDN_MASK_SFT (0x1 << 8)
1799 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK 0x1
1800 #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT (0x1 << 7)
1802 #define RG_AUDNCP_CK_PDN_MASK 0x1
1803 #define RG_AUDNCP_CK_PDN_MASK_SFT (0x1 << 6)
1805 #define RG_ZCD13M_CK_PDN_MASK 0x1
1806 #define RG_ZCD13M_CK_PDN_MASK_SFT (0x1 << 5)
1808 #define RG_AUDIF_CK_PDN_MASK 0x1
1809 #define RG_AUDIF_CK_PDN_MASK_SFT (0x1 << 2)
1811 #define RG_AUD_CK_PDN_MASK 0x1
1812 #define RG_AUD_CK_PDN_MASK_SFT (0x1 << 1)
1813 #define RG_ACCDET_CK_PDN_SFT 0
1814 #define RG_ACCDET_CK_PDN_MASK 0x1
1815 #define RG_ACCDET_CK_PDN_MASK_SFT (0x1 << 0)
1818 #define RG_AUD_TOP_CKPDN_CON0_SET_SFT 0
1819 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK 0x3fff
1820 #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT (0x3fff << 0)
1823 #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT 0
1824 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK 0x3fff
1825 #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT (0x3fff << 0)
1829 #define RG_AUDIF_CK_CKSEL_MASK 0x1
1830 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
1832 #define RG_AUD_CK_CKSEL_MASK 0x1
1833 #define RG_AUD_CK_CKSEL_MASK_SFT (0x1 << 2)
1836 #define RG_AUD_TOP_CKSEL_CON0_SET_SFT 0
1837 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK 0xf
1838 #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT (0xf << 0)
1841 #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT 0
1842 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK 0xf
1843 #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT (0xf << 0)
1847 #define RG_VOW13M_CK_TSTSEL_MASK 0x1
1848 #define RG_VOW13M_CK_TSTSEL_MASK_SFT (0x1 << 9)
1850 #define RG_VOW13M_CK_TST_DIS_MASK 0x1
1851 #define RG_VOW13M_CK_TST_DIS_MASK_SFT (0x1 << 8)
1853 #define RG_AUD26M_CK_TSTSEL_MASK 0x1
1854 #define RG_AUD26M_CK_TSTSEL_MASK_SFT (0x1 << 4)
1856 #define RG_AUDIF_CK_TSTSEL_MASK 0x1
1857 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
1859 #define RG_AUD_CK_TSTSEL_MASK 0x1
1860 #define RG_AUD_CK_TSTSEL_MASK_SFT (0x1 << 2)
1861 #define RG_AUD26M_CK_TST_DIS_SFT 0
1862 #define RG_AUD26M_CK_TST_DIS_MASK 0x1
1863 #define RG_AUD26M_CK_TST_DIS_MASK_SFT (0x1 << 0)
1866 #define RG_AUD_INTRP_CK_PDN_HWEN_SFT 0
1867 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK 0x1
1868 #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT (0x1 << 0)
1871 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT 0
1872 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK 0xffff
1873 #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT (0xffff << 0)
1876 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT 0
1877 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK 0xffff
1878 #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT (0xffff << 0)
1882 #define RG_AUDNCP_RST_MASK 0x1
1883 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
1885 #define RG_ZCD_RST_MASK 0x1
1886 #define RG_ZCD_RST_MASK_SFT (0x1 << 2)
1888 #define RG_ACCDET_RST_MASK 0x1
1889 #define RG_ACCDET_RST_MASK_SFT (0x1 << 1)
1890 #define RG_AUDIO_RST_SFT 0
1891 #define RG_AUDIO_RST_MASK 0x1
1892 #define RG_AUDIO_RST_MASK_SFT (0x1 << 0)
1895 #define RG_AUD_TOP_RST_CON0_SET_SFT 0
1896 #define RG_AUD_TOP_RST_CON0_SET_MASK 0xf
1897 #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT (0xf << 0)
1900 #define RG_AUD_TOP_RST_CON0_CLR_SFT 0
1901 #define RG_AUD_TOP_RST_CON0_CLR_MASK 0xf
1902 #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT (0xf << 0)
1906 #define BANK_AUDZCD_SWRST_MASK 0x1
1907 #define BANK_AUDZCD_SWRST_MASK_SFT (0x1 << 2)
1909 #define BANK_AUDIO_SWRST_MASK 0x1
1910 #define BANK_AUDIO_SWRST_MASK_SFT (0x1 << 1)
1911 #define BANK_ACCDET_SWRST_SFT 0
1912 #define BANK_ACCDET_SWRST_MASK 0x1
1913 #define BANK_ACCDET_SWRST_MASK_SFT (0x1 << 0)
1917 #define AFE_UL_LR_SWAP_MASK 0x1
1918 #define AFE_UL_LR_SWAP_MASK_SFT (0x1 << 15)
1920 #define AFE_DL_LR_SWAP_MASK 0x1
1921 #define AFE_DL_LR_SWAP_MASK_SFT (0x1 << 14)
1922 #define AFE_ON_SFT 0
1923 #define AFE_ON_MASK 0x1
1924 #define AFE_ON_MASK_SFT (0x1 << 0)
1927 #define DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
1928 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK 0x1
1929 #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT (0x1 << 0)
1933 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
1934 #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
1936 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
1937 #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
1939 #define C_TWO_DIGITAL_MIC_CTL_MASK 0x1
1940 #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
1944 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
1945 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
1947 #define DIGMIC_4P33M_SEL_CTL_MASK 0x1
1948 #define DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
1950 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1951 #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1953 #define UL_LOOP_BACK_MODE_CTL_MASK 0x1
1954 #define UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1956 #define UL_SDM_3_LEVEL_CTL_MASK 0x1
1957 #define UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1958 #define UL_SRC_ON_TMP_CTL_SFT 0
1959 #define UL_SRC_ON_TMP_CTL_MASK 0x1
1960 #define UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1964 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK 0x7
1965 #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT (0x7 << 11)
1967 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK 0x7
1968 #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT (0x7 << 8)
1970 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK 0x1
1971 #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT (0x1 << 7)
1975 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
1976 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
1978 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK 0x1
1979 #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT (0x1 << 6)
1981 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK 0x1
1982 #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT (0x1 << 5)
1984 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK 0x1
1985 #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT (0x1 << 2)
1987 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK 0x1
1988 #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT (0x1 << 1)
1989 #define ADDA6_UL_SRC_ON_TMP_CTL_SFT 0
1990 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK 0x1
1991 #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT (0x1 << 0)
1995 #define ADDA6_MTKAIF_SINE_ON_MASK 0x1
1996 #define ADDA6_MTKAIF_SINE_ON_MASK_SFT (0x1 << 4)
1998 #define ADDA6_UL_SINE_ON_MASK 0x1
1999 #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
2001 #define MTKAIF_SINE_ON_MASK 0x1
2002 #define MTKAIF_SINE_ON_MASK_SFT (0x1 << 2)
2004 #define UL_SINE_ON_MASK 0x1
2005 #define UL_SINE_ON_MASK_SFT (0x1 << 1)
2006 #define DL_SINE_ON_SFT 0
2007 #define DL_SINE_ON_MASK 0x1
2008 #define DL_SINE_ON_MASK_SFT (0x1 << 0)
2012 #define PDN_AFE_CTL_MASK 0x1
2013 #define PDN_AFE_CTL_MASK_SFT (0x1 << 7)
2015 #define PDN_DAC_CTL_MASK 0x1
2016 #define PDN_DAC_CTL_MASK_SFT (0x1 << 6)
2018 #define PDN_ADC_CTL_MASK 0x1
2019 #define PDN_ADC_CTL_MASK_SFT (0x1 << 5)
2021 #define PDN_ADDA6_ADC_CTL_MASK 0x1
2022 #define PDN_ADDA6_ADC_CTL_MASK_SFT (0x1 << 4)
2024 #define PDN_I2S_DL_CTL_MASK 0x1
2025 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
2027 #define PWR_CLK_DIS_CTL_MASK 0x1
2028 #define PWR_CLK_DIS_CTL_MASK_SFT (0x1 << 2)
2030 #define PDN_AFE_TESTMODEL_CTL_MASK 0x1
2031 #define PDN_AFE_TESTMODEL_CTL_MASK_SFT (0x1 << 1)
2032 #define PDN_RESERVED_SFT 0
2033 #define PDN_RESERVED_MASK 0x1
2034 #define PDN_RESERVED_MASK_SFT (0x1 << 0)
2038 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
2039 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
2041 #define AUDIO_SYS_TOP_MON_SEL_MASK 0x1f
2042 #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT (0x1f << 8)
2043 #define AFE_MON_SEL_SFT 0
2044 #define AFE_MON_SEL_MASK 0xff
2045 #define AFE_MON_SEL_MASK_SFT (0xff << 0)
2049 #define CCI_AUD_ANACK_SEL_MASK 0x1
2050 #define CCI_AUD_ANACK_SEL_MASK_SFT (0x1 << 15)
2052 #define CCI_AUDIO_FIFO_WPTR_MASK 0x7
2053 #define CCI_AUDIO_FIFO_WPTR_MASK_SFT (0x7 << 12)
2055 #define CCI_SCRAMBLER_CG_EN_MASK 0x1
2056 #define CCI_SCRAMBLER_CG_EN_MASK_SFT (0x1 << 11)
2058 #define CCI_LCH_INV_MASK 0x1
2059 #define CCI_LCH_INV_MASK_SFT (0x1 << 10)
2061 #define CCI_RAND_EN_MASK 0x1
2062 #define CCI_RAND_EN_MASK_SFT (0x1 << 9)
2064 #define CCI_SPLT_SCRMB_CLK_ON_MASK 0x1
2065 #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT (0x1 << 8)
2067 #define CCI_SPLT_SCRMB_ON_MASK 0x1
2068 #define CCI_SPLT_SCRMB_ON_MASK_SFT (0x1 << 7)
2070 #define CCI_AUD_IDAC_TEST_EN_MASK 0x1
2071 #define CCI_AUD_IDAC_TEST_EN_MASK_SFT (0x1 << 6)
2073 #define CCI_ZERO_PAD_DISABLE_MASK 0x1
2074 #define CCI_ZERO_PAD_DISABLE_MASK_SFT (0x1 << 5)
2076 #define CCI_AUD_SPLIT_TEST_EN_MASK 0x1
2077 #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT (0x1 << 4)
2079 #define CCI_AUD_SDM_MUTEL_MASK 0x1
2080 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
2082 #define CCI_AUD_SDM_MUTER_MASK 0x1
2083 #define CCI_AUD_SDM_MUTER_MASK_SFT (0x1 << 2)
2085 #define CCI_AUD_SDM_7BIT_SEL_MASK 0x1
2086 #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT (0x1 << 1)
2087 #define CCI_SCRAMBLER_EN_SFT 0
2088 #define CCI_SCRAMBLER_EN_MASK 0x1
2089 #define CCI_SCRAMBLER_EN_MASK_SFT (0x1 << 0)
2093 #define AUD_SDM_TEST_L_MASK 0xff
2094 #define AUD_SDM_TEST_L_MASK_SFT (0xff << 8)
2095 #define AUD_SDM_TEST_R_SFT 0
2096 #define AUD_SDM_TEST_R_MASK 0xff
2097 #define AUD_SDM_TEST_R_MASK_SFT (0xff << 0)
2101 #define CCI_AUD_DAC_ANA_MUTE_MASK 0x1
2102 #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT (0x1 << 7)
2104 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK 0x1
2105 #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT (0x1 << 6)
2107 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK 0x1
2108 #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT (0x1 << 4)
2110 #define CCI_AUDIO_FIFO_ENABLE_MASK 0x1
2111 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
2113 #define CCI_ACD_MODE_MASK 0x1
2114 #define CCI_ACD_MODE_MASK_SFT (0x1 << 2)
2116 #define CCI_AFIFO_CLK_PWDB_MASK 0x1
2117 #define CCI_AFIFO_CLK_PWDB_MASK_SFT (0x1 << 1)
2118 #define CCI_ACD_FUNC_RSTB_SFT 0
2119 #define CCI_ACD_FUNC_RSTB_MASK 0x1
2120 #define CCI_ACD_FUNC_RSTB_MASK_SFT (0x1 << 0)
2124 #define SDM_ANA13M_TESTCK_SEL_MASK 0x1
2125 #define SDM_ANA13M_TESTCK_SEL_MASK_SFT (0x1 << 15)
2127 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK 0x7
2128 #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 12)
2130 #define SDM_TESTCK_SRC_SEL_MASK 0x7
2131 #define SDM_TESTCK_SRC_SEL_MASK_SFT (0x7 << 8)
2133 #define DIGMIC_TESTCK_SRC_SEL_MASK 0x7
2134 #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 4)
2135 #define DIGMIC_TESTCK_SEL_SFT 0
2136 #define DIGMIC_TESTCK_SEL_MASK 0x1
2137 #define DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 0)
2141 #define UL_FIFO_WCLK_INV_MASK 0x1
2142 #define UL_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
2144 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
2145 #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
2147 #define UL_FIFO_WDATA_TESTEN_MASK 0x1
2148 #define UL_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
2150 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
2151 #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
2153 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
2154 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2155 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
2156 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
2157 #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
2161 #define R_AUD_DAC_POS_LARGE_MONO_MASK 0xff
2162 #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT (0xff << 8)
2163 #define R_AUD_DAC_NEG_LARGE_MONO_SFT 0
2164 #define R_AUD_DAC_NEG_LARGE_MONO_MASK 0xff
2165 #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT (0xff << 0)
2169 #define R_AUD_DAC_POS_SMALL_MONO_MASK 0xf
2170 #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT (0xf << 12)
2172 #define R_AUD_DAC_NEG_SMALL_MONO_MASK 0xf
2173 #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT (0xf << 8)
2175 #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
2176 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
2178 #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
2179 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
2181 #define R_AUD_DAC_MONO_SEL_MASK 0x1
2182 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
2184 #define R_AUD_DAC_3TH_SEL_MASK 0x1
2185 #define R_AUD_DAC_3TH_SEL_MASK_SFT (0x1 << 1)
2186 #define R_AUD_DAC_SW_RSTB_SFT 0
2187 #define R_AUD_DAC_SW_RSTB_MASK 0x1
2188 #define R_AUD_DAC_SW_RSTB_MASK_SFT (0x1 << 0)
2192 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK 0x7
2193 #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT (0x7 << 10)
2195 #define UL2_DIGMIC_TESTCK_SEL_MASK 0x1
2196 #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT (0x1 << 9)
2198 #define UL2_FIFO_WCLK_INV_MASK 0x1
2199 #define UL2_FIFO_WCLK_INV_MASK_SFT (0x1 << 8)
2201 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK 0x1
2202 #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 6)
2204 #define UL2_FIFO_WDATA_TESTEN_MASK 0x1
2205 #define UL2_FIFO_WDATA_TESTEN_MASK_SFT (0x1 << 5)
2207 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK 0x1
2208 #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT (0x1 << 4)
2210 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK 0x1
2211 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
2212 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT 0
2213 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK 0x7
2214 #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT (0x7 << 0)
2218 #define SPLITTER2_DITHER_EN_MASK 0x1
2219 #define SPLITTER2_DITHER_EN_MASK_SFT (0x1 << 9)
2221 #define SPLITTER1_DITHER_EN_MASK 0x1
2222 #define SPLITTER1_DITHER_EN_MASK_SFT (0x1 << 8)
2224 #define SPLITTER2_DITHER_GAIN_MASK 0xf
2225 #define SPLITTER2_DITHER_GAIN_MASK_SFT (0xf << 4)
2226 #define SPLITTER1_DITHER_GAIN_SFT 0
2227 #define SPLITTER1_DITHER_GAIN_MASK 0xf
2228 #define SPLITTER1_DITHER_GAIN_MASK_SFT (0xf << 0)
2232 #define CCI_AUD_ANACK_SEL_2ND_MASK 0x1
2233 #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT (0x1 << 15)
2235 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK 0x7
2236 #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT (0x7 << 12)
2238 #define CCI_SCRAMBLER_CG_EN_2ND_MASK 0x1
2239 #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT (0x1 << 11)
2241 #define CCI_LCH_INV_2ND_MASK 0x1
2242 #define CCI_LCH_INV_2ND_MASK_SFT (0x1 << 10)
2244 #define CCI_RAND_EN_2ND_MASK 0x1
2245 #define CCI_RAND_EN_2ND_MASK_SFT (0x1 << 9)
2247 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK 0x1
2248 #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT (0x1 << 8)
2250 #define CCI_SPLT_SCRMB_ON_2ND_MASK 0x1
2251 #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT (0x1 << 7)
2253 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK 0x1
2254 #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT (0x1 << 6)
2256 #define CCI_ZERO_PAD_DISABLE_2ND_MASK 0x1
2257 #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT (0x1 << 5)
2259 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK 0x1
2260 #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT (0x1 << 4)
2262 #define CCI_AUD_SDM_MUTEL_2ND_MASK 0x1
2263 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
2265 #define CCI_AUD_SDM_MUTER_2ND_MASK 0x1
2266 #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT (0x1 << 2)
2268 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK 0x1
2269 #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT (0x1 << 1)
2270 #define CCI_SCRAMBLER_EN_2ND_SFT 0
2271 #define CCI_SCRAMBLER_EN_2ND_MASK 0x1
2272 #define CCI_SCRAMBLER_EN_2ND_MASK_SFT (0x1 << 0)
2276 #define AUD_SDM_TEST_L_2ND_MASK 0xff
2277 #define AUD_SDM_TEST_L_2ND_MASK_SFT (0xff << 8)
2278 #define AUD_SDM_TEST_R_2ND_SFT 0
2279 #define AUD_SDM_TEST_R_2ND_MASK 0xff
2280 #define AUD_SDM_TEST_R_2ND_MASK_SFT (0xff << 0)
2284 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK 0x1
2285 #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT (0x1 << 7)
2287 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK 0x1
2288 #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT (0x1 << 6)
2290 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK 0x1
2291 #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT (0x1 << 4)
2293 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK 0x1
2294 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
2296 #define CCI_ACD_MODE_2ND_MASK 0x1
2297 #define CCI_ACD_MODE_2ND_MASK_SFT (0x1 << 2)
2299 #define CCI_AFIFO_CLK_PWDB_2ND_MASK 0x1
2300 #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT (0x1 << 1)
2301 #define CCI_ACD_FUNC_RSTB_2ND_SFT 0
2302 #define CCI_ACD_FUNC_RSTB_2ND_MASK 0x1
2303 #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT (0x1 << 0)
2307 #define SPLITTER2_DITHER_EN_2ND_MASK 0x1
2308 #define SPLITTER2_DITHER_EN_2ND_MASK_SFT (0x1 << 9)
2310 #define SPLITTER1_DITHER_EN_2ND_MASK 0x1
2311 #define SPLITTER1_DITHER_EN_2ND_MASK_SFT (0x1 << 8)
2313 #define SPLITTER2_DITHER_GAIN_2ND_MASK 0xf
2314 #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT (0xf << 4)
2315 #define SPLITTER1_DITHER_GAIN_2ND_SFT 0
2316 #define SPLITTER1_DITHER_GAIN_2ND_MASK 0xf
2317 #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT (0xf << 0)
2321 #define AUD_SCR_OUT_L_MASK 0xff
2322 #define AUD_SCR_OUT_L_MASK_SFT (0xff << 8)
2323 #define AUD_SCR_OUT_R_SFT 0
2324 #define AUD_SCR_OUT_R_MASK 0xff
2325 #define AUD_SCR_OUT_R_MASK_SFT (0xff << 0)
2329 #define AUD_SCR_OUT_L_2ND_MASK 0xff
2330 #define AUD_SCR_OUT_L_2ND_MASK_SFT (0xff << 8)
2331 #define AUD_SCR_OUT_R_2ND_SFT 0
2332 #define AUD_SCR_OUT_R_2ND_MASK 0xff
2333 #define AUD_SCR_OUT_R_2ND_MASK_SFT (0xff << 0)
2337 #define ASYNC_TEST_OUT_BCK_MASK 0x1
2338 #define ASYNC_TEST_OUT_BCK_MASK_SFT (0x1 << 15)
2340 #define RGS_AUDRCTUNE1READ_MASK 0x1f
2341 #define RGS_AUDRCTUNE1READ_MASK_SFT (0x1f << 8)
2342 #define RGS_AUDRCTUNE0READ_SFT 0
2343 #define RGS_AUDRCTUNE0READ_MASK 0x1f
2344 #define RGS_AUDRCTUNE0READ_MASK_SFT (0x1f << 0)
2348 #define AFE_RESERVED_MASK 0x7fff
2349 #define AFE_RESERVED_MASK_SFT (0x7fff << 1)
2350 #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT 0
2351 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK 0x1
2352 #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT (0x1 << 0)
2356 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK 0x1
2357 #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT (0x1 << 1)
2358 #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT 0
2359 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK 0x1
2360 #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT (0x1 << 0)
2364 #define MTKAIFTX_V3_SYNC_OUT_MASK 0x1
2365 #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT (0x1 << 15)
2367 #define MTKAIFTX_V3_SDATA_OUT3_MASK 0x1
2368 #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT (0x1 << 14)
2370 #define MTKAIFTX_V3_SDATA_OUT2_MASK 0x1
2371 #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT (0x1 << 13)
2373 #define MTKAIFTX_V3_SDATA_OUT1_MASK 0x1
2374 #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT (0x1 << 12)
2375 #define MTKAIF_RXIF_FIFO_STATUS_SFT 0
2376 #define MTKAIF_RXIF_FIFO_STATUS_MASK 0xfff
2377 #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT (0xfff << 0)
2381 #define MTKAIFRX_V3_SYNC_IN_MASK 0x1
2382 #define MTKAIFRX_V3_SYNC_IN_MASK_SFT (0x1 << 15)
2384 #define MTKAIFRX_V3_SDATA_IN3_MASK 0x1
2385 #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT (0x1 << 14)
2387 #define MTKAIFRX_V3_SDATA_IN2_MASK 0x1
2388 #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT (0x1 << 13)
2390 #define MTKAIFRX_V3_SDATA_IN1_MASK 0x1
2391 #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT (0x1 << 12)
2393 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK 0x1
2394 #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT (0x1 << 11)
2396 #define MTKAIF_RXIF_INVALID_FLAG_MASK 0x1
2397 #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT (0x1 << 8)
2398 #define MTKAIF_RXIF_INVALID_CYCLE_SFT 0
2399 #define MTKAIF_RXIF_INVALID_CYCLE_MASK 0xff
2400 #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT (0xff << 0)
2404 #define MTKAIF_TXIF_IN_CH2_MASK 0xff
2405 #define MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
2406 #define MTKAIF_TXIF_IN_CH1_SFT 0
2407 #define MTKAIF_TXIF_IN_CH1_MASK 0xff
2408 #define MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
2412 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK 0xff
2413 #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT (0xff << 8)
2414 #define ADDA6_MTKAIF_TXIF_IN_CH1_SFT 0
2415 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK 0xff
2416 #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT (0xff << 0)
2420 #define MTKAIF_RXIF_OUT_CH2_MASK 0xff
2421 #define MTKAIF_RXIF_OUT_CH2_MASK_SFT (0xff << 8)
2422 #define MTKAIF_RXIF_OUT_CH1_SFT 0
2423 #define MTKAIF_RXIF_OUT_CH1_MASK 0xff
2424 #define MTKAIF_RXIF_OUT_CH1_MASK_SFT (0xff << 0)
2427 #define MTKAIF_RXIF_OUT_CH3_SFT 0
2428 #define MTKAIF_RXIF_OUT_CH3_MASK 0xff
2429 #define MTKAIF_RXIF_OUT_CH3_MASK_SFT (0xff << 0)
2433 #define RG_MTKAIF_RXIF_CLKINV_MASK 0x1
2434 #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT (0x1 << 15)
2436 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
2437 #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 9)
2439 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK 0x1
2440 #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT (0x1 << 8)
2442 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
2443 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
2445 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK 0x1
2446 #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT (0x1 << 5)
2448 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK 0x1
2449 #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT (0x1 << 4)
2451 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
2452 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
2454 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK 0x1
2455 #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 2)
2457 #define RG_MTKAIF_LOOPBACK_TEST2_MASK 0x1
2458 #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT (0x1 << 1)
2459 #define RG_MTKAIF_LOOPBACK_TEST1_SFT 0
2460 #define RG_MTKAIF_LOOPBACK_TEST1_MASK 0x1
2461 #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT (0x1 << 0)
2465 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK 0xf
2466 #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT (0xf << 12)
2468 #define RG_MTKAIF_RXIF_DATA_BIT_MASK 0x7
2469 #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT (0x7 << 8)
2471 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK 0x7
2472 #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT (0x7 << 4)
2474 #define RG_MTKAIF_RXIF_DETECT_ON_MASK 0x1
2475 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
2476 #define RG_MTKAIF_RXIF_DATA_MODE_SFT 0
2477 #define RG_MTKAIF_RXIF_DATA_MODE_MASK 0x1
2478 #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT (0x1 << 0)
2482 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK 0xf
2483 #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT (0xf << 12)
2485 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK 0xf
2486 #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT (0xf << 8)
2488 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK 0xf
2489 #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT (0xf << 4)
2490 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT 0
2491 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK 0xf
2492 #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT (0xf << 0)
2496 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK 0x1
2497 #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT (0x1 << 15)
2499 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK 0x1
2500 #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT (0x1 << 14)
2502 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK 0x1
2503 #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT (0x1 << 13)
2505 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK 0x1
2506 #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT (0x1 << 12)
2507 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT 0
2508 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK 0xfff
2509 #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT (0xfff << 0)
2513 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK 0x1
2514 #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT (0x1 << 7)
2516 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK 0x7
2517 #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT (0x7 << 4)
2519 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK 0x1
2520 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
2524 #define RG_MTKAIF_RX_SYNC_WORD2_MASK 0x7
2525 #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT (0x7 << 4)
2526 #define RG_MTKAIF_RX_SYNC_WORD1_SFT 0
2527 #define RG_MTKAIF_RX_SYNC_WORD1_MASK 0x7
2528 #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT (0x7 << 0)
2532 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK 0x7
2533 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 12)
2535 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK 0x7
2536 #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 8)
2538 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK 0x7
2539 #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT (0x7 << 4)
2540 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT 0
2541 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK 0x7
2542 #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT (0x7 << 0)
2546 #define SGEN_AMP_DIV_CH1_CTL_MASK 0xf
2547 #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT (0xf << 12)
2549 #define SGEN_DAC_EN_CTL_MASK 0x1
2550 #define SGEN_DAC_EN_CTL_MASK_SFT (0x1 << 7)
2552 #define SGEN_MUTE_SW_CTL_MASK 0x1
2553 #define SGEN_MUTE_SW_CTL_MASK_SFT (0x1 << 6)
2555 #define R_AUD_SDM_MUTE_L_MASK 0x1
2556 #define R_AUD_SDM_MUTE_L_MASK_SFT (0x1 << 5)
2558 #define R_AUD_SDM_MUTE_R_MASK 0x1
2559 #define R_AUD_SDM_MUTE_R_MASK_SFT (0x1 << 4)
2561 #define R_AUD_SDM_MUTE_L_2ND_MASK 0x1
2562 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
2564 #define R_AUD_SDM_MUTE_R_2ND_MASK 0x1
2565 #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT (0x1 << 2)
2569 #define C_SGEN_RCH_INV_5BIT_MASK 0x1
2570 #define C_SGEN_RCH_INV_5BIT_MASK_SFT (0x1 << 15)
2572 #define C_SGEN_RCH_INV_8BIT_MASK 0x1
2573 #define C_SGEN_RCH_INV_8BIT_MASK_SFT (0x1 << 14)
2574 #define SGEN_FREQ_DIV_CH1_CTL_SFT 0
2575 #define SGEN_FREQ_DIV_CH1_CTL_MASK 0x1f
2576 #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT (0x1f << 0)
2580 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
2581 #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
2583 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK 0x1
2584 #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2586 #define RG_AMIC_UL_ADC_CLK_SEL_MASK 0x1
2587 #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT (0x1 << 1)
2591 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK 0x1
2592 #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT (0x1 << 5)
2594 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK 0x1
2595 #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT (0x1 << 4)
2599 #define DCCLK_DIV_MASK 0x7ff
2600 #define DCCLK_DIV_MASK_SFT (0x7ff << 5)
2602 #define DCCLK_INV_MASK 0x1
2603 #define DCCLK_INV_MASK_SFT (0x1 << 4)
2605 #define DCCLK_REF_CK_SEL_MASK 0x3
2606 #define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)
2608 #define DCCLK_PDN_MASK 0x1
2609 #define DCCLK_PDN_MASK_SFT (0x1 << 1)
2610 #define DCCLK_GEN_ON_SFT 0
2611 #define DCCLK_GEN_ON_MASK 0x1
2612 #define DCCLK_GEN_ON_MASK_SFT (0x1 << 0)
2616 #define RESYNC_SRC_SEL_MASK 0x3
2617 #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
2619 #define RESYNC_SRC_CK_INV_MASK 0x1
2620 #define RESYNC_SRC_CK_INV_MASK_SFT (0x1 << 9)
2622 #define DCCLK_RESYNC_BYPASS_MASK 0x1
2623 #define DCCLK_RESYNC_BYPASS_MASK_SFT (0x1 << 8)
2625 #define DCCLK_PHASE_SEL_MASK 0xf
2626 #define DCCLK_PHASE_SEL_MASK_SFT (0xf << 4)
2630 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK 0x1
2631 #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT (0x1 << 15)
2633 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK 0x7f
2634 #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT (0x7f << 8)
2636 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK 0x1
2637 #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT (0x1 << 7)
2638 #define RG_AUD_PAD_TOP_PHASE_MODE_SFT 0
2639 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK 0x7f
2640 #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT (0x7f << 0)
2644 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK 0x1
2645 #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT (0x1 << 7)
2646 #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT 0
2647 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK 0x7f
2648 #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT (0x7f << 0)
2652 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK 0x7
2653 #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT (0x7 << 12)
2655 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK 0x1
2656 #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT (0x1 << 11)
2658 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK 0x1
2659 #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT (0x1 << 8)
2662 #define ADDA_AUD_PAD_TOP_MON_SFT 0
2663 #define ADDA_AUD_PAD_TOP_MON_MASK 0xffff
2664 #define ADDA_AUD_PAD_TOP_MON_MASK_SFT (0xffff << 0)
2667 #define ADDA_AUD_PAD_TOP_MON1_SFT 0
2668 #define ADDA_AUD_PAD_TOP_MON1_MASK 0xffff
2669 #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT (0xffff << 0)
2672 #define ADDA_AUD_PAD_TOP_MON2_SFT 0
2673 #define ADDA_AUD_PAD_TOP_MON2_MASK 0xffff
2674 #define ADDA_AUD_PAD_TOP_MON2_MASK_SFT (0xffff << 0)
2678 #define NLE_RCH_HPGAIN_SEL_MASK 0x1
2679 #define NLE_RCH_HPGAIN_SEL_MASK_SFT (0x1 << 10)
2681 #define NLE_RCH_CH_SEL_MASK 0x1
2682 #define NLE_RCH_CH_SEL_MASK_SFT (0x1 << 9)
2684 #define NLE_RCH_ON_MASK 0x1
2685 #define NLE_RCH_ON_MASK_SFT (0x1 << 8)
2687 #define NLE_LCH_HPGAIN_SEL_MASK 0x1
2688 #define NLE_LCH_HPGAIN_SEL_MASK_SFT (0x1 << 2)
2690 #define NLE_LCH_CH_SEL_MASK 0x1
2691 #define NLE_LCH_CH_SEL_MASK_SFT (0x1 << 1)
2692 #define NLE_LCH_ON_SFT 0
2693 #define NLE_LCH_ON_MASK 0x1
2694 #define NLE_LCH_ON_MASK_SFT (0x1 << 0)
2697 #define NLE_MONITOR_SFT 0
2698 #define NLE_MONITOR_MASK 0x3fff
2699 #define NLE_MONITOR_MASK_SFT (0x3fff << 0)
2702 #define CK_CG_EN_MON_SFT 0
2703 #define CK_CG_EN_MON_MASK 0x3f
2704 #define CK_CG_EN_MON_MASK_SFT (0x3f << 0)
2708 #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3
2709 #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)
2711 #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3
2712 #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)
2714 #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3
2715 #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)
2717 #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3
2718 #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)
2720 #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3
2721 #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)
2722 #define RG_DMIC_ADC3_SOURCE_SEL_SFT 0
2723 #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3
2724 #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)
2728 #define RG_CHOP_DIV_SEL_MASK 0x1f
2729 #define RG_CHOP_DIV_SEL_MASK_SFT (0x1f << 4)
2730 #define RG_CHOP_DIV_EN_SFT 0
2731 #define RG_CHOP_DIV_EN_MASK 0x1
2732 #define RG_CHOP_DIV_EN_MASK_SFT (0x1 << 0)
2736 #define RG_ADDA6_EN_SEL_MASK 0x1
2737 #define RG_ADDA6_EN_SEL_MASK_SFT (0x1 << 12)
2739 #define RG_ADDA6_CH2_SEL_MASK 0x3
2740 #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)
2742 #define RG_ADDA6_CH1_SEL_MASK 0x3
2743 #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)
2745 #define RG_ADDA_EN_SEL_MASK 0x1
2746 #define RG_ADDA_EN_SEL_MASK_SFT (0x1 << 4)
2748 #define RG_ADDA_CH2_SEL_MASK 0x3
2749 #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)
2750 #define RG_ADDA_CH1_SEL_SFT 0
2751 #define RG_ADDA_CH1_SEL_MASK 0x3
2752 #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)
2755 #define RG_UP8X_SYNC_WORD_SFT 0
2756 #define RG_UP8X_SYNC_WORD_MASK 0xffff
2757 #define RG_UP8X_SYNC_WORD_MASK_SFT (0xffff << 0)
2761 #define RG_NCP_CK1_VALID_CNT_MASK 0x7f
2762 #define RG_NCP_CK1_VALID_CNT_MASK_SFT (0x7f << 9)
2764 #define RG_NCP_ADITH_MASK 0x1
2765 #define RG_NCP_ADITH_MASK_SFT (0x1 << 8)
2767 #define RG_NCP_DITHER_EN_MASK 0x1
2768 #define RG_NCP_DITHER_EN_MASK_SFT (0x1 << 7)
2770 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK 0x7
2771 #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT (0x7 << 4)
2773 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK 0x7
2774 #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT (0x7 << 1)
2775 #define RG_NCP_ON_SFT 0
2776 #define RG_NCP_ON_MASK 0x1
2777 #define RG_NCP_ON_MASK_SFT (0x1 << 0)
2781 #define RG_XY_VAL_CFG_EN_MASK 0x1
2782 #define RG_XY_VAL_CFG_EN_MASK_SFT (0x1 << 15)
2784 #define RG_X_VAL_CFG_MASK 0x7f
2785 #define RG_X_VAL_CFG_MASK_SFT (0x7f << 8)
2786 #define RG_Y_VAL_CFG_SFT 0
2787 #define RG_Y_VAL_CFG_MASK 0x7f
2788 #define RG_Y_VAL_CFG_MASK_SFT (0x7f << 0)
2792 #define RG_NCP_NONCLK_SET_MASK 0x1
2793 #define RG_NCP_NONCLK_SET_MASK_SFT (0x1 << 1)
2794 #define RG_NCP_PDDIS_EN_SFT 0
2795 #define RG_NCP_PDDIS_EN_MASK 0x1
2796 #define RG_NCP_PDDIS_EN_MASK_SFT (0x1 << 0)
2799 #define RG_AUDPREAMPLON_SFT 0
2800 #define RG_AUDPREAMPLON_MASK 0x1
2801 #define RG_AUDPREAMPLON_MASK_SFT (0x1 << 0)
2803 #define RG_AUDPREAMPLDCCEN_MASK 0x1
2804 #define RG_AUDPREAMPLDCCEN_MASK_SFT (0x1 << 1)
2806 #define RG_AUDPREAMPLDCPRECHARGE_MASK 0x1
2807 #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT (0x1 << 2)
2809 #define RG_AUDPREAMPLPGATEST_MASK 0x1
2810 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
2812 #define RG_AUDPREAMPLVSCALE_MASK 0x3
2813 #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
2815 #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
2816 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
2818 #define RG_AUDPREAMPLGAIN_MASK 0x7
2819 #define RG_AUDPREAMPLGAIN_MASK_SFT (0x7 << 8)
2821 #define RG_BULKL_VCM_EN_MASK 0x1
2822 #define RG_BULKL_VCM_EN_MASK_SFT (0x1 << 11)
2824 #define RG_AUDADCLPWRUP_MASK 0x1
2825 #define RG_AUDADCLPWRUP_MASK_SFT (0x1 << 12)
2827 #define RG_AUDADCLINPUTSEL_MASK 0x3
2828 #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
2831 #define RG_AUDPREAMPRON_SFT 0
2832 #define RG_AUDPREAMPRON_MASK 0x1
2833 #define RG_AUDPREAMPRON_MASK_SFT (0x1 << 0)
2835 #define RG_AUDPREAMPRDCCEN_MASK 0x1
2836 #define RG_AUDPREAMPRDCCEN_MASK_SFT (0x1 << 1)
2838 #define RG_AUDPREAMPRDCPRECHARGE_MASK 0x1
2839 #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT (0x1 << 2)
2841 #define RG_AUDPREAMPRPGATEST_MASK 0x1
2842 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
2844 #define RG_AUDPREAMPRVSCALE_MASK 0x3
2845 #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
2847 #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
2848 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
2850 #define RG_AUDPREAMPRGAIN_MASK 0x7
2851 #define RG_AUDPREAMPRGAIN_MASK_SFT (0x7 << 8)
2853 #define RG_BULKR_VCM_EN_MASK 0x1
2854 #define RG_BULKR_VCM_EN_MASK_SFT (0x1 << 11)
2856 #define RG_AUDADCRPWRUP_MASK 0x1
2857 #define RG_AUDADCRPWRUP_MASK_SFT (0x1 << 12)
2859 #define RG_AUDADCRINPUTSEL_MASK 0x3
2860 #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
2863 #define RG_AUDPREAMP3ON_SFT 0
2864 #define RG_AUDPREAMP3ON_MASK 0x1
2865 #define RG_AUDPREAMP3ON_MASK_SFT (0x1 << 0)
2867 #define RG_AUDPREAMP3DCCEN_MASK 0x1
2868 #define RG_AUDPREAMP3DCCEN_MASK_SFT (0x1 << 1)
2870 #define RG_AUDPREAMP3DCPRECHARGE_MASK 0x1
2871 #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT (0x1 << 2)
2873 #define RG_AUDPREAMP3PGATEST_MASK 0x1
2874 #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
2876 #define RG_AUDPREAMP3VSCALE_MASK 0x3
2877 #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)
2879 #define RG_AUDPREAMP3INPUTSEL_MASK 0x3
2880 #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)
2882 #define RG_AUDPREAMP3GAIN_MASK 0x7
2883 #define RG_AUDPREAMP3GAIN_MASK_SFT (0x7 << 8)
2885 #define RG_BULK3_VCM_EN_MASK 0x1
2886 #define RG_BULK3_VCM_EN_MASK_SFT (0x1 << 11)
2888 #define RG_AUDADC3PWRUP_MASK 0x1
2889 #define RG_AUDADC3PWRUP_MASK_SFT (0x1 << 12)
2891 #define RG_AUDADC3INPUTSEL_MASK 0x3
2892 #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)
2895 #define RG_AUDULHALFBIAS_SFT 0
2896 #define RG_AUDULHALFBIAS_MASK 0x1
2897 #define RG_AUDULHALFBIAS_MASK_SFT (0x1 << 0)
2899 #define RG_AUDGLBVOWLPWEN_MASK 0x1
2900 #define RG_AUDGLBVOWLPWEN_MASK_SFT (0x1 << 1)
2902 #define RG_AUDPREAMPLPEN_MASK 0x1
2903 #define RG_AUDPREAMPLPEN_MASK_SFT (0x1 << 2)
2905 #define RG_AUDADC1STSTAGELPEN_MASK 0x1
2906 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2908 #define RG_AUDADC2NDSTAGELPEN_MASK 0x1
2909 #define RG_AUDADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
2911 #define RG_AUDADCFLASHLPEN_MASK 0x1
2912 #define RG_AUDADCFLASHLPEN_MASK_SFT (0x1 << 5)
2914 #define RG_AUDPREAMPIDDTEST_MASK 0x3
2915 #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
2917 #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
2918 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
2920 #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
2921 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
2923 #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
2924 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
2926 #define RG_AUDADCFLASHIDDTEST_MASK 0x3
2927 #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
2930 #define RG_AUDRULHALFBIAS_SFT 0
2931 #define RG_AUDRULHALFBIAS_MASK 0x1
2932 #define RG_AUDRULHALFBIAS_MASK_SFT (0x1 << 0)
2934 #define RG_AUDGLBRVOWLPWEN_MASK 0x1
2935 #define RG_AUDGLBRVOWLPWEN_MASK_SFT (0x1 << 1)
2937 #define RG_AUDRPREAMPLPEN_MASK 0x1
2938 #define RG_AUDRPREAMPLPEN_MASK_SFT (0x1 << 2)
2940 #define RG_AUDRADC1STSTAGELPEN_MASK 0x1
2941 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
2943 #define RG_AUDRADC2NDSTAGELPEN_MASK 0x1
2944 #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT (0x1 << 4)
2946 #define RG_AUDRADCFLASHLPEN_MASK 0x1
2947 #define RG_AUDRADCFLASHLPEN_MASK_SFT (0x1 << 5)
2949 #define RG_AUDRPREAMPIDDTEST_MASK 0x3
2950 #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)
2952 #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3
2953 #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
2955 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3
2956 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
2958 #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3
2959 #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
2961 #define RG_AUDRADCFLASHIDDTEST_MASK 0x3
2962 #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
2965 #define RG_AUDADCCLKRSTB_SFT 0
2966 #define RG_AUDADCCLKRSTB_MASK 0x1
2967 #define RG_AUDADCCLKRSTB_MASK_SFT (0x1 << 0)
2969 #define RG_AUDADCCLKSEL_MASK 0x3
2970 #define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)
2972 #define RG_AUDADCCLKSOURCE_MASK 0x3
2973 #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)
2975 #define RG_AUDADCCLKGENMODE_MASK 0x3
2976 #define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)
2978 #define RG_AUDPREAMP_ACCFS_MASK 0x1
2979 #define RG_AUDPREAMP_ACCFS_MASK_SFT (0x1 << 7)
2981 #define RG_AUDPREAMPAAFEN_MASK 0x1
2982 #define RG_AUDPREAMPAAFEN_MASK_SFT (0x1 << 8)
2984 #define RG_DCCVCMBUFLPMODSEL_MASK 0x1
2985 #define RG_DCCVCMBUFLPMODSEL_MASK_SFT (0x1 << 9)
2987 #define RG_DCCVCMBUFLPSWEN_MASK 0x1
2988 #define RG_DCCVCMBUFLPSWEN_MASK_SFT (0x1 << 10)
2990 #define RG_AUDSPAREPGA_MASK 0x1f
2991 #define RG_AUDSPAREPGA_MASK_SFT (0x1f << 11)
2994 #define RG_AUDADC1STSTAGESDENB_SFT 0
2995 #define RG_AUDADC1STSTAGESDENB_MASK 0x1
2996 #define RG_AUDADC1STSTAGESDENB_MASK_SFT (0x1 << 0)
2998 #define RG_AUDADC2NDSTAGERESET_MASK 0x1
2999 #define RG_AUDADC2NDSTAGERESET_MASK_SFT (0x1 << 1)
3001 #define RG_AUDADC3RDSTAGERESET_MASK 0x1
3002 #define RG_AUDADC3RDSTAGERESET_MASK_SFT (0x1 << 2)
3004 #define RG_AUDADCFSRESET_MASK 0x1
3005 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
3007 #define RG_AUDADCWIDECM_MASK 0x1
3008 #define RG_AUDADCWIDECM_MASK_SFT (0x1 << 4)
3010 #define RG_AUDADCNOPATEST_MASK 0x1
3011 #define RG_AUDADCNOPATEST_MASK_SFT (0x1 << 5)
3013 #define RG_AUDADCBYPASS_MASK 0x1
3014 #define RG_AUDADCBYPASS_MASK_SFT (0x1 << 6)
3016 #define RG_AUDADCFFBYPASS_MASK 0x1
3017 #define RG_AUDADCFFBYPASS_MASK_SFT (0x1 << 7)
3019 #define RG_AUDADCDACFBCURRENT_MASK 0x1
3020 #define RG_AUDADCDACFBCURRENT_MASK_SFT (0x1 << 8)
3022 #define RG_AUDADCDACIDDTEST_MASK 0x3
3023 #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
3025 #define RG_AUDADCDACNRZ_MASK 0x1
3026 #define RG_AUDADCDACNRZ_MASK_SFT (0x1 << 11)
3028 #define RG_AUDADCNODEM_MASK 0x1
3029 #define RG_AUDADCNODEM_MASK_SFT (0x1 << 12)
3031 #define RG_AUDADCDACTEST_MASK 0x1
3032 #define RG_AUDADCDACTEST_MASK_SFT (0x1 << 13)
3034 #define RG_AUDADCDAC0P25FS_MASK 0x1
3035 #define RG_AUDADCDAC0P25FS_MASK_SFT (0x1 << 14)
3037 #define RG_AUDADCRDAC0P25FS_MASK 0x1
3038 #define RG_AUDADCRDAC0P25FS_MASK_SFT (0x1 << 15)
3041 #define RG_AUDADCTESTDATA_SFT 0
3042 #define RG_AUDADCTESTDATA_MASK 0xffff
3043 #define RG_AUDADCTESTDATA_MASK_SFT (0xffff << 0)
3046 #define RG_AUDRCTUNEL_SFT 0
3047 #define RG_AUDRCTUNEL_MASK 0x1f
3048 #define RG_AUDRCTUNEL_MASK_SFT (0x1f << 0)
3050 #define RG_AUDRCTUNELSEL_MASK 0x1
3051 #define RG_AUDRCTUNELSEL_MASK_SFT (0x1 << 5)
3053 #define RG_AUDRCTUNER_MASK 0x1f
3054 #define RG_AUDRCTUNER_MASK_SFT (0x1f << 8)
3056 #define RG_AUDRCTUNERSEL_MASK 0x1
3057 #define RG_AUDRCTUNERSEL_MASK_SFT (0x1 << 13)
3060 #define RG_AUD3CTUNEL_SFT 0
3061 #define RG_AUD3CTUNEL_MASK 0x1f
3062 #define RG_AUD3CTUNEL_MASK_SFT (0x1f << 0)
3064 #define RG_AUD3CTUNELSEL_MASK 0x1
3065 #define RG_AUD3CTUNELSEL_MASK_SFT (0x1 << 5)
3067 #define RGS_AUDRCTUNE3READ_MASK 0x1f
3068 #define RGS_AUDRCTUNE3READ_MASK_SFT (0x1f << 6)
3070 #define RG_AUD3SPARE_MASK 0x1f
3071 #define RG_AUD3SPARE_MASK_SFT (0x1f << 11)
3074 #define RGS_AUDRCTUNELREAD_SFT 0
3075 #define RGS_AUDRCTUNELREAD_MASK 0x1f
3076 #define RGS_AUDRCTUNELREAD_MASK_SFT (0x1f << 0)
3078 #define RGS_AUDRCTUNERREAD_MASK 0x1f
3079 #define RGS_AUDRCTUNERREAD_MASK_SFT (0x1f << 8)
3082 #define RG_AUDSPAREVA30_SFT 0
3083 #define RG_AUDSPAREVA30_MASK 0xff
3084 #define RG_AUDSPAREVA30_MASK_SFT (0xff << 0)
3086 #define RG_AUDSPAREVA18_MASK 0xff
3087 #define RG_AUDSPAREVA18_MASK_SFT (0xff << 8)
3090 #define RG_AUDPGA_DECAP_SFT 0
3091 #define RG_AUDPGA_DECAP_MASK 0x1
3092 #define RG_AUDPGA_DECAP_MASK_SFT (0x1 << 0)
3094 #define RG_AUDPGA_CAPRA_MASK 0x1
3095 #define RG_AUDPGA_CAPRA_MASK_SFT (0x1 << 1)
3097 #define RG_AUDPGA_ACCCMP_MASK 0x1
3098 #define RG_AUDPGA_ACCCMP_MASK_SFT (0x1 << 2)
3100 #define RG_AUDENC_SPARE2_MASK 0x1fff
3101 #define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)
3104 #define RG_AUDDIGMICEN_SFT 0
3105 #define RG_AUDDIGMICEN_MASK 0x1
3106 #define RG_AUDDIGMICEN_MASK_SFT (0x1 << 0)
3108 #define RG_AUDDIGMICBIAS_MASK 0x3
3109 #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
3111 #define RG_DMICHPCLKEN_MASK 0x1
3112 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
3114 #define RG_AUDDIGMICPDUTY_MASK 0x3
3115 #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
3117 #define RG_AUDDIGMICNDUTY_MASK 0x3
3118 #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
3120 #define RG_DMICMONEN_MASK 0x1
3121 #define RG_DMICMONEN_MASK_SFT (0x1 << 8)
3123 #define RG_DMICMONSEL_MASK 0x7
3124 #define RG_DMICMONSEL_MASK_SFT (0x7 << 9)
3127 #define RG_AUDDIGMIC1EN_SFT 0
3128 #define RG_AUDDIGMIC1EN_MASK 0x1
3129 #define RG_AUDDIGMIC1EN_MASK_SFT (0x1 << 0)
3131 #define RG_AUDDIGMICBIAS1_MASK 0x3
3132 #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)
3134 #define RG_DMIC1HPCLKEN_MASK 0x1
3135 #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
3137 #define RG_AUDDIGMIC1PDUTY_MASK 0x3
3138 #define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)
3140 #define RG_AUDDIGMIC1NDUTY_MASK 0x3
3141 #define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)
3143 #define RG_DMIC1MONEN_MASK 0x1
3144 #define RG_DMIC1MONEN_MASK_SFT (0x1 << 8)
3146 #define RG_DMIC1MONSEL_MASK 0x7
3147 #define RG_DMIC1MONSEL_MASK_SFT (0x7 << 9)
3149 #define RG_AUDSPAREVMIC_MASK 0xf
3150 #define RG_AUDSPAREVMIC_MASK_SFT (0xf << 12)
3153 #define RG_AUDPWDBMICBIAS0_SFT 0
3154 #define RG_AUDPWDBMICBIAS0_MASK 0x1
3155 #define RG_AUDPWDBMICBIAS0_MASK_SFT (0x1 << 0)
3157 #define RG_AUDMICBIAS0BYPASSEN_MASK 0x1
3158 #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT (0x1 << 1)
3160 #define RG_AUDMICBIAS0LOWPEN_MASK 0x1
3161 #define RG_AUDMICBIAS0LOWPEN_MASK_SFT (0x1 << 2)
3163 #define RG_AUDPWDBMICBIAS3_MASK 0x1
3164 #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
3166 #define RG_AUDMICBIAS0VREF_MASK 0x7
3167 #define RG_AUDMICBIAS0VREF_MASK_SFT (0x7 << 4)
3169 #define RG_AUDMICBIAS0DCSW0P1EN_MASK 0x1
3170 #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT (0x1 << 8)
3172 #define RG_AUDMICBIAS0DCSW0P2EN_MASK 0x1
3173 #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT (0x1 << 9)
3175 #define RG_AUDMICBIAS0DCSW0NEN_MASK 0x1
3176 #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT (0x1 << 10)
3178 #define RG_AUDMICBIAS0DCSW2P1EN_MASK 0x1
3179 #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT (0x1 << 12)
3181 #define RG_AUDMICBIAS0DCSW2P2EN_MASK 0x1
3182 #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT (0x1 << 13)
3184 #define RG_AUDMICBIAS0DCSW2NEN_MASK 0x1
3185 #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT (0x1 << 14)
3188 #define RG_AUDPWDBMICBIAS1_SFT 0
3189 #define RG_AUDPWDBMICBIAS1_MASK 0x1
3190 #define RG_AUDPWDBMICBIAS1_MASK_SFT (0x1 << 0)
3192 #define RG_AUDMICBIAS1BYPASSEN_MASK 0x1
3193 #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT (0x1 << 1)
3195 #define RG_AUDMICBIAS1LOWPEN_MASK 0x1
3196 #define RG_AUDMICBIAS1LOWPEN_MASK_SFT (0x1 << 2)
3198 #define RG_AUDMICBIAS1VREF_MASK 0x7
3199 #define RG_AUDMICBIAS1VREF_MASK_SFT (0x7 << 4)
3201 #define RG_AUDMICBIAS1DCSW1PEN_MASK 0x1
3202 #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT (0x1 << 8)
3204 #define RG_AUDMICBIAS1DCSW1NEN_MASK 0x1
3205 #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT (0x1 << 9)
3207 #define RG_BANDGAPGEN_MASK 0x1
3208 #define RG_BANDGAPGEN_MASK_SFT (0x1 << 10)
3210 #define RG_AUDMICBIAS1HVEN_MASK 0x1
3211 #define RG_AUDMICBIAS1HVEN_MASK_SFT (0x1 << 12)
3213 #define RG_AUDMICBIAS1HVVREF_MASK 0x1
3214 #define RG_AUDMICBIAS1HVVREF_MASK_SFT (0x1 << 13)
3217 #define RG_AUDPWDBMICBIAS2_SFT 0
3218 #define RG_AUDPWDBMICBIAS2_MASK 0x1
3219 #define RG_AUDPWDBMICBIAS2_MASK_SFT (0x1 << 0)
3221 #define RG_AUDMICBIAS2BYPASSEN_MASK 0x1
3222 #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT (0x1 << 1)
3224 #define RG_AUDMICBIAS2LOWPEN_MASK 0x1
3225 #define RG_AUDMICBIAS2LOWPEN_MASK_SFT (0x1 << 2)
3227 #define RG_AUDMICBIAS2VREF_MASK 0x7
3228 #define RG_AUDMICBIAS2VREF_MASK_SFT (0x7 << 4)
3230 #define RG_AUDMICBIAS2DCSW3P1EN_MASK 0x1
3231 #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT (0x1 << 8)
3233 #define RG_AUDMICBIAS2DCSW3P2EN_MASK 0x1
3234 #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT (0x1 << 9)
3236 #define RG_AUDMICBIAS2DCSW3NEN_MASK 0x1
3237 #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT (0x1 << 10)
3239 #define RG_AUDMICBIASSPARE_MASK 0xf
3240 #define RG_AUDMICBIASSPARE_MASK_SFT (0xf << 12)
3243 #define RG_AUDACCDETMICBIAS0PULLLOW_SFT 0
3244 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
3245 #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT (0x1 << 0)
3247 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
3248 #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT (0x1 << 1)
3250 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK 0x1
3251 #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT (0x1 << 2)
3253 #define RG_AUDACCDETVIN1PULLLOW_MASK 0x1
3254 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
3256 #define RG_AUDACCDETVTHACAL_MASK 0x1
3257 #define RG_AUDACCDETVTHACAL_MASK_SFT (0x1 << 4)
3259 #define RG_AUDACCDETVTHBCAL_MASK 0x1
3260 #define RG_AUDACCDETVTHBCAL_MASK_SFT (0x1 << 5)
3262 #define RG_AUDACCDETTVDET_MASK 0x1
3263 #define RG_AUDACCDETTVDET_MASK_SFT (0x1 << 6)
3265 #define RG_ACCDETSEL_MASK 0x1
3266 #define RG_ACCDETSEL_MASK_SFT (0x1 << 7)
3268 #define RG_SWBUFMODSEL_MASK 0x1
3269 #define RG_SWBUFMODSEL_MASK_SFT (0x1 << 8)
3271 #define RG_SWBUFSWEN_MASK 0x1
3272 #define RG_SWBUFSWEN_MASK_SFT (0x1 << 9)
3274 #define RG_EINT0NOHYS_MASK 0x1
3275 #define RG_EINT0NOHYS_MASK_SFT (0x1 << 10)
3277 #define RG_EINT0CONFIGACCDET_MASK 0x1
3278 #define RG_EINT0CONFIGACCDET_MASK_SFT (0x1 << 11)
3280 #define RG_EINT0HIRENB_MASK 0x1
3281 #define RG_EINT0HIRENB_MASK_SFT (0x1 << 12)
3283 #define RG_ACCDET2AUXRESBYPASS_MASK 0x1
3284 #define RG_ACCDET2AUXRESBYPASS_MASK_SFT (0x1 << 13)
3286 #define RG_ACCDET2AUXSWEN_MASK 0x1
3287 #define RG_ACCDET2AUXSWEN_MASK_SFT (0x1 << 14)
3289 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK 0x1
3290 #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT (0x1 << 15)
3293 #define RG_EINT1CONFIGACCDET_SFT 0
3294 #define RG_EINT1CONFIGACCDET_MASK 0x1
3295 #define RG_EINT1CONFIGACCDET_MASK_SFT (0x1 << 0)
3297 #define RG_EINT1HIRENB_MASK 0x1
3298 #define RG_EINT1HIRENB_MASK_SFT (0x1 << 1)
3300 #define RG_EINT1NOHYS_MASK 0x1
3301 #define RG_EINT1NOHYS_MASK_SFT (0x1 << 2)
3303 #define RG_EINTCOMPVTH_MASK 0xf
3304 #define RG_EINTCOMPVTH_MASK_SFT (0xf << 4)
3306 #define RG_MTEST_EN_MASK 0x1
3307 #define RG_MTEST_EN_MASK_SFT (0x1 << 8)
3309 #define RG_MTEST_SEL_MASK 0x1
3310 #define RG_MTEST_SEL_MASK_SFT (0x1 << 9)
3312 #define RG_MTEST_CURRENT_MASK 0x1
3313 #define RG_MTEST_CURRENT_MASK_SFT (0x1 << 10)
3315 #define RG_ANALOGFDEN_MASK 0x1
3316 #define RG_ANALOGFDEN_MASK_SFT (0x1 << 12)
3318 #define RG_FDVIN1PPULLLOW_MASK 0x1
3319 #define RG_FDVIN1PPULLLOW_MASK_SFT (0x1 << 13)
3321 #define RG_FDEINT0TYPE_MASK 0x1
3322 #define RG_FDEINT0TYPE_MASK_SFT (0x1 << 14)
3324 #define RG_FDEINT1TYPE_MASK 0x1
3325 #define RG_FDEINT1TYPE_MASK_SFT (0x1 << 15)
3328 #define RG_EINT0CMPEN_SFT 0
3329 #define RG_EINT0CMPEN_MASK 0x1
3330 #define RG_EINT0CMPEN_MASK_SFT (0x1 << 0)
3332 #define RG_EINT0CMPMEN_MASK 0x1
3333 #define RG_EINT0CMPMEN_MASK_SFT (0x1 << 1)
3335 #define RG_EINT0EN_MASK 0x1
3336 #define RG_EINT0EN_MASK_SFT (0x1 << 2)
3338 #define RG_EINT0CEN_MASK 0x1
3339 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
3341 #define RG_EINT0INVEN_MASK 0x1
3342 #define RG_EINT0INVEN_MASK_SFT (0x1 << 4)
3344 #define RG_EINT0CTURBO_MASK 0x7
3345 #define RG_EINT0CTURBO_MASK_SFT (0x7 << 5)
3347 #define RG_EINT1CMPEN_MASK 0x1
3348 #define RG_EINT1CMPEN_MASK_SFT (0x1 << 8)
3350 #define RG_EINT1CMPMEN_MASK 0x1
3351 #define RG_EINT1CMPMEN_MASK_SFT (0x1 << 9)
3353 #define RG_EINT1EN_MASK 0x1
3354 #define RG_EINT1EN_MASK_SFT (0x1 << 10)
3356 #define RG_EINT1CEN_MASK 0x1
3357 #define RG_EINT1CEN_MASK_SFT (0x1 << 11)
3359 #define RG_EINT1INVEN_MASK 0x1
3360 #define RG_EINT1INVEN_MASK_SFT (0x1 << 12)
3362 #define RG_EINT1CTURBO_MASK 0x7
3363 #define RG_EINT1CTURBO_MASK_SFT (0x7 << 13)
3366 #define RG_ACCDETSPARE_SFT 0
3367 #define RG_ACCDETSPARE_MASK 0xffff
3368 #define RG_ACCDETSPARE_MASK_SFT (0xffff << 0)
3371 #define RG_AUDENCSPAREVA30_SFT 0
3372 #define RG_AUDENCSPAREVA30_MASK 0xff
3373 #define RG_AUDENCSPAREVA30_MASK_SFT (0xff << 0)
3375 #define RG_AUDENCSPAREVA18_MASK 0xff
3376 #define RG_AUDENCSPAREVA18_MASK_SFT (0xff << 8)
3379 #define RG_CLKSQ_EN_SFT 0
3380 #define RG_CLKSQ_EN_MASK 0x1
3381 #define RG_CLKSQ_EN_MASK_SFT (0x1 << 0)
3383 #define RG_CLKSQ_IN_SEL_TEST_MASK 0x1
3384 #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT (0x1 << 1)
3386 #define RG_CM_REFGENSEL_MASK 0x1
3387 #define RG_CM_REFGENSEL_MASK_SFT (0x1 << 2)
3389 #define RG_AUDIO_VOW_EN_MASK 0x1
3390 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
3392 #define RG_CLKSQ_EN_VOW_MASK 0x1
3393 #define RG_CLKSQ_EN_VOW_MASK_SFT (0x1 << 4)
3395 #define RG_CLKAND_EN_VOW_MASK 0x1
3396 #define RG_CLKAND_EN_VOW_MASK_SFT (0x1 << 5)
3398 #define RG_VOWCLK_SEL_EN_VOW_MASK 0x1
3399 #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT (0x1 << 6)
3401 #define RG_SPARE_VOW_MASK 0x7
3402 #define RG_SPARE_VOW_MASK_SFT (0x7 << 7)
3405 #define RG_AUDDACLPWRUP_VAUDP32_SFT 0
3406 #define RG_AUDDACLPWRUP_VAUDP32_MASK 0x1
3407 #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3409 #define RG_AUDDACRPWRUP_VAUDP32_MASK 0x1
3410 #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
3412 #define RG_AUD_DAC_PWR_UP_VA32_MASK 0x1
3413 #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT (0x1 << 2)
3415 #define RG_AUD_DAC_PWL_UP_VA32_MASK 0x1
3416 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
3418 #define RG_AUDHPLPWRUP_VAUDP32_MASK 0x1
3419 #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT (0x1 << 4)
3421 #define RG_AUDHPRPWRUP_VAUDP32_MASK 0x1
3422 #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT (0x1 << 5)
3424 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK 0x1
3425 #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 6)
3427 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK 0x1
3428 #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 7)
3430 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x3
3431 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)
3433 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x3
3434 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)
3436 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK 0x1
3437 #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 12)
3439 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK 0x1
3440 #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT (0x1 << 13)
3442 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK 0x1
3443 #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 14)
3445 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK 0x1
3446 #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 15)
3449 #define RG_AUDHPLOUTPWRUP_VAUDP32_SFT 0
3450 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK 0x1
3451 #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3453 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK 0x1
3454 #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT (0x1 << 1)
3456 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK 0x1
3457 #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 2)
3459 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK 0x1
3460 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
3462 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK 0x1
3463 #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 4)
3465 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK 0x1
3466 #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT (0x1 << 5)
3468 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK 0x1
3469 #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT (0x1 << 6)
3471 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK 0x1
3472 #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT (0x1 << 7)
3474 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK 0x7
3475 #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 8)
3477 #define RG_HPROUTSTGCTRL_VAUDP32_MASK 0x7
3478 #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT (0x7 << 12)
3481 #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT 0
3482 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK 0x7
3483 #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 0)
3485 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK 0x7
3486 #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT (0x7 << 4)
3488 #define RG_AUDHPSTARTUP_VAUDP32_MASK 0x1
3489 #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT (0x1 << 7)
3491 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK 0x1
3492 #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT (0x1 << 8)
3494 #define RG_HPINPUTSTBENH_VAUDP32_MASK 0x1
3495 #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 9)
3497 #define RG_HPINPUTRESET0_VAUDP32_MASK 0x1
3498 #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3500 #define RG_HPOUTPUTRESET0_VAUDP32_MASK 0x1
3501 #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 11)
3503 #define RG_HPPSHORT2VCM_VAUDP32_MASK 0x7
3504 #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT (0x7 << 12)
3506 #define RG_AUDHPTRIM_EN_VAUDP32_MASK 0x1
3507 #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT (0x1 << 15)
3510 #define RG_AUDHPLTRIM_VAUDP32_SFT 0
3511 #define RG_AUDHPLTRIM_VAUDP32_MASK 0x1f
3512 #define RG_AUDHPLTRIM_VAUDP32_MASK_SFT (0x1f << 0)
3514 #define RG_AUDHPLFINETRIM_VAUDP32_MASK 0x7
3515 #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT (0x7 << 5)
3517 #define RG_AUDHPRTRIM_VAUDP32_MASK 0x1f
3518 #define RG_AUDHPRTRIM_VAUDP32_MASK_SFT (0x1f << 8)
3520 #define RG_AUDHPRFINETRIM_VAUDP32_MASK 0x7
3521 #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT (0x7 << 13)
3524 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT 0
3525 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK 0x7
3526 #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT (0x7 << 0)
3528 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK 0x7
3529 #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 4)
3531 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK 0x7
3532 #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT (0x7 << 8)
3534 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x3
3535 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)
3537 #define RG_AUDHPCOMP_EN_VAUDP32_MASK 0x1
3538 #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT (0x1 << 15)
3541 #define RG_AUDHPDECMGAINADJ_VAUDP32_SFT 0
3542 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK 0x7
3543 #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT (0x7 << 0)
3545 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK 0x7
3546 #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT (0x7 << 4)
3549 #define RG_AUDHSPWRUP_VAUDP32_SFT 0
3550 #define RG_AUDHSPWRUP_VAUDP32_MASK 0x1
3551 #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3553 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK 0x1
3554 #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
3556 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x3
3557 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
3559 #define RG_AUDHSSCDISABLE_VAUDP32_MASK 0x1
3560 #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
3562 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK 0x1
3563 #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
3565 #define RG_AUDHSSTARTUP_VAUDP32_MASK 0x1
3566 #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
3568 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK 0x1
3569 #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
3571 #define RG_HSINPUTSTBENH_VAUDP32_MASK 0x1
3572 #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
3574 #define RG_HSINPUTRESET0_VAUDP32_MASK 0x1
3575 #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
3577 #define RG_HSOUTPUTRESET0_VAUDP32_MASK 0x1
3578 #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3580 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK 0x1
3581 #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
3584 #define RG_AUDLOLPWRUP_VAUDP32_SFT 0
3585 #define RG_AUDLOLPWRUP_VAUDP32_MASK 0x1
3586 #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT (0x1 << 0)
3588 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK 0x1
3589 #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT (0x1 << 1)
3591 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x3
3592 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
3594 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK 0x1
3595 #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT (0x1 << 4)
3597 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK 0x1
3598 #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT (0x1 << 5)
3600 #define RG_AUDLOSTARTUP_VAUDP32_MASK 0x1
3601 #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT (0x1 << 6)
3603 #define RG_LOINPUTSTBENH_VAUDP32_MASK 0x1
3604 #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 7)
3606 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK 0x1
3607 #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT (0x1 << 8)
3609 #define RG_LOINPUTRESET0_VAUDP32_MASK 0x1
3610 #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT (0x1 << 9)
3612 #define RG_LOOUTPUTRESET0_VAUDP32_MASK 0x1
3613 #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT (0x1 << 10)
3615 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK 0x1
3616 #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT (0x1 << 11)
3618 #define RG_AUDDACTPWRUP_VAUDP32_MASK 0x1
3619 #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT (0x1 << 12)
3621 #define RG_AUD_DAC_PWT_UP_VA32_MASK 0x1
3622 #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT (0x1 << 13)
3625 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT 0
3626 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK 0xf
3627 #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT (0xf << 0)
3629 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x3
3630 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)
3632 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK 0x1
3633 #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT (0x1 << 6)
3635 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x3
3636 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)
3638 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x3
3639 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)
3641 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK 0x1
3642 #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT (0x1 << 12)
3645 #define RG_ABIDEC_RSVD0_VA32_SFT 0
3646 #define RG_ABIDEC_RSVD0_VA32_MASK 0xff
3647 #define RG_ABIDEC_RSVD0_VA32_MASK_SFT (0xff << 0)
3649 #define RG_ABIDEC_RSVD0_VAUDP32_MASK 0xff
3650 #define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT (0xff << 8)
3653 #define RG_ABIDEC_RSVD1_VAUDP32_SFT 0
3654 #define RG_ABIDEC_RSVD1_VAUDP32_MASK 0xff
3655 #define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT (0xff << 0)
3657 #define RG_ABIDEC_RSVD2_VAUDP32_MASK 0xff
3658 #define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT (0xff << 8)
3661 #define RG_AUDZCDMUXSEL_VAUDP32_SFT 0
3662 #define RG_AUDZCDMUXSEL_VAUDP32_MASK 0x7
3663 #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT (0x7 << 0)
3665 #define RG_AUDZCDCLKSEL_VAUDP32_MASK 0x1
3666 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
3668 #define RG_AUDBIASADJ_0_VAUDP32_MASK 0x1ff
3669 #define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT (0x1ff << 7)
3672 #define RG_AUDBIASADJ_1_VAUDP32_SFT 0
3673 #define RG_AUDBIASADJ_1_VAUDP32_MASK 0xff
3674 #define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT (0xff << 0)
3676 #define RG_AUDIBIASPWRDN_VAUDP32_MASK 0x1
3677 #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT (0x1 << 8)
3680 #define RG_RSTB_DECODER_VA32_SFT 0
3681 #define RG_RSTB_DECODER_VA32_MASK 0x1
3682 #define RG_RSTB_DECODER_VA32_MASK_SFT (0x1 << 0)
3684 #define RG_SEL_DECODER_96K_VA32_MASK 0x1
3685 #define RG_SEL_DECODER_96K_VA32_MASK_SFT (0x1 << 1)
3687 #define RG_SEL_DELAY_VCORE_MASK 0x1
3688 #define RG_SEL_DELAY_VCORE_MASK_SFT (0x1 << 2)
3690 #define RG_AUDGLB_PWRDN_VA32_MASK 0x1
3691 #define RG_AUDGLB_PWRDN_VA32_MASK_SFT (0x1 << 4)
3693 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK 0x1
3694 #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT (0x1 << 5)
3696 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK 0x1
3697 #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT (0x1 << 6)
3700 #define RG_LCLDO_DEC_EN_VA32_SFT 0
3701 #define RG_LCLDO_DEC_EN_VA32_MASK 0x1
3702 #define RG_LCLDO_DEC_EN_VA32_MASK_SFT (0x1 << 0)
3704 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK 0x1
3705 #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT (0x1 << 1)
3707 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK 0x1
3708 #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT (0x1 << 2)
3710 #define RG_NVREG_EN_VAUDP32_MASK 0x1
3711 #define RG_NVREG_EN_VAUDP32_MASK_SFT (0x1 << 4)
3713 #define RG_NVREG_PULL0V_VAUDP32_MASK 0x1
3714 #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT (0x1 << 5)
3716 #define RG_AUDPMU_RSVD_VA18_MASK 0xff
3717 #define RG_AUDPMU_RSVD_VA18_MASK_SFT (0xff << 8)
3720 #define RG_AUDZCDENABLE_SFT 0
3721 #define RG_AUDZCDENABLE_MASK 0x1
3722 #define RG_AUDZCDENABLE_MASK_SFT (0x1 << 0)
3724 #define RG_AUDZCDGAINSTEPTIME_MASK 0x7
3725 #define RG_AUDZCDGAINSTEPTIME_MASK_SFT (0x7 << 1)
3727 #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
3728 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
3730 #define RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
3731 #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT (0x1 << 6)
3734 #define RG_AUDLOLGAIN_SFT 0
3735 #define RG_AUDLOLGAIN_MASK 0x1f
3736 #define RG_AUDLOLGAIN_MASK_SFT (0x1f << 0)
3738 #define RG_AUDLORGAIN_MASK 0x1f
3739 #define RG_AUDLORGAIN_MASK_SFT (0x1f << 7)
3742 #define RG_AUDHPLGAIN_SFT 0
3743 #define RG_AUDHPLGAIN_MASK 0x1f
3744 #define RG_AUDHPLGAIN_MASK_SFT (0x1f << 0)
3746 #define RG_AUDHPRGAIN_MASK 0x1f
3747 #define RG_AUDHPRGAIN_MASK_SFT (0x1f << 7)
3750 #define RG_AUDHSGAIN_SFT 0
3751 #define RG_AUDHSGAIN_MASK 0x1f
3752 #define RG_AUDHSGAIN_MASK_SFT (0x1f << 0)
3755 #define RG_AUDIVLGAIN_SFT 0
3756 #define RG_AUDIVLGAIN_MASK 0x7
3757 #define RG_AUDIVLGAIN_MASK_SFT (0x7 << 0)
3759 #define RG_AUDIVRGAIN_MASK 0x7
3760 #define RG_AUDIVRGAIN_MASK_SFT (0x7 << 8)
3763 #define RG_AUDINTGAIN1_SFT 0
3764 #define RG_AUDINTGAIN1_MASK 0x3f
3765 #define RG_AUDINTGAIN1_MASK_SFT (0x3f << 0)
3767 #define RG_AUDINTGAIN2_MASK 0x3f
3768 #define RG_AUDINTGAIN2_MASK_SFT (0x3f << 8)
3771 #define MT6359_GPIO_DIR0 0x88
3772 #define MT6359_GPIO_DIR0_SET 0x8a
3773 #define MT6359_GPIO_DIR0_CLR 0x8c
3774 #define MT6359_GPIO_DIR1 0x8e
3775 #define MT6359_GPIO_DIR1_SET 0x90
3776 #define MT6359_GPIO_DIR1_CLR 0x92
3778 #define MT6359_DCXO_CW11 0x7a6
3779 #define MT6359_DCXO_CW12 0x7a8
3781 #define MT6359_GPIO_MODE0 0xcc
3782 #define MT6359_GPIO_MODE0_SET 0xce
3783 #define MT6359_GPIO_MODE0_CLR 0xd0
3784 #define MT6359_GPIO_MODE1 0xd2
3785 #define MT6359_GPIO_MODE1_SET 0xd4
3786 #define MT6359_GPIO_MODE1_CLR 0xd6
3787 #define MT6359_GPIO_MODE2 0xd8
3788 #define MT6359_GPIO_MODE2_SET 0xda
3789 #define MT6359_GPIO_MODE2_CLR 0xdc
3790 #define MT6359_GPIO_MODE3 0xde
3791 #define MT6359_GPIO_MODE3_SET 0xe0
3792 #define MT6359_GPIO_MODE3_CLR 0xe2
3793 #define MT6359_GPIO_MODE4 0xe4
3794 #define MT6359_GPIO_MODE4_SET 0xe6
3795 #define MT6359_GPIO_MODE4_CLR 0xe8
3797 #define MT6359_AUD_TOP_ID 0x2300
3798 #define MT6359_AUD_TOP_REV0 0x2302
3799 #define MT6359_AUD_TOP_DBI 0x2304
3800 #define MT6359_AUD_TOP_DXI 0x2306
3801 #define MT6359_AUD_TOP_CKPDN_TPM0 0x2308
3802 #define MT6359_AUD_TOP_CKPDN_TPM1 0x230a
3803 #define MT6359_AUD_TOP_CKPDN_CON0 0x230c
3804 #define MT6359_AUD_TOP_CKPDN_CON0_SET 0x230e
3805 #define MT6359_AUD_TOP_CKPDN_CON0_CLR 0x2310
3806 #define MT6359_AUD_TOP_CKSEL_CON0 0x2312
3807 #define MT6359_AUD_TOP_CKSEL_CON0_SET 0x2314
3808 #define MT6359_AUD_TOP_CKSEL_CON0_CLR 0x2316
3809 #define MT6359_AUD_TOP_CKTST_CON0 0x2318
3810 #define MT6359_AUD_TOP_CLK_HWEN_CON0 0x231a
3811 #define MT6359_AUD_TOP_CLK_HWEN_CON0_SET 0x231c
3812 #define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR 0x231e
3813 #define MT6359_AUD_TOP_RST_CON0 0x2320
3814 #define MT6359_AUD_TOP_RST_CON0_SET 0x2322
3815 #define MT6359_AUD_TOP_RST_CON0_CLR 0x2324
3816 #define MT6359_AUD_TOP_RST_BANK_CON0 0x2326
3817 #define MT6359_AUD_TOP_INT_CON0 0x2328
3818 #define MT6359_AUD_TOP_INT_CON0_SET 0x232a
3819 #define MT6359_AUD_TOP_INT_CON0_CLR 0x232c
3820 #define MT6359_AUD_TOP_INT_MASK_CON0 0x232e
3821 #define MT6359_AUD_TOP_INT_MASK_CON0_SET 0x2330
3822 #define MT6359_AUD_TOP_INT_MASK_CON0_CLR 0x2332
3823 #define MT6359_AUD_TOP_INT_STATUS0 0x2334
3824 #define MT6359_AUD_TOP_INT_RAW_STATUS0 0x2336
3825 #define MT6359_AUD_TOP_INT_MISC_CON0 0x2338
3826 #define MT6359_AUD_TOP_MON_CON0 0x233a
3827 #define MT6359_AUDIO_DIG_DSN_ID 0x2380
3828 #define MT6359_AUDIO_DIG_DSN_REV0 0x2382
3829 #define MT6359_AUDIO_DIG_DSN_DBI 0x2384
3830 #define MT6359_AUDIO_DIG_DSN_DXI 0x2386
3831 #define MT6359_AFE_UL_DL_CON0 0x2388
3832 #define MT6359_AFE_DL_SRC2_CON0_L 0x238a
3833 #define MT6359_AFE_UL_SRC_CON0_H 0x238c
3834 #define MT6359_AFE_UL_SRC_CON0_L 0x238e
3835 #define MT6359_AFE_ADDA6_L_SRC_CON0_H 0x2390
3836 #define MT6359_AFE_ADDA6_UL_SRC_CON0_L 0x2392
3837 #define MT6359_AFE_TOP_CON0 0x2394
3838 #define MT6359_AUDIO_TOP_CON0 0x2396
3839 #define MT6359_AFE_MON_DEBUG0 0x2398
3840 #define MT6359_AFUNC_AUD_CON0 0x239a
3841 #define MT6359_AFUNC_AUD_CON1 0x239c
3842 #define MT6359_AFUNC_AUD_CON2 0x239e
3843 #define MT6359_AFUNC_AUD_CON3 0x23a0
3844 #define MT6359_AFUNC_AUD_CON4 0x23a2
3845 #define MT6359_AFUNC_AUD_CON5 0x23a4
3846 #define MT6359_AFUNC_AUD_CON6 0x23a6
3847 #define MT6359_AFUNC_AUD_CON7 0x23a8
3848 #define MT6359_AFUNC_AUD_CON8 0x23aa
3849 #define MT6359_AFUNC_AUD_CON9 0x23ac
3850 #define MT6359_AFUNC_AUD_CON10 0x23ae
3851 #define MT6359_AFUNC_AUD_CON11 0x23b0
3852 #define MT6359_AFUNC_AUD_CON12 0x23b2
3853 #define MT6359_AFUNC_AUD_MON0 0x23b4
3854 #define MT6359_AFUNC_AUD_MON1 0x23b6
3855 #define MT6359_AUDRC_TUNE_MON0 0x23b8
3856 #define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0 0x23ba
3857 #define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1 0x23bc
3858 #define MT6359_AFE_ADDA_MTKAIF_MON0 0x23be
3859 #define MT6359_AFE_ADDA_MTKAIF_MON1 0x23c0
3860 #define MT6359_AFE_ADDA_MTKAIF_MON2 0x23c2
3861 #define MT6359_AFE_ADDA6_MTKAIF_MON3 0x23c4
3862 #define MT6359_AFE_ADDA_MTKAIF_MON4 0x23c6
3863 #define MT6359_AFE_ADDA_MTKAIF_MON5 0x23c8
3864 #define MT6359_AFE_ADDA_MTKAIF_CFG0 0x23ca
3865 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG0 0x23cc
3866 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG1 0x23ce
3867 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG2 0x23d0
3868 #define MT6359_AFE_ADDA_MTKAIF_RX_CFG3 0x23d2
3869 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0 0x23d4
3870 #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1 0x23d6
3871 #define MT6359_AFE_SGEN_CFG0 0x23d8
3872 #define MT6359_AFE_SGEN_CFG1 0x23da
3873 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG 0x23dc
3874 #define MT6359_AFE_ADC_ASYNC_FIFO_CFG1 0x23de
3875 #define MT6359_AFE_DCCLK_CFG0 0x23e0
3876 #define MT6359_AFE_DCCLK_CFG1 0x23e2
3877 #define MT6359_AUDIO_DIG_CFG 0x23e4
3878 #define MT6359_AUDIO_DIG_CFG1 0x23e6
3879 #define MT6359_AFE_AUD_PAD_TOP 0x23e8
3880 #define MT6359_AFE_AUD_PAD_TOP_MON 0x23ea
3881 #define MT6359_AFE_AUD_PAD_TOP_MON1 0x23ec
3882 #define MT6359_AFE_AUD_PAD_TOP_MON2 0x23ee
3883 #define MT6359_AFE_DL_NLE_CFG 0x23f0
3884 #define MT6359_AFE_DL_NLE_MON 0x23f2
3885 #define MT6359_AFE_CG_EN_MON 0x23f4
3886 #define MT6359_AFE_MIC_ARRAY_CFG 0x23f6
3887 #define MT6359_AFE_CHOP_CFG0 0x23f8
3888 #define MT6359_AFE_MTKAIF_MUX_CFG 0x23fa
3889 #define MT6359_AUDIO_DIG_2ND_DSN_ID 0x2400
3890 #define MT6359_AUDIO_DIG_2ND_DSN_REV0 0x2402
3891 #define MT6359_AUDIO_DIG_2ND_DSN_DBI 0x2404
3892 #define MT6359_AUDIO_DIG_2ND_DSN_DXI 0x2406
3893 #define MT6359_AFE_PMIC_NEWIF_CFG3 0x2408
3894 #define MT6359_AUDIO_DIG_3RD_DSN_ID 0x2480
3895 #define MT6359_AUDIO_DIG_3RD_DSN_REV0 0x2482
3896 #define MT6359_AUDIO_DIG_3RD_DSN_DBI 0x2484
3897 #define MT6359_AUDIO_DIG_3RD_DSN_DXI 0x2486
3898 #define MT6359_AFE_NCP_CFG0 0x24de
3899 #define MT6359_AFE_NCP_CFG1 0x24e0
3900 #define MT6359_AFE_NCP_CFG2 0x24e2
3901 #define MT6359_AUDENC_DSN_ID 0x2500
3902 #define MT6359_AUDENC_DSN_REV0 0x2502
3903 #define MT6359_AUDENC_DSN_DBI 0x2504
3904 #define MT6359_AUDENC_DSN_FPI 0x2506
3905 #define MT6359_AUDENC_ANA_CON0 0x2508
3906 #define MT6359_AUDENC_ANA_CON1 0x250a
3907 #define MT6359_AUDENC_ANA_CON2 0x250c
3908 #define MT6359_AUDENC_ANA_CON3 0x250e
3909 #define MT6359_AUDENC_ANA_CON4 0x2510
3910 #define MT6359_AUDENC_ANA_CON5 0x2512
3911 #define MT6359_AUDENC_ANA_CON6 0x2514
3912 #define MT6359_AUDENC_ANA_CON7 0x2516
3913 #define MT6359_AUDENC_ANA_CON8 0x2518
3914 #define MT6359_AUDENC_ANA_CON9 0x251a
3915 #define MT6359_AUDENC_ANA_CON10 0x251c
3916 #define MT6359_AUDENC_ANA_CON11 0x251e
3917 #define MT6359_AUDENC_ANA_CON12 0x2520
3918 #define MT6359_AUDENC_ANA_CON13 0x2522
3919 #define MT6359_AUDENC_ANA_CON14 0x2524
3920 #define MT6359_AUDENC_ANA_CON15 0x2526
3921 #define MT6359_AUDENC_ANA_CON16 0x2528
3922 #define MT6359_AUDENC_ANA_CON17 0x252a
3923 #define MT6359_AUDENC_ANA_CON18 0x252c
3924 #define MT6359_AUDENC_ANA_CON19 0x252e
3925 #define MT6359_AUDENC_ANA_CON20 0x2530
3926 #define MT6359_AUDENC_ANA_CON21 0x2532
3927 #define MT6359_AUDENC_ANA_CON22 0x2534
3928 #define MT6359_AUDENC_ANA_CON23 0x2536
3929 #define MT6359_AUDDEC_DSN_ID 0x2580
3930 #define MT6359_AUDDEC_DSN_REV0 0x2582
3931 #define MT6359_AUDDEC_DSN_DBI 0x2584
3932 #define MT6359_AUDDEC_DSN_FPI 0x2586
3933 #define MT6359_AUDDEC_ANA_CON0 0x2588
3934 #define MT6359_AUDDEC_ANA_CON1 0x258a
3935 #define MT6359_AUDDEC_ANA_CON2 0x258c
3936 #define MT6359_AUDDEC_ANA_CON3 0x258e
3937 #define MT6359_AUDDEC_ANA_CON4 0x2590
3938 #define MT6359_AUDDEC_ANA_CON5 0x2592
3939 #define MT6359_AUDDEC_ANA_CON6 0x2594
3940 #define MT6359_AUDDEC_ANA_CON7 0x2596
3941 #define MT6359_AUDDEC_ANA_CON8 0x2598
3942 #define MT6359_AUDDEC_ANA_CON9 0x259a
3943 #define MT6359_AUDDEC_ANA_CON10 0x259c
3944 #define MT6359_AUDDEC_ANA_CON11 0x259e
3945 #define MT6359_AUDDEC_ANA_CON12 0x25a0
3946 #define MT6359_AUDDEC_ANA_CON13 0x25a2
3947 #define MT6359_AUDDEC_ANA_CON14 0x25a4
3948 #define MT6359_AUDZCD_DSN_ID 0x2600
3949 #define MT6359_AUDZCD_DSN_REV0 0x2602
3950 #define MT6359_AUDZCD_DSN_DBI 0x2604
3951 #define MT6359_AUDZCD_DSN_FPI 0x2606
3952 #define MT6359_ZCD_CON0 0x2608
3953 #define MT6359_ZCD_CON1 0x260a
3954 #define MT6359_ZCD_CON2 0x260c
3955 #define MT6359_ZCD_CON3 0x260e
3956 #define MT6359_ZCD_CON4 0x2610
3957 #define MT6359_ZCD_CON5 0x2612
3958 #define MT6359_ACCDET_DSN_DIG_ID 0x2680
3959 #define MT6359_ACCDET_DSN_DIG_REV0 0x2682
3960 #define MT6359_ACCDET_DSN_DBI 0x2684
3961 #define MT6359_ACCDET_DSN_FPI 0x2686
3962 #define MT6359_ACCDET_CON0 0x2688
3963 #define MT6359_ACCDET_CON1 0x268a
3964 #define MT6359_ACCDET_CON2 0x268c
3965 #define MT6359_ACCDET_CON3 0x268e
3966 #define MT6359_ACCDET_CON4 0x2690
3967 #define MT6359_ACCDET_CON5 0x2692
3968 #define MT6359_ACCDET_CON6 0x2694
3969 #define MT6359_ACCDET_CON7 0x2696
3970 #define MT6359_ACCDET_CON8 0x2698
3971 #define MT6359_ACCDET_CON9 0x269a
3972 #define MT6359_ACCDET_CON10 0x269c
3973 #define MT6359_ACCDET_CON11 0x269e
3974 #define MT6359_ACCDET_CON12 0x26a0
3975 #define MT6359_ACCDET_CON13 0x26a2
3976 #define MT6359_ACCDET_CON14 0x26a4
3977 #define MT6359_ACCDET_CON15 0x26a6
3978 #define MT6359_ACCDET_CON16 0x26a8
3979 #define MT6359_ACCDET_CON17 0x26aa
3980 #define MT6359_ACCDET_CON18 0x26ac
3981 #define MT6359_ACCDET_CON19 0x26ae
3982 #define MT6359_ACCDET_CON20 0x26b0
3983 #define MT6359_ACCDET_CON21 0x26b2
3984 #define MT6359_ACCDET_CON22 0x26b4
3985 #define MT6359_ACCDET_CON23 0x26b6
3986 #define MT6359_ACCDET_CON24 0x26b8
3987 #define MT6359_ACCDET_CON25 0x26ba
3988 #define MT6359_ACCDET_CON26 0x26bc
3989 #define MT6359_ACCDET_CON27 0x26be
3990 #define MT6359_ACCDET_CON28 0x26c0
3991 #define MT6359_ACCDET_CON29 0x26c2
3992 #define MT6359_ACCDET_CON30 0x26c4
3993 #define MT6359_ACCDET_CON31 0x26c6
3994 #define MT6359_ACCDET_CON32 0x26c8
3995 #define MT6359_ACCDET_CON33 0x26ca
3996 #define MT6359_ACCDET_CON34 0x26cc
3997 #define MT6359_ACCDET_CON35 0x26ce
3998 #define MT6359_ACCDET_CON36 0x26d0
3999 #define MT6359_ACCDET_CON37 0x26d2
4000 #define MT6359_ACCDET_CON38 0x26d4
4001 #define MT6359_ACCDET_CON39 0x26d6
4002 #define MT6359_ACCDET_CON40 0x26d8
4006 #define DRBIAS_MASK 0x7
4007 #define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
4013 #define IBIAS_MASK 0x3
4014 #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
4027 #define DL_GAIN_REG_MASK 0x0f9f
4037 MT6359_MTKAIF_PROTOCOL_1 = 0,
4043 MT6359_AIF_1 = 0, /* dl: hp, rcv, hp+lo */
4062 MUX_MIC_TYPE_0, /* ain0, micbias 0 */
4082 HP_GAIN_CTL_ZCD = 0,
4088 HP_MUX_OPEN = 0,
4093 HP_MUX_MASK = 0x7,
4097 RCV_MUX_OPEN = 0,
4101 RCV_MUX_MASK = 0x3,
4105 LO_MUX_OPEN = 0,
4109 LO_MUX_MASK = 0x3,
4150 CH_L = 0,
4156 DRBIAS_4UA = 0,
4167 IBIAS_4UA = 0,
4174 IBIAS_ZCD_3UA = 0,
4181 MIC_BIAS_1P7 = 0,
4193 DL_GAIN_8DB = 0,
4198 DL_GAIN_N_40DB = 0x1f,
4203 MIC_TYPE_MUX_IDLE = 0,
4213 UL_SRC_MUX_AMIC = 0,
4219 MISO_MUX_UL1_CH1 = 0,
4227 DMIC_MUX_DMIC_DATA0 = 0,
4235 ADC_MUX_IDLE = 0,
4243 PGA_L_MUX_NONE = 0,
4250 PGA_R_MUX_NONE = 0,
4258 PGA_3_MUX_NONE = 0,