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Searched +full:0 +full:x2008 (Results 1 – 25 of 127) sorted by relevance

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/linux/drivers/reset/
H A Dreset-uniphier.c19 #define UNIPHIER_RESET_ACTIVE_LOW BIT(0)
44 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
45 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (Ether, HSC, MIO) */
50 UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
51 UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
52 UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
53 UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
54 UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
55 UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
56 UNIPHIER_RESETX(28, 0x2000, 18), /* SATA0 */
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/linux/sound/soc/codecs/
H A Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
H A Dmax98373.h7 #define MAX98373_R2000_SW_RESET 0x2000
8 #define MAX98373_R2001_INT_RAW1 0x2001
9 #define MAX98373_R2002_INT_RAW2 0x2002
10 #define MAX98373_R2003_INT_RAW3 0x2003
11 #define MAX98373_R2004_INT_STATE1 0x2004
12 #define MAX98373_R2005_INT_STATE2 0x2005
13 #define MAX98373_R2006_INT_STATE3 0x2006
14 #define MAX98373_R2007_INT_FLAG1 0x2007
15 #define MAX98373_R2008_INT_FLAG2 0x2008
16 #define MAX98373_R2009_INT_FLAG3 0x2009
[all …]
/linux/drivers/clk/qcom/
H A Dtcsrcc-nord.c28 .halt_reg = 0xa008,
31 .enable_reg = 0xa008,
32 .enable_mask = BIT(0),
45 .halt_reg = 0xb008,
48 .enable_reg = 0xb008,
49 .enable_mask = BIT(0),
62 .halt_reg = 0xc008,
65 .enable_reg = 0xc008,
66 .enable_mask = BIT(0),
79 .halt_reg = 0xd008,
[all …]
H A Ddispcc-qcm2290.c43 .l = 0x28,
44 .vco_val = 0x2 << 20,
46 .main_output_mask = BIT(0),
47 .config_ctl_val = 0x4001055B,
51 .offset = 0x0,
69 { P_BI_TCXO, 0 },
79 { P_BI_TCXO, 0 },
87 { P_BI_TCXO_AO, 0 },
97 { P_BI_TCXO, 0 },
109 { P_BI_TCXO, 0 },
[all …]
H A Ddispcc-sm6375.c39 { 249600000, 2000000000, 0 },
44 .l = 0x20,
45 .alpha = 0x800,
46 .config_ctl_val = 0x20485699,
47 .config_ctl_hi_val = 0x00002261,
48 .config_ctl_hi1_val = 0x329a299c,
49 .user_ctl_val = 0x00000001,
50 .user_ctl_hi_val = 0x00000805,
51 .user_ctl_hi1_val = 0x00000000,
55 .offset = 0x0,
[all …]
H A Ddispcc-sm6115.c51 .l = 0x28,
52 .vco_val = 0x2 << 20,
54 .main_output_mask = BIT(0),
55 .config_ctl_val = 0x4001055B,
59 .offset = 0x0,
74 { 0x0, 1 },
78 .offset = 0x0,
96 { P_BI_TCXO, 0 },
106 { P_BI_TCXO, 0 },
114 { P_BI_TCXO, 0 },
[all …]
/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6115-dpu.yaml63 reg = <0x05e01000 0x8f000>,
64 <0x05eb0000 0x2008>;
79 interrupts = <0>;
83 #size-cells = <0>;
85 port@0 {
86 reg = <0>;
H A Dqcom,sdm845-dpu.yaml63 reg = <0x0ae01000 0x8f000>,
64 <0x0aeb0000 0x2008>;
75 interrupts = <0>;
81 #size-cells = <0>;
83 port@0 {
84 reg = <0>;
H A Dqcom,msm8998-dpu.yaml64 reg = <0x0c901000 0x8f000>,
65 <0x0c9a8e00 0xf0>,
66 <0x0c9b0000 0x2008>,
67 <0x0c9b8000 0x1040>;
78 interrupts = <0>;
84 #size-cells = <0>;
86 port@0 {
87 reg = <0>;
H A Dqcom,sc7180-dpu.yaml87 reg = <0x0ae01000 0x8f000>,
88 <0x0aeb0000 0x2008>;
102 interrupts = <0>;
108 #size-cells = <0>;
110 port@0 {
111 reg = <0>;
H A Dqcom,sm6150-dpu.yaml52 reg = <0x0ae01000 0x8f000>,
53 <0x0aeb0000 0x2008>;
69 interrupts = <0>;
73 #size-cells = <0>;
75 port@0 {
76 reg = <0>;
H A Dqcom,sm7150-dpu.yaml62 reg = <0x0ae01000 0x8f000>,
63 <0x0aeb0000 0x2008>;
86 interrupts = <0>;
90 #size-cells = <0>;
92 port@0 {
93 reg = <0>;
H A Dqcom,sm6115-mdss.yaml43 "^display-controller@[0-9a-f]+$":
51 "^dsi@[0-9a-f]+$":
65 "^phy@[0-9a-f]+$":
90 reg = <0x05e00000 0x1000>;
101 iommus = <&apps_smmu 0x420 0x2>,
102 <&apps_smmu 0x421 0x0>;
107 reg = <0x05e01000 0x8f000>,
108 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
[all …]
H A Dqcom,sm6125-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
102 iommus = <&apps_smmu 0x400 0x0>;
110 reg = <0x05e01000 0x83208>,
111 <0x05eb0000 0x2008>;
115 interrupts = <0>;
139 #size-cells = <0>;
141 port@0 {
[all …]
H A Dqcom,sm6375-mdss.yaml48 "^display-controller@[0-9a-f]+$":
56 "^dsi@[0-9a-f]+$":
66 "^phy@[0-9a-f]+$":
86 reg = <0x05e00000 0x1000>;
100 iommus = <&apps_smmu 0x820 0x2>;
107 reg = <0x05e01000 0x8e030>,
108 <0x05eb0000 0x2008>;
133 interrupts = <0>;
137 #size-cells = <0>;
139 port@0 {
[all …]
/linux/drivers/clk/samsung/
H A Dclk-exynos5260.h15 #define MUX_SEL_AUD 0x0200
16 #define MUX_ENABLE_AUD 0x0300
17 #define MUX_STAT_AUD 0x0400
18 #define MUX_IGNORE_AUD 0x0500
19 #define DIV_AUD0 0x0600
20 #define DIV_AUD1 0x0604
21 #define DIV_STAT_AUD0 0x0700
22 #define DIV_STAT_AUD1 0x0704
23 #define EN_ACLK_AUD 0x0800
24 #define EN_PCLK_AUD 0x0900
[all …]
H A Dclk-fsd.c22 /* Register Offset definitions for CMU_CMU (0x11c10000) */
23 #define PLL_LOCKTIME_PLL_SHARED0 0x0
24 #define PLL_LOCKTIME_PLL_SHARED1 0x4
25 #define PLL_LOCKTIME_PLL_SHARED2 0x8
26 #define PLL_LOCKTIME_PLL_SHARED3 0xc
27 #define PLL_CON0_PLL_SHARED0 0x100
28 #define PLL_CON0_PLL_SHARED1 0x120
29 #define PLL_CON0_PLL_SHARED2 0x140
30 #define PLL_CON0_PLL_SHARED3 0x160
31 #define MUX_CMU_CIS0_CLKMUX 0x1000
[all …]
H A Dclk-exynos2200.c32 /* Register Offset definitions for CMU_TOP (0x1a320000) */
33 #define PLL_LOCKTIME_PLL_MMC 0x0
34 #define PLL_LOCKTIME_PLL_SHARED0 0x4
35 #define PLL_LOCKTIME_PLL_SHARED1 0x8
36 #define PLL_LOCKTIME_PLL_SHARED2 0xc
37 #define PLL_LOCKTIME_PLL_SHARED3 0x10
38 #define PLL_LOCKTIME_PLL_SHARED4 0x14
39 #define PLL_LOCKTIME_PLL_SHARED_MIF 0x18
40 #define PLL_CON3_PLL_MMC 0x10c
41 #define PLL_CON8_PLL_MMC 0x120
[all …]
/linux/drivers/dma/xilinx/
H A Dxdma-regs.h33 #define XDMA_DESC_MAGIC 0xad4bUL
35 #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0)
36 #define XDMA_DESC_STOPPED BIT(0)
76 #define XDMA_CHAN_IDENTIFIER 0x0
77 #define XDMA_CHAN_CONTROL 0x4
78 #define XDMA_CHAN_CONTROL_W1S 0x8
79 #define XDMA_CHAN_CONTROL_W1C 0xc
80 #define XDMA_CHAN_STATUS 0x40
81 #define XDMA_CHAN_STATUS_RC 0x44
82 #define XDMA_CHAN_COMPLETED_DESC 0x48
[all …]
/linux/drivers/media/platform/samsung/s5p-mfc/
H A Dregs-mfc.h20 #define S5P_FIMV_START_ADDR 0x0000
21 #define S5P_FIMV_END_ADDR 0xe008
23 #define S5P_FIMV_SW_RESET 0x0000
24 #define S5P_FIMV_RISC_HOST_INT 0x0008
27 #define S5P_FIMV_HOST2RISC_CMD 0x0030
28 #define S5P_FIMV_HOST2RISC_ARG1 0x0034
29 #define S5P_FIMV_HOST2RISC_ARG2 0x0038
30 #define S5P_FIMV_HOST2RISC_ARG3 0x003c
31 #define S5P_FIMV_HOST2RISC_ARG4 0x0040
34 #define S5P_FIMV_RISC2HOST_CMD 0x0044
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
[all …]
/linux/include/linux/mfd/mt6359p/
H A Dregisters.h9 #define MT6359P_CHIP_VER 0x5930
12 #define MT6359P_HWCID 0x8
13 #define MT6359P_TOP_TRAP 0x50
14 #define MT6359P_TOP_TMA_KEY 0x3a8
15 #define MT6359P_BUCK_VCORE_ELR_NUM 0x152a
16 #define MT6359P_BUCK_VCORE_ELR0 0x152c
17 #define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa
18 #define MT6359P_BUCK_VGPU11_ELR0 0x15b4
19 #define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44
20 #define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]

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