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/freebsd/sys/dev/bxe/
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mp-tqma8mpql-mba8mpxl.dts26 io-channels = <&adc 0>, <&adc 1>;
44 pinctrl-0 = <&pinctrl_backlight>;
45 pwms = <&pwm2 0 5000000 0>;
46 brightness-levels = <0 4 8 16 32 64 128 255>;
55 #clock-cells = <0>;
64 pinctrl-0 = <&pinctrl_usbcon0>;
77 pinctrl-0 = <&pinctrl_pwmfan>;
81 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
82 cooling-levels = <0 3
[all...]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/freebsd/sys/dev/ath/ath_hal/ar9003/
H A Dar9300_devid.h48 #define AR_SREV_VERSION_AR9380 0x1C0
49 #define AR_SREV_VERSION_AR9580 0x1C0
50 #define AR_SREV_VERSION_AR9460 0x280
51 #define AR_SREV_VERSION_QCA9565 0x2c0
53 #define AR_SREV_VERSION_AR9330 0x200
54 #define AR_SREV_VERSION_AR9340 0x300
55 #define AR_SREV_VERSION_QCA9550 0x400
56 #define AR_SREV_VERSION_AR9485 0x240
57 #define AR_SREV_VERSION_QCA9530 0x500
59 #define AR_SREV_REVISION_AR9380_10 0 /* AR9380 1.0 */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_devid.h48 #define AR_SREV_VERSION_AR9380 0x1C0
49 #define AR_SREV_VERSION_AR9580 0x1C0
50 #define AR_SREV_VERSION_AR9460 0x280
52 #define AR_SREV_VERSION_AR9330 0x200
53 #define AR_SREV_VERSION_AR9340 0x300
54 #define AR_SREV_VERSION_QCA9550 0x400
55 #define AR_SREV_VERSION_AR9485 0x240
57 #define AR_SREV_REVISION_AR9380_10 0 /* AR9380 1.0 */
62 #define AR_SREV_REVISION_AR9330_10 0 /* AR9330 1.0 */
65 #define AR_SREV_REVISION_AR9330_11_MASK 0xf /* AR9330 1.1 revision mask */
[all …]
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
25 operator Rd() { return Rd{rd + (shift ? 8 : 0)}; } in Rd()
26 operator Rs() { return Rs{rd + (shift ? 8 : 0)}; } in Rs()
35 return RxC{(inst & 0x7C) >> 2, false}; in DecodeCR_RS2()
38 constexpr RxC DecodeCIW_RD(uint32_t inst) { return RxC{(inst & 0x1C) >> 2}; } in DecodeCIW_RD()
40 constexpr RxC DecodeCA_RD(uint32_t inst) { return RxC{(inst & 0x380) >> 7}; } in DecodeCA_RD()
54 uint16_t offset = ((inst << 4) & 0xc0) // offset[7:6] in DecodeC_LWSP()
55 | ((inst >> 7) & 0x20) // offset[5] in DecodeC_LWSP()
56 | ((inst >> 2) & 0x1c); // offset[4:2] in DecodeC_LWSP()
57 if (rd == 0) in DecodeC_LWSP()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx25-eukrea-cpuimx25.dtsi14 reg = <0x80000000 0x4000000>; /* 64M */
21 pinctrl-0 = <&pinctrl_fec>;
27 pinctrl-0 = <&pinctrl_i2c1>;
32 reg = <0x51>;
40 MX25_PAD_FEC_MDC__FEC_MDC 0x80000000
41 MX25_PAD_FEC_MDIO__FEC_MDIO 0x400001e0
42 MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
43 MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
44 MX25_PAD_FEC_TX_EN__FEC_TX_EN 0x8000000
[all...]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Damlogic,axg-fifo.txt19 - #sound-dai-cells: must be 0.
28 reg = <0x0 0x1c0 0x0 0x1c>;
29 #sound-dai-cells = <0>;
H A Damlogic,axg-fifo.yaml33 const: 0
105 reg = <0x1c0 0x1c>;
106 #sound-dai-cells = <0>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,edp-phy.yaml44 const: 0
66 reg = <0x0aec2a00 0x1c0>,
67 <0x0aec2200 0xa0>,
68 <0x0aec2600 0xa0>,
69 <0x0aec2000 0x19c>;
71 clocks = <&dispcc 0>, <&dispcc 1>;
75 #phy-cells = <0>;
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.h99 #define BWN_NTAB_TYPEMASK 0xF0000000
100 #define BWN_NTAB_8BIT 0x10000000
101 #define BWN_NTAB_16BIT 0x20000000
102 #define BWN_NTAB_32BIT 0x30000000
108 #define BWN_NTAB_FRAMESTRUCT BWN_NTAB32(0x0A, 0x000) /* Frame Struct Table */
110 #define BWN_NTAB_FRAMELT BWN_NTAB8 (0x18, 0x000) /* Frame Lookup Table */
112 #define BWN_NTAB_TMAP BWN_NTAB32(0x0C, 0x000) /* T Map Table */
114 #define BWN_NTAB_TDTRN BWN_NTAB32(0x0E, 0x000) /* TDTRN Table */
116 #define BWN_NTAB_INTLEVEL BWN_NTAB32(0x0D, 0x000) /* Int Level Table */
118 #define BWN_NTAB_PILOT BWN_NTAB16(0x0B, 0x000) /* Pilot Table */
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dxilinx13 0 beshort 0x0009
14 >2 belong =0x0ff00ff0
15 >>&0 belong =0x0ff00ff0
16 >>>&0 byte =0x00
17 >>>&1 beshort =0x0001
20 >>>>&0 pstring/H x - from %s
24 >>>>>>&0 pstring/H x - for %s
28 >>>>>>>>&0 pstring/H x - built %s
32 >>>>>>>>>>&0 pstring/H x \b(%s)
36 >>>>>>>>>>>>&0 belong x - data length %#x
[all …]
H A Despressif9 # cfg_holder=4617=0x1209
10 0 uleshort 4617
11 # remaining settings normally 0x5A+offset XORed; free_1D5[20] empty since 5.12.0e
12 >0x1D5 ubequad 0x2f30313233343536 configuration of Tasmota firmware (ESP8266)
15 # version like 6.2.1.0 ~ 0x06020100 XORed to 0x63666262
16 >>11 ubyte^0x65 x \b, version %u
17 >>10 ubyte^0x64 x \b.%u
18 >>9 ubyte^0x63 x \b.%u
19 >>8 ubyte^0x62 x \b.%u
22 >>0x165 ubyte^0x1BF x \b, hostname %c
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dbrcm,cru.yaml61 reg = <0x1800c100 0x1d0>;
69 reg = <0x100 0x14>;
77 reg = <0x140 0x24>;
85 reg = <0x164 0x4>;
89 #phy-cells = <0>;
94 reg = <0x180 0x4>;
99 reg = <0x1c0 0x24>;
105 reg = <0x2c0 0x10>;
106 #thermal-sensor-cells = <0>;
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dmotorola-mapphone-common.dtsi15 reg = <0x80000000 0x3fd00000>; /* 1021 MB */
21 pinctrl-0 = <&poweroff_gpio>;
28 pinctrl-0 = <&hdmi_hpd_gpio>;
118 pinctrl-0 = <&dss_hdmi_pins>;
125 lanes = <1 0 3 2 5 4 7 6>;
133 reg = <0x48>;
134 pinctrl-0 = <&tmp105_irq>;
138 &omap4_pmx_core 0x14e>;
158 pinctrl-0
[all...]
/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h44 #define AL_PCI_COMMAND 0x04 /* 16 bits */
45 #define AL_PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
46 #define AL_PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
47 #define AL_PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
49 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
51 #define AL_PCI_BASE_ADDRESS_SPACE_IO 0x01
52 #define AL_PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
53 #define AL_PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
54 #define AL_PCI_BASE_ADDRESS_DEVICE_ID 0x0c
56 #define AL_PCI_BASE_ADDRESS_0 0x10
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/BLAKE3/
H A Dblake3_avx2_x86-64_windows_gnu.S20 and rsp, 0xFFFFFFFFFFFFFFC0
21 vmovdqa xmmword ptr [rsp+0x2D0], xmm6
22 vmovdqa xmmword ptr [rsp+0x2E0], xmm7
23 vmovdqa xmmword ptr [rsp+0x2F0], xmm8
24 vmovdqa xmmword ptr [rsp+0x300], xmm9
25 vmovdqa xmmword ptr [rsp+0x310], xmm10
26 vmovdqa xmmword ptr [rsp+0x320], xmm11
27 vmovdqa xmmword ptr [rsp+0x330], xmm12
28 vmovdqa xmmword ptr [rsp+0x340], xmm13
29 vmovdqa xmmword ptr [rsp+0x350], xmm14
[all …]
H A Dblake3_avx2_x86-64_unix.S47 and rsp, 0xFFFFFFFFFFFFFFC0
51 vmovdqa ymmword ptr [rsp+0x280], ymm0
54 vmovdqa ymmword ptr [rsp+0x220], ymm2
58 vmovdqa ymmword ptr [rsp+0x240], ymm2
66 vmovdqa ymmword ptr [rsp+0x260], ymm3
68 mov qword ptr [rsp+0x2A0], rdx
73 vpbroadcastd ymm1, dword ptr [rcx+0x4]
74 vpbroadcastd ymm2, dword ptr [rcx+0x8]
75 vpbroadcastd ymm3, dword ptr [rcx+0xC]
76 vpbroadcastd ymm4, dword ptr [rcx+0x10]
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/blake3/
H A Dblake3_avx2.S46 and rsp, 0xFFFFFFFFFFFFFFC0
50 vmovdqa ymmword ptr [rsp+0x280], ymm0
53 vmovdqa ymmword ptr [rsp+0x220], ymm2
57 vmovdqa ymmword ptr [rsp+0x240], ymm2
65 vmovdqa ymmword ptr [rsp+0x260], ymm3
67 mov qword ptr [rsp+0x2A0], rdx
72 vpbroadcastd ymm1, dword ptr [rcx+0x4]
73 vpbroadcastd ymm2, dword ptr [rcx+0x8]
74 vpbroadcastd ymm3, dword ptr [rcx+0xC]
75 vpbroadcastd ymm4, dword ptr [rcx+0x10]
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Domap5.h8 #define OMAP5_CLKCTRL_OFFSET 0x20
12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
[all …]

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