Home
last modified time | relevance | path

Searched +full:0 +full:x11f20000 (Results 1 – 15 of 15) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,mt7988-xfi-tphy.yaml49 const: 0
70 reg = <0 0x11f20000 0 0x10000>;
76 #phy-cells = <0>;
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8192-pinctrl.yaml149 reg = <0x10005000 0x1000>,
150 <0x11c20000 0x1000>,
151 <0x11d10000 0x1000>,
152 <0x11d30000 0x1000>,
153 <0x11d40000 0x1000>,
154 <0x11e20000 0x1000>,
155 <0x11e70000 0x1000>,
156 <0x11ea0000 0x1000>,
157 <0x11f20000 0x1000>,
158 <0x11f30000 0x1000>,
[all …]
H A Dmediatek,mt6893-pinctrl.yaml153 #define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
159 reg = <0x10005000 0x1000>,
160 <0x11c20000 0x0200>,
161 <0x11d10000 0x0200>,
162 <0x11e20000 0x0200>,
163 <0x11e70000 0x0200>,
164 <0x11ea0000 0x0200>,
165 <0x11f20000 0x0200>,
166 <0x11f30000 0x0200>,
167 <0x1100b000 0x1000>;
[all …]
H A Dmediatek,mt8189-pinctrl.yaml181 reg = <0x10005000 0x1000>,
182 <0x11b50000 0x1000>,
183 <0x11c50000 0x1000>,
184 <0x11c60000 0x1000>,
185 <0x11d20000 0x1000>,
186 <0x11d30000 0x1000>,
187 <0x11d40000 0x1000>,
188 <0x11e20000 0x1000>,
189 <0x11e30000 0x1000>,
190 <0x11f20000 0x1000>,
[all …]
H A Dmediatek,mt6779-pinctrl.yaml114 '-[0-9]*$':
158 enum: [0, 1]
165 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
166 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
167 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
170 enum: [0, 1, 2, 3]
177 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
178 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
179 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
182 enum: [0, 1, 2, 3]
[all …]
H A Dmediatek,mt8183-pinctrl.yaml126 When E1=0/E0=0, the strength is 0.125mA.
127 When E1=0/E0=1, the strength is 0.25mA.
128 When E1=1/E0=0, the strength is 0.5mA.
132 0: (E1, E0, EN) = (0, 0, 0)
133 1: (E1, E0, EN) = (0, 0, 1)
134 2: (E1, E0, EN) = (0, 1, 0)
135 3: (E1, E0, EN) = (0, 1, 1)
136 4: (E1, E0, EN) = (1, 0, 0)
137 5: (E1, E0, EN) = (1, 0, 1)
138 6: (E1, E0, EN) = (1, 1, 0)
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7981b.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0x0>;
26 reg = <0x1>;
36 #clock-cells = <0>;
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
62 reg = <0 0x10001000 0 0x1000>;
68 reg = <0 0x1001b000 0 0x1000>;
74 reg = <0 0x1001c000 0 0x1000>;
[all …]
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
H A Dmt8188.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x000>;
78 performance-domains = <&performance 0>;
85 reg = <0x100>;
97 performance-domains = <&performance 0>;
104 reg = <0x200>;
116 performance-domains = <&performance 0>;
123 reg = <0x300>;
135 performance-domains = <&performance 0>;
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt8183.c13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000,
14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000,
15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000.
21 _x_bits, 32, 0)
28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4),
32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1),
36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1),
40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1),
44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1),
45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1),
[all …]
H A Dpinctrl-mt8192.c13 * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000,
14 * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000,
15 * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000,
16 * iocfg_tl:0x11F30000
22 32, 0)
29 PIN_FIELD(0, 228, 0x300, 0x10, 0, 4),
33 PIN_FIELD(0, 228, 0x0, 0x10, 0, 1),
37 PIN_FIELD(0, 228, 0x200, 0x10, 0, 1),
41 PIN_FIELD(0, 228, 0x100, 0x10, 0, 1),
45 PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1),
[all …]