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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmediatek,mt8189-pinctrl.yaml181 reg = <0x10005000 0x1000>,
182 <0x11b50000 0x1000>,
183 <0x11c50000 0x1000>,
184 <0x11c60000 0x1000>,
185 <0x11d20000 0x1000>,
186 <0x11d30000 0x1000>,
187 <0x11d40000 0x1000>,
188 <0x11e20000 0x1000>,
189 <0x11e30000 0x1000>,
190 <0x11f20000 0x1000>,
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
[all …]