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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dqcom,wcd934x-gpio.yaml42 reg = <0x042 0x2>;
/freebsd/sys/contrib/dev/mediatek/mt76/mt7603/
H A Deeprom.h9 MT_EE_CHIP_ID = 0x000,
10 MT_EE_VERSION = 0x002,
11 MT_EE_MAC_ADDR = 0x004,
12 MT_EE_NIC_CONF_0 = 0x034,
13 MT_EE_NIC_CONF_1 = 0x036,
14 MT_EE_NIC_CONF_2 = 0x042,
16 MT_EE_XTAL_TRIM_1 = 0x03a,
18 MT_EE_RSSI_OFFSET_2G = 0x046,
19 MT_EE_WIFI_RF_SETTING = 0x048,
20 MT_EE_RSSI_OFFSET_5G = 0x04a,
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_eeprom.h13 MT_EE_CHIP_ID = 0x000,
14 MT_EE_VERSION = 0x002,
15 MT_EE_MAC_ADDR = 0x004,
16 MT_EE_PCI_ID = 0x00A,
17 MT_EE_ANTENNA = 0x022,
18 MT_EE_CFG1_INIT = 0x024,
19 MT_EE_NIC_CONF_0 = 0x034,
20 MT_EE_NIC_CONF_1 = 0x036,
21 MT_EE_COUNTRY_REGION_5GHZ = 0x038,
22 MT_EE_COUNTRY_REGION_2GHZ = 0x039,
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-kc1.dts15 reg = <0x80000000 0x20000000>; /* 512 MB */
23 pwms = <&twl_pwm 0 7812500>;
40 OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */
41 OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */
47 OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
48 OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
54 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
55 OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
61 OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
62 OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
[all …]
H A Domap4-var-som-om44.dtsi15 reg = <0x80000000 0x40000000>; /* 1 GB */
38 pinctrl-0 = <
45 #phy-cells = <0>;
64 pinctrl-0 = <
70 OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */
71 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
77 OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */
78 OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */
84 OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
85 OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
[all …]
/freebsd/sys/dev/hid/
H A Dhcons.c60 HCONS_MAP_KEY(0x030, KEY_POWER),
61 HCONS_MAP_KEY(0x031, KEY_RESTART),
62 HCONS_MAP_KEY(0x032, KEY_SLEEP),
63 HCONS_MAP_KEY(0x034, KEY_SLEEP),
64 HCONS_MAP_KEY(0x035, KEY_KBDILLUMTOGGLE),
65 HCONS_MAP_KEY(0x036, BTN_MISC),
66 HCONS_MAP_KEY(0x040, KEY_MENU), /* Menu */
67 HCONS_MAP_KEY(0x041, KEY_SELECT), /* Menu Pick */
68 HCONS_MAP_KEY(0x042, KEY_UP), /* Menu Up */
69 HCONS_MAP_KEY(0x043, KEY_DOWN), /* Menu Down */
[all …]
/freebsd/sys/arm/nvidia/drm2/
H A Dtegra_hdmi_reg.h35 #define HDMI_NV_PDISP_SOR_STATE0 0x001
36 #define SOR_STATE0_UPDATE (1 << 0)
38 #define HDMI_NV_PDISP_SOR_STATE1 0x002
41 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0)
42 #define ASY_HEAD_OPMODE_SLEEP 0
46 #define HDMI_NV_PDISP_SOR_STATE2 0x003
50 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8)
53 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6)
54 #define ASY_CRCMODE_ACTIVE 0
57 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4)
[all …]
H A Dtegra_dc_reg.h37 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
38 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
40 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
42 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
43 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
44 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
45 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
46 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
47 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
48 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
[all …]
/freebsd/sys/dev/pms/RefTisa/tisa/sassata/common/
H A Dwcs.h33 0x011, // 00000 = 0 - PHY_RESET_START
34 0x0ca, // 0x001 = 1 - JUMP_IF_PHY_READY
35 0x009, // 0x002 = 2 -
36 0x0ba, // 0x003 = 3 - JUMP_IF_HARD_RESET_PRIMITIVE
37 0x010, // 0x004 = 4 -
38 0x0bb, // 0x005 = 5 - JUMP_IF_IDENTIFY_FRAME_RECEIVED
39 0x01e, // 0x006 = 6 -
40 0x0ff, // 0x007 = 7 - JUMP
41 0x001, // 0x008 = 8 -
42 0x010, // 0x009 = 9 - SEND_ID_FRAME
[all …]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_radio_2057.h32 #define R2057_DACBUF_VINCM_CORE0 0x000
33 #define R2057_IDCODE 0x001
34 #define R2057_RCCAL_MASTER 0x002
35 #define R2057_RCCAL_CAP_SIZE 0x003
36 #define R2057_RCAL_CONFIG 0x004
37 #define R2057_GPAIO_CONFIG 0x005
38 #define R2057_GPAIO_SEL1 0x006
39 #define R2057_GPAIO_SEL0 0x007
40 #define R2057_CLPO_CONFIG 0x008
41 #define R2057_BANDGAP_CONFIG 0x009
[all …]
/freebsd/contrib/llvm-project/openmp/runtime/src/include/
H A Domp-tools.h.var7 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
66 macro (ompt_state_undefined, 0x102) /* undefined thread state */ \
68 /* work states (0..15) */ \
69 macro (ompt_state_work_serial, 0x000) /* working outside parallel */ \
70 macro (ompt_state_work_parallel, 0x001) /* working within parallel */ \
71 macro (ompt_state_work_reduction, 0x002) /* performing a reduction */ \
74 macro (ompt_state_wait_barrier, 0x010) /* waiting at a barrier */ \
75 macro (ompt_state_wait_barrier_implicit_parallel, 0x011) \
77 macro (ompt_state_wait_barrier_implicit_workshare, 0x012) \
79 macro (ompt_state_wait_barrier_implicit, 0x013) /* implicit barrier */ \
[all …]
/freebsd/lib/libomp/
H A Domp-tools.h7 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
66 macro (ompt_state_undefined, 0x102) /* undefined thread state */ \
68 /* work states (0..15) */ \
69 macro (ompt_state_work_serial, 0x000) /* working outside parallel */ \
70 macro (ompt_state_work_parallel, 0x001) /* working within parallel */ \
71 macro (ompt_state_work_reduction, 0x002) /* performing a reduction */ \
74 macro (ompt_state_wait_barrier, 0x010) /* waiting at a barrier */ \
75 macro (ompt_state_wait_barrier_implicit_parallel, 0x011) \
77 macro (ompt_state_wait_barrier_implicit_workshare, 0x012) \
79 macro (ompt_state_wait_barrier_implicit, 0x013) /* implicit barrier */ \
[all …]
/freebsd/sys/dev/rtwn/rtl8188e/
H A Dr88e_calib.c71 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0); in r88e_iq_calib_chain()
72 rtwn_rf_write(sc, 0, R88E_RF_WE_LUT, 0x800a0); in r88e_iq_calib_chain()
73 rtwn_rf_write(sc, 0, R92C_RF_RCK_OS, 0x30000); in r88e_iq_calib_chain()
74 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(0), 0xf); in r88e_iq_calib_chain()
75 rtwn_rf_write(sc, 0, R92C_RF_TXPA_G(1), 0xf117b); in r88e_iq_calib_chain()
76 rtwn_bb_write(sc, R92C_FPGA0_IQK, 0x80800000); in r88e_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_TX_IQK, 0x01007c00); in r88e_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_RX_IQK, 0x81004800); in r88e_iq_calib_chain()
82 /* IQ calibration settings for chain 0. */ in r88e_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1c); in r88e_iq_calib_chain()
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/pci/
H A Dr92ce_calib.c76 if (chain == 0) { /* IQ calibration for chain 0. */ in r92ce_iq_calib_chain()
77 /* IQ calibration settings for chain 0. */ in r92ce_iq_calib_chain()
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92ce_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92ce_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92ce_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92ce_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92ce_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92ce_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92ce_iq_calib_chain()
[all …]
/freebsd/sys/dev/rtwn/rtl8192c/
H A Dr92c_calib.c76 if (chain == 0) { /* IQ calibration for chain 0. */ in r92c_iq_calib_chain()
77 /* IQ calibration settings for chain 0. */ in r92c_iq_calib_chain()
78 rtwn_bb_write(sc, R92C_TX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
79 rtwn_bb_write(sc, R92C_RX_IQK_TONE(0), 0x10008c1f); in r92c_iq_calib_chain()
80 rtwn_bb_write(sc, R92C_TX_IQK_PI(0), 0x82140102); in r92c_iq_calib_chain()
83 rtwn_bb_write(sc, R92C_RX_IQK_PI(0), 0x28160202); in r92c_iq_calib_chain()
85 rtwn_bb_write(sc, R92C_TX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
86 rtwn_bb_write(sc, R92C_RX_IQK_TONE(1), 0x10008c22); in r92c_iq_calib_chain()
87 rtwn_bb_write(sc, R92C_TX_IQK_PI(1), 0x82140102); in r92c_iq_calib_chain()
88 rtwn_bb_write(sc, R92C_RX_IQK_PI(1), 0x28160202); in r92c_iq_calib_chain()
[all …]
H A Dr92c_reg.h28 #define R92C_SYS_ISO_CTRL 0x000
29 #define R92C_SYS_FUNC_EN 0x002
30 #define R92C_APS_FSMCO 0x004
31 #define R92C_SYS_CLKR 0x008
32 #define R92C_AFE_MISC 0x010
33 #define R92C_SPS0_CTRL 0x011
34 #define R92C_SPS_OCP_CFG 0x018
35 #define R92C_RSV_CTRL 0x01c
36 #define R92C_RF_CTRL 0x01f
37 #define R92C_LDOA15_CTRL 0x020
[all …]
/freebsd/usr.sbin/bluetooth/bthidd/
H A Dbtuinput.c74 static uint16_t const keymap[0x100] = {
75 /* 0x00 - 0x27 */
81 /* 0x28 - 0x3f */
88 /* 0x40 - 0x5f */
97 /* 0x60 - 0x7f */
106 /* 0x80 - 0x9f */
115 /* 0xa0 - 0xbf */
124 /* 0xc0 - 0xdf */
133 /* 0xe0 - 0xff */
145 static uint16_t const consmap[0x300] = {
[all …]
/freebsd/sys/dev/bhnd/nvram/
H A Dnvram_map36 help "Antennas 0-3 are marked as available if the
41 help "Antennas 0-3 are marked as available if the
46 desc "Antenna 0 Gain"
72 help "TX chains 0-3 are marked as available if the
80 help "RX chains 0-3 are marked as available if the
1863 0x048: u8 il0macaddr[6] { +0x1, +0x0, +0x3, +0x2, +0x5, +0x4 }
1864 0x04C: u16 boardnum
1865 0x054: u8 et1macaddr[6] { +0x1, +0x0, +0x3, +0x2, +0x5, +0x4 }
1866 0x05C: u8 boardrev
1867 0x05D: u8 aa5g (&0xC0, >>6)
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
32 let hasSideEffects = 0;
38 bits<1> is_flat_global = 0;
39 bits<1> is_flat_scratch = 0;
48 bits<1> has_saddr = 0;
49 bits<1> enabled_saddr = 0;
50 bits<7> saddr_value = 0;
55 bits<1> glcValue = 0;
57 bits<1> dlcValue = 0;
59 bits<1> sccbValue = 0;
[all …]
H A DVOP3PInstructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
14 bit HasDPP = 0> : VOP3_Profile<P, Features> {
29 bit useTiedOutput = 0> : VOP3P_Profile<P, Features, 1> {
58 SDPatternOperator node = null_frag, bit IsDOT = 0> {
112 let SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 in {
115 } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0
231 (i32 0), (i32 0),
241 (i32 0), (i32 0),
252 let isCommutable = 1, mayRaiseFPException = 0 in {
260 let ClampLo = 0, ClampHi = 1 in {
[all …]
H A DSOPInstructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 bits<1> has_sdst = 0;
34 let mayLoad = 0;
35 let mayStore = 0;
36 let hasSideEffects = 0;
53 let isPseudo = 0;
54 let isCodeGenOnly = 0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
78 let Inst{31-23} = 0x17d; //encoding;
81 class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <
[all …]
H A DVOPCInstructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 let Inst{8-0} = src0;
20 let Inst{31-25} = 0x3e;
26 let Inst{8-0} = 0xf9; // sdwa
27 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
29 let Inst{31-25} = 0x3e; // encoding
35 let Inst{8-0} = 0xf9; // sdwa
36 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
38 let Inst{31-25} = 0x3e; // encoding
39 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x
[all...]
/freebsd/sys/dev/bwn/
H A Dif_bwnreg.h36 #define BWN_IOCTL_PHYCLOCK_ENABLE 0x0004
37 #define BWN_IOCTL_PHYRESET 0x0008
38 #define BWN_IOCTL_MACPHYCLKEN 0x0010 /* MAC PHY Clock Control Enable (rev >= 5) */
39 #define BWN_IOCTL_PLLREFSEL 0x0020 /* PLL Frequency Reference Select (rev >= 5) */
41 #define BWN_IOCTL_PHY_BANDWIDTH 0x00C0
42 #define BWN_IOCTL_PHY_BANDWIDTH_10MHZ 0x0000
43 #define BWN_IOCTL_PHY_BANDWIDTH_20MHZ 0x0040
44 #define BWN_IOCTL_PHY_BANDWIDTH_40MHZ 0x0080
45 #define BWN_IOCTL_SUPPORT_G 0x2000
48 #define BWN_IOST_HAVE_2GHZ 0x0001
[all …]
/freebsd/sys/dev/otus/
H A Dif_otusreg.h30 #define AR_FW_DOWNLOAD 0x30
31 #define AR_FW_DOWNLOAD_COMPLETE 0x31
36 #define AR_FW_INIT_ADDR 0x102800
37 #define AR_FW_MAIN_ADDR 0x200000
38 #define AR_USB_MODE_CTRL 0x1e1108
43 #define AR_MAC_REG_BASE 0x1c3000
44 #define AR_MAC_REG_DMA_TRIGGER (AR_MAC_REG_BASE + 0xd30)
45 #define AR_MAC_REG_MAC_ADDR_L (AR_MAC_REG_BASE + 0x610)
46 #define AR_MAC_REG_MAC_ADDR_H (AR_MAC_REG_BASE + 0x614)
47 #define AR_MAC_REG_BSSID_L (AR_MAC_REG_BASE + 0x618)
[all …]

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