Lines Matching +full:0 +full:x042
35 #define HDMI_NV_PDISP_SOR_STATE0 0x001
36 #define SOR_STATE0_UPDATE (1 << 0)
38 #define HDMI_NV_PDISP_SOR_STATE1 0x002
41 #define SOR_STATE1_ASY_HEAD_OPMODE(x) (((x) & 0x3) << 0)
42 #define ASY_HEAD_OPMODE_SLEEP 0
46 #define HDMI_NV_PDISP_SOR_STATE2 0x003
50 #define SOR_STATE2_ASY_PROTOCOL(x) (((x) & 0xf) << 8)
53 #define SOR_STATE2_ASY_CRCMODE(x) (((x) & 0x3) << 6)
54 #define ASY_CRCMODE_ACTIVE 0
57 #define SOR_STATE2_ASY_SUBOWNER(x) (((x) & 0x3) << 4)
58 #define ASY_SUBOWNER_NONE 0
62 #define SOR_STATE2_ASY_OWNER(x) (((x) & 0x3) << 0)
63 #define ASY_OWNER_NONE 0
66 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x01e
67 #define AUDIO_INFOFRAME_CTRL_ENABLE (1 << 0)
68 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x01f
69 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x020
70 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x021
71 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x022
72 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
73 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
74 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
76 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x023
77 #define AVI_INFOFRAME_CTRL_ENABLE (1 << 0)
78 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x024
79 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x025
80 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x026
81 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x027
82 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x028
83 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x029
85 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x02a
90 #define GENERIC_CTRL_ENABLE (1 << 0)
91 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x02b
92 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x02c
93 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x02d
94 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x02e
95 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x02f
96 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x030
97 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x031
98 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x032
99 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x033
100 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x034
102 #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x035
103 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x036
104 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x037
105 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x038
106 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x039
107 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x03a
108 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x03b
109 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x03c
110 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x03d
111 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x03e
112 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x03f
113 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x040
114 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x041
115 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x042
116 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x043
118 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
119 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
121 #define HDMI_NV_PDISP_HDMI_CTRL 0x044
128 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
132 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
134 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x046
136 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
137 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
139 #define HDMI_NV_PDISP_HDMI_SPARE 0x04f
141 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
144 #define SPARE_HW_CTS (1 << 0)
146 #define HDMI_NV_PDISP_SOR_PWR 0x055
150 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
152 #define HDMI_NV_PDISP_SOR_PLL0 0x057
153 #define SOR_PLL0_TX_REG_LOAD(x) (((x) & 0xf) << 28)
154 #define SOR_PLL0_ICHPMP(x) (((x) & 0xf) << 24)
155 #define SOR_PLL0_FILTER(x) (((x) & 0xf) << 16)
156 #define SOR_PLL0_BG_V17_S(x) (((x) & 0xf) << 12)
157 #define SOR_PLL0_VCOCAP(x) (((x) & 0xf) << 8)
163 #define SOR_PLL0_PWR (1 << 0)
165 #define HDMI_NV_PDISP_SOR_PLL1 0x058
169 #define SOR_PLL1_LOADADJ(x) (((x) & 0xf) << 20)
170 #define SOR_PLL1_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
173 #define HDMI_NV_PDISP_SOR_CSTM 0x05a
174 #define SOR_CSTM_ROTAT(x) (((x) & 0xf) << 28)
175 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
183 #define SOR_CSTM_MODE(x) (((x) & 0x3) << 12)
184 #define CSTM_MODE_LVDS 0
187 #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x05f
190 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
191 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
192 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
193 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
194 #define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)
196 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x060 + (x))
209 #define SOR_SEQ_INST_WAIT_UNITS(x) (((x) & 0x3) << 12)
210 #define WAIT_UNITS_US 0
213 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
215 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x07e
217 #define HDMI_NV_PDISP_AUDIO_N 0x08c
221 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
223 #define HDMI_NV_PDISP_SOR_REFCLK 0x095
224 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
225 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
227 #define HDMI_NV_PDISP_INPUT_CONTROL 0x097
229 #define HDMI_SRC_DISPLAYB (1 << 0)
231 #define HDMI_NV_PDISP_PE_CURRENT 0x099
232 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0x0ac
234 #define SOR_AUDIO_CNTRL0_SOURCE_SELECT(x) (((x) & 0x03) << 20)
235 #define SOURCE_SELECT_AUTO 0
240 #define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0x0ae
243 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0320 0x0af
244 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0441 0x0b0
245 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0882 0x0b1
246 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1764 0x0b2
247 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0480 0x0b3
248 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_0960 0x0b4
249 #define HDMI_NV_PDISP_SOR_AUDIO_NVAL_1920 0x0b5
250 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH0 0x0b6
251 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH1 0x0b7
252 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH2 0x0b8
253 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_SCRATCH3 0x0b9
254 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0x0ba
255 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0x0bb
256 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0x0bc
257 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0x0bd
259 #define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)
261 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0x0bf
262 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0x0c0
263 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0x0c1
264 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0x0c2
265 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0x0c3
266 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0x0c4
267 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0x0c5
268 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0x0c6
270 #define HDMI_NV_PDISP_INT_STATUS 0x0cc
274 #define INT_CODEC_SCRATCH0 (1 << 0)
276 #define HDMI_NV_PDISP_INT_MASK 0x0cd
277 #define HDMI_NV_PDISP_INT_ENABLE 0x0ce
278 #define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0x0d1
279 #define HDMI_NV_PDISP_SOR_PAD_CTLS0 0x0d2