Lines Matching +full:0 +full:x042
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
23 bits<1> has_sdst = 0;
34 let mayLoad = 0;
35 let mayStore = 0;
36 let hasSideEffects = 0;
53 let isPseudo = 0;
54 let isCodeGenOnly = 0;
75 let Inst{7-0} = !if(ps.has_src0, src0, ?);
78 let Inst{31-23} = 0x17d; //encoding;
81 class SOP1_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <
98 let has_sdst = 0;
115 let has_sdst = 0;
136 class SOP1_64_32 <string opName, list<dag> pattern=[], bit tied_in = 0> : SOP1_Pseudo <
147 let has_src0 = 0;
153 let has_sdst = 0;
457 let has_sdst = 0 in {
521 } // End has_sdst = 0
545 let mayLoad = 0;
546 let mayStore = 0;
547 let hasSideEffects = 0;
559 // field bits<7> sdst = 0;
567 let isPseudo = 0;
568 let isCodeGenOnly = 0;
592 let Inst{7-0} = src0;
596 let Inst{31-30} = 0x2; // encoding
601 let Inst{7-0} = src0;
605 let Inst{31-30} = 0x2; // encoding
826 let has_sdst = 0;
841 let has_sdst = 0;
963 let mayLoad = 0;
964 let mayStore = 0;
965 let hasSideEffects = 0;
980 let isPseudo = 0;
981 let isCodeGenOnly = 0;
1009 let Inst{15-0} = simm16;
1012 let Inst{31-28} = 0xb; //encoding
1018 let Inst{15-0} = simm16;
1021 let Inst{31-28} = 0xb; //encoding
1100 def S_CMPK_EQ_U32 : SOPK_SCC <"s_cmpk_eq_u32", "s_cmp_eq_u32", 0>;
1101 def S_CMPK_LG_U32 : SOPK_SCC <"s_cmpk_lg_u32", "s_cmp_lg_u32", 0>;
1102 def S_CMPK_GT_U32 : SOPK_SCC <"s_cmpk_gt_u32", "s_cmp_gt_u32", 0>;
1103 def S_CMPK_GE_U32 : SOPK_SCC <"s_cmpk_ge_u32", "s_cmp_ge_u32", 0>;
1104 def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;
1105 def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;
1155 let hasSideEffects = 0;
1159 //def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;
1166 let has_sdst = 0;
1176 let hasSideEffects = 0;
1214 let has_sdst = 0;
1235 let mayLoad = 0;
1236 let mayStore = 0;
1237 let hasSideEffects = 0;
1251 let isPseudo = 0;
1252 let isCodeGenOnly = 0;
1270 let Inst{7-0} = src0;
1273 let Inst{31-23} = 0x17e;
1292 SOPKInstTable<0, opName> {
1301 SOPKInstTable<0, opName> {
1313 SOPKInstTable<0, opName> {
1420 let mayLoad = 0;
1421 let mayStore = 0;
1422 let hasSideEffects = 0;
1429 bits <1> fixed_imm = 0;
1443 let isPseudo = 0;
1444 let isCodeGenOnly = 0;
1467 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);
1469 let Inst{31-23} = 0x17f;
1475 let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16);
1477 let Inst{31-23} = 0x17f;
1479 let Inst{47-32} = 0x0;
1480 let Inst{54-48} = 0x0;
1481 let Inst{63-55} = 0x17f;
1504 let simm16 = 0;
1511 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
1514 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
1518 let isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1 in {
1521 } // End isBarrier = 1, isReturn = 1, simm16 = 0, fixed_imm = 1
1591 let simm16 = 0;
1605 let simm16 = 0;
1613 let simm16 = 0;
1627 // For example, a S_WAITCNT_soft 0 can be completely removed in a function
1678 let simm16 = 0;
1691 let simm16 = 0;
1697 let simm16 = 0;
1720 let simm16 = 0;
1726 let hasSideEffects = 0, Uses = [MODE], Defs = [MODE] in {
1792 (S_ENDPGM (i16 0))
1797 (S_ENDPGM (i16 0))
1804 (S_MOV_B32 (i32 0)), sub1))
1824 def : GCNPat <(int_amdgcn_s_wait_event_export_ready), (S_WAIT_EVENT (i16 0))>;
1870 HWREG.MODE, 0,
1932 (i32 (COPY_TO_REGCLASS (S_AND_B32 $src, (S_MOV_B32 (i32 0xffff))), SGPR_32)), sub0,
1933 (S_MOV_B32 (i32 0)), sub1)
1944 (S_AND_B32 (S_MOV_B32 (i32 0xffff)), $src)
2011 let Inst{7-0} = M0_gfx11plus.HWEncoding{7-0}; // Set Src0 encoding to M0
2024 defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>;
2025 defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>;
2026 defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>;
2027 defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>;
2028 defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>;
2029 defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>;
2030 defm S_FF1_I32_B32 : SOP1_Real_gfx11_gfx12<0x008, "s_ctz_i32_b32">;
2031 defm S_FF1_I32_B64 : SOP1_Real_gfx11_gfx12<0x009, "s_ctz_i32_b64">;
2032 defm S_FLBIT_I32_B32 : SOP1_Real_gfx11_gfx12<0x00a, "s_clz_i32_u32">;
2033 defm S_FLBIT_I32_B64 : SOP1_Real_gfx11_gfx12<0x00b, "s_clz_i32_u64">;
2034 defm S_FLBIT_I32 : SOP1_Real_gfx11_gfx12<0x00c, "s_cls_i32">;
2035 defm S_FLBIT_I32_I64 : SOP1_Real_gfx11_gfx12<0x00d, "s_cls_i32_i64">;
2036 defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>;
2037 defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>;
2038 defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>;
2039 defm S_BITSET0_B64 : SOP1_Real_gfx11_gfx12<0x011>;
2040 defm S_BITSET1_B32 : SOP1_Real_gfx11_gfx12<0x012>;
2041 defm S_BITSET1_B64 : SOP1_Real_gfx11_gfx12<0x013>;
2042 defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx11_gfx12<0x014>;
2043 defm S_ABS_I32 : SOP1_Real_gfx11_gfx12<0x015>;
2044 defm S_BCNT0_I32_B32 : SOP1_Real_gfx11_gfx12<0x016>;
2045 defm S_BCNT0_I32_B64 : SOP1_Real_gfx11_gfx12<0x017>;
2046 defm S_BCNT1_I32_B32 : SOP1_Real_gfx11_gfx12<0x018>;
2047 defm S_BCNT1_I32_B64 : SOP1_Real_gfx11_gfx12<0x019>;
2048 defm S_QUADMASK_B32 : SOP1_Real_gfx11_gfx12<0x01a>;
2049 defm S_QUADMASK_B64 : SOP1_Real_gfx11_gfx12<0x01b>;
2050 defm S_WQM_B32 : SOP1_Real_gfx11_gfx12<0x01c>;
2051 defm S_WQM_B64 : SOP1_Real_gfx11_gfx12<0x01d>;
2052 defm S_NOT_B32 : SOP1_Real_gfx11_gfx12<0x01e>;
2053 defm S_NOT_B64 : SOP1_Real_gfx11_gfx12<0x01f>;
2054 defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x020>;
2055 defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x021>;
2056 defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x022>;
2057 defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x023>;
2058 defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x024>;
2059 defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x025>;
2060 defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x026>;
2061 defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x027>;
2062 defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>;
2063 defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>;
2064 defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>;
2065 defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02c, "s_and_not0_saveexec_b32">;
2066 defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02d, "s_and_not0_saveexec_b64">;
2067 defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02e, "s_or_not0_saveexec_b32">;
2068 defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02f, "s_or_not0_saveexec_b64">;
2069 defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x030, "s_and_not1_saveexec_b32">;
2070 defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x031, "s_and_not1_saveexec_b64">;
2071 defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x032, "s_or_not1_saveexec_b32">;
2072 defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x033, "s_or_not1_saveexec_b64">;
2073 defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x034, "s_and_not0_wrexec_b32">;
2074 defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x035, "s_and_not0_wrexec_b64">;
2075 defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x036, "s_and_not1_wrexec_b32">;
2076 defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x037, "s_and_not1_wrexec_b64">;
2077 defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>;
2078 defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>;
2079 defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>;
2080 defm S_MOVRELD_B64 : SOP1_Real_gfx11_gfx12<0x043>;
2081 defm S_MOVRELSD_2_B32 : SOP1_Real_gfx11_gfx12<0x044>;
2082 defm S_GETPC_B64 : SOP1_Real_gfx11_gfx12<0x047>;
2083 defm S_SETPC_B64 : SOP1_Real_gfx11_gfx12<0x048>;
2084 defm S_SWAPPC_B64 : SOP1_Real_gfx11_gfx12<0x049>;
2085 defm S_RFE_B64 : SOP1_Real_gfx11_gfx12<0x04a>;
2086 defm S_SENDMSG_RTN_B32 : SOP1_Real_gfx11_gfx12<0x04c>;
2087 defm S_SENDMSG_RTN_B64 : SOP1_Real_gfx11_gfx12<0x04d>;
2088 defm S_BARRIER_SIGNAL_M0 : SOP1_M0_Real_gfx12<0x04e>;
2089 defm S_BARRIER_SIGNAL_ISFIRST_M0 : SOP1_M0_Real_gfx12<0x04f>;
2090 defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>;
2091 defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12<0x051>;
2092 defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12<0x052>;
2093 defm S_WAKEUP_BARRIER_M0 : SOP1_M0_Real_gfx12<0x057>;
2094 defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12<0x04e>;
2095 defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12<0x04f>;
2096 defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12<0x050>;
2097 defm S_BARRIER_INIT_IMM : SOP1_IMM_Real_gfx12<0x051>;
2098 defm S_BARRIER_JOIN_IMM : SOP1_IMM_Real_gfx12<0x052>;
2099 defm S_WAKEUP_BARRIER_IMM : SOP1_IMM_Real_gfx12<0x057>;
2100 defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12<0x058>;
2106 defm S_CEIL_F32 : SOP1_Real_gfx11_gfx12<0x060>;
2107 defm S_FLOOR_F32 : SOP1_Real_gfx11_gfx12<0x061>;
2108 defm S_TRUNC_F32 : SOP1_Real_gfx11_gfx12<0x062>;
2109 defm S_RNDNE_F32 : SOP1_Real_gfx11_gfx12<0x063>;
2110 defm S_CVT_F32_I32 : SOP1_Real_gfx11_gfx12<0x064>;
2111 defm S_CVT_F32_U32 : SOP1_Real_gfx11_gfx12<0x065>;
2112 defm S_CVT_I32_F32 : SOP1_Real_gfx11_gfx12<0x066>;
2113 defm S_CVT_U32_F32 : SOP1_Real_gfx11_gfx12<0x067>;
2114 defm S_CVT_F16_F32 : SOP1_Real_gfx11_gfx12<0x068>;
2115 defm S_CVT_F32_F16 : SOP1_Real_gfx11_gfx12<0x069>;
2116 defm S_CVT_HI_F32_F16 : SOP1_Real_gfx11_gfx12<0x06a>;
2117 defm S_CEIL_F16 : SOP1_Real_gfx11_gfx12<0x06b>;
2118 defm S_FLOOR_F16 : SOP1_Real_gfx11_gfx12<0x06c>;
2119 defm S_TRUNC_F16 : SOP1_Real_gfx11_gfx12<0x06d>;
2120 defm S_RNDNE_F16 : SOP1_Real_gfx11_gfx12<0x06e>;
2135 defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x037>;
2136 defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx10<0x038>;
2137 defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx10<0x039>;
2138 defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx10<0x03a>;
2139 defm S_BITREPLICATE_B64_B32 : SOP1_Real_gfx10<0x03b>;
2140 defm S_AND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03c>;
2141 defm S_OR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03d>;
2142 defm S_XOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03e>;
2143 defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x03f>;
2144 defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx10<0x040>;
2145 defm S_NAND_SAVEEXEC_B32 : SOP1_Real_gfx10<0x041>;
2146 defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x042>;
2147 defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx10<0x043>;
2148 defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x044>;
2149 defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx10<0x045>;
2150 defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx10<0x046>;
2151 defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx10<0x047>;
2152 defm S_MOVRELSD_2_B32 : SOP1_Real_gfx10<0x049>;
2171 defm S_CBRANCH_JOIN : SOP1_Real_gfx6_gfx7<0x032>;
2173 defm S_MOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x003>;
2174 defm S_MOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x004>;
2175 defm S_CMOV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x005>;
2176 defm S_CMOV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x006>;
2177 defm S_NOT_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x007>;
2178 defm S_NOT_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x008>;
2179 defm S_WQM_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x009>;
2180 defm S_WQM_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00a>;
2181 defm S_BREV_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00b>;
2182 defm S_BREV_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00c>;
2183 defm S_BCNT0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00d>;
2184 defm S_BCNT0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x00e>;
2185 defm S_BCNT1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x00f>;
2186 defm S_BCNT1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x010>;
2187 defm S_FF0_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x011>;
2188 defm S_FF0_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x012>;
2189 defm S_FF1_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x013>;
2190 defm S_FF1_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x014>;
2191 defm S_FLBIT_I32_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x015>;
2192 defm S_FLBIT_I32_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x016>;
2193 defm S_FLBIT_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x017>;
2194 defm S_FLBIT_I32_I64 : SOP1_Real_gfx6_gfx7_gfx10<0x018>;
2195 defm S_SEXT_I32_I8 : SOP1_Real_gfx6_gfx7_gfx10<0x019>;
2196 defm S_SEXT_I32_I16 : SOP1_Real_gfx6_gfx7_gfx10<0x01a>;
2197 defm S_BITSET0_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01b>;
2198 defm S_BITSET0_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01c>;
2199 defm S_BITSET1_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x01d>;
2200 defm S_BITSET1_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01e>;
2201 defm S_GETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x01f>;
2202 defm S_SETPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x020>;
2203 defm S_SWAPPC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x021>;
2204 defm S_RFE_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x022>;
2205 defm S_AND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x024>;
2206 defm S_OR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x025>;
2207 defm S_XOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x026>;
2208 defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x027>;
2209 defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x028>;
2210 defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x029>;
2211 defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02a>;
2212 defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x02b>;
2213 defm S_QUADMASK_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02c>;
2214 defm S_QUADMASK_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02d>;
2215 defm S_MOVRELS_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x02e>;
2216 defm S_MOVRELS_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x02f>;
2217 defm S_MOVRELD_B32 : SOP1_Real_gfx6_gfx7_gfx10<0x030>;
2218 defm S_MOVRELD_B64 : SOP1_Real_gfx6_gfx7_gfx10<0x031>;
2219 defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>;
2235 defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>;
2236 defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>;
2237 defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>;
2238 defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>;
2257 defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>;
2258 defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>;
2259 defm S_LSHL_B64 : SOP2_Real_gfx11_gfx12<0x009>;
2260 defm S_LSHR_B32 : SOP2_Real_gfx11_gfx12<0x00a>;
2261 defm S_LSHR_B64 : SOP2_Real_gfx11_gfx12<0x00b>;
2262 defm S_ASHR_I32 : SOP2_Real_gfx11_gfx12<0x00c>;
2263 defm S_ASHR_I64 : SOP2_Real_gfx11_gfx12<0x00d>;
2264 defm S_LSHL1_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00e>;
2265 defm S_LSHL2_ADD_U32 : SOP2_Real_gfx11_gfx12<0x00f>;
2266 defm S_LSHL3_ADD_U32 : SOP2_Real_gfx11_gfx12<0x010>;
2267 defm S_LSHL4_ADD_U32 : SOP2_Real_gfx11_gfx12<0x011>;
2268 defm S_MIN_I32 : SOP2_Real_gfx11_gfx12<0x012>;
2269 defm S_MIN_U32 : SOP2_Real_gfx11_gfx12<0x013>;
2270 defm S_MAX_I32 : SOP2_Real_gfx11_gfx12<0x014>;
2271 defm S_MAX_U32 : SOP2_Real_gfx11_gfx12<0x015>;
2272 defm S_AND_B32 : SOP2_Real_gfx11_gfx12<0x016>;
2273 defm S_AND_B64 : SOP2_Real_gfx11_gfx12<0x017>;
2274 defm S_OR_B32 : SOP2_Real_gfx11_gfx12<0x018>;
2275 defm S_OR_B64 : SOP2_Real_gfx11_gfx12<0x019>;
2276 defm S_XOR_B32 : SOP2_Real_gfx11_gfx12<0x01a>;
2277 defm S_XOR_B64 : SOP2_Real_gfx11_gfx12<0x01b>;
2278 defm S_NAND_B32 : SOP2_Real_gfx11_gfx12<0x01c>;
2279 defm S_NAND_B64 : SOP2_Real_gfx11_gfx12<0x01d>;
2280 defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>;
2281 defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>;
2282 defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>;
2283 defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>;
2284 defm S_ANDN2_B32 : SOP2_Real_gfx11_gfx12<0x022, "s_and_not1_b32">;
2285 defm S_ANDN2_B64 : SOP2_Real_gfx11_gfx12<0x023, "s_and_not1_b64">;
2286 defm S_ORN2_B32 : SOP2_Real_gfx11_gfx12<0x024, "s_or_not1_b32">;
2287 defm S_ORN2_B64 : SOP2_Real_gfx11_gfx12<0x025, "s_or_not1_b64">;
2288 defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>;
2289 defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>;
2290 defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>;
2291 defm S_BFE_I64 : SOP2_Real_gfx11_gfx12<0x029>;
2292 defm S_BFM_B32 : SOP2_Real_gfx11_gfx12<0x02a>;
2293 defm S_BFM_B64 : SOP2_Real_gfx11_gfx12<0x02b>;
2294 defm S_MUL_I32 : SOP2_Real_gfx11_gfx12<0x02c>;
2295 defm S_MUL_HI_U32 : SOP2_Real_gfx11_gfx12<0x02d>;
2296 defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>;
2297 defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>;
2298 defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>;
2299 defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>;
2300 defm S_ADD_U64 : SOP2_Real_gfx12<0x053, "s_add_nc_u64">;
2301 defm S_SUB_U64 : SOP2_Real_gfx12<0x054, "s_sub_nc_u64">;
2302 defm S_MUL_U64 : SOP2_Real_gfx12<0x055>;
2321 defm S_ADD_F32 : SOP2_Real_gfx11_gfx12<0x040>;
2322 defm S_SUB_F32 : SOP2_Real_gfx11_gfx12<0x041>;
2323 defm S_MUL_F32 : SOP2_Real_gfx11_gfx12<0x044>;
2324 defm S_FMAAK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x045>;
2325 defm S_FMAMK_F32 : SOP2_Real_FMAK_gfx11_gfx12<0x046>;
2326 defm S_FMAC_F32 : SOP2_Real_gfx11_gfx12<0x047>;
2327 defm S_CVT_PK_RTZ_F16_F32 : SOP2_Real_gfx11_gfx12<0x048>;
2328 defm S_ADD_F16 : SOP2_Real_gfx11_gfx12<0x049>;
2329 defm S_SUB_F16 : SOP2_Real_gfx11_gfx12<0x04a>;
2330 defm S_MUL_F16 : SOP2_Real_gfx11_gfx12<0x04d>;
2331 defm S_FMAC_F16 : SOP2_Real_gfx11_gfx12<0x04e>;
2340 defm S_MIN_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x042, "s_min_num_f32">;
2341 defm S_MAX_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x043, "s_max_num_f32">;
2342 defm S_MIN_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04b, "s_min_num_f16">;
2343 defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">;
2358 defm S_LSHL1_ADD_U32 : SOP2_Real_gfx10<0x02e>;
2359 defm S_LSHL2_ADD_U32 : SOP2_Real_gfx10<0x02f>;
2360 defm S_LSHL3_ADD_U32 : SOP2_Real_gfx10<0x030>;
2361 defm S_LSHL4_ADD_U32 : SOP2_Real_gfx10<0x031>;
2362 defm S_PACK_LL_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x032>;
2363 defm S_PACK_LH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x033>;
2364 defm S_PACK_HH_B32_B16 : SOP2_Real_gfx10_gfx11_gfx12<0x034>;
2365 defm S_MUL_HI_U32 : SOP2_Real_gfx10<0x035>;
2366 defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>;
2385 defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>;
2387 defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x000, "s_add_co_u32">;
2388 defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x001, "s_sub_co_u32">;
2389 defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x002, "s_add_co_i32">;
2390 defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x003, "s_sub_co_i32">;
2391 defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x004, "s_add_co_ci_u32">;
2392 defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x005, "s_sub_co_ci_u32">;
2393 defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>;
2394 defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>;
2395 defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>;
2396 defm S_MAX_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x009>;
2397 defm S_CSELECT_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00a>;
2398 defm S_CSELECT_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00b>;
2399 defm S_AND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x00e>;
2400 defm S_AND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x00f>;
2401 defm S_OR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x010>;
2402 defm S_OR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x011>;
2403 defm S_XOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x012>;
2404 defm S_XOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x013>;
2405 defm S_ANDN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x014>;
2406 defm S_ANDN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x015>;
2407 defm S_ORN2_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x016>;
2408 defm S_ORN2_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x017>;
2409 defm S_NAND_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x018>;
2410 defm S_NAND_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x019>;
2411 defm S_NOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01a>;
2412 defm S_NOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01b>;
2413 defm S_XNOR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01c>;
2414 defm S_XNOR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01d>;
2415 defm S_LSHL_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x01e>;
2416 defm S_LSHL_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x01f>;
2417 defm S_LSHR_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x020>;
2418 defm S_LSHR_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x021>;
2419 defm S_ASHR_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x022>;
2420 defm S_ASHR_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x023>;
2421 defm S_BFM_B32 : SOP2_Real_gfx6_gfx7_gfx10<0x024>;
2422 defm S_BFM_B64 : SOP2_Real_gfx6_gfx7_gfx10<0x025>;
2423 defm S_MUL_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x026>;
2424 defm S_BFE_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x027>;
2425 defm S_BFE_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x028>;
2426 defm S_BFE_U64 : SOP2_Real_gfx6_gfx7_gfx10<0x029>;
2427 defm S_BFE_I64 : SOP2_Real_gfx6_gfx7_gfx10<0x02a>;
2428 defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>;
2465 defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>;
2466 defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>;
2467 defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>;
2468 defm S_CALL_B64 : SOPK_Real32_gfx11_gfx12<0x014>;
2469 defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx11<0x016>;
2470 defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx11<0x017>;
2471 defm S_WAITCNT_VSCNT : SOPK_Real32_gfx11<0x018>;
2472 defm S_WAITCNT_VMCNT : SOPK_Real32_gfx11<0x019>;
2473 defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx11<0x01a>;
2474 defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx11<0x01b>;
2498 defm S_VERSION : SOPK_Real32_gfx10_gfx11_gfx12<0x001>;
2499 defm S_CALL_B64 : SOPK_Real32_gfx10<0x016>;
2500 defm S_WAITCNT_VSCNT : SOPK_Real32_gfx10<0x017>;
2501 defm S_WAITCNT_VMCNT : SOPK_Real32_gfx10<0x018>;
2502 defm S_WAITCNT_EXPCNT : SOPK_Real32_gfx10<0x019>;
2503 defm S_WAITCNT_LGKMCNT : SOPK_Real32_gfx10<0x01a>;
2504 defm S_SUBVECTOR_LOOP_BEGIN : SOPK_Real32_gfx10<0x01b>;
2505 defm S_SUBVECTOR_LOOP_END : SOPK_Real32_gfx10<0x01c>;
2539 defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>;
2541 defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x000>;
2542 defm S_CMOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>;
2543 defm S_CMPK_EQ_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x003>;
2544 defm S_CMPK_LG_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x004>;
2545 defm S_CMPK_GT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x005>;
2546 defm S_CMPK_GE_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x006>;
2547 defm S_CMPK_LT_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x007>;
2548 defm S_CMPK_LE_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x008>;
2549 defm S_CMPK_EQ_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x009>;
2550 defm S_CMPK_LG_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00a>;
2551 defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00b>;
2552 defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00c>;
2553 defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00d>;
2554 defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00e>;
2555 defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x00f, "s_addk_co_i32">;
2556 defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x010>;
2557 defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>;
2558 defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>;
2559 defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>;
2575 defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>;
2576 defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>;
2577 defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>;
2578 defm S_WAIT_STORECNT : SOPP_Real_32_gfx12<0x041>;
2579 defm S_WAIT_SAMPLECNT : SOPP_Real_32_gfx12<0x042>;
2580 defm S_WAIT_BVHCNT : SOPP_Real_32_gfx12<0x043>;
2581 defm S_WAIT_EXPCNT : SOPP_Real_32_gfx12<0x044>;
2582 defm S_WAIT_DSCNT : SOPP_Real_32_gfx12<0x046>;
2583 defm S_WAIT_KMCNT : SOPP_Real_32_gfx12<0x047>;
2584 defm S_WAIT_LOADCNT_DSCNT : SOPP_Real_32_gfx12<0x048>;
2585 defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>;
2596 SOPPRelaxTable<0, ps.KeyName, "_gfx11">;
2636 defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>;
2637 defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>;
2638 defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>;
2639 defm S_INST_PREFETCH : SOPP_Real_32_gfx11<0x004, "s_set_inst_prefetch_distance">;
2640 defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>;
2641 defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>;
2642 defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11_Renamed_gfx12<0x008, "s_wait_alu">;
2643 defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>;
2644 defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>;
2645 defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>;
2646 defm S_TRAP : SOPP_Real_32_gfx11_gfx12<0x010>;
2647 defm S_ROUND_MODE : SOPP_Real_32_gfx11_gfx12<0x011>;
2648 defm S_DENORM_MODE : SOPP_Real_32_gfx11_gfx12<0x012>;
2649 defm S_BRANCH : SOPP_Real_With_Relaxation_gfx11_gfx12<0x020>;
2650 defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x021>;
2651 defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx11_gfx12<0x022>;
2652 defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x023>;
2653 defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x024>;
2654 defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x025>;
2655 defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx11_gfx12<0x026>;
2656 defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx11<0x027>;
2657 defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx11<0x028>;
2658 defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx11<0x029>;
2659 defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx11<0x02a>;
2660 defm S_ENDPGM : SOPP_Real_32_gfx11_gfx12<0x030>;
2661 defm S_ENDPGM_SAVED : SOPP_Real_32_gfx11_gfx12<0x031>;
2662 defm S_WAKEUP : SOPP_Real_32_gfx11_gfx12<0x034>;
2663 defm S_SETPRIO : SOPP_Real_32_gfx11_gfx12<0x035>;
2664 defm S_SENDMSG : SOPP_Real_32_gfx11_gfx12<0x036>;
2665 defm S_SENDMSGHALT : SOPP_Real_32_gfx11_gfx12<0x037>;
2666 defm S_INCPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x038>;
2667 defm S_DECPERFLEVEL : SOPP_Real_32_gfx11_gfx12<0x039>;
2668 defm S_TTRACEDATA : SOPP_Real_32_gfx11_gfx12<0x03a>;
2669 defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx11_gfx12<0x03b>;
2670 defm S_ICACHE_INV : SOPP_Real_32_gfx11_gfx12<0x03c>;
2672 defm S_BARRIER : SOPP_Real_32_gfx11<0x03d>;
2678 defm S_SINGLEUSE_VDST : SOPP_Real_32_gfx11_gfx12<0x013>;
2688 SOPPRelaxTable<0, ps.KeyName, "_gfx6_gfx7">;
2695 SOPPRelaxTable<0, ps.KeyName, "_vi">;
2702 SOPPRelaxTable<0, ps.KeyName, "_gfx10">;
2755 defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x000>;
2756 defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001>;
2757 defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>;
2758 defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>;
2759 defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>;
2760 defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00d>;
2761 defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00b>;
2762 defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00e>;
2763 defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00f>;
2764 defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x010>;
2765 defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x011>;
2766 defm S_TRAP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x012>;
2767 defm S_ICACHE_INV : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x013>;
2768 defm S_INCPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x014>;
2769 defm S_DECPERFLEVEL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x015>;
2770 defm S_TTRACEDATA : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x016>;
2771 defm S_ENDPGM_SAVED : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x01B>;
2772 defm S_SET_GPR_IDX_OFF : SOPP_Real_32_gfx8_gfx9<0x01c>;
2773 defm S_SET_GPR_IDX_MODE : SOPP_Real_32_gfx8_gfx9<0x01d>;
2774 defm S_ENDPGM_ORDERED_PS_DONE : SOPP_Real_32_gfx8_gfx9_gfx10<0x01e>;
2775 defm S_CODE_END : SOPP_Real_32_gfx10_gfx11_gfx12<0x01f>;
2776 defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>;
2777 defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>;
2778 defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>;
2779 defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10<0x023>;
2780 defm S_ROUND_MODE : SOPP_Real_32_gfx10<0x024>;
2781 defm S_DENORM_MODE : SOPP_Real_32_gfx10<0x025>;
2782 defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10<0x028>;
2785 defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x002>;
2786 defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x004>;
2787 defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x005>;
2788 defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x006>;
2789 defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x007>;
2790 defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x008>;
2791 defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x009>;
2792 defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x017>;
2793 defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x018>;
2794 defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x019>;
2795 defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x01A>;
2815 defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>;
2816 defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>;
2822 defm S_CMP_LT_F32 : SOPC_Real_gfx11_gfx12<0x41>;
2823 defm S_CMP_EQ_F32 : SOPC_Real_gfx11_gfx12<0x42>;
2824 defm S_CMP_LE_F32 : SOPC_Real_gfx11_gfx12<0x43>;
2825 defm S_CMP_GT_F32 : SOPC_Real_gfx11_gfx12<0x44>;
2826 defm S_CMP_LG_F32 : SOPC_Real_gfx11_gfx12<0x45>;
2827 defm S_CMP_GE_F32 : SOPC_Real_gfx11_gfx12<0x46>;
2828 defm S_CMP_O_F32 : SOPC_Real_gfx11_gfx12<0x47>;
2829 defm S_CMP_U_F32 : SOPC_Real_gfx11_gfx12<0x48>;
2830 defm S_CMP_NGE_F32 : SOPC_Real_gfx11_gfx12<0x49>;
2831 defm S_CMP_NLG_F32 : SOPC_Real_gfx11_gfx12<0x4a>;
2832 defm S_CMP_NGT_F32 : SOPC_Real_gfx11_gfx12<0x4b>;
2833 defm S_CMP_NLE_F32 : SOPC_Real_gfx11_gfx12<0x4c>;
2834 defm S_CMP_NEQ_F32 : SOPC_Real_gfx11_gfx12<0x4d>;
2835 defm S_CMP_NLT_F32 : SOPC_Real_gfx11_gfx12<0x4e>;
2837 defm S_CMP_LT_F16 : SOPC_Real_gfx11_gfx12<0x51>;
2838 defm S_CMP_EQ_F16 : SOPC_Real_gfx11_gfx12<0x52>;
2839 defm S_CMP_LE_F16 : SOPC_Real_gfx11_gfx12<0x53>;
2840 defm S_CMP_GT_F16 : SOPC_Real_gfx11_gfx12<0x54>;
2841 defm S_CMP_LG_F16 : SOPC_Real_gfx11_gfx12<0x55>;
2842 defm S_CMP_GE_F16 : SOPC_Real_gfx11_gfx12<0x56>;
2843 defm S_CMP_O_F16 : SOPC_Real_gfx11_gfx12<0x57>;
2844 defm S_CMP_U_F16 : SOPC_Real_gfx11_gfx12<0x58>;
2845 defm S_CMP_NGE_F16 : SOPC_Real_gfx11_gfx12<0x59>;
2846 defm S_CMP_NLG_F16 : SOPC_Real_gfx11_gfx12<0x5a>;
2847 defm S_CMP_NGT_F16 : SOPC_Real_gfx11_gfx12<0x5b>;
2848 defm S_CMP_NLE_F16 : SOPC_Real_gfx11_gfx12<0x5c>;
2849 defm S_CMP_NEQ_F16 : SOPC_Real_gfx11_gfx12<0x5d>;
2850 defm S_CMP_NLT_F16 : SOPC_Real_gfx11_gfx12<0x5e>;
2884 defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x00>;
2885 defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x01>;
2886 defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x02>;
2887 defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x03>;
2888 defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x04>;
2889 defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x05>;
2890 defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x06>;
2891 defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x07>;
2892 defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x08>;
2893 defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x09>;
2894 defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0a>;
2895 defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0b>;
2896 defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0c>;
2897 defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0d>;
2898 defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0e>;
2899 defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0f>;
2900 defm S_SETVSKIP : SOPC_Real_gfx6_gfx7_gfx8_gfx9<0x10>;
2901 defm S_SET_GPR_IDX_ON : SOPC_Real_gfx8_gfx9<0x11>;
2902 defm S_CMP_EQ_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x12>;
2903 defm S_CMP_LG_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x13>;
2921 def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>;
2922 def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>;
2923 def S_CMOV_B32_vi : SOP1_Real_vi <0x02, S_CMOV_B32>;
2924 def S_CMOV_B64_vi : SOP1_Real_vi <0x03, S_CMOV_B64>;
2925 def S_NOT_B32_vi : SOP1_Real_vi <0x04, S_NOT_B32>;
2926 def S_NOT_B64_vi : SOP1_Real_vi <0x05, S_NOT_B64>;
2927 def S_WQM_B32_vi : SOP1_Real_vi <0x06, S_WQM_B32>;
2928 def S_WQM_B64_vi : SOP1_Real_vi <0x07, S_WQM_B64>;
2929 def S_BREV_B32_vi : SOP1_Real_vi <0x08, S_BREV_B32>;
2930 def S_BREV_B64_vi : SOP1_Real_vi <0x09, S_BREV_B64>;
2931 def S_BCNT0_I32_B32_vi : SOP1_Real_vi <0x0a, S_BCNT0_I32_B32>;
2932 def S_BCNT0_I32_B64_vi : SOP1_Real_vi <0x0b, S_BCNT0_I32_B64>;
2933 def S_BCNT1_I32_B32_vi : SOP1_Real_vi <0x0c, S_BCNT1_I32_B32>;
2934 def S_BCNT1_I32_B64_vi : SOP1_Real_vi <0x0d, S_BCNT1_I32_B64>;
2935 def S_FF0_I32_B32_vi : SOP1_Real_vi <0x0e, S_FF0_I32_B32>;
2936 def S_FF0_I32_B64_vi : SOP1_Real_vi <0x0f, S_FF0_I32_B64>;
2937 def S_FF1_I32_B32_vi : SOP1_Real_vi <0x10, S_FF1_I32_B32>;
2938 def S_FF1_I32_B64_vi : SOP1_Real_vi <0x11, S_FF1_I32_B64>;
2939 def S_FLBIT_I32_B32_vi : SOP1_Real_vi <0x12, S_FLBIT_I32_B32>;
2940 def S_FLBIT_I32_B64_vi : SOP1_Real_vi <0x13, S_FLBIT_I32_B64>;
2941 def S_FLBIT_I32_vi : SOP1_Real_vi <0x14, S_FLBIT_I32>;
2942 def S_FLBIT_I32_I64_vi : SOP1_Real_vi <0x15, S_FLBIT_I32_I64>;
2943 def S_SEXT_I32_I8_vi : SOP1_Real_vi <0x16, S_SEXT_I32_I8>;
2944 def S_SEXT_I32_I16_vi : SOP1_Real_vi <0x17, S_SEXT_I32_I16>;
2945 def S_BITSET0_B32_vi : SOP1_Real_vi <0x18, S_BITSET0_B32>;
2946 def S_BITSET0_B64_vi : SOP1_Real_vi <0x19, S_BITSET0_B64>;
2947 def S_BITSET1_B32_vi : SOP1_Real_vi <0x1a, S_BITSET1_B32>;
2948 def S_BITSET1_B64_vi : SOP1_Real_vi <0x1b, S_BITSET1_B64>;
2949 def S_GETPC_B64_vi : SOP1_Real_vi <0x1c, S_GETPC_B64>;
2950 def S_SETPC_B64_vi : SOP1_Real_vi <0x1d, S_SETPC_B64>;
2951 def S_SWAPPC_B64_vi : SOP1_Real_vi <0x1e, S_SWAPPC_B64>;
2952 def S_RFE_B64_vi : SOP1_Real_vi <0x1f, S_RFE_B64>;
2953 def S_AND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x20, S_AND_SAVEEXEC_B64>;
2954 def S_OR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x21, S_OR_SAVEEXEC_B64>;
2955 def S_XOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x22, S_XOR_SAVEEXEC_B64>;
2956 def S_ANDN2_SAVEEXEC_B64_vi: SOP1_Real_vi <0x23, S_ANDN2_SAVEEXEC_B64>;
2957 def S_ORN2_SAVEEXEC_B64_vi : SOP1_Real_vi <0x24, S_ORN2_SAVEEXEC_B64>;
2958 def S_NAND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x25, S_NAND_SAVEEXEC_B64>;
2959 def S_NOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x26, S_NOR_SAVEEXEC_B64>;
2960 def S_XNOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x27, S_XNOR_SAVEEXEC_B64>;
2961 def S_QUADMASK_B32_vi : SOP1_Real_vi <0x28, S_QUADMASK_B32>;
2962 def S_QUADMASK_B64_vi : SOP1_Real_vi <0x29, S_QUADMASK_B64>;
2963 def S_MOVRELS_B32_vi : SOP1_Real_vi <0x2a, S_MOVRELS_B32>;
2964 def S_MOVRELS_B64_vi : SOP1_Real_vi <0x2b, S_MOVRELS_B64>;
2965 def S_MOVRELD_B32_vi : SOP1_Real_vi <0x2c, S_MOVRELD_B32>;
2966 def S_MOVRELD_B64_vi : SOP1_Real_vi <0x2d, S_MOVRELD_B64>;
2967 def S_CBRANCH_JOIN_vi : SOP1_Real_vi <0x2e, S_CBRANCH_JOIN>;
2968 def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>;
2969 def S_SET_GPR_IDX_IDX_vi : SOP1_Real_vi <0x32, S_SET_GPR_IDX_IDX>;
2971 def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>;
2972 def S_ADD_I32_vi : SOP2_Real_vi <0x02, S_ADD_I32>;
2973 def S_SUB_U32_vi : SOP2_Real_vi <0x01, S_SUB_U32>;
2974 def S_SUB_I32_vi : SOP2_Real_vi <0x03, S_SUB_I32>;
2975 def S_ADDC_U32_vi : SOP2_Real_vi <0x04, S_ADDC_U32>;
2976 def S_SUBB_U32_vi : SOP2_Real_vi <0x05, S_SUBB_U32>;
2977 def S_MIN_I32_vi : SOP2_Real_vi <0x06, S_MIN_I32>;
2978 def S_MIN_U32_vi : SOP2_Real_vi <0x07, S_MIN_U32>;
2979 def S_MAX_I32_vi : SOP2_Real_vi <0x08, S_MAX_I32>;
2980 def S_MAX_U32_vi : SOP2_Real_vi <0x09, S_MAX_U32>;
2981 def S_CSELECT_B32_vi : SOP2_Real_vi <0x0a, S_CSELECT_B32>;
2982 def S_CSELECT_B64_vi : SOP2_Real_vi <0x0b, S_CSELECT_B64>;
2983 def S_AND_B32_vi : SOP2_Real_vi <0x0c, S_AND_B32>;
2984 def S_AND_B64_vi : SOP2_Real_vi <0x0d, S_AND_B64>;
2985 def S_OR_B32_vi : SOP2_Real_vi <0x0e, S_OR_B32>;
2986 def S_OR_B64_vi : SOP2_Real_vi <0x0f, S_OR_B64>;
2987 def S_XOR_B32_vi : SOP2_Real_vi <0x10, S_XOR_B32>;
2988 def S_XOR_B64_vi : SOP2_Real_vi <0x11, S_XOR_B64>;
2989 def S_ANDN2_B32_vi : SOP2_Real_vi <0x12, S_ANDN2_B32>;
2990 def S_ANDN2_B64_vi : SOP2_Real_vi <0x13, S_ANDN2_B64>;
2991 def S_ORN2_B32_vi : SOP2_Real_vi <0x14, S_ORN2_B32>;
2992 def S_ORN2_B64_vi : SOP2_Real_vi <0x15, S_ORN2_B64>;
2993 def S_NAND_B32_vi : SOP2_Real_vi <0x16, S_NAND_B32>;
2994 def S_NAND_B64_vi : SOP2_Real_vi <0x17, S_NAND_B64>;
2995 def S_NOR_B32_vi : SOP2_Real_vi <0x18, S_NOR_B32>;
2996 def S_NOR_B64_vi : SOP2_Real_vi <0x19, S_NOR_B64>;
2997 def S_XNOR_B32_vi : SOP2_Real_vi <0x1a, S_XNOR_B32>;
2998 def S_XNOR_B64_vi : SOP2_Real_vi <0x1b, S_XNOR_B64>;
2999 def S_LSHL_B32_vi : SOP2_Real_vi <0x1c, S_LSHL_B32>;
3000 def S_LSHL_B64_vi : SOP2_Real_vi <0x1d, S_LSHL_B64>;
3001 def S_LSHR_B32_vi : SOP2_Real_vi <0x1e, S_LSHR_B32>;
3002 def S_LSHR_B64_vi : SOP2_Real_vi <0x1f, S_LSHR_B64>;
3003 def S_ASHR_I32_vi : SOP2_Real_vi <0x20, S_ASHR_I32>;
3004 def S_ASHR_I64_vi : SOP2_Real_vi <0x21, S_ASHR_I64>;
3005 def S_BFM_B32_vi : SOP2_Real_vi <0x22, S_BFM_B32>;
3006 def S_BFM_B64_vi : SOP2_Real_vi <0x23, S_BFM_B64>;
3007 def S_MUL_I32_vi : SOP2_Real_vi <0x24, S_MUL_I32>;
3008 def S_BFE_U32_vi : SOP2_Real_vi <0x25, S_BFE_U32>;
3009 def S_BFE_I32_vi : SOP2_Real_vi <0x26, S_BFE_I32>;
3010 def S_BFE_U64_vi : SOP2_Real_vi <0x27, S_BFE_U64>;
3011 def S_BFE_I64_vi : SOP2_Real_vi <0x28, S_BFE_I64>;
3012 def S_CBRANCH_G_FORK_vi : SOP2_Real_vi <0x29, S_CBRANCH_G_FORK>;
3013 def S_ABSDIFF_I32_vi : SOP2_Real_vi <0x2a, S_ABSDIFF_I32>;
3014 def S_PACK_LL_B32_B16_vi : SOP2_Real_vi <0x32, S_PACK_LL_B32_B16>;
3015 def S_PACK_LH_B32_B16_vi : SOP2_Real_vi <0x33, S_PACK_LH_B32_B16>;
3016 def S_PACK_HH_B32_B16_vi : SOP2_Real_vi <0x34, S_PACK_HH_B32_B16>;
3017 def S_RFE_RESTORE_B64_vi : SOP2_Real_vi <0x2b, S_RFE_RESTORE_B64>;
3019 def S_MOVK_I32_vi : SOPK_Real_vi <0x00, S_MOVK_I32>;
3020 def S_CMOVK_I32_vi : SOPK_Real_vi <0x01, S_CMOVK_I32>;
3021 def S_CMPK_EQ_I32_vi : SOPK_Real_vi <0x02, S_CMPK_EQ_I32>;
3022 def S_CMPK_LG_I32_vi : SOPK_Real_vi <0x03, S_CMPK_LG_I32>;
3023 def S_CMPK_GT_I32_vi : SOPK_Real_vi <0x04, S_CMPK_GT_I32>;
3024 def S_CMPK_GE_I32_vi : SOPK_Real_vi <0x05, S_CMPK_GE_I32>;
3025 def S_CMPK_LT_I32_vi : SOPK_Real_vi <0x06, S_CMPK_LT_I32>;
3026 def S_CMPK_LE_I32_vi : SOPK_Real_vi <0x07, S_CMPK_LE_I32>;
3027 def S_CMPK_EQ_U32_vi : SOPK_Real_vi <0x08, S_CMPK_EQ_U32>;
3028 def S_CMPK_LG_U32_vi : SOPK_Real_vi <0x09, S_CMPK_LG_U32>;
3029 def S_CMPK_GT_U32_vi : SOPK_Real_vi <0x0A, S_CMPK_GT_U32>;
3030 def S_CMPK_GE_U32_vi : SOPK_Real_vi <0x0B, S_CMPK_GE_U32>;
3031 def S_CMPK_LT_U32_vi : SOPK_Real_vi <0x0C, S_CMPK_LT_U32>;
3032 def S_CMPK_LE_U32_vi : SOPK_Real_vi <0x0D, S_CMPK_LE_U32>;
3033 def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>;
3034 def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>;
3035 def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
3036 def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
3037 def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
3038 //def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
3039 def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
3042 def S_CALL_B64_vi : SOPK_Real_vi <0x15, S_CALL_B64>;
3048 def S_ANDN1_SAVEEXEC_B64_vi : SOP1_Real_vi<0x33, S_ANDN1_SAVEEXEC_B64>;
3049 def S_ORN1_SAVEEXEC_B64_vi : SOP1_Real_vi<0x34, S_ORN1_SAVEEXEC_B64>;
3050 def S_ANDN1_WREXEC_B64_vi : SOP1_Real_vi<0x35, S_ANDN1_WREXEC_B64>;
3051 def S_ANDN2_WREXEC_B64_vi : SOP1_Real_vi<0x36, S_ANDN2_WREXEC_B64>;
3052 def S_BITREPLICATE_B64_B32_vi : SOP1_Real_vi<0x37, S_BITREPLICATE_B64_B32>;
3058 def S_LSHL1_ADD_U32_vi : SOP2_Real_vi<0x2e, S_LSHL1_ADD_U32>;
3059 def S_LSHL2_ADD_U32_vi : SOP2_Real_vi<0x2f, S_LSHL2_ADD_U32>;
3060 def S_LSHL3_ADD_U32_vi : SOP2_Real_vi<0x30, S_LSHL3_ADD_U32>;
3061 def S_LSHL4_ADD_U32_vi : SOP2_Real_vi<0x31, S_LSHL4_ADD_U32>;
3062 def S_MUL_HI_U32_vi : SOP2_Real_vi<0x2c, S_MUL_HI_U32>;
3063 def S_MUL_HI_I32_vi : SOP2_Real_vi<0x2d, S_MUL_HI_I32>;