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/linux/drivers/gpu/drm/vc4/
H A Dvc4_hdmi_regs.h8 #define VC4_HDMI_PACKET_STRIDE 0x24
11 VC4_INVALID = 0,
183 VC4_HD_REG(HDMI_M_CTL, 0x000c),
184 VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
185 VC4_HD_REG(HDMI_MAI_THR, 0x0018),
186 VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
187 VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
188 VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
189 VC4_HD_REG(HDMI_VID_CTL, 0x0038),
190 VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8195-apusys_pll.c18 #define MT8195_PLL_EN_BIT (0)
19 #define MT8195_PCW_SHIFT (0)
33 .en_mask = 0, \
34 .flags = 0, \
35 .rst_bar_mask = 0, \
42 .tuner_reg = 0, \
43 .tuner_en_reg = 0, \
44 .tuner_en_bit = 0, \
47 .pcw_chg_reg = 0, \
48 .en_reg = 0, \
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-pcs-pcie-v6_20.h10 #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15 #define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0
16 #define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4
17 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
18 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
[all …]
H A Dphy-qcom-qmp-pcs-pcie-v5_20.h10 #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
12 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
13 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
14 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
15 #define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
16 #define QPHY_PCIE_V5_20_PCS_G3_RXEQEVAL_TIME 0x0f0
17 #define QPHY_PCIE_V5_20_PCS_G4_RXEQEVAL_TIME 0x0f4
18 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
19 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
[all …]
H A Dphy-qcom-qmp-pcs-usb-v5.h10 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
H A Dphy-qcom-qmp-pcs-usb-v4.h10 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000
11 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004
12 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008
13 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c
14 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010
15 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014
16 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018
17 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c
18 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020
19 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024
[all …]
H A Dphy-qcom-qmp-dp-phy.h10 #define QSERDES_DP_PHY_REVISION_ID0 0x000
11 #define QSERDES_DP_PHY_REVISION_ID1 0x004
12 #define QSERDES_DP_PHY_REVISION_ID2 0x008
13 #define QSERDES_DP_PHY_REVISION_ID3 0x00c
14 #define QSERDES_DP_PHY_CFG 0x010
15 #define QSERDES_DP_PHY_CFG_1 0x014
16 #define QSERDES_DP_PHY_PD_CTL 0x018
17 #define QSERDES_DP_PHY_MODE 0x01c
18 #define QSERDES_DP_PHY_AUX_CFG0 0x020
19 #define QSERDES_DP_PHY_AUX_CFG1 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v3.h10 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008
12 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c
13 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c
14 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024
15 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028
16 #define QSERDES_V3_TX_TX_BAND 0x02c
17 #define QSERDES_V3_TX_SLEW_CNTL 0x030
18 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034
19 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v8.h10 #define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1 0x000
11 #define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1 0x004
12 #define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1 0x008
13 #define QSERDES_V8_COM_CP_CTRL_MODE1 0x010
14 #define QSERDES_V8_COM_PLL_RCTRL_MODE1 0x014
15 #define QSERDES_V8_COM_PLL_CCTRL_MODE1 0x018
16 #define QSERDES_V8_COM_CORECLK_DIV_MODE1 0x01c
17 #define QSERDES_V8_COM_LOCK_CMP1_MODE1 0x020
18 #define QSERDES_V8_COM_LOCK_CMP2_MODE1 0x024
19 #define QSERDES_V8_COM_DEC_START_MODE1 0x028
[all …]
H A Dphy-qcom-qmp-qserdes-pll.h10 #define QSERDES_PLL_BG_TIMER 0x00c
11 #define QSERDES_PLL_SSC_EN_CENTER 0x010
12 #define QSERDES_PLL_SSC_ADJ_PER1 0x014
13 #define QSERDES_PLL_SSC_ADJ_PER2 0x018
14 #define QSERDES_PLL_SSC_PER1 0x01c
15 #define QSERDES_PLL_SSC_PER2 0x020
16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024
17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028
18 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c
19 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030
[all …]
/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_wo.h37 MTK_WED_WO_EVT_LOG_DUMP = 0x1,
38 MTK_WED_WO_EVT_PROFILING = 0x2,
39 MTK_WED_WO_EVT_RXCNT_INFO = 0x3,
47 MTK_WED_WARP_CMD_FLAG_RSP = BIT(0),
52 #define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR 0x15194050
53 #define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK 0x20
54 #define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK 0x1
97 #define MTK_WO_MCU_CFG_LS_BASE 0
98 #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x000)
99 #define MTK_WO_MCU_CFG_LS_FW_VER_ADDR (MTK_WO_MCU_CFG_LS_BASE + 0x004)
[all …]
/linux/drivers/video/fbdev/via/
H A Daccel.h14 #define MMIO_VGABASE 0x8000
15 #define MMIO_CR_READ (MMIO_VGABASE + 0x3D4)
16 #define MMIO_CR_WRITE (MMIO_VGABASE + 0x3D5)
17 #define MMIO_SR_READ (MMIO_VGABASE + 0x3C4)
18 #define MMIO_SR_WRITE (MMIO_VGABASE + 0x3C5)
21 #define HW_Cursor_ON 0
27 #define VIA_MMIO_BLTBASE 0x200000
28 #define VIA_MMIO_BLTSIZE 0x200000
31 #define VIA_REG_GECMD 0x000
32 #define VIA_REG_GEMODE 0x004
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dbrcm,spi-bcm-qspi.yaml103 reg = <0xf03e3400 0x188>, <0xf03e3200 0x50>, <0xf03e0920 0x4>;
105 interrupts = <0x5>, <0x6>, <0x1>, <0x2>, <0x3>, <0x4>, <0x0>;
115 #address-cells = <0x1>;
116 #size-cells = <0x0>;
118 flash@0 {
119 #size-cells = <0x2>;
120 #address-cells = <0x2>;
122 reg = <0x0>;
123 spi-max-frequency = <0x2625a00>;
132 reg = <0xf0416000 0x180>;
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_reg_hdr.h10 #define MDP_HDR_TOP (0x000)
11 #define MDP_HDR_RELAY (0x004)
12 #define MDP_HDR_SIZE_0 (0x014)
13 #define MDP_HDR_SIZE_1 (0x018)
14 #define MDP_HDR_SIZE_2 (0x01C)
15 #define MDP_HDR_HIST_CTRL_0 (0x020)
16 #define MDP_HDR_HIST_CTRL_1 (0x024)
17 #define MDP_HDR_HIST_ADDR (0x0DC)
18 #define MDP_HDR_TILE_POS (0x118)
21 #define MDP_HDR_RELAY_MASK (0x01)
[all …]
H A Dmdp_reg_rsz.h10 #define PRZ_ENABLE 0x000
11 #define PRZ_CONTROL_1 0x004
12 #define PRZ_CONTROL_2 0x008
13 #define PRZ_INPUT_IMAGE 0x010
14 #define PRZ_OUTPUT_IMAGE 0x014
15 #define PRZ_HORIZONTAL_COEFF_STEP 0x018
16 #define PRZ_VERTICAL_COEFF_STEP 0x01c
17 #define PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET 0x020
18 #define PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET 0x024
19 #define PRZ_LUMA_VERTICAL_INTEGER_OFFSET 0x028
[all …]
H A Dmdp_reg_wdma.h10 #define WDMA_EN 0x008
11 #define WDMA_RST 0x00c
12 #define WDMA_CFG 0x014
13 #define WDMA_SRC_SIZE 0x018
14 #define WDMA_CLIP_SIZE 0x01c
15 #define WDMA_CLIP_COORD 0x020
16 #define WDMA_DST_W_IN_BYTE 0x028
17 #define WDMA_ALPHA 0x02c
18 #define WDMA_BUF_CON2 0x03c
19 #define WDMA_DST_UV_PITCH 0x078
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhikey970-pinctrl.dtsi16 reg = <0x0 0xe896c000 0x0 0x72c>;
18 #gpio-range-cells = <0x3>;
19 pinctrl-single,register-width = <0x20>;
20 pinctrl-single,function-mask = <0x7>;
22 pinctrl-single,gpio-range = <&range 0 82 0>;
26 0x054 MUX_M2 /* UART0_RXD */
27 0x058 MUX_M2 /* UART0_TXD */
33 0x700 MUX_M2 /* UART2_CTS_N */
34 0x704 MUX_M2 /* UART2_RTS_N */
35 0x708 MUX_M2 /* UART2_RXD */
[all …]
/linux/include/linux/amba/
H A Dsp810.h18 #define SCCTRL 0x000
19 #define SCSYSSTAT 0x004
20 #define SCIMCTRL 0x008
21 #define SCIMSTAT 0x00C
22 #define SCXTALCTRL 0x010
23 #define SCPLLCTRL 0x014
24 #define SCPLLFCTRL 0x018
25 #define SCPERCTRL0 0x01C
26 #define SCPERCTRL1 0x020
27 #define SCPEREN 0x024
[all …]
/linux/drivers/media/usb/gspca/
H A Dstk1135.h8 #define STK1135_REG_GCTRL 0x000 /* GPIO control */
9 #define STK1135_REG_ICTRL 0x004 /* Interrupt control */
10 #define STK1135_REG_IDATA 0x008 /* Interrupt data */
11 #define STK1135_REG_RMCTL 0x00c /* Remote wakeup control */
12 #define STK1135_REG_POSVA 0x010 /* Power-on strapping data */
14 #define STK1135_REG_SENSO 0x018 /* Sensor select options */
15 #define STK1135_REG_PLLFD 0x01c /* PLL frequency divider */
17 #define STK1135_REG_SCTRL 0x100 /* Sensor control register */
18 #define STK1135_REG_DCTRL 0x104 /* Decimation control register */
19 #define STK1135_REG_CISPO 0x110 /* Capture image starting position */
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]

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