1*73e00953SMoudy Ho /* SPDX-License-Identifier: GPL-2.0-only */ 2*73e00953SMoudy Ho /* 3*73e00953SMoudy Ho * Copyright (c) 2022 MediaTek Inc. 4*73e00953SMoudy Ho * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> 5*73e00953SMoudy Ho */ 6*73e00953SMoudy Ho 7*73e00953SMoudy Ho #ifndef __MDP_REG_HDR_H__ 8*73e00953SMoudy Ho #define __MDP_REG_HDR_H__ 9*73e00953SMoudy Ho 10*73e00953SMoudy Ho #define MDP_HDR_TOP (0x000) 11*73e00953SMoudy Ho #define MDP_HDR_RELAY (0x004) 12*73e00953SMoudy Ho #define MDP_HDR_SIZE_0 (0x014) 13*73e00953SMoudy Ho #define MDP_HDR_SIZE_1 (0x018) 14*73e00953SMoudy Ho #define MDP_HDR_SIZE_2 (0x01C) 15*73e00953SMoudy Ho #define MDP_HDR_HIST_CTRL_0 (0x020) 16*73e00953SMoudy Ho #define MDP_HDR_HIST_CTRL_1 (0x024) 17*73e00953SMoudy Ho #define MDP_HDR_HIST_ADDR (0x0DC) 18*73e00953SMoudy Ho #define MDP_HDR_TILE_POS (0x118) 19*73e00953SMoudy Ho 20*73e00953SMoudy Ho /* MASK */ 21*73e00953SMoudy Ho #define MDP_HDR_RELAY_MASK (0x01) 22*73e00953SMoudy Ho #define MDP_HDR_TOP_MASK (0xFF0FEB6D) 23*73e00953SMoudy Ho #define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF) 24*73e00953SMoudy Ho #define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF) 25*73e00953SMoudy Ho #define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF) 26*73e00953SMoudy Ho #define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF) 27*73e00953SMoudy Ho #define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF) 28*73e00953SMoudy Ho #define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F) 29*73e00953SMoudy Ho #define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF) 30*73e00953SMoudy Ho 31*73e00953SMoudy Ho #endif // __MDP_REG_HDR_H__ 32