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/linux/Documentation/userspace-api/media/v4l/
H A Dsubdev-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
23 - ``height``
[all …]
H A Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
50 Less Than 8 Bits Per Component
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
[all …]
H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
[all …]
H A Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
24 bytes. Each of the first 4 bytes contain the 8 high order bits
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
29 with alternating green-red and green-blue rows. They are conventionally
38 .. flat-table::
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H A Dmt2110t.svg1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later -->
3 <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
4 …-rule="evenodd" stroke-width="28.222" stroke-linejoin="round" xmlns="http://www.w3.org/2000/svg" x…
14 <font id="EmbeddedFont_1" horiz-adv-x="2048">
15 …<font-face font-family="Liberation Sans embedded" units-per-em="2048" font-weight="normal" font-st…
16 <missing-glyph horiz-adv-x="2048" d="M 0,0 L 2047,0 2047,2047 0,2047 0,0 Z"/>
17 …-adv-x="1033" d="M 191,-425 C 142,-425 100,-421 67,-414 L 67,-279 C 92,-283 120,-285 151,-285 263,…
18 …<glyph unicode="x" horiz-adv-x="1006" d="M 801,0 L 510,444 217,0 23,0 408,556 41,1082 240,1082 510…
19 …glyph unicode="w" horiz-adv-x="1509" d="M 1174,0 L 965,0 776,765 740,934 C 734,904 725,861 712,805…
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/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/gpu/drm/exynos/regs-gsc.h
7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
18 #define GSC_ENABLE_CLK_GATE_MODE_MASK (1 << 8)
19 #define GSC_ENABLE_CLK_GATE_MODE_FREE (1 << 8)
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
45 /* G-Scaler input control */
70 #define GSC_IN_FORMAT_MASK (7 << 8)
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/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
29 /* G-Scaler input control */
50 #define GSC_IN_FORMAT_MASK (7 << 8)
51 #define GSC_IN_XRGB8888 (0 << 8)
52 #define GSC_IN_RGB565 (1 << 8)
[all …]
/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
22 corresponds to a color channel (i.e. R, G, B, X, A, Y, Cb, Cr).
32 * Component 1: G
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
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/linux/arch/arm/crypto/
H A Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
75 .arch armv8-a
76 .fpu crypto-neon-fp-armv8
118 vld1.64 {q11-q12}, [buf]!
125 CPU_LE( vrev64.8 q11, q11 )
126 CPU_LE( vrev64.8 q12, q12 )
130 veor.8 \reg1, \reg1, q8
131 veor.8 \reg2, \reg2, q9
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/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
32 /* LARB 0 -- MMSYS */
[all …]
H A Dmt8195-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
[all …]
/linux/tools/perf/util/
H A Dsvghelper.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * svghelper.c - helper functions for outputting svg
62 X = 1.0 * svg_page_width * (__time - first_time) / (last_time - first_time); in time2pixels()
77 while (loop--) { in round_text_size()
102 new_width = (last_time - first_tim in open_svg()
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/linux/arch/x86/crypto/
H A Dpolyval-clmulni_asm.S1 /* SPDX-License-Identifier: GPL-2.0 */
6 * This is an efficient implementation of POLYVAL using intel PCLMULQDQ-NI
7 * instructions. It works on 8 blocks at a time, by precomputing the first 8
8 * keys powers h^8, ..., h^1 in the POLYVAL finite field. This precomputation
12 * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
16 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
18 * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
20 * two-step process only requires 1 finite field reduction for every 8
28 #define STRIDE_BLOCKS 8
54 * Performs schoolbook1_iteration on two lists of 128-bit polynomials of length
[all …]
H A Dsm3-avx-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * specified in: https://datatracker.ietf.org/doc/html/draft-sca-cfrg-sm3-02
22 #define state_h2 8
34 #define K1 -208106958 /* 0xf3988a32 */
35 #define K2 -416213915 /* 0xe7311465 */
36 #define K3 -832427829 /* 0xce6228cb */
37 #define K4 -1664855657 /* 0x9cc45197 */
40 #define K7 -433943364 /* 0xe6228cbc */
41 #define K8 -867886727 /* 0xcc451979 */
42 #define K9 -1735773453 /* 0x988a32f3 */
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H A Dsha512-avx2-asm.S2 # Implement fast SHA-512 with AVX2 instructions. (x86_64)
22 # - Redistributions of source code must retain the above
26 # - Redistributions in binary form must reproduce the above
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
91 g = %r10 define
101 XFER_SIZE = 4*8
102 SRND_SIZE = 1*8
103 INP_SIZE = 1*8
104 INPEND_SIZE = 1*8
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/linux/arch/arm64/crypto/
H A Dcrct10dif-ce-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
14 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
62 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
69 .arch armv8-a+crypto
116 movi perm4.8b, #8
119 ushr perm2.2d, perm1.2d, #8
136 ext t4.8b, ad.8b, ad.8b, #1 // A1
137 ext t5.8b, ad.8b, ad.8b, #2 // A2
138 ext t6.8b, ad.8b, ad.8b, #3 // A3
140 pmull t4.8h, t4.8b, fold_consts.8b // F = A1*B
[all …]
H A Dpolyval-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
9 * It works on 8 blocks at a time, by precomputing the first 8 keys powers h^8,
14 * than 128. We then compute p(x) = h^8m_0 + ... + h^1m_7 where multiplication
18 * modulus g(x) = x^128 + x^127 + x^126 + x^121 + 1.
20 * This two step process is equivalent to computing h^8m_0 + ... + h^1m_7 where
22 * two-step process only requires 1 finite field reduction for every 8
28 #define STRIDE_BLOCKS 8
65 .arch armv8-a+crypto
72 * Computes the product of two 128-bit polynomials in X and Y and XORs the
73 * components of the 256-bit product into LO, MI, HI.
[all …]
/linux/lib/crypto/
H A Dblake2s-generic.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2015-2019 Jason A. Donenfeld <Jason@zx2c4.com>. All Rights Reserved.
20 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 },
21 { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 },
22 { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 },
23 { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 },
24 { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 },
25 { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 },
26 { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 },
27 { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 },
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/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_defs_mfg_comm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
35 BFA_MFG_TYPE_FC8P2 = 825, /*!< 8G 2port FC card */
36 BFA_MFG_TYPE_FC8P1 = 815, /*!< 8G 1port FC card */
37 BFA_MFG_TYPE_FC4P2 = 425, /*!< 4G 2port FC card */
38 BFA_MFG_TYPE_FC4P1 = 415, /*!< 4G 1port FC card */
39 BFA_MFG_TYPE_CNA10P2 = 1020, /*!< 10G 2port CNA card */
40 BFA_MFG_TYPE_CNA10P1 = 1010, /*!< 10G 1port CNA card */
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h1 /* SPDX-License-Identifier: GPL-2.0+
7 /* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100.
25 TARGET_ANA_L3 = 8,
87 #define ANA_AC_PROBE_CFG(g) \ argument
88 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4)
127 #define ANA_AC_PROBE_PORT_CFG(g) \ argument
128 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4)
131 #define ANA_AC_PROBE_PORT_CFG1(g) \ argument
132 __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4)
135 #define ANA_AC_PROBE_PORT_CFG2(g) \ argument
[all …]
/linux/drivers/net/ethernet/microchip/lan966x/
H A Dlan966x_regs.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 /* This file is autogenerated by cml-utils 2021-10-10 13:25:08 +0200.
35 #define AFI_PORT_FRM_OUT(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 0, 0, 1, 4) argument
44 #define AFI_PORT_CFG(g) __REG(TARGET_AFI, 0, 1, 98816, g, 10, 8, 4, 0, 1, 4) argument
68 #define ANA_VLANMASK __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 8, 0, 1, 4)
97 #define ANA_MIRRORPORTS_MIRRORPORTS GENMASK(8, 0)
106 #define ANA_EMIRRORPORTS_EMIRRORPORTS GENMASK(8, 0)
113 #define ANA_FLOODING(r) __REG(TARGET_ANA, 0, 1, 29824, 0, 1, 244, 68, r, 8, 4)
161 #define ANA_PGID(g) __REG(TARGET_ANA, 0, 1, 27648, g, 89, 8, 0, 0, 1, 4) argument
163 #define ANA_PGID_PGID GENMASK(8, 0)
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/linux/include/uapi/drm/
H A Ddrm_fourcc.h39 * further describe the buffer's format - for example tiling or compression.
42 * ----------------
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
58 * may preserve meaning - such as number of planes - from the fourcc code,
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
93 * -----------------------
98 * upstream in-kernel or open source userspace user does not apply.
105 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
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/linux/arch/x86/math-emu/
H A Dpoly.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*---------------------------------------------------------------------------+
5 | Header file for the FPU-emu poly*.c source files. |
9 | Australia. E-mail billm@melbpc.org.au |
11 | Declarations and definitions for functions operating on Xsig (12-byte |
12 | extended-significand) quantities. |
14 +---------------------------------------------------------------------------*/
19 /* This 12-byte structure is used to improve the accuracy of computation
21 Intended to be used to get results better than 8-byte computation
22 allows. 9-byte would probably be sufficient.
[all …]
/linux/drivers/gpio/
H A Dgpio-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
6 // based on previous work and know-how from:
32 * the style for 8 lines each for a total of 16 GPIO lines.
48 #define IXP4XX_GPCLK_MUX14 BIT(8)
55 * struct ixp4xx_gpio - IXP4 GPIO state container
58 * @base: remapped I/O-memory base
59 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered,
72 struct ixp4xx_gpio *g = gpiochip_get_data(gc); in ixp4xx_gpio_irq_ack() local
74 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); in ixp4xx_gpio_irq_ack()
82 gpiochip_disable_irq(gc, d->hwirq); in ixp4xx_gpio_mask_irq()
[all …]
/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]

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