1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-dispcc.h> 7#include <dt-bindings/clock/qcom,glymur-gcc.h> 8#include <dt-bindings/clock/qcom,glymur-tcsr.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interconnect/qcom,icc.h> 13#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom,rpmhpd.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/spmi/spmi.h> 22 23#include "glymur-ipcc.h" 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 cpus { 31 #address-cells = <2>; 32 #size-cells = <0>; 33 34 cpu0: cpu@0 { 35 device_type = "cpu"; 36 compatible = "qcom,oryon-2-2"; 37 reg = <0x0 0x0>; 38 enable-method = "psci"; 39 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 40 power-domain-names = "psci", "perf"; 41 next-level-cache = <&l2_0>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 }; 48 }; 49 50 cpu1: cpu@100 { 51 device_type = "cpu"; 52 compatible = "qcom,oryon-2-2"; 53 reg = <0x0 0x100>; 54 enable-method = "psci"; 55 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 56 power-domain-names = "psci", "perf"; 57 next-level-cache = <&l2_0>; 58 }; 59 60 cpu2: cpu@200 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon-2-2"; 63 reg = <0x0 0x200>; 64 enable-method = "psci"; 65 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 66 power-domain-names = "psci", "perf"; 67 next-level-cache = <&l2_0>; 68 }; 69 70 cpu3: cpu@300 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon-2-2"; 73 reg = <0x0 0x300>; 74 enable-method = "psci"; 75 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 76 power-domain-names = "psci", "perf"; 77 next-level-cache = <&l2_0>; 78 }; 79 80 cpu4: cpu@400 { 81 device_type = "cpu"; 82 compatible = "qcom,oryon-2-2"; 83 reg = <0x0 0x400>; 84 enable-method = "psci"; 85 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 86 power-domain-names = "psci", "perf"; 87 next-level-cache = <&l2_0>; 88 }; 89 90 cpu5: cpu@500 { 91 device_type = "cpu"; 92 compatible = "qcom,oryon-2-2"; 93 reg = <0x0 0x500>; 94 enable-method = "psci"; 95 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 96 power-domain-names = "psci", "perf"; 97 next-level-cache = <&l2_0>; 98 }; 99 100 cpu6: cpu@10000 { 101 device_type = "cpu"; 102 compatible = "qcom,oryon-2-1"; 103 reg = <0x0 0x10000>; 104 enable-method = "psci"; 105 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 106 power-domain-names = "psci", "perf"; 107 next-level-cache = <&l2_1>; 108 109 l2_1: l2-cache { 110 compatible = "cache"; 111 cache-level = <2>; 112 cache-unified; 113 }; 114 }; 115 116 cpu7: cpu@10100 { 117 device_type = "cpu"; 118 compatible = "qcom,oryon-2-1"; 119 reg = <0x0 0x10100>; 120 enable-method = "psci"; 121 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 122 power-domain-names = "psci", "perf"; 123 next-level-cache = <&l2_1>; 124 }; 125 126 cpu8: cpu@10200 { 127 device_type = "cpu"; 128 compatible = "qcom,oryon-2-1"; 129 reg = <0x0 0x10200>; 130 enable-method = "psci"; 131 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 132 power-domain-names = "psci", "perf"; 133 next-level-cache = <&l2_1>; 134 }; 135 136 cpu9: cpu@10300 { 137 device_type = "cpu"; 138 compatible = "qcom,oryon-2-1"; 139 reg = <0x0 0x10300>; 140 enable-method = "psci"; 141 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 142 power-domain-names = "psci", "perf"; 143 next-level-cache = <&l2_1>; 144 }; 145 146 cpu10: cpu@10400 { 147 device_type = "cpu"; 148 compatible = "qcom,oryon-2-1"; 149 reg = <0x0 0x10400>; 150 enable-method = "psci"; 151 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 152 power-domain-names = "psci", "perf"; 153 next-level-cache = <&l2_1>; 154 }; 155 156 cpu11: cpu@10500 { 157 device_type = "cpu"; 158 compatible = "qcom,oryon-2-1"; 159 reg = <0x0 0x10500>; 160 enable-method = "psci"; 161 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 162 power-domain-names = "psci", "perf"; 163 next-level-cache = <&l2_1>; 164 }; 165 166 cpu12: cpu@20000 { 167 device_type = "cpu"; 168 compatible = "qcom,oryon-2-1"; 169 reg = <0x0 0x20000>; 170 enable-method = "psci"; 171 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 172 power-domain-names = "psci", "perf"; 173 next-level-cache = <&l2_2>; 174 175 l2_2: l2-cache { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 }; 180 }; 181 182 cpu13: cpu@20100 { 183 device_type = "cpu"; 184 compatible = "qcom,oryon-2-1"; 185 reg = <0x0 0x20100>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 188 power-domain-names = "psci", "perf"; 189 next-level-cache = <&l2_2>; 190 }; 191 192 cpu14: cpu@20200 { 193 device_type = "cpu"; 194 compatible = "qcom,oryon-2-1"; 195 reg = <0x0 0x20200>; 196 enable-method = "psci"; 197 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 198 power-domain-names = "psci", "perf"; 199 next-level-cache = <&l2_2>; 200 }; 201 202 cpu15: cpu@20300 { 203 device_type = "cpu"; 204 compatible = "qcom,oryon-2-1"; 205 reg = <0x0 0x20300>; 206 enable-method = "psci"; 207 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 208 power-domain-names = "psci", "perf"; 209 next-level-cache = <&l2_2>; 210 }; 211 212 cpu16: cpu@20400 { 213 device_type = "cpu"; 214 compatible = "qcom,oryon-2-1"; 215 reg = <0x0 0x20400>; 216 enable-method = "psci"; 217 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 218 power-domain-names = "psci", "perf"; 219 next-level-cache = <&l2_2>; 220 }; 221 222 cpu17: cpu@20500 { 223 device_type = "cpu"; 224 compatible = "qcom,oryon-2-1"; 225 reg = <0x0 0x20500>; 226 enable-method = "psci"; 227 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 228 power-domain-names = "psci", "perf"; 229 next-level-cache = <&l2_2>; 230 }; 231 232 cpu-map { 233 cluster0 { 234 core0 { 235 cpu = <&cpu0>; 236 }; 237 238 core1 { 239 cpu = <&cpu1>; 240 }; 241 242 core2 { 243 cpu = <&cpu2>; 244 }; 245 246 core3 { 247 cpu = <&cpu3>; 248 }; 249 250 core4 { 251 cpu = <&cpu4>; 252 }; 253 254 core5 { 255 cpu = <&cpu5>; 256 }; 257 }; 258 259 cluster1 { 260 core0 { 261 cpu = <&cpu6>; 262 }; 263 264 core1 { 265 cpu = <&cpu7>; 266 }; 267 268 core2 { 269 cpu = <&cpu8>; 270 }; 271 272 core3 { 273 cpu = <&cpu9>; 274 }; 275 276 core4 { 277 cpu = <&cpu10>; 278 }; 279 280 core5 { 281 cpu = <&cpu11>; 282 }; 283 }; 284 285 cpu_map_cluster2: cluster2 { 286 core0 { 287 cpu = <&cpu12>; 288 }; 289 290 core1 { 291 cpu = <&cpu13>; 292 }; 293 294 core2 { 295 cpu = <&cpu14>; 296 }; 297 298 core3 { 299 cpu = <&cpu15>; 300 }; 301 302 core4 { 303 cpu = <&cpu16>; 304 }; 305 306 core5 { 307 cpu = <&cpu17>; 308 }; 309 }; 310 }; 311 312 idle-states { 313 entry-method = "psci"; 314 315 cpu_c4: cpu-sleep-0 { 316 compatible = "arm,idle-state"; 317 idle-state-name = "ret"; 318 arm,psci-suspend-param = <0x00000004>; 319 entry-latency-us = <180>; 320 exit-latency-us = <320>; 321 min-residency-us = <1000>; 322 }; 323 }; 324 325 domain-idle-states { 326 cluster_cl5: cluster-sleep-0 { 327 compatible = "domain-idle-state"; 328 arm,psci-suspend-param = <0x01000054>; 329 entry-latency-us = <2000>; 330 exit-latency-us = <2000>; 331 min-residency-us = <9000>; 332 }; 333 334 domain_ss3: domain-sleep-0 { 335 compatible = "domain-idle-state"; 336 arm,psci-suspend-param = <0x0200c354>; 337 entry-latency-us = <2800>; 338 exit-latency-us = <4400>; 339 min-residency-us = <10150>; 340 }; 341 }; 342 }; 343 344 firmware { 345 scm: scm { 346 compatible = "qcom,scm-glymur", "qcom,scm"; 347 qcom,dload-mode = <&tcsr 0x4000>; 348 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 349 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 350 }; 351 352 scmi { 353 compatible = "arm,scmi"; 354 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 355 mbox-names = "tx", "rx"; 356 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 357 358 #address-cells = <1>; 359 #size-cells = <0>; 360 361 scmi_perf: protocol@13 { 362 reg = <0x13>; 363 #power-domain-cells = <1>; 364 }; 365 }; 366 }; 367 368 clk_virt: interconnect-0 { 369 compatible = "qcom,glymur-clk-virt"; 370 #interconnect-cells = <2>; 371 qcom,bcm-voters = <&apps_bcm_voter>; 372 }; 373 374 mc_virt: interconnect-1 { 375 compatible = "qcom,glymur-mc-virt"; 376 #interconnect-cells = <2>; 377 qcom,bcm-voters = <&apps_bcm_voter>; 378 }; 379 380 pmu { 381 compatible = "arm,armv8-pmuv3"; 382 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 383 }; 384 385 psci { 386 compatible = "arm,psci-1.0"; 387 method = "smc"; 388 389 cpu_pd0: power-domain-cpu0 { 390 #power-domain-cells = <0>; 391 power-domains = <&cluster0_pd>; 392 domain-idle-states = <&cpu_c4>; 393 }; 394 395 cpu_pd1: power-domain-cpu1 { 396 #power-domain-cells = <0>; 397 power-domains = <&cluster0_pd>; 398 domain-idle-states = <&cpu_c4>; 399 }; 400 401 cpu_pd2: power-domain-cpu2 { 402 #power-domain-cells = <0>; 403 power-domains = <&cluster0_pd>; 404 domain-idle-states = <&cpu_c4>; 405 }; 406 407 cpu_pd3: power-domain-cpu3 { 408 #power-domain-cells = <0>; 409 power-domains = <&cluster0_pd>; 410 domain-idle-states = <&cpu_c4>; 411 }; 412 413 cpu_pd4: power-domain-cpu4 { 414 #power-domain-cells = <0>; 415 power-domains = <&cluster0_pd>; 416 domain-idle-states = <&cpu_c4>; 417 }; 418 419 cpu_pd5: power-domain-cpu5 { 420 #power-domain-cells = <0>; 421 power-domains = <&cluster0_pd>; 422 domain-idle-states = <&cpu_c4>; 423 }; 424 425 cpu_pd6: power-domain-cpu6 { 426 #power-domain-cells = <0>; 427 power-domains = <&cluster1_pd>; 428 domain-idle-states = <&cpu_c4>; 429 }; 430 431 cpu_pd7: power-domain-cpu7 { 432 #power-domain-cells = <0>; 433 power-domains = <&cluster1_pd>; 434 domain-idle-states = <&cpu_c4>; 435 }; 436 437 cpu_pd8: power-domain-cpu8 { 438 #power-domain-cells = <0>; 439 power-domains = <&cluster1_pd>; 440 domain-idle-states = <&cpu_c4>; 441 }; 442 443 cpu_pd9: power-domain-cpu9 { 444 #power-domain-cells = <0>; 445 power-domains = <&cluster1_pd>; 446 domain-idle-states = <&cpu_c4>; 447 }; 448 449 cpu_pd10: power-domain-cpu10 { 450 #power-domain-cells = <0>; 451 power-domains = <&cluster1_pd>; 452 domain-idle-states = <&cpu_c4>; 453 }; 454 455 cpu_pd11: power-domain-cpu11 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster1_pd>; 458 domain-idle-states = <&cpu_c4>; 459 }; 460 461 cpu_pd12: power-domain-cpu12 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster2_pd>; 464 domain-idle-states = <&cpu_c4>; 465 }; 466 467 cpu_pd13: power-domain-cpu13 { 468 #power-domain-cells = <0>; 469 power-domains = <&cluster2_pd>; 470 domain-idle-states = <&cpu_c4>; 471 }; 472 473 cpu_pd14: power-domain-cpu14 { 474 #power-domain-cells = <0>; 475 power-domains = <&cluster2_pd>; 476 domain-idle-states = <&cpu_c4>; 477 }; 478 479 cpu_pd15: power-domain-cpu15 { 480 #power-domain-cells = <0>; 481 power-domains = <&cluster2_pd>; 482 domain-idle-states = <&cpu_c4>; 483 }; 484 485 cpu_pd16: power-domain-cpu16 { 486 #power-domain-cells = <0>; 487 power-domains = <&cluster2_pd>; 488 domain-idle-states = <&cpu_c4>; 489 }; 490 491 cpu_pd17: power-domain-cpu17 { 492 #power-domain-cells = <0>; 493 power-domains = <&cluster2_pd>; 494 domain-idle-states = <&cpu_c4>; 495 }; 496 497 cluster0_pd: power-domain-cpu-cluster0 { 498 #power-domain-cells = <0>; 499 power-domains = <&system_pd>; 500 domain-idle-states = <&cluster_cl5>; 501 }; 502 503 cluster1_pd: power-domain-cpu-cluster1 { 504 #power-domain-cells = <0>; 505 power-domains = <&system_pd>; 506 domain-idle-states = <&cluster_cl5>; 507 }; 508 509 cluster2_pd: power-domain-cpu-cluster2 { 510 #power-domain-cells = <0>; 511 power-domains = <&system_pd>; 512 domain-idle-states = <&cluster_cl5>; 513 }; 514 515 system_pd: power-domain-system { 516 #power-domain-cells = <0>; 517 domain-idle-states = <&domain_ss3>; 518 }; 519 }; 520 521 reserved-memory { 522 #address-cells = <2>; 523 #size-cells = <2>; 524 ranges; 525 526 pdp_mem: pdp@81400000 { 527 reg = <0x0 0x81400000 0x0 0x100000>; 528 no-map; 529 }; 530 531 aop_cmd_db_mem: aop-cmd-db@81c60000 { 532 compatible = "qcom,cmd-db"; 533 reg = <0x0 0x81c60000 0x0 0x20000>; 534 no-map; 535 }; 536 537 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 538 reg = <0x0 0x81e00000 0x0 0x200000>; 539 no-map; 540 }; 541 542 oobdaretag_mem: oobdaretag@86e10000 { 543 reg = <0x0 0x86e10000 0x0 0x360000>; 544 no-map; 545 }; 546 547 oob_secure_mem: oob-secure@87170000 { 548 reg = <0x0 0x87170000 0x0 0xbc0000>; 549 no-map; 550 }; 551 552 oobdtbqc_mem: oobdtbqc@87d30000 { 553 reg = <0x0 0x87d30000 0x0 0x20000>; 554 no-map; 555 }; 556 557 oobdtboem_mem: oobdtboem@87d50000 { 558 reg = <0x0 0x87d50000 0x0 0x20000>; 559 no-map; 560 }; 561 562 oob_nonsecure_mem: oob-nonsecure@87e00000 { 563 reg = <0x0 0x87e00000 0x0 0xc00000>; 564 no-map; 565 }; 566 567 spss_region_mem: spss@88a00000 { 568 reg = <0x0 0x88a00000 0x0 0x400000>; 569 no-map; 570 }; 571 572 soccpdtb_mem: soccpdtb@892e0000 { 573 reg = <0x0 0x892e0000 0x0 0x20000>; 574 no-map; 575 }; 576 577 soccp_mem: soccp@89300000 { 578 reg = <0x0 0x89300000 0x0 0x400000>; 579 no-map; 580 }; 581 582 cvp_mem: cvp@89700000 { 583 reg = <0x0 0x89700000 0x0 0x700000>; 584 no-map; 585 }; 586 587 adspslpi_mem: adspslpi@89e00000 { 588 reg = <0x0 0x89e00000 0x0 0x3a00000>; 589 no-map; 590 }; 591 592 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 593 reg = <0x0 0x8d800000 0x0 0x80000>; 594 no-map; 595 }; 596 597 cdsp_mem: cdsp@8d900000 { 598 reg = <0x0 0x8d900000 0x0 0x4000000>; 599 no-map; 600 }; 601 602 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 603 reg = <0x0 0x91900000 0x0 0x80000>; 604 no-map; 605 }; 606 607 gpu_microcode_mem: gpu-microcode@919fe000 { 608 reg = <0x0 0x919fe000 0x0 0x2000>; 609 no-map; 610 }; 611 612 camera_mem: camera@91a00000 { 613 reg = <0x0 0x91a00000 0x0 0x800000>; 614 no-map; 615 }; 616 617 av1_encoder_mem: av1-encoder@92200000 { 618 reg = <0x0 0x92200000 0x0 0x700000>; 619 no-map; 620 }; 621 622 video_mem: video@92900000 { 623 reg = <0x0 0x92900000 0x0 0xc00000>; 624 no-map; 625 }; 626 627 smem_mem: smem@ffe00000 { 628 compatible = "qcom,smem"; 629 reg = <0x0 0xffe00000 0x0 0x200000>; 630 hwlocks = <&tcsr_mutex 3>; 631 no-map; 632 }; 633 }; 634 635 smp2p-adsp { 636 compatible = "qcom,smp2p"; 637 638 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 639 IPCC_MPROC_SIGNAL_SMP2P 640 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 643 644 qcom,smem = <443>, <429>; 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <2>; 647 648 smp2p_adsp_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_adsp_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-cdsp { 661 compatible = "qcom,smp2p"; 662 663 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 664 IPCC_MPROC_SIGNAL_SMP2P 665 IRQ_TYPE_EDGE_RISING>; 666 667 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 668 669 qcom,smem = <94>, <432>; 670 qcom,local-pid = <0>; 671 qcom,remote-pid = <5>; 672 673 smp2p_cdsp_out: master-kernel { 674 qcom,entry-name = "master-kernel"; 675 #qcom,smem-state-cells = <1>; 676 }; 677 678 smp2p_cdsp_in: slave-kernel { 679 qcom,entry-name = "slave-kernel"; 680 interrupt-controller; 681 #interrupt-cells = <2>; 682 }; 683 }; 684 685 smp2p-soccp { 686 compatible = "qcom,smp2p"; 687 688 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 689 IPCC_MPROC_SIGNAL_SMP2P 690 IRQ_TYPE_EDGE_RISING>; 691 692 mboxes = <&ipcc IPCC_MPROC_SOCCP 693 IPCC_MPROC_SIGNAL_SMP2P>; 694 695 qcom,smem = <617>, <616>; 696 qcom,local-pid = <0>; 697 qcom,remote-pid = <19>; 698 699 soccp_smp2p_out: master-kernel { 700 qcom,entry-name = "master-kernel"; 701 #qcom,smem-state-cells = <1>; 702 }; 703 704 soccp_smp2p_in: slave-kernel { 705 qcom,entry-name = "slave-kernel"; 706 interrupt-controller; 707 #interrupt-cells = <2>; 708 }; 709 }; 710 711 soc: soc@0 { 712 compatible = "simple-bus"; 713 #address-cells = <2>; 714 #size-cells = <2>; 715 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 716 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 717 718 gcc: clock-controller@100000 { 719 compatible = "qcom,glymur-gcc"; 720 reg = <0x0 0x00100000 0x0 0x1f9000>; 721 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 722 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 723 <&sleep_clk>, /* Sleep */ 724 <0>, /* USB 0 Phy DP0 GMUX */ 725 <0>, /* USB 0 Phy DP1 GMUX */ 726 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 727 <0>, /* USB 0 Phy PIPEGMUX */ 728 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 729 <0>, /* USB 1 Phy DP0 GMUX 2 */ 730 <0>, /* USB 1 Phy DP1 GMUX 2 */ 731 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 732 <0>, /* USB 1 Phy PIPEGMUX */ 733 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 734 <0>, /* USB 2 Phy DP0 GMUX 2 */ 735 <0>, /* USB 2 Phy DP1 GMUX 2 */ 736 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 737 <0>, /* USB 2 Phy PIPEGMUX */ 738 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 739 <0>, /* PCIe 3a */ 740 <&pcie3b_phy>, /* PCIe 3b */ 741 <&pcie4_phy>, /* PCIe 4 */ 742 <&pcie5_phy>, /* PCIe 5 */ 743 <&pcie6_phy>, /* PCIe 6 */ 744 <0>, /* QUSB4 0 PHY RX 0 */ 745 <0>, /* QUSB4 0 PHY RX 1 */ 746 <0>, /* QUSB4 1 PHY RX 0 */ 747 <0>, /* QUSB4 1 PHY RX 1 */ 748 <0>, /* QUSB4 2 PHY RX 0 */ 749 <0>, /* QUSB4 2 PHY RX 1 */ 750 <0>, /* UFS PHY RX Symbol 0 */ 751 <0>, /* UFS PHY RX Symbol 1 */ 752 <0>, /* UFS PHY TX Symbol 0 */ 753 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 754 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 755 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 756 <&usb_mp_qmpphy0 QMP_USB43DP_USB3_PIPE_CLK>, 757 <&usb_mp_qmpphy1 QMP_USB43DP_USB3_PIPE_CLK>, 758 <0>, /* USB4 PHY 0 pcie pipe */ 759 <0>, /* USB4 PHY 0 Max pipe */ 760 <0>, /* USB4 PHY 1 pcie pipe */ 761 <0>, /* USB4 PHY 1 Max pipe */ 762 <0>, /* USB4 PHY 2 pcie */ 763 <0>; /* USB4 PHY 2 Max */ 764 #clock-cells = <1>; 765 #reset-cells = <1>; 766 #power-domain-cells = <1>; 767 }; 768 769 gpi_dma2: dma-controller@800000 { 770 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 771 reg = <0x0 0x00800000 0x0 0x60000>; 772 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 788 dma-channels = <16>; 789 dma-channel-mask = <0x3f>; 790 #dma-cells = <3>; 791 iommus = <&apps_smmu 0xd76 0x0>; 792 }; 793 794 qupv3_2: geniqup@8c0000 { 795 compatible = "qcom,geni-se-qup"; 796 reg = <0x0 0x008c0000 0x0 0x3000>; 797 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 798 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 799 clock-names = "m-ahb", 800 "s-ahb"; 801 iommus = <&apps_smmu 0xd63 0x0>; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 806 i2c16: i2c@880000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0x0 0x00880000 0x0 0x4000>; 809 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 811 clock-names = "se"; 812 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 813 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 814 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 815 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 816 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 817 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 818 interconnect-names = "qup-core", 819 "qup-config", 820 "qup-memory"; 821 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 822 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 823 dma-names = "tx", 824 "rx"; 825 pinctrl-0 = <&qup_i2c16_data_clk>; 826 pinctrl-names = "default"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 830 status = "disabled"; 831 }; 832 833 spi16: spi@880000 { 834 compatible = "qcom,geni-spi"; 835 reg = <0x0 0x00880000 0x0 0x4000>; 836 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 838 clock-names = "se"; 839 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 840 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 841 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 842 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 843 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 844 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 845 interconnect-names = "qup-core", 846 "qup-config", 847 "qup-memory"; 848 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 849 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 850 dma-names = "tx", 851 "rx"; 852 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 853 pinctrl-names = "default"; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 status = "disabled"; 858 }; 859 860 i2c17: i2c@884000 { 861 compatible = "qcom,geni-i2c"; 862 reg = <0x0 0x00884000 0x0 0x4000>; 863 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 865 clock-names = "se"; 866 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 867 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 868 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 869 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 870 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 871 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 872 interconnect-names = "qup-core", 873 "qup-config", 874 "qup-memory"; 875 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 876 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 877 dma-names = "tx", 878 "rx"; 879 pinctrl-0 = <&qup_i2c17_data_clk>; 880 pinctrl-names = "default"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 884 status = "disabled"; 885 }; 886 887 spi17: spi@884000 { 888 compatible = "qcom,geni-spi"; 889 reg = <0x0 0x00884000 0x0 0x4000>; 890 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 892 clock-names = "se"; 893 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 894 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 895 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 896 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 897 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 898 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 899 interconnect-names = "qup-core", 900 "qup-config", 901 "qup-memory"; 902 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 903 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 904 dma-names = "tx", 905 "rx"; 906 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 907 pinctrl-names = "default"; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 status = "disabled"; 912 }; 913 914 i2c18: i2c@888000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x0 0x00888000 0x0 0x4000>; 917 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 919 clock-names = "se"; 920 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 921 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 922 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 923 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 924 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 925 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 926 interconnect-names = "qup-core", 927 "qup-config", 928 "qup-memory"; 929 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 930 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 931 dma-names = "tx", 932 "rx"; 933 pinctrl-0 = <&qup_i2c18_data_clk>; 934 pinctrl-names = "default"; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 status = "disabled"; 939 }; 940 941 spi18: spi@888000 { 942 compatible = "qcom,geni-spi"; 943 reg = <0x0 0x00888000 0x0 0x4000>; 944 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 946 clock-names = "se"; 947 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 948 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 949 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 950 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 951 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 953 interconnect-names = "qup-core", 954 "qup-config", 955 "qup-memory"; 956 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 957 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 958 dma-names = "tx", 959 "rx"; 960 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 961 pinctrl-names = "default"; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 965 status = "disabled"; 966 }; 967 968 i2c19: i2c@88c000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0x0 0x0088c000 0x0 0x4000>; 971 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 972 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 973 clock-names = "se"; 974 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 975 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 976 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 977 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 978 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 979 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 980 interconnect-names = "qup-core", 981 "qup-config", 982 "qup-memory"; 983 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 984 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 985 dma-names = "tx", 986 "rx"; 987 pinctrl-0 = <&qup_i2c19_data_clk>; 988 pinctrl-names = "default"; 989 #address-cells = <1>; 990 #size-cells = <0>; 991 992 status = "disabled"; 993 }; 994 995 spi19: spi@88c000 { 996 compatible = "qcom,geni-spi"; 997 reg = <0x0 0x0088c000 0x0 0x4000>; 998 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1000 clock-names = "se"; 1001 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1002 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1003 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1004 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1005 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1006 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1007 interconnect-names = "qup-core", 1008 "qup-config", 1009 "qup-memory"; 1010 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1011 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1012 dma-names = "tx", 1013 "rx"; 1014 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1015 pinctrl-names = "default"; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 1019 status = "disabled"; 1020 }; 1021 1022 uart19: serial@88c000 { 1023 compatible = "qcom,geni-uart"; 1024 reg = <0x0 0x0088c000 0x0 0x4000>; 1025 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1027 clock-names = "se"; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1030 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 pinctrl-0 = <&qup_uart19_default>; 1035 pinctrl-names = "default"; 1036 1037 status = "disabled"; 1038 }; 1039 1040 i2c20: i2c@890000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0x0 0x00890000 0x0 0x4000>; 1043 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1045 clock-names = "se"; 1046 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1047 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1048 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1049 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1051 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1052 interconnect-names = "qup-core", 1053 "qup-config", 1054 "qup-memory"; 1055 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1056 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1057 dma-names = "tx", 1058 "rx"; 1059 pinctrl-0 = <&qup_i2c20_data_clk>; 1060 pinctrl-names = "default"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 1064 status = "disabled"; 1065 }; 1066 1067 spi20: spi@890000 { 1068 compatible = "qcom,geni-spi"; 1069 reg = <0x0 0x00890000 0x0 0x4000>; 1070 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1072 clock-names = "se"; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1074 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1075 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1076 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1077 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1079 interconnect-names = "qup-core", 1080 "qup-config", 1081 "qup-memory"; 1082 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1083 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1084 dma-names = "tx", 1085 "rx"; 1086 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1087 pinctrl-names = "default"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 1091 status = "disabled"; 1092 }; 1093 1094 i2c21: i2c@894000 { 1095 compatible = "qcom,geni-i2c"; 1096 reg = <0x0 0x00894000 0x0 0x4000>; 1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1099 clock-names = "se"; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1101 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1102 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1103 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1104 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1106 interconnect-names = "qup-core", 1107 "qup-config", 1108 "qup-memory"; 1109 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1110 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1111 dma-names = "tx", 1112 "rx"; 1113 pinctrl-0 = <&qup_i2c21_data_clk>; 1114 pinctrl-names = "default"; 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 1118 status = "disabled"; 1119 }; 1120 1121 spi21: spi@894000 { 1122 compatible = "qcom,geni-spi"; 1123 reg = <0x0 0x00894000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1126 clock-names = "se"; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1129 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1130 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1131 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1137 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1138 dma-names = "tx", 1139 "rx"; 1140 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1141 pinctrl-names = "default"; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 status = "disabled"; 1146 }; 1147 1148 uart21: serial@894000 { 1149 compatible = "qcom,geni-debug-uart"; 1150 reg = <0x0 0x00894000 0x0 0x4000>; 1151 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1152 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1153 clock-names = "se"; 1154 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1155 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1156 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1157 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1158 interconnect-names = "qup-core", 1159 "qup-config"; 1160 pinctrl-0 = <&qup_uart21_default>; 1161 pinctrl-names = "default"; 1162 }; 1163 1164 i2c22: i2c@898000 { 1165 compatible = "qcom,geni-i2c"; 1166 reg = <0x0 0x00898000 0x0 0x4000>; 1167 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1169 clock-names = "se"; 1170 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1171 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1172 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1173 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1174 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1175 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1176 interconnect-names = "qup-core", 1177 "qup-config", 1178 "qup-memory"; 1179 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1180 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1181 dma-names = "tx", 1182 "rx"; 1183 pinctrl-0 = <&qup_i2c22_data_clk>; 1184 pinctrl-names = "default"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 1188 status = "disabled"; 1189 }; 1190 1191 spi22: spi@898000 { 1192 compatible = "qcom,geni-spi"; 1193 reg = <0x0 0x00898000 0x0 0x4000>; 1194 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1196 clock-names = "se"; 1197 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1198 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1199 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1200 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1201 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1203 interconnect-names = "qup-core", 1204 "qup-config", 1205 "qup-memory"; 1206 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1207 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1208 dma-names = "tx", 1209 "rx"; 1210 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1211 pinctrl-names = "default"; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 1215 status = "disabled"; 1216 }; 1217 1218 uart22: serial@898000 { 1219 compatible = "qcom,geni-uart"; 1220 reg = <0x0 0x00898000 0x0 0x4000>; 1221 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1223 clock-names = "se"; 1224 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1225 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1226 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1227 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1228 interconnect-names = "qup-core", 1229 "qup-config"; 1230 pinctrl-0 = <&qup_uart22_default>; 1231 pinctrl-names = "default"; 1232 1233 status = "disabled"; 1234 }; 1235 1236 i2c23: i2c@89c000 { 1237 compatible = "qcom,geni-i2c"; 1238 reg = <0x0 0x0089c000 0x0 0x4000>; 1239 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1241 clock-names = "se"; 1242 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1243 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1244 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1245 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1246 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1247 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1248 interconnect-names = "qup-core", 1249 "qup-config", 1250 "qup-memory"; 1251 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1252 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1253 dma-names = "tx", 1254 "rx"; 1255 pinctrl-0 = <&qup_i2c23_data_clk>; 1256 pinctrl-names = "default"; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 1260 status = "disabled"; 1261 }; 1262 1263 spi23: spi@89c000 { 1264 compatible = "qcom,geni-spi"; 1265 reg = <0x0 0x0089c000 0x0 0x4000>; 1266 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1267 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1268 clock-names = "se"; 1269 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1270 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1271 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1272 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1273 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1274 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config", 1277 "qup-memory"; 1278 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1279 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1280 dma-names = "tx", 1281 "rx"; 1282 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1283 pinctrl-names = "default"; 1284 #address-cells = <1>; 1285 #size-cells = <0>; 1286 1287 status = "disabled"; 1288 }; 1289 }; 1290 1291 gpi_dma1: dma-controller@a00000 { 1292 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1293 reg = <0x0 0x00a00000 0x0 0x60000>; 1294 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1310 dma-channels = <16>; 1311 dma-channel-mask = <0x3f>; 1312 #dma-cells = <3>; 1313 iommus = <&apps_smmu 0xcb6 0x0>; 1314 }; 1315 1316 qupv3_1: geniqup@ac0000 { 1317 compatible = "qcom,geni-se-qup"; 1318 reg = <0x0 0x00ac0000 0x0 0x3000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1320 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1321 clock-names = "m-ahb", 1322 "s-ahb"; 1323 iommus = <&apps_smmu 0xca3 0x0>; 1324 #address-cells = <2>; 1325 #size-cells = <2>; 1326 ranges; 1327 1328 i2c8: i2c@a80000 { 1329 compatible = "qcom,geni-i2c"; 1330 reg = <0x0 0x00a80000 0x0 0x4000>; 1331 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1333 clock-names = "se"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1336 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1345 dma-names = "tx", 1346 "rx"; 1347 pinctrl-0 = <&qup_i2c8_data_clk>; 1348 pinctrl-names = "default"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 status = "disabled"; 1353 }; 1354 1355 spi8: spi@a80000 { 1356 compatible = "qcom,geni-spi"; 1357 reg = <0x0 0x00a80000 0x0 0x4000>; 1358 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1359 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1360 clock-names = "se"; 1361 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1362 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1363 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1364 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1365 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1366 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1367 interconnect-names = "qup-core", 1368 "qup-config", 1369 "qup-memory"; 1370 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1371 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1372 dma-names = "tx", 1373 "rx"; 1374 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1375 pinctrl-names = "default"; 1376 #address-cells = <1>; 1377 #size-cells = <0>; 1378 1379 status = "disabled"; 1380 }; 1381 1382 i2c9: i2c@a84000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x00a84000 0x0 0x4000>; 1385 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1387 clock-names = "se"; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1389 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1390 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1391 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1392 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1393 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1394 interconnect-names = "qup-core", 1395 "qup-config", 1396 "qup-memory"; 1397 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1398 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1399 dma-names = "tx", 1400 "rx"; 1401 pinctrl-0 = <&qup_i2c9_data_clk>; 1402 pinctrl-names = "default"; 1403 #address-cells = <1>; 1404 #size-cells = <0>; 1405 1406 status = "disabled"; 1407 }; 1408 1409 spi9: spi@a84000 { 1410 compatible = "qcom,geni-spi"; 1411 reg = <0x0 0x00a84000 0x0 0x4000>; 1412 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1414 clock-names = "se"; 1415 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1416 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1417 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1418 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1419 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1420 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1425 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1426 dma-names = "tx", 1427 "rx"; 1428 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1429 pinctrl-names = "default"; 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 status = "disabled"; 1434 }; 1435 1436 i2c10: i2c@a88000 { 1437 compatible = "qcom,geni-i2c"; 1438 reg = <0x0 0x00a88000 0x0 0x4000>; 1439 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1440 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1441 clock-names = "se"; 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1443 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1444 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1445 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1446 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1448 interconnect-names = "qup-core", 1449 "qup-config", 1450 "qup-memory"; 1451 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1452 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1453 dma-names = "tx", 1454 "rx"; 1455 pinctrl-0 = <&qup_i2c10_data_clk>; 1456 pinctrl-names = "default"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 1460 status = "disabled"; 1461 }; 1462 1463 spi10: spi@a88000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0x0 0x00a88000 0x0 0x4000>; 1466 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1467 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1468 clock-names = "se"; 1469 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1470 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1471 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1472 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1473 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1474 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1475 interconnect-names = "qup-core", 1476 "qup-config", 1477 "qup-memory"; 1478 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1479 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1480 dma-names = "tx", 1481 "rx"; 1482 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1483 pinctrl-names = "default"; 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 status = "disabled"; 1488 }; 1489 1490 i2c11: i2c@a8c000 { 1491 compatible = "qcom,geni-i2c"; 1492 reg = <0x0 0x00a8c000 0x0 0x4000>; 1493 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1494 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1495 clock-names = "se"; 1496 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1497 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1498 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1499 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1500 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1501 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1502 interconnect-names = "qup-core", 1503 "qup-config", 1504 "qup-memory"; 1505 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1506 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1507 dma-names = "tx", 1508 "rx"; 1509 pinctrl-0 = <&qup_i2c11_data_clk>; 1510 pinctrl-names = "default"; 1511 #address-cells = <1>; 1512 #size-cells = <0>; 1513 1514 status = "disabled"; 1515 }; 1516 1517 spi11: spi@a8c000 { 1518 compatible = "qcom,geni-spi"; 1519 reg = <0x0 0x00a8c000 0x0 0x4000>; 1520 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1521 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1522 clock-names = "se"; 1523 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1524 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1525 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1526 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1527 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1528 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1529 interconnect-names = "qup-core", 1530 "qup-config", 1531 "qup-memory"; 1532 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1533 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1534 dma-names = "tx", 1535 "rx"; 1536 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1537 pinctrl-names = "default"; 1538 #address-cells = <1>; 1539 #size-cells = <0>; 1540 1541 status = "disabled"; 1542 }; 1543 1544 i2c12: i2c@a90000 { 1545 compatible = "qcom,geni-i2c"; 1546 reg = <0x0 0x00a90000 0x0 0x4000>; 1547 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1549 clock-names = "se"; 1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1551 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1552 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1553 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1554 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1555 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1556 interconnect-names = "qup-core", 1557 "qup-config", 1558 "qup-memory"; 1559 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1560 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1561 dma-names = "tx", 1562 "rx"; 1563 pinctrl-0 = <&qup_i2c12_data_clk>; 1564 pinctrl-names = "default"; 1565 #address-cells = <1>; 1566 #size-cells = <0>; 1567 1568 status = "disabled"; 1569 }; 1570 1571 spi12: spi@a90000 { 1572 compatible = "qcom,geni-spi"; 1573 reg = <0x0 0x00a90000 0x0 0x4000>; 1574 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1575 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1576 clock-names = "se"; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1578 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1579 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1581 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1582 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1583 interconnect-names = "qup-core", 1584 "qup-config", 1585 "qup-memory"; 1586 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1587 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1588 dma-names = "tx", 1589 "rx"; 1590 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1591 pinctrl-names = "default"; 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 status = "disabled"; 1596 }; 1597 1598 i2c13: i2c@a94000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0x0 0x00a94000 0x0 0x4000>; 1601 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1602 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1603 clock-names = "se"; 1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1605 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1606 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1607 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1608 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1609 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1610 interconnect-names = "qup-core", 1611 "qup-config", 1612 "qup-memory"; 1613 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1614 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1615 dma-names = "tx", 1616 "rx"; 1617 pinctrl-0 = <&qup_i2c13_data_clk>; 1618 pinctrl-names = "default"; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 1622 status = "disabled"; 1623 }; 1624 1625 spi13: spi@a94000 { 1626 compatible = "qcom,geni-spi"; 1627 reg = <0x0 0x00a94000 0x0 0x4000>; 1628 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1629 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1630 clock-names = "se"; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1632 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1633 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1634 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1635 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1636 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", 1638 "qup-config", 1639 "qup-memory"; 1640 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1641 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1642 dma-names = "tx", 1643 "rx"; 1644 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1645 pinctrl-names = "default"; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 1649 status = "disabled"; 1650 }; 1651 1652 i2c14: i2c@a98000 { 1653 compatible = "qcom,geni-i2c"; 1654 reg = <0x0 0x00a98000 0x0 0x4000>; 1655 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1656 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1657 clock-names = "se"; 1658 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1659 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1660 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1661 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1662 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1663 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1664 interconnect-names = "qup-core", 1665 "qup-config", 1666 "qup-memory"; 1667 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1668 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1669 dma-names = "tx", 1670 "rx"; 1671 pinctrl-0 = <&qup_i2c14_data_clk>; 1672 pinctrl-names = "default"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 1676 status = "disabled"; 1677 }; 1678 1679 spi14: spi@a98000 { 1680 compatible = "qcom,geni-spi"; 1681 reg = <0x0 0x00a98000 0x0 0x4000>; 1682 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1684 clock-names = "se"; 1685 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1686 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1687 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1688 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1689 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1690 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1691 interconnect-names = "qup-core", 1692 "qup-config", 1693 "qup-memory"; 1694 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1695 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1696 dma-names = "tx", 1697 "rx"; 1698 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1699 pinctrl-names = "default"; 1700 #address-cells = <1>; 1701 #size-cells = <0>; 1702 1703 status = "disabled"; 1704 }; 1705 1706 uart14: serial@a98000 { 1707 compatible = "qcom,geni-uart"; 1708 reg = <0x0 0x00a98000 0x0 0x4000>; 1709 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1710 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1711 clock-names = "se"; 1712 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1713 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1714 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1715 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1716 interconnect-names = "qup-core", 1717 "qup-config"; 1718 pinctrl-0 = <&qup_uart14_default>; 1719 pinctrl-names = "default"; 1720 1721 status = "disabled"; 1722 }; 1723 1724 i2c15: i2c@a9c000 { 1725 compatible = "qcom,geni-i2c"; 1726 reg = <0x0 0x00a9c000 0x0 0x4000>; 1727 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1728 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1729 clock-names = "se"; 1730 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1731 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1732 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1733 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1734 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1735 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1736 interconnect-names = "qup-core", 1737 "qup-config", 1738 "qup-memory"; 1739 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1740 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1741 dma-names = "tx", 1742 "rx"; 1743 pinctrl-0 = <&qup_i2c15_data_clk>; 1744 pinctrl-names = "default"; 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 status = "disabled"; 1749 }; 1750 1751 spi15: spi@a9c000 { 1752 compatible = "qcom,geni-spi"; 1753 reg = <0x0 0x00a9c000 0x0 0x4000>; 1754 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1755 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1756 clock-names = "se"; 1757 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1758 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1759 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1760 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1761 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1762 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1763 interconnect-names = "qup-core", 1764 "qup-config", 1765 "qup-memory"; 1766 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1767 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1768 dma-names = "tx", 1769 "rx"; 1770 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1771 pinctrl-names = "default"; 1772 #address-cells = <1>; 1773 #size-cells = <0>; 1774 1775 status = "disabled"; 1776 }; 1777 }; 1778 1779 gpi_dma0: dma-controller@b00000 { 1780 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1781 reg = <0x0 0x00b00000 0x0 0x60000>; 1782 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1783 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1784 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1785 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1786 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1787 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1788 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1789 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1790 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1791 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1792 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1794 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1795 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1796 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1798 dma-channels = <16>; 1799 dma-channel-mask = <0x3f>; 1800 #dma-cells = <3>; 1801 iommus = <&apps_smmu 0xd36 0x0>; 1802 }; 1803 1804 qupv3_0: geniqup@bc0000 { 1805 compatible = "qcom,geni-se-qup"; 1806 reg = <0x0 0x00bc0000 0x0 0x3000>; 1807 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1808 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1809 clock-names = "m-ahb", 1810 "s-ahb"; 1811 iommus = <&apps_smmu 0xd23 0x0>; 1812 #address-cells = <2>; 1813 #size-cells = <2>; 1814 ranges; 1815 1816 i2c0: i2c@b80000 { 1817 compatible = "qcom,geni-i2c"; 1818 reg = <0x0 0x00b80000 0x0 0x4000>; 1819 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1821 clock-names = "se"; 1822 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1823 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1824 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1825 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1826 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1827 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1828 interconnect-names = "qup-core", 1829 "qup-config", 1830 "qup-memory"; 1831 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1832 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1833 dma-names = "tx", 1834 "rx"; 1835 pinctrl-0 = <&qup_i2c0_data_clk>; 1836 pinctrl-names = "default"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 status = "disabled"; 1841 }; 1842 1843 spi0: spi@b80000 { 1844 compatible = "qcom,geni-spi"; 1845 reg = <0x0 0x00b80000 0x0 0x4000>; 1846 interrupts = <GIC_SPI 1052 IRQ_TYPE_LEVEL_HIGH>; 1847 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1848 clock-names = "se"; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1850 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1851 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1852 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1853 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1854 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1855 interconnect-names = "qup-core", 1856 "qup-config", 1857 "qup-memory"; 1858 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1859 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1860 dma-names = "tx", 1861 "rx"; 1862 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1863 pinctrl-names = "default"; 1864 #address-cells = <1>; 1865 #size-cells = <0>; 1866 1867 status = "disabled"; 1868 }; 1869 1870 i2c1: i2c@b84000 { 1871 compatible = "qcom,geni-i2c"; 1872 reg = <0x0 0x00b84000 0x0 0x4000>; 1873 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1874 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1875 clock-names = "se"; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1877 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1878 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1879 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1880 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1881 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1882 interconnect-names = "qup-core", 1883 "qup-config", 1884 "qup-memory"; 1885 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1886 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1887 dma-names = "tx", 1888 "rx"; 1889 pinctrl-0 = <&qup_i2c1_data_clk>; 1890 pinctrl-names = "default"; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 1894 status = "disabled"; 1895 }; 1896 1897 spi1: spi@b84000 { 1898 compatible = "qcom,geni-spi"; 1899 reg = <0x0 0x00b84000 0x0 0x4000>; 1900 interrupts = <GIC_SPI 1053 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1902 clock-names = "se"; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1904 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1905 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1906 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1907 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1908 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1909 interconnect-names = "qup-core", 1910 "qup-config", 1911 "qup-memory"; 1912 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1913 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1914 dma-names = "tx", 1915 "rx"; 1916 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1917 pinctrl-names = "default"; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 1921 status = "disabled"; 1922 }; 1923 1924 i2c2: i2c@b88000 { 1925 compatible = "qcom,geni-i2c"; 1926 reg = <0x0 0x00b88000 0x0 0x4000>; 1927 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1929 clock-names = "se"; 1930 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1931 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1932 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1933 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1934 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1935 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1936 interconnect-names = "qup-core", 1937 "qup-config", 1938 "qup-memory"; 1939 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1940 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1941 dma-names = "tx", 1942 "rx"; 1943 pinctrl-0 = <&qup_i2c2_data_clk>; 1944 pinctrl-names = "default"; 1945 #address-cells = <1>; 1946 #size-cells = <0>; 1947 1948 status = "disabled"; 1949 }; 1950 1951 spi2: spi@b88000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0x0 0x00b88000 0x0 0x4000>; 1954 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1956 clock-names = "se"; 1957 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1958 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1959 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1960 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1961 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1962 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config", 1965 "qup-memory"; 1966 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1967 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1968 dma-names = "tx", 1969 "rx"; 1970 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1971 pinctrl-names = "default"; 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 status = "disabled"; 1976 }; 1977 1978 uart2: serial@b88000 { 1979 compatible = "qcom,geni-uart"; 1980 reg = <0x0 0x00b88000 0x0 0x4000>; 1981 interrupts = <GIC_SPI 1054 IRQ_TYPE_LEVEL_HIGH>; 1982 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1983 clock-names = "se"; 1984 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1985 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1986 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1987 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1988 interconnect-names = "qup-core", 1989 "qup-config"; 1990 pinctrl-0 = <&qup_uart2_default>; 1991 pinctrl-names = "default"; 1992 1993 status = "disabled"; 1994 }; 1995 1996 i2c3: i2c@b8c000 { 1997 compatible = "qcom,geni-i2c"; 1998 reg = <0x0 0x00b8c000 0x0 0x4000>; 1999 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2001 clock-names = "se"; 2002 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2003 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2004 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2005 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2006 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2007 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2008 interconnect-names = "qup-core", 2009 "qup-config", 2010 "qup-memory"; 2011 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2012 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2013 dma-names = "tx", 2014 "rx"; 2015 pinctrl-0 = <&qup_i2c3_data_clk>; 2016 pinctrl-names = "default"; 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 2020 status = "disabled"; 2021 }; 2022 2023 spi3: spi@b8c000 { 2024 compatible = "qcom,geni-spi"; 2025 reg = <0x0 0x00b8c000 0x0 0x4000>; 2026 interrupts = <GIC_SPI 1055 IRQ_TYPE_LEVEL_HIGH>; 2027 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2028 clock-names = "se"; 2029 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2030 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2031 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2032 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2033 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2034 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2035 interconnect-names = "qup-core", 2036 "qup-config", 2037 "qup-memory"; 2038 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2039 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2040 dma-names = "tx", 2041 "rx"; 2042 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2043 pinctrl-names = "default"; 2044 #address-cells = <1>; 2045 #size-cells = <0>; 2046 2047 status = "disabled"; 2048 }; 2049 2050 i2c4: i2c@b90000 { 2051 compatible = "qcom,geni-i2c"; 2052 reg = <0x0 0x00b90000 0x0 0x4000>; 2053 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2054 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2055 clock-names = "se"; 2056 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2057 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2058 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2059 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2060 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2062 interconnect-names = "qup-core", 2063 "qup-config", 2064 "qup-memory"; 2065 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2066 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 pinctrl-0 = <&qup_i2c4_data_clk>; 2070 pinctrl-names = "default"; 2071 #address-cells = <1>; 2072 #size-cells = <0>; 2073 2074 status = "disabled"; 2075 }; 2076 2077 spi4: spi@b90000 { 2078 compatible = "qcom,geni-spi"; 2079 reg = <0x0 0x00b90000 0x0 0x4000>; 2080 interrupts = <GIC_SPI 1056 IRQ_TYPE_LEVEL_HIGH>; 2081 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2082 clock-names = "se"; 2083 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2084 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2085 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2086 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2087 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2088 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2089 interconnect-names = "qup-core", 2090 "qup-config", 2091 "qup-memory"; 2092 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2093 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2094 dma-names = "tx", 2095 "rx"; 2096 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2097 pinctrl-names = "default"; 2098 #address-cells = <1>; 2099 #size-cells = <0>; 2100 2101 status = "disabled"; 2102 }; 2103 2104 i2c5: i2c@b94000 { 2105 compatible = "qcom,geni-i2c"; 2106 reg = <0x0 0x00b94000 0x0 0x4000>; 2107 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2108 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2109 clock-names = "se"; 2110 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2111 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2112 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2113 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2114 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2115 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2116 interconnect-names = "qup-core", 2117 "qup-config", 2118 "qup-memory"; 2119 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2120 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2121 dma-names = "tx", 2122 "rx"; 2123 pinctrl-0 = <&qup_i2c5_data_clk>; 2124 pinctrl-names = "default"; 2125 #address-cells = <1>; 2126 #size-cells = <0>; 2127 2128 status = "disabled"; 2129 }; 2130 2131 spi5: spi@b94000 { 2132 compatible = "qcom,geni-spi"; 2133 reg = <0x0 0x00b94000 0x0 0x4000>; 2134 interrupts = <GIC_SPI 1057 IRQ_TYPE_LEVEL_HIGH>; 2135 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2136 clock-names = "se"; 2137 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2138 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2139 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2140 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2141 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2143 interconnect-names = "qup-core", 2144 "qup-config", 2145 "qup-memory"; 2146 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2147 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2148 dma-names = "tx", 2149 "rx"; 2150 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2151 pinctrl-names = "default"; 2152 #address-cells = <1>; 2153 #size-cells = <0>; 2154 2155 status = "disabled"; 2156 }; 2157 2158 i2c6: i2c@b98000 { 2159 compatible = "qcom,geni-i2c"; 2160 reg = <0x0 0x00b98000 0x0 0x4000>; 2161 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2162 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2163 clock-names = "se"; 2164 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2165 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2166 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2167 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2168 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2169 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2170 interconnect-names = "qup-core", 2171 "qup-config", 2172 "qup-memory"; 2173 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2174 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2175 dma-names = "tx", 2176 "rx"; 2177 pinctrl-0 = <&qup_i2c6_data_clk>; 2178 pinctrl-names = "default"; 2179 #address-cells = <1>; 2180 #size-cells = <0>; 2181 2182 status = "disabled"; 2183 }; 2184 2185 spi6: spi@b98000 { 2186 compatible = "qcom,geni-spi"; 2187 reg = <0x0 0x00b98000 0x0 0x4000>; 2188 interrupts = <GIC_SPI 1058 IRQ_TYPE_LEVEL_HIGH>; 2189 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2190 clock-names = "se"; 2191 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2192 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2193 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2194 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2195 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2196 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2197 interconnect-names = "qup-core", 2198 "qup-config", 2199 "qup-memory"; 2200 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2201 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2202 dma-names = "tx", 2203 "rx"; 2204 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2205 pinctrl-names = "default"; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 status = "disabled"; 2210 }; 2211 2212 i2c7: i2c@b9c000 { 2213 compatible = "qcom,geni-i2c"; 2214 reg = <0x0 0x00b9c000 0x0 0x4000>; 2215 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2216 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2217 clock-names = "se"; 2218 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2219 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2220 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2221 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2222 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2223 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2224 interconnect-names = "qup-core", 2225 "qup-config", 2226 "qup-memory"; 2227 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2228 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2229 dma-names = "tx", 2230 "rx"; 2231 pinctrl-0 = <&qup_i2c7_data_clk>; 2232 pinctrl-names = "default"; 2233 #address-cells = <1>; 2234 #size-cells = <0>; 2235 2236 status = "disabled"; 2237 }; 2238 2239 spi7: spi@b9c000 { 2240 compatible = "qcom,geni-spi"; 2241 reg = <0x0 0x00b9c000 0x0 0x4000>; 2242 interrupts = <GIC_SPI 1059 IRQ_TYPE_LEVEL_HIGH>; 2243 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2244 clock-names = "se"; 2245 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2246 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2247 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2248 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2249 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2250 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2251 interconnect-names = "qup-core", 2252 "qup-config", 2253 "qup-memory"; 2254 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2255 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2256 dma-names = "tx", 2257 "rx"; 2258 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2259 pinctrl-names = "default"; 2260 #address-cells = <1>; 2261 #size-cells = <0>; 2262 2263 status = "disabled"; 2264 }; 2265 }; 2266 2267 usb_hs_phy: phy@fa0000 { 2268 compatible = "qcom,glymur-m31-eusb2-phy", 2269 "qcom,sm8750-m31-eusb2-phy"; 2270 reg = <0x0 0x00fa0000 0x0 0x154>; 2271 #phy-cells = <0>; 2272 2273 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2274 clock-names = "ref"; 2275 2276 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2277 2278 status = "disabled"; 2279 }; 2280 2281 usb_mp_hsphy0: phy@fa1000 { 2282 compatible = "qcom,glymur-m31-eusb2-phy", 2283 "qcom,sm8750-m31-eusb2-phy"; 2284 2285 reg = <0x0 0x00fa1000 0x0 0x29c>; 2286 #phy-cells = <0>; 2287 2288 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2289 clock-names = "ref"; 2290 2291 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2292 2293 status = "disabled"; 2294 }; 2295 2296 usb_mp_hsphy1: phy@fa2000 { 2297 compatible = "qcom,glymur-m31-eusb2-phy", 2298 "qcom,sm8750-m31-eusb2-phy"; 2299 2300 reg = <0x0 0x00fa2000 0x0 0x29c>; 2301 #phy-cells = <0>; 2302 2303 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2304 clock-names = "ref"; 2305 2306 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2307 2308 status = "disabled"; 2309 }; 2310 2311 usb_mp_qmpphy0: phy@fa3000 { 2312 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2313 reg = <0x0 0x00fa3000 0x0 0x2000>; 2314 2315 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2316 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2317 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2318 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2319 clock-names = "aux", 2320 "ref", 2321 "com_aux", 2322 "pipe"; 2323 2324 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2325 2326 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2327 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2328 reset-names = "phy", 2329 "phy_phy"; 2330 2331 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2332 #clock-cells = <0>; 2333 #phy-cells = <0>; 2334 2335 status = "disabled"; 2336 }; 2337 2338 usb_mp_qmpphy1: phy@fa5000 { 2339 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2340 reg = <0x0 0x00fa5000 0x0 0x2000>; 2341 2342 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2343 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2344 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2345 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2346 clock-names = "aux", 2347 "ref", 2348 "com_aux", 2349 "pipe"; 2350 2351 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2352 2353 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2354 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2355 reset-names = "phy", 2356 "phy_phy"; 2357 2358 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2359 2360 #clock-cells = <0>; 2361 #phy-cells = <0>; 2362 2363 status = "disabled"; 2364 }; 2365 2366 mdss_dp3_phy: phy@faac00 { 2367 compatible = "qcom,glymur-dp-phy"; 2368 reg = <0x0 0x00faac00 0x0 0x1d0>, 2369 <0x0 0x00faa400 0x0 0x128>, 2370 <0x0 0x00faa800 0x0 0x128>, 2371 <0x0 0x00faa000 0x0 0x358>; 2372 2373 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2374 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2375 <&tcsr TCSR_EDP_CLKREF_EN>; 2376 clock-names = "aux", 2377 "cfg_ahb", 2378 "ref"; 2379 2380 power-domains = <&rpmhpd RPMHPD_MX>; 2381 2382 #clock-cells = <1>; 2383 #phy-cells = <0>; 2384 2385 status = "disabled"; 2386 }; 2387 2388 usb_0_hsphy: phy@fd3000 { 2389 compatible = "qcom,glymur-m31-eusb2-phy", 2390 "qcom,sm8750-m31-eusb2-phy"; 2391 2392 reg = <0x0 0x00fd3000 0x0 0x29c>; 2393 #phy-cells = <0>; 2394 2395 clocks = <&rpmhcc RPMH_CXO_CLK>; 2396 clock-names = "ref"; 2397 2398 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2399 2400 status = "disabled"; 2401 }; 2402 2403 usb_0_qmpphy: phy@fd5000 { 2404 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2405 reg = <0x0 0x00fd5000 0x0 0x8000>; 2406 2407 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2408 <&rpmhcc RPMH_CXO_CLK>, 2409 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2410 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2411 clock-names = "aux", 2412 "ref", 2413 "com_aux", 2414 "usb3_pipe"; 2415 2416 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2417 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2418 2419 reset-names = "phy", 2420 "common"; 2421 2422 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2423 2424 #clock-cells = <1>; 2425 #phy-cells = <1>; 2426 2427 mode-switch; 2428 orientation-switch; 2429 2430 status = "disabled"; 2431 2432 ports { 2433 #address-cells = <1>; 2434 #size-cells = <0>; 2435 2436 port@0 { 2437 reg = <0>; 2438 2439 usb_0_qmpphy_out: endpoint { 2440 }; 2441 }; 2442 2443 port@1 { 2444 reg = <1>; 2445 2446 usb_0_qmpphy_usb_ss_in: endpoint { 2447 remote-endpoint = <&usb_0_dwc3_ss>; 2448 }; 2449 }; 2450 2451 port@2 { 2452 reg = <2>; 2453 2454 usb_dp_qmpphy_dp_in: endpoint { 2455 remote-endpoint = <&mdss_dp0_out>; 2456 }; 2457 }; 2458 }; 2459 }; 2460 2461 usb_1_hsphy: phy@fdd000 { 2462 compatible = "qcom,glymur-m31-eusb2-phy", 2463 "qcom,sm8750-m31-eusb2-phy"; 2464 2465 reg = <0x0 0x00fdd000 0x0 0x29c>; 2466 #phy-cells = <0>; 2467 2468 clocks = <&rpmhcc RPMH_CXO_CLK>; 2469 clock-names = "ref"; 2470 2471 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2472 2473 status = "disabled"; 2474 }; 2475 2476 usb_1_qmpphy: phy@fde000 { 2477 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2478 reg = <0x0 0x00fde000 0x0 0x8000>; 2479 2480 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2481 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2482 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2483 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2484 clock-names = "aux", 2485 "ref", 2486 "com_aux", 2487 "usb3_pipe"; 2488 2489 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2490 2491 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2492 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2493 reset-names = "phy", 2494 "common"; 2495 2496 #clock-cells = <1>; 2497 #phy-cells = <1>; 2498 2499 mode-switch; 2500 orientation-switch; 2501 2502 status = "disabled"; 2503 2504 ports { 2505 #address-cells = <1>; 2506 #size-cells = <0>; 2507 2508 port@0 { 2509 reg = <0>; 2510 2511 usb_1_qmpphy_out: endpoint { 2512 }; 2513 }; 2514 2515 port@1 { 2516 reg = <1>; 2517 2518 usb_1_qmpphy_usb_ss_in: endpoint { 2519 remote-endpoint = <&usb_1_dwc3_ss>; 2520 }; 2521 }; 2522 2523 port@2 { 2524 reg = <2>; 2525 2526 usb_1_qmpphy_dp_in: endpoint { 2527 remote-endpoint = <&mdss_dp1_out>; 2528 }; 2529 }; 2530 }; 2531 }; 2532 2533 2534 /* cluster0 */ 2535 bwmon_cluster0: pmu@100c400 { 2536 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2537 reg = <0x0 0x0100c400 0x0 0x600>; 2538 2539 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2540 2541 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2542 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2543 2544 operating-points-v2 = <&cpu_bwmon_opp_table>; 2545 2546 cpu_bwmon_opp_table: opp-table { 2547 compatible = "operating-points-v2"; 2548 2549 opp-0 { 2550 opp-peak-kBps = <800000>; 2551 }; 2552 2553 opp-1 { 2554 opp-peak-kBps = <2188800>; 2555 }; 2556 2557 opp-2 { 2558 opp-peak-kBps = <5414400>; 2559 }; 2560 2561 opp-3 { 2562 opp-peak-kBps = <6220800>; 2563 }; 2564 2565 opp-4 { 2566 opp-peak-kBps = <6835200>; 2567 }; 2568 2569 opp-5 { 2570 opp-peak-kBps = <8371200>; 2571 }; 2572 2573 opp-6 { 2574 opp-peak-kBps = <10944000>; 2575 }; 2576 2577 opp-7 { 2578 opp-peak-kBps = <12748800>; 2579 }; 2580 2581 opp-8 { 2582 opp-peak-kBps = <14745600>; 2583 }; 2584 2585 opp-9 { 2586 opp-peak-kBps = <16896000>; 2587 }; 2588 2589 opp-10 { 2590 opp-peak-kBps = <19046400>; 2591 }; 2592 2593 opp-11 { 2594 opp-peak-kBps = <21332000>; 2595 }; 2596 }; 2597 }; 2598 2599 /* cluster1 */ 2600 bwmon_cluster1: pmu@100d400 { 2601 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2602 reg = <0x0 0x0100d400 0x0 0x600>; 2603 2604 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2605 2606 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2607 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2608 2609 operating-points-v2 = <&cpu_bwmon_opp_table>; 2610 }; 2611 2612 /* cluster2 */ 2613 bwmon_cluster2: pmu@100e400 { 2614 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2615 reg = <0x0 0x0100e400 0x0 0x600>; 2616 2617 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2618 2619 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2621 2622 operating-points-v2 = <&cpu_bwmon_opp_table>; 2623 }; 2624 cnoc_main: interconnect@1500000 { 2625 compatible = "qcom,glymur-cnoc-main"; 2626 reg = <0x0 0x01500000 0x0 0x17080>; 2627 qcom,bcm-voters = <&apps_bcm_voter>; 2628 #interconnect-cells = <2>; 2629 }; 2630 2631 config_noc: interconnect@1600000 { 2632 compatible = "qcom,glymur-cnoc-cfg"; 2633 reg = <0x0 0x01600000 0x0 0x6600>; 2634 qcom,bcm-voters = <&apps_bcm_voter>; 2635 #interconnect-cells = <2>; 2636 }; 2637 2638 system_noc: interconnect@1680000 { 2639 compatible = "qcom,glymur-system-noc"; 2640 reg = <0x0 0x01680000 0x0 0x1c080>; 2641 qcom,bcm-voters = <&apps_bcm_voter>; 2642 #interconnect-cells = <2>; 2643 }; 2644 2645 pcie_west_anoc: interconnect@16c0000 { 2646 compatible = "qcom,glymur-pcie-west-anoc"; 2647 reg = <0x0 0x016c0000 0x0 0xf580>; 2648 qcom,bcm-voters = <&apps_bcm_voter>; 2649 #interconnect-cells = <2>; 2650 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2651 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2652 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2653 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2654 }; 2655 2656 pcie_east_anoc: interconnect@16d0000 { 2657 compatible = "qcom,glymur-pcie-east-anoc"; 2658 reg = <0x0 0x016d0000 0x0 0xf300>; 2659 qcom,bcm-voters = <&apps_bcm_voter>; 2660 #interconnect-cells = <2>; 2661 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2662 }; 2663 2664 aggre1_noc: interconnect@16e0000 { 2665 compatible = "qcom,glymur-aggre1-noc"; 2666 reg = <0x0 0x016e0000 0x0 0x14400>; 2667 qcom,bcm-voters = <&apps_bcm_voter>; 2668 #interconnect-cells = <2>; 2669 }; 2670 2671 aggre2_noc: interconnect@1720000 { 2672 compatible = "qcom,glymur-aggre2-noc"; 2673 reg = <0x0 0x01720000 0x0 0x14400>; 2674 qcom,bcm-voters = <&apps_bcm_voter>; 2675 #interconnect-cells = <2>; 2676 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2677 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2678 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2679 }; 2680 2681 aggre3_noc: interconnect@1700000 { 2682 compatible = "qcom,glymur-aggre3-noc"; 2683 reg = <0x0 0x01700000 0x0 0x1d400>; 2684 qcom,bcm-voters = <&apps_bcm_voter>; 2685 #interconnect-cells = <2>; 2686 }; 2687 2688 aggre4_noc: interconnect@1740000 { 2689 compatible = "qcom,glymur-aggre4-noc"; 2690 reg = <0x0 0x01740000 0x0 0x14400>; 2691 qcom,bcm-voters = <&apps_bcm_voter>; 2692 #interconnect-cells = <2>; 2693 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2694 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2695 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2696 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2697 }; 2698 2699 mmss_noc: interconnect@1780000 { 2700 compatible = "qcom,glymur-mmss-noc"; 2701 reg = <0x0 0x01780000 0x0 0x5b800>; 2702 qcom,bcm-voters = <&apps_bcm_voter>; 2703 #interconnect-cells = <2>; 2704 }; 2705 2706 pcie_east_slv_noc: interconnect@1900000 { 2707 compatible = "qcom,glymur-pcie-east-slv-noc"; 2708 reg = <0x0 0x01900000 0x0 0xe080>; 2709 qcom,bcm-voters = <&apps_bcm_voter>; 2710 #interconnect-cells = <2>; 2711 }; 2712 2713 pcie_west_slv_noc: interconnect@1920000 { 2714 compatible = "qcom,glymur-pcie-west-slv-noc"; 2715 reg = <0x0 0x01920000 0x0 0xf180>; 2716 qcom,bcm-voters = <&apps_bcm_voter>; 2717 #interconnect-cells = <2>; 2718 }; 2719 2720 pcie4: pci@1bf0000 { 2721 device_type = "pci"; 2722 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2723 reg = <0x0 0x01bf0000 0x0 0x3000>, 2724 <0x0 0x78000000 0x0 0xf20>, 2725 <0x0 0x78000f40 0x0 0xa8>, 2726 <0x0 0x78001000 0x0 0x4000>, 2727 <0x0 0x78005000 0x0 0x100000>, 2728 <0x0 0x01bf3000 0x0 0x1000>; 2729 reg-names = "parf", 2730 "dbi", 2731 "elbi", 2732 "atu", 2733 "config", 2734 "mhi"; 2735 #address-cells = <3>; 2736 #size-cells = <2>; 2737 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2738 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2739 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2740 bus-range = <0x00 0xff>; 2741 2742 dma-coherent; 2743 2744 linux,pci-domain = <4>; 2745 num-lanes = <2>; 2746 2747 operating-points-v2 = <&pcie4_opp_table>; 2748 2749 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2750 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2751 2752 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2753 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2754 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2755 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2756 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2757 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2758 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2759 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2760 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2761 interrupt-names = "msi0", 2762 "msi1", 2763 "msi2", 2764 "msi3", 2765 "msi4", 2766 "msi5", 2767 "msi6", 2768 "msi7", 2769 "global"; 2770 2771 #interrupt-cells = <1>; 2772 interrupt-map-mask = <0 0 0 0x7>; 2773 interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>, 2774 <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>, 2775 <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>, 2776 <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>; 2777 2778 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2779 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2780 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2781 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2782 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2783 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2784 clock-names = "aux", 2785 "cfg", 2786 "bus_master", 2787 "bus_slave", 2788 "slave_q2a", 2789 "noc_aggr"; 2790 2791 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2792 assigned-clock-rates = <19200000>; 2793 2794 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2795 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2796 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2797 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2798 interconnect-names = "pcie-mem", 2799 "cpu-pcie"; 2800 2801 resets = <&gcc GCC_PCIE_4_BCR>, 2802 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2803 reset-names = "pci", 2804 "link_down"; 2805 2806 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2807 2808 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2809 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2810 2811 status = "disabled"; 2812 2813 pcie4_opp_table: opp-table { 2814 compatible = "operating-points-v2"; 2815 2816 /* GEN 1 x1 */ 2817 opp-2500000-1 { 2818 opp-hz = /bits/ 64 <2500000>; 2819 required-opps = <&rpmhpd_opp_low_svs>; 2820 opp-peak-kBps = <250000 1>; 2821 opp-level = <1>; 2822 }; 2823 2824 /* GEN 1 x2 */ 2825 opp-5000000-1 { 2826 opp-hz = /bits/ 64 <5000000>; 2827 required-opps = <&rpmhpd_opp_low_svs>; 2828 opp-peak-kBps = <500000 1>; 2829 opp-level = <1>; 2830 }; 2831 2832 /* GEN 2 x1 */ 2833 opp-5000000-2 { 2834 opp-hz = /bits/ 64 <5000000>; 2835 required-opps = <&rpmhpd_opp_low_svs>; 2836 opp-peak-kBps = <500000 1>; 2837 opp-level = <2>; 2838 }; 2839 2840 /* GEN 2 x2 */ 2841 opp-10000000-2 { 2842 opp-hz = /bits/ 64 <10000000>; 2843 required-opps = <&rpmhpd_opp_low_svs>; 2844 opp-peak-kBps = <1000000 1>; 2845 opp-level = <2>; 2846 }; 2847 2848 /* GEN 3 x1 */ 2849 opp-8000000-3 { 2850 opp-hz = /bits/ 64 <8000000>; 2851 required-opps = <&rpmhpd_opp_low_svs>; 2852 opp-peak-kBps = <984500 1>; 2853 opp-level = <3>; 2854 }; 2855 2856 /* GEN 3 x2 */ 2857 opp-16000000-3 { 2858 opp-hz = /bits/ 64 <16000000>; 2859 required-opps = <&rpmhpd_opp_low_svs>; 2860 opp-peak-kBps = <1969000 1>; 2861 opp-level = <3>; 2862 }; 2863 2864 /* GEN 4 x1 */ 2865 opp-16000000-4 { 2866 opp-hz = /bits/ 64 <16000000>; 2867 required-opps = <&rpmhpd_opp_low_svs>; 2868 opp-peak-kBps = <1969000 1>; 2869 opp-level = <4>; 2870 }; 2871 2872 /* GEN 4 x2 */ 2873 opp-32000000-4 { 2874 opp-hz = /bits/ 64 <32000000>; 2875 required-opps = <&rpmhpd_opp_low_svs>; 2876 opp-peak-kBps = <3938000 1>; 2877 opp-level = <4>; 2878 }; 2879 2880 }; 2881 2882 pcie4_port0: pcie@0 { 2883 device_type = "pci"; 2884 reg = <0x0 0x0 0x0 0x0 0x0>; 2885 bus-range = <0x01 0xff>; 2886 2887 phys = <&pcie4_phy>; 2888 2889 #address-cells = <3>; 2890 #size-cells = <2>; 2891 ranges; 2892 }; 2893 }; 2894 2895 pcie4_phy: phy@1bf6000 { 2896 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 2897 reg = <0x0 0x01bf6000 0x0 0x2000>; 2898 2899 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 2900 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2901 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 2902 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 2903 <&gcc GCC_PCIE_4_PIPE_CLK>, 2904 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 2905 clock-names = "aux", 2906 "cfg_ahb", 2907 "ref", 2908 "rchng", 2909 "pipe", 2910 "pipediv2"; 2911 2912 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 2913 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 2914 reset-names = "phy", 2915 "phy_nocsr"; 2916 2917 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 2918 assigned-clock-rates = <100000000>; 2919 2920 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 2921 2922 #clock-cells = <0>; 2923 clock-output-names = "pcie4_pipe_clk"; 2924 2925 #phy-cells = <0>; 2926 2927 status = "disabled"; 2928 }; 2929 2930 pcie5: pci@1b40000 { 2931 device_type = "pci"; 2932 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2933 reg = <0x0 0x01b40000 0x0 0x3000>, 2934 <0x0 0x7a000000 0x0 0xf20>, 2935 <0x0 0x7a000f40 0x0 0xa8>, 2936 <0x0 0x7a001000 0x0 0x4000>, 2937 <0x0 0x7a100000 0x0 0x100000>, 2938 <0x0 0x01b43000 0x0 0x1000>; 2939 reg-names = "parf", 2940 "dbi", 2941 "elbi", 2942 "atu", 2943 "config", 2944 "mhi"; 2945 #address-cells = <3>; 2946 #size-cells = <2>; 2947 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 2948 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 2949 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 2950 bus-range = <0x00 0xff>; 2951 2952 dma-coherent; 2953 2954 linux,pci-domain = <5>; 2955 num-lanes = <4>; 2956 2957 operating-points-v2 = <&pcie5_opp_table>; 2958 2959 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 2960 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 2961 2962 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 2963 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2964 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 2965 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 2966 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 2967 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2968 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2969 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 2970 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 2971 interrupt-names = "msi0", 2972 "msi1", 2973 "msi2", 2974 "msi3", 2975 "msi4", 2976 "msi5", 2977 "msi6", 2978 "msi7", 2979 "global"; 2980 2981 #interrupt-cells = <1>; 2982 interrupt-map-mask = <0 0 0 0x7>; 2983 interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>, 2984 <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>, 2985 <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>, 2986 <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>; 2987 2988 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 2989 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 2990 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 2991 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 2992 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 2993 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2994 clock-names = "aux", 2995 "cfg", 2996 "bus_master", 2997 "bus_slave", 2998 "slave_q2a", 2999 "noc_aggr"; 3000 3001 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3002 assigned-clock-rates = <19200000>; 3003 3004 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3006 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3007 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3008 interconnect-names = "pcie-mem", 3009 "cpu-pcie"; 3010 3011 resets = <&gcc GCC_PCIE_5_BCR>, 3012 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3013 reset-names = "pci", 3014 "link_down"; 3015 3016 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3017 3018 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3019 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3020 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3021 3022 status = "disabled"; 3023 3024 pcie5_opp_table: opp-table { 3025 compatible = "operating-points-v2"; 3026 3027 /* GEN 1 x1 */ 3028 opp-2500000-1 { 3029 opp-hz = /bits/ 64 <2500000>; 3030 required-opps = <&rpmhpd_opp_low_svs>; 3031 opp-peak-kBps = <250000 1>; 3032 opp-level = <1>; 3033 }; 3034 3035 /* GEN 1 x2 */ 3036 opp-5000000-1 { 3037 opp-hz = /bits/ 64 <5000000>; 3038 required-opps = <&rpmhpd_opp_low_svs>; 3039 opp-peak-kBps = <500000 1>; 3040 opp-level = <1>; 3041 }; 3042 3043 /* GEN 1 x4 */ 3044 opp-10000000-1 { 3045 opp-hz = /bits/ 64 <10000000>; 3046 required-opps = <&rpmhpd_opp_low_svs>; 3047 opp-peak-kBps = <1000000 1>; 3048 opp-level = <1>; 3049 }; 3050 3051 /* GEN 2 x1 */ 3052 opp-5000000-2 { 3053 opp-hz = /bits/ 64 <5000000>; 3054 required-opps = <&rpmhpd_opp_low_svs>; 3055 opp-peak-kBps = <500000 1>; 3056 opp-level = <2>; 3057 }; 3058 3059 /* GEN 2 x2 */ 3060 opp-10000000-2 { 3061 opp-hz = /bits/ 64 <10000000>; 3062 required-opps = <&rpmhpd_opp_low_svs>; 3063 opp-peak-kBps = <1000000 1>; 3064 opp-level = <2>; 3065 }; 3066 3067 /* GEN 2 x4 */ 3068 opp-20000000-2 { 3069 opp-hz = /bits/ 64 <20000000>; 3070 required-opps = <&rpmhpd_opp_low_svs>; 3071 opp-peak-kBps = <2000000 1>; 3072 opp-level = <2>; 3073 }; 3074 3075 /* GEN 3 x1 */ 3076 opp-8000000-3 { 3077 opp-hz = /bits/ 64 <8000000>; 3078 required-opps = <&rpmhpd_opp_low_svs>; 3079 opp-peak-kBps = <984500 1>; 3080 opp-level = <3>; 3081 }; 3082 3083 /* GEN 3 x2 */ 3084 opp-16000000-3 { 3085 opp-hz = /bits/ 64 <16000000>; 3086 required-opps = <&rpmhpd_opp_low_svs>; 3087 opp-peak-kBps = <1969000 1>; 3088 opp-level = <3>; 3089 }; 3090 3091 /* GEN 3 x4 */ 3092 opp-32000000-3 { 3093 opp-hz = /bits/ 64 <32000000>; 3094 required-opps = <&rpmhpd_opp_low_svs>; 3095 opp-peak-kBps = <3938000 1>; 3096 opp-level = <3>; 3097 }; 3098 3099 /* GEN 4 x1 */ 3100 opp-16000000-4 { 3101 opp-hz = /bits/ 64 <16000000>; 3102 required-opps = <&rpmhpd_opp_svs>; 3103 opp-peak-kBps = <1969000 1>; 3104 opp-level = <4>; 3105 }; 3106 3107 /* GEN 4 x2 */ 3108 opp-32000000-4 { 3109 opp-hz = /bits/ 64 <32000000>; 3110 required-opps = <&rpmhpd_opp_svs>; 3111 opp-peak-kBps = <3938000 1>; 3112 opp-level = <4>; 3113 }; 3114 3115 /* GEN 4 x4 */ 3116 opp-64000000-4 { 3117 opp-hz = /bits/ 64 <64000000>; 3118 required-opps = <&rpmhpd_opp_svs>; 3119 opp-peak-kBps = <7876000 1>; 3120 opp-level = <4>; 3121 }; 3122 3123 /* GEN 5 x1 */ 3124 opp-32000000-5 { 3125 opp-hz = /bits/ 64 <32000000>; 3126 required-opps = <&rpmhpd_opp_nom>; 3127 opp-peak-kBps = <3938000 1>; 3128 opp-level = <5>; 3129 }; 3130 3131 /* GEN 5 x2 */ 3132 opp-64000000-5 { 3133 opp-hz = /bits/ 64 <64000000>; 3134 required-opps = <&rpmhpd_opp_nom>; 3135 opp-peak-kBps = <7876000 1>; 3136 opp-level = <5>; 3137 }; 3138 3139 /* GEN 5 x4 */ 3140 opp-128000000-5 { 3141 opp-hz = /bits/ 64 <128000000>; 3142 required-opps = <&rpmhpd_opp_nom>; 3143 opp-peak-kBps = <15753000 1>; 3144 opp-level = <5>; 3145 }; 3146 }; 3147 3148 pcie5_port0: pcie@0 { 3149 device_type = "pci"; 3150 reg = <0x0 0x0 0x0 0x0 0x0>; 3151 bus-range = <0x01 0xff>; 3152 3153 phys = <&pcie5_phy>; 3154 3155 #address-cells = <3>; 3156 #size-cells = <2>; 3157 ranges; 3158 }; 3159 }; 3160 3161 pcie5_phy: phy@1b50000 { 3162 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3163 reg = <0x0 0x01b50000 0x0 0x10000>; 3164 3165 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3166 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3167 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3168 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3169 <&gcc GCC_PCIE_5_PIPE_CLK>, 3170 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3171 clock-names = "aux", 3172 "cfg_ahb", 3173 "ref", 3174 "rchng", 3175 "pipe", 3176 "pipediv2"; 3177 3178 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3179 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3180 reset-names = "phy", 3181 "phy_nocsr"; 3182 3183 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3184 assigned-clock-rates = <100000000>; 3185 3186 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3187 3188 #clock-cells = <0>; 3189 clock-output-names = "pcie5_pipe_clk"; 3190 3191 #phy-cells = <0>; 3192 3193 status = "disabled"; 3194 }; 3195 3196 pcie6: pci@1c00000 { 3197 device_type = "pci"; 3198 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3199 reg = <0x0 0x01c00000 0x0 0x3000>, 3200 <0x0 0x7e000000 0x0 0xf20>, 3201 <0x0 0x7e000f40 0x0 0xa8>, 3202 <0x0 0x7e001000 0x0 0x4000>, 3203 <0x0 0x7e100000 0x0 0x100000>, 3204 <0x0 0x01c03000 0x0 0x1000>; 3205 reg-names = "parf", 3206 "dbi", 3207 "elbi", 3208 "atu", 3209 "config", 3210 "mhi"; 3211 #address-cells = <3>; 3212 #size-cells = <2>; 3213 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3214 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3215 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3216 bus-range = <0x00 0xff>; 3217 3218 dma-coherent; 3219 3220 linux,pci-domain = <6>; 3221 num-lanes = <2>; 3222 3223 operating-points-v2 = <&pcie6_opp_table>; 3224 3225 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3226 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3227 3228 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3229 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3230 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3231 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3232 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3233 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3234 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3235 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3236 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3237 interrupt-names = "msi0", 3238 "msi1", 3239 "msi2", 3240 "msi3", 3241 "msi4", 3242 "msi5", 3243 "msi6", 3244 "msi7", 3245 "global"; 3246 3247 #interrupt-cells = <1>; 3248 interrupt-map-mask = <0 0 0 0x7>; 3249 interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>, 3250 <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>, 3251 <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>, 3252 <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>; 3253 3254 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3255 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3256 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3257 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3258 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3259 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3260 clock-names = "aux", 3261 "cfg", 3262 "bus_master", 3263 "bus_slave", 3264 "slave_q2a", 3265 "noc_aggr"; 3266 3267 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3268 assigned-clock-rates = <19200000>; 3269 3270 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3271 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3272 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3273 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3274 interconnect-names = "pcie-mem", 3275 "cpu-pcie"; 3276 3277 resets = <&gcc GCC_PCIE_6_BCR>, 3278 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3279 reset-names = "pci", 3280 "link_down"; 3281 3282 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3283 3284 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3285 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3286 3287 status = "disabled"; 3288 3289 pcie6_opp_table: opp-table { 3290 compatible = "operating-points-v2"; 3291 3292 /* GEN 1 x1 */ 3293 opp-2500000-1 { 3294 opp-hz = /bits/ 64 <2500000>; 3295 required-opps = <&rpmhpd_opp_low_svs>; 3296 opp-peak-kBps = <250000 1>; 3297 opp-level = <1>; 3298 }; 3299 3300 /* GEN 1 x2 */ 3301 opp-5000000-1 { 3302 opp-hz = /bits/ 64 <5000000>; 3303 required-opps = <&rpmhpd_opp_low_svs>; 3304 opp-peak-kBps = <500000 1>; 3305 opp-level = <1>; 3306 }; 3307 3308 /* GEN 2 x1 */ 3309 opp-5000000-2 { 3310 opp-hz = /bits/ 64 <5000000>; 3311 required-opps = <&rpmhpd_opp_low_svs>; 3312 opp-peak-kBps = <500000 1>; 3313 opp-level = <2>; 3314 }; 3315 3316 /* GEN 2 x2 */ 3317 opp-10000000-2 { 3318 opp-hz = /bits/ 64 <10000000>; 3319 required-opps = <&rpmhpd_opp_low_svs>; 3320 opp-peak-kBps = <1000000 1>; 3321 opp-level = <2>; 3322 }; 3323 3324 /* GEN 3 x1 */ 3325 opp-8000000-3 { 3326 opp-hz = /bits/ 64 <8000000>; 3327 required-opps = <&rpmhpd_opp_low_svs>; 3328 opp-peak-kBps = <984500 1>; 3329 opp-level = <3>; 3330 }; 3331 3332 /* GEN 3 x2 */ 3333 opp-16000000-3 { 3334 opp-hz = /bits/ 64 <16000000>; 3335 required-opps = <&rpmhpd_opp_low_svs>; 3336 opp-peak-kBps = <1969000 1>; 3337 opp-level = <3>; 3338 }; 3339 3340 /* GEN 4 x1 */ 3341 opp-16000000-4 { 3342 opp-hz = /bits/ 64 <16000000>; 3343 required-opps = <&rpmhpd_opp_low_svs>; 3344 opp-peak-kBps = <1969000 1>; 3345 opp-level = <4>; 3346 }; 3347 3348 /* GEN 4 x2 */ 3349 opp-32000000-4 { 3350 opp-hz = /bits/ 64 <32000000>; 3351 required-opps = <&rpmhpd_opp_low_svs>; 3352 opp-peak-kBps = <3938000 1>; 3353 opp-level = <4>; 3354 }; 3355 3356 }; 3357 3358 pcie6_port0: pcie@0 { 3359 device_type = "pci"; 3360 reg = <0x0 0x0 0x0 0x0 0x0>; 3361 bus-range = <0x01 0xff>; 3362 3363 phys = <&pcie6_phy>; 3364 3365 #address-cells = <3>; 3366 #size-cells = <2>; 3367 ranges; 3368 }; 3369 }; 3370 3371 pcie6_phy: phy@1c06000 { 3372 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3373 reg = <0x0 0x01c06000 0x0 0x2000>; 3374 3375 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3376 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3377 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3378 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3379 <&gcc GCC_PCIE_6_PIPE_CLK>, 3380 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3381 clock-names = "aux", 3382 "cfg_ahb", 3383 "ref", 3384 "rchng", 3385 "pipe", 3386 "pipediv2"; 3387 3388 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3389 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3390 reset-names = "phy", 3391 "phy_nocsr"; 3392 3393 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3394 assigned-clock-rates = <100000000>; 3395 3396 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3397 3398 #clock-cells = <0>; 3399 clock-output-names = "pcie6_pipe_clk"; 3400 3401 #phy-cells = <0>; 3402 3403 status = "disabled"; 3404 }; 3405 3406 pcie3b: pci@1b80000 { 3407 device_type = "pci"; 3408 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3409 reg = <0x0 0x01b80000 0x0 0x3000>, 3410 <0x0 0x74000000 0x0 0xf20>, 3411 <0x0 0x74000f40 0x0 0xa8>, 3412 <0x0 0x74001000 0x0 0x4000>, 3413 <0x0 0x74100000 0x0 0x100000>, 3414 <0x0 0x01b83000 0x0 0x1000>; 3415 reg-names = "parf", 3416 "dbi", 3417 "elbi", 3418 "atu", 3419 "config", 3420 "mhi"; 3421 #address-cells = <3>; 3422 #size-cells = <2>; 3423 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3424 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3425 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3426 bus-range = <0x00 0xff>; 3427 3428 dma-coherent; 3429 3430 linux,pci-domain = <7>; 3431 num-lanes = <4>; 3432 3433 operating-points-v2 = <&pcie3b_opp_table>; 3434 3435 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3436 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3437 3438 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3447 interrupt-names = "msi0", 3448 "msi1", 3449 "msi2", 3450 "msi3", 3451 "msi4", 3452 "msi5", 3453 "msi6", 3454 "msi7", 3455 "global"; 3456 3457 #interrupt-cells = <1>; 3458 interrupt-map-mask = <0 0 0 0x7>; 3459 interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>, 3460 <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>, 3461 <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>, 3462 <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>; 3463 3464 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3465 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3466 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3467 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3468 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3469 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3470 clock-names = "aux", 3471 "cfg", 3472 "bus_master", 3473 "bus_slave", 3474 "slave_q2a", 3475 "noc_aggr"; 3476 3477 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3478 assigned-clock-rates = <19200000>; 3479 3480 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3481 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3482 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3483 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3484 interconnect-names = "pcie-mem", 3485 "cpu-pcie"; 3486 3487 resets = <&gcc GCC_PCIE_3B_BCR>, 3488 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3489 reset-names = "pci", 3490 "link_down"; 3491 3492 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3493 3494 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3495 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3496 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3497 3498 status = "disabled"; 3499 3500 pcie3b_opp_table: opp-table { 3501 compatible = "operating-points-v2"; 3502 3503 /* GEN 1 x1 */ 3504 opp-2500000-1 { 3505 opp-hz = /bits/ 64 <2500000>; 3506 required-opps = <&rpmhpd_opp_low_svs>; 3507 opp-peak-kBps = <250000 1>; 3508 opp-level = <1>; 3509 }; 3510 3511 /* GEN 1 x2 */ 3512 opp-5000000-1 { 3513 opp-hz = /bits/ 64 <5000000>; 3514 required-opps = <&rpmhpd_opp_low_svs>; 3515 opp-peak-kBps = <500000 1>; 3516 opp-level = <1>; 3517 }; 3518 3519 /* GEN 1 x4 */ 3520 opp-10000000-1 { 3521 opp-hz = /bits/ 64 <10000000>; 3522 required-opps = <&rpmhpd_opp_low_svs>; 3523 opp-peak-kBps = <1000000 1>; 3524 opp-level = <1>; 3525 }; 3526 3527 /* GEN 2 x1 */ 3528 opp-5000000-2 { 3529 opp-hz = /bits/ 64 <5000000>; 3530 required-opps = <&rpmhpd_opp_low_svs>; 3531 opp-peak-kBps = <500000 1>; 3532 opp-level = <2>; 3533 }; 3534 3535 /* GEN 2 x2 */ 3536 opp-10000000-2 { 3537 opp-hz = /bits/ 64 <10000000>; 3538 required-opps = <&rpmhpd_opp_low_svs>; 3539 opp-peak-kBps = <1000000 1>; 3540 opp-level = <2>; 3541 }; 3542 3543 /* GEN 2 x4 */ 3544 opp-20000000-2 { 3545 opp-hz = /bits/ 64 <20000000>; 3546 required-opps = <&rpmhpd_opp_low_svs>; 3547 opp-peak-kBps = <2000000 1>; 3548 opp-level = <2>; 3549 }; 3550 3551 /* GEN 3 x1 */ 3552 opp-8000000-3 { 3553 opp-hz = /bits/ 64 <8000000>; 3554 required-opps = <&rpmhpd_opp_low_svs>; 3555 opp-peak-kBps = <984500 1>; 3556 opp-level = <3>; 3557 }; 3558 3559 /* GEN 3 x2 */ 3560 opp-16000000-3 { 3561 opp-hz = /bits/ 64 <16000000>; 3562 required-opps = <&rpmhpd_opp_low_svs>; 3563 opp-peak-kBps = <1969000 1>; 3564 opp-level = <3>; 3565 }; 3566 3567 /* GEN 3 x4 */ 3568 opp-32000000-3 { 3569 opp-hz = /bits/ 64 <32000000>; 3570 required-opps = <&rpmhpd_opp_low_svs>; 3571 opp-peak-kBps = <3938000 1>; 3572 opp-level = <3>; 3573 }; 3574 3575 /* GEN 4 x1 */ 3576 opp-16000000-4 { 3577 opp-hz = /bits/ 64 <16000000>; 3578 required-opps = <&rpmhpd_opp_svs>; 3579 opp-peak-kBps = <1969000 1>; 3580 opp-level = <4>; 3581 }; 3582 3583 /* GEN 4 x2 */ 3584 opp-32000000-4 { 3585 opp-hz = /bits/ 64 <32000000>; 3586 required-opps = <&rpmhpd_opp_svs>; 3587 opp-peak-kBps = <3938000 1>; 3588 opp-level = <4>; 3589 }; 3590 3591 /* GEN 4 x4 */ 3592 opp-64000000-4 { 3593 opp-hz = /bits/ 64 <64000000>; 3594 required-opps = <&rpmhpd_opp_svs>; 3595 opp-peak-kBps = <7876000 1>; 3596 opp-level = <4>; 3597 }; 3598 3599 /* GEN 5 x1 */ 3600 opp-32000000-5 { 3601 opp-hz = /bits/ 64 <32000000>; 3602 required-opps = <&rpmhpd_opp_nom>; 3603 opp-peak-kBps = <3938000 1>; 3604 opp-level = <5>; 3605 }; 3606 3607 /* GEN 5 x2 */ 3608 opp-64000000-5 { 3609 opp-hz = /bits/ 64 <64000000>; 3610 required-opps = <&rpmhpd_opp_nom>; 3611 opp-peak-kBps = <7876000 1>; 3612 opp-level = <5>; 3613 }; 3614 3615 /* GEN 5 x4 */ 3616 opp-128000000-5 { 3617 opp-hz = /bits/ 64 <128000000>; 3618 required-opps = <&rpmhpd_opp_nom>; 3619 opp-peak-kBps = <15753000 1>; 3620 opp-level = <5>; 3621 }; 3622 }; 3623 3624 pcie3b_port0: pcie@0 { 3625 device_type = "pci"; 3626 reg = <0x0 0x0 0x0 0x0 0x0>; 3627 bus-range = <0x01 0xff>; 3628 3629 phys = <&pcie3b_phy>; 3630 3631 #address-cells = <3>; 3632 #size-cells = <2>; 3633 ranges; 3634 }; 3635 }; 3636 3637 pcie3b_phy: phy@f10000 { 3638 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3639 reg = <0x0 0x00f10000 0x0 0x10000>; 3640 3641 clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 3642 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3643 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 3644 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 3645 <&gcc GCC_PCIE_3B_PIPE_CLK>, 3646 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 3647 clock-names = "aux", 3648 "cfg_ahb", 3649 "ref", 3650 "rchng", 3651 "pipe", 3652 "pipediv2"; 3653 3654 resets = <&gcc GCC_PCIE_3B_PHY_BCR>, 3655 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 3656 reset-names = "phy", 3657 "phy_nocsr"; 3658 3659 assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 3660 assigned-clock-rates = <100000000>; 3661 3662 power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; 3663 3664 #clock-cells = <0>; 3665 clock-output-names = "pcie3b_pipe_clk"; 3666 3667 #phy-cells = <0>; 3668 3669 status = "disabled"; 3670 }; 3671 3672 tcsr_mutex: hwlock@1f40000 { 3673 compatible = "qcom,tcsr-mutex"; 3674 reg = <0x0 0x01f40000 0x0 0x20000>; 3675 3676 #hwlock-cells = <1>; 3677 }; 3678 3679 tcsr: clock-controller@1fd5000 { 3680 compatible = "qcom,glymur-tcsr", 3681 "syscon"; 3682 reg = <0x0 0x1fd5000 0x0 0x21000>; 3683 clocks = <&rpmhcc RPMH_CXO_CLK>; 3684 #clock-cells = <1>; 3685 #reset-cells = <1>; 3686 }; 3687 3688 hsc_noc: interconnect@2000000 { 3689 compatible = "qcom,glymur-hscnoc"; 3690 reg = <0x0 0x02000000 0x0 0x93a080>; 3691 qcom,bcm-voters = <&apps_bcm_voter>; 3692 #interconnect-cells = <2>; 3693 }; 3694 3695 ipcc: mailbox@3e04000 { 3696 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 3697 reg = <0x0 0x03e04000 0x0 0x1000>; 3698 3699 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3700 interrupt-controller; 3701 #interrupt-cells = <3>; 3702 3703 #mbox-cells = <2>; 3704 }; 3705 3706 lpass_lpiaon_noc: interconnect@7400000 { 3707 compatible = "qcom,glymur-lpass-lpiaon-noc"; 3708 reg = <0x0 0x07400000 0x0 0x19080>; 3709 qcom,bcm-voters = <&apps_bcm_voter>; 3710 #interconnect-cells = <2>; 3711 }; 3712 3713 lpass_lpicx_noc: interconnect@7420000 { 3714 compatible = "qcom,glymur-lpass-lpicx-noc"; 3715 reg = <0x0 0x07420000 0x0 0x44080>; 3716 qcom,bcm-voters = <&apps_bcm_voter>; 3717 #interconnect-cells = <2>; 3718 }; 3719 3720 lpass_ag_noc: interconnect@7e40000 { 3721 compatible = "qcom,glymur-lpass-ag-noc"; 3722 reg = <0x0 0x07e40000 0x0 0xe080>; 3723 qcom,bcm-voters = <&apps_bcm_voter>; 3724 #interconnect-cells = <2>; 3725 }; 3726 3727 usb_2_hsphy: phy@88e0000 { 3728 compatible = "qcom,glymur-m31-eusb2-phy", 3729 "qcom,sm8750-m31-eusb2-phy"; 3730 3731 reg = <0x0 0x088e0000 0x0 0x29c>; 3732 #phy-cells = <0>; 3733 3734 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 3735 clock-names = "ref"; 3736 3737 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 3738 3739 status = "disabled"; 3740 }; 3741 3742 usb_2_qmpphy: phy@88e1000 { 3743 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 3744 reg = <0x0 0x088e1000 0x0 0x8000>; 3745 3746 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 3747 <&tcsr TCSR_USB4_2_CLKREF_EN>, 3748 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 3749 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 3750 clock-names = "aux", 3751 "ref", 3752 "com_aux", 3753 "usb3_pipe"; 3754 3755 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 3756 3757 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 3758 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 3759 reset-names = "phy", 3760 "common"; 3761 3762 #clock-cells = <1>; 3763 #phy-cells = <1>; 3764 3765 mode-switch; 3766 orientation-switch; 3767 3768 status = "disabled"; 3769 3770 ports { 3771 #address-cells = <1>; 3772 #size-cells = <0>; 3773 3774 port@0 { 3775 reg = <0>; 3776 3777 usb_2_qmpphy_out: endpoint { 3778 }; 3779 }; 3780 3781 port@1 { 3782 reg = <1>; 3783 3784 usb_2_qmpphy_usb_ss_in: endpoint { 3785 remote-endpoint = <&usb_2_dwc3_ss>; 3786 }; 3787 }; 3788 3789 port@2 { 3790 reg = <2>; 3791 3792 usb_2_qmpphy_dp_in: endpoint { 3793 remote-endpoint = <&mdss_dp2_out>; 3794 }; 3795 }; 3796 }; 3797 }; 3798 3799 usb_0: usb@a600000 { 3800 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3801 reg = <0x0 0x0a600000 0x0 0xfc100>; 3802 3803 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3804 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3805 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3806 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3807 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3808 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3809 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3810 clock-names = "cfg_noc", 3811 "core", 3812 "iface", 3813 "sleep", 3814 "mock_utmi", 3815 "noc_aggr_north", 3816 "noc_aggr_south"; 3817 3818 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 3819 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 3820 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 3821 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 3822 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 3823 interrupt-names = "dwc_usb3", 3824 "pwr_event", 3825 "dp_hs_phy_irq", 3826 "dm_hs_phy_irq", 3827 "ss_phy_irq"; 3828 3829 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 3830 resets = <&gcc GCC_USB30_PRIM_BCR>; 3831 3832 iommus = <&apps_smmu 0x1420 0x0>; 3833 phys = <&usb_0_hsphy>, 3834 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3835 phy-names = "usb2-phy", 3836 "usb3-phy"; 3837 3838 snps,hird-threshold = /bits/ 8 <0x0>; 3839 snps,dis-u1-entry-quirk; 3840 snps,dis-u2-entry-quirk; 3841 snps,is-utmi-l1-suspend; 3842 snps,usb3_lpm_capable; 3843 snps,has-lpm-erratum; 3844 tx-fifo-resize; 3845 snps,dis_u2_susphy_quirk; 3846 snps,dis_enblslpm_quirk; 3847 3848 usb-role-switch; 3849 3850 status = "disabled"; 3851 3852 ports { 3853 #address-cells = <1>; 3854 #size-cells = <0>; 3855 3856 port@0 { 3857 reg = <0>; 3858 3859 usb_0_dwc3_hs: endpoint { 3860 }; 3861 }; 3862 3863 port@1 { 3864 reg = <1>; 3865 3866 usb_0_dwc3_ss: endpoint { 3867 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 3868 }; 3869 }; 3870 }; 3871 }; 3872 3873 usb_1: usb@a800000 { 3874 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3875 reg = <0x0 0x0a800000 0x0 0xfc100>; 3876 3877 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3878 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3879 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3880 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3881 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3882 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3883 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3884 clock-names = "cfg_noc", 3885 "core", 3886 "iface", 3887 "sleep", 3888 "mock_utmi", 3889 "noc_aggr_north", 3890 "noc_aggr_south"; 3891 3892 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 3893 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 3894 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 3895 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 3896 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 3897 interrupt-names = "dwc_usb3", 3898 "pwr_event", 3899 "dp_hs_phy_irq", 3900 "dm_hs_phy_irq", 3901 "ss_phy_irq"; 3902 3903 resets = <&gcc GCC_USB30_SEC_BCR>; 3904 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 3905 3906 iommus = <&apps_smmu 0x1460 0x0>; 3907 3908 phys = <&usb_1_hsphy>, 3909 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3910 phy-names = "usb2-phy", 3911 "usb3-phy"; 3912 3913 snps,hird-threshold = /bits/ 8 <0x0>; 3914 snps,dis-u1-entry-quirk; 3915 snps,dis-u2-entry-quirk; 3916 snps,is-utmi-l1-suspend; 3917 snps,usb3_lpm_capable; 3918 snps,has-lpm-erratum; 3919 tx-fifo-resize; 3920 snps,dis_u2_susphy_quirk; 3921 snps,dis_enblslpm_quirk; 3922 3923 status = "disabled"; 3924 3925 ports { 3926 #address-cells = <1>; 3927 #size-cells = <0>; 3928 3929 port@0 { 3930 reg = <0>; 3931 3932 usb_1_dwc3_hs: endpoint { 3933 }; 3934 }; 3935 3936 port@1 { 3937 reg = <1>; 3938 3939 usb_1_dwc3_ss: endpoint { 3940 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3941 }; 3942 }; 3943 }; 3944 }; 3945 3946 usb_2: usb@a000000 { 3947 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 3948 reg = <0x0 0x0a000000 0x0 0xfc100>; 3949 3950 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 3951 <&gcc GCC_USB30_TERT_MASTER_CLK>, 3952 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 3953 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 3954 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 3955 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 3956 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 3957 clock-names = "cfg_noc", 3958 "core", 3959 "iface", 3960 "sleep", 3961 "mock_utmi", 3962 "noc_aggr_north", 3963 "noc_aggr_south"; 3964 3965 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 3966 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 3967 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 3968 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 3969 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 3970 interrupt-names = "dwc_usb3", 3971 "pwr_event", 3972 "dp_hs_phy_irq", 3973 "dm_hs_phy_irq", 3974 "ss_phy_irq"; 3975 3976 resets = <&gcc GCC_USB30_TERT_BCR>; 3977 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 3978 3979 iommus = <&apps_smmu 0x420 0x0>; 3980 3981 phys = <&usb_2_hsphy>, 3982 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 3983 phy-names = "usb2-phy", 3984 "usb3-phy"; 3985 3986 snps,hird-threshold = /bits/ 8 <0x0>; 3987 snps,dis-u1-entry-quirk; 3988 snps,dis-u2-entry-quirk; 3989 snps,is-utmi-l1-suspend; 3990 snps,usb3_lpm_capable; 3991 snps,has-lpm-erratum; 3992 tx-fifo-resize; 3993 snps,dis_u2_susphy_quirk; 3994 snps,dis_enblslpm_quirk; 3995 3996 status = "disabled"; 3997 3998 ports { 3999 #address-cells = <1>; 4000 #size-cells = <0>; 4001 4002 port@0 { 4003 reg = <0>; 4004 4005 usb_2_dwc3_hs: endpoint { 4006 }; 4007 }; 4008 4009 port@1 { 4010 reg = <1>; 4011 4012 usb_2_dwc3_ss: endpoint { 4013 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 4014 }; 4015 }; 4016 }; 4017 }; 4018 4019 usb_hs: usb@a2f8800 { 4020 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4021 reg = <0x0 0x0a200000 0x0 0xfc100>; 4022 4023 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4024 <&gcc GCC_USB20_MASTER_CLK>, 4025 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4026 <&gcc GCC_USB20_SLEEP_CLK>, 4027 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4028 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4029 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4030 clock-names = "cfg_noc", 4031 "core", 4032 "iface", 4033 "sleep", 4034 "mock_utmi", 4035 "noc_aggr_north", 4036 "noc_aggr_south"; 4037 4038 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4039 <&gcc GCC_USB20_MASTER_CLK>; 4040 assigned-clock-rates = <19200000>, <200000000>; 4041 4042 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4043 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 4044 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 4045 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 4046 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 4047 interrupt-names = "dwc_usb3", 4048 "pwr_event", 4049 "dp_hs_phy_irq", 4050 "dm_hs_phy_irq", 4051 "hs_phy_irq"; 4052 4053 resets = <&gcc GCC_USB20_PRIM_BCR>; 4054 4055 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4056 required-opps = <&rpmhpd_opp_nom>; 4057 4058 iommus = <&apps_smmu 0x0ce0 0x0>; 4059 4060 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4061 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4062 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4063 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4064 interconnect-names = "usb-ddr", 4065 "apps-usb"; 4066 4067 phys = <&usb_hs_phy>; 4068 phy-names = "usb2-phy"; 4069 4070 snps,hird-threshold = /bits/ 8 <0x0>; 4071 snps,dis-u1-entry-quirk; 4072 snps,dis-u2-entry-quirk; 4073 snps,is-utmi-l1-suspend; 4074 snps,usb3_lpm_capable; 4075 snps,has-lpm-erratum; 4076 tx-fifo-resize; 4077 snps,dis_u2_susphy_quirk; 4078 snps,dis_enblslpm_quirk; 4079 4080 dr_mode = "host"; 4081 4082 maximum-speed = "high-speed"; 4083 4084 status = "disabled"; 4085 }; 4086 4087 usb_mp: usb@a400000 { 4088 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 4089 reg = <0x0 0x0a400000 0x0 0xfc100>; 4090 4091 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 4092 <&gcc GCC_USB30_MP_MASTER_CLK>, 4093 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 4094 <&gcc GCC_USB30_MP_SLEEP_CLK>, 4095 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 4096 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4097 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4098 clock-names = "cfg_noc", 4099 "core", 4100 "iface", 4101 "sleep", 4102 "mock_utmi", 4103 "noc_aggr_north", 4104 "noc_aggr_south"; 4105 4106 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4107 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4108 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 4109 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 4110 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 4111 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 4112 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 4113 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 4114 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 4115 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 4116 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 4117 interrupt-names = "dwc_usb3", 4118 "pwr_event_1", 4119 "pwr_event_2", 4120 "hs_phy_1", 4121 "hs_phy_2", 4122 "dp_hs_phy_1", 4123 "dm_hs_phy_1", 4124 "dp_hs_phy_2", 4125 "dm_hs_phy_2", 4126 "ss_phy_1", 4127 "ss_phy_2"; 4128 4129 resets = <&gcc GCC_USB30_MP_BCR>; 4130 power-domains = <&gcc GCC_USB30_MP_GDSC>; 4131 4132 iommus = <&apps_smmu 0xda0 0x0>; 4133 4134 phys = <&usb_mp_hsphy0>, 4135 <&usb_mp_qmpphy0>, 4136 <&usb_mp_hsphy1>, 4137 <&usb_mp_qmpphy1>; 4138 phy-names = "usb2-0", 4139 "usb3-0", 4140 "usb2-1", 4141 "usb3-1"; 4142 4143 snps,hird-threshold = /bits/ 8 <0x0>; 4144 snps,dis-u1-entry-quirk; 4145 snps,dis-u2-entry-quirk; 4146 snps,is-utmi-l1-suspend; 4147 snps,usb3_lpm_capable; 4148 snps,has-lpm-erratum; 4149 tx-fifo-resize; 4150 snps,dis_u2_susphy_quirk; 4151 snps,dis_enblslpm_quirk; 4152 4153 dr_mode = "host"; 4154 4155 status = "disabled"; 4156 }; 4157 4158 mdss: display-subsystem@ae00000 { 4159 compatible = "qcom,glymur-mdss"; 4160 reg = <0x0 0x0ae00000 0x0 0x1000>; 4161 reg-names = "mdss"; 4162 4163 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4164 4165 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4166 <&gcc GCC_DISP_HF_AXI_CLK>, 4167 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4168 4169 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 4170 4171 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 4172 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4173 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4174 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 4175 interconnect-names = "mdp0-mem", 4176 "cpu-cfg"; 4177 4178 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 4179 4180 iommus = <&apps_smmu 0x1de0 0x2>; 4181 4182 interrupt-controller; 4183 #interrupt-cells = <1>; 4184 4185 #address-cells = <2>; 4186 #size-cells = <2>; 4187 ranges; 4188 4189 status = "disabled"; 4190 4191 mdss_mdp: display-controller@ae01000 { 4192 compatible = "qcom,glymur-dpu"; 4193 reg = <0x0 0x0ae01000 0x0 0x93000>, 4194 <0x0 0x0aeb0000 0x0 0x3000>; 4195 reg-names = "mdp", 4196 "vbif"; 4197 4198 interrupts-extended = <&mdss 0>; 4199 4200 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4201 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4202 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 4203 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4204 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4205 clock-names = "nrt_bus", 4206 "iface", 4207 "lut", 4208 "core", 4209 "vsync"; 4210 4211 operating-points-v2 = <&mdp_opp_table>; 4212 4213 power-domains = <&rpmhpd RPMHPD_MMCX>; 4214 4215 ports { 4216 #address-cells = <1>; 4217 #size-cells = <0>; 4218 4219 port@0 { 4220 reg = <0>; 4221 4222 dpu_intf0_out: endpoint { 4223 remote-endpoint = <&mdss_dp0_in>; 4224 }; 4225 }; 4226 4227 port@4 { 4228 reg = <4>; 4229 4230 mdss_intf4_out: endpoint { 4231 remote-endpoint = <&mdss_dp1_in>; 4232 }; 4233 }; 4234 4235 port@5 { 4236 reg = <5>; 4237 4238 mdss_intf5_out: endpoint { 4239 remote-endpoint = <&mdss_dp3_in>; 4240 }; 4241 }; 4242 4243 port@6 { 4244 reg = <6>; 4245 4246 mdss_intf6_out: endpoint { 4247 remote-endpoint = <&mdss_dp2_in>; 4248 }; 4249 }; 4250 }; 4251 4252 mdp_opp_table: opp-table { 4253 compatible = "operating-points-v2"; 4254 4255 opp-156000000 { 4256 opp-hz = /bits/ 64 <156000000>; 4257 required-opps = <&rpmhpd_opp_low_svs_d1>; 4258 }; 4259 4260 opp-205000000 { 4261 opp-hz = /bits/ 64 <205000000>; 4262 required-opps = <&rpmhpd_opp_low_svs>; 4263 }; 4264 4265 opp-337000000 { 4266 opp-hz = /bits/ 64 <337000000>; 4267 required-opps = <&rpmhpd_opp_svs>; 4268 }; 4269 4270 opp-417000000 { 4271 opp-hz = /bits/ 64 <417000000>; 4272 required-opps = <&rpmhpd_opp_svs_l1>; 4273 }; 4274 4275 opp-532000000 { 4276 opp-hz = /bits/ 64 <532000000>; 4277 required-opps = <&rpmhpd_opp_nom>; 4278 }; 4279 4280 opp-600000000 { 4281 opp-hz = /bits/ 64 <600000000>; 4282 required-opps = <&rpmhpd_opp_nom_l1>; 4283 }; 4284 4285 opp-660000000 { 4286 opp-hz = /bits/ 64 <660000000>; 4287 required-opps = <&rpmhpd_opp_turbo>; 4288 }; 4289 4290 opp-717000000 { 4291 opp-hz = /bits/ 64 <717000000>; 4292 required-opps = <&rpmhpd_opp_turbo_l1>; 4293 }; 4294 }; 4295 }; 4296 4297 mdss_dp0: displayport-controller@af54000 { 4298 compatible = "qcom,glymur-dp"; 4299 reg = <0x0 0xaf54000 0x0 0x200>, 4300 <0x0 0xaf54200 0x0 0x200>, 4301 <0x0 0xaf55000 0x0 0xc00>, 4302 <0x0 0xaf56000 0x0 0x400>, 4303 <0x0 0xaf57000 0x0 0x400>, 4304 <0x0 0xaf58000 0x0 0x400>, 4305 <0x0 0xaf59000 0x0 0x400>, 4306 <0x0 0xaf5a000 0x0 0x600>, 4307 <0x0 0xaf5b000 0x0 0x600>; 4308 4309 interrupts-extended = <&mdss 12>; 4310 4311 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4312 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 4313 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 4314 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4315 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 4316 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 4317 clock-names = "core_iface", 4318 "core_aux", 4319 "ctrl_link", 4320 "ctrl_link_iface", 4321 "stream_pixel", 4322 "stream_1_pixel"; 4323 4324 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4325 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 4326 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 4327 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4328 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4329 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4330 4331 operating-points-v2 = <&mdss_dp0_opp_table>; 4332 4333 power-domains = <&rpmhpd RPMHPD_MMCX>; 4334 4335 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4336 phy-names = "dp"; 4337 4338 #sound-dai-cells = <0>; 4339 4340 status = "disabled"; 4341 4342 ports { 4343 #address-cells = <1>; 4344 #size-cells = <0>; 4345 4346 port@0 { 4347 reg = <0>; 4348 4349 mdss_dp0_in: endpoint { 4350 remote-endpoint = <&dpu_intf0_out>; 4351 }; 4352 }; 4353 4354 port@1 { 4355 reg = <1>; 4356 4357 mdss_dp0_out: endpoint { 4358 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 4359 }; 4360 }; 4361 }; 4362 4363 mdss_dp0_opp_table: opp-table { 4364 compatible = "operating-points-v2"; 4365 4366 opp-270000000 { 4367 opp-hz = /bits/ 64 <270000000>; 4368 required-opps = <&rpmhpd_opp_low_svs>; 4369 }; 4370 4371 opp-540000000 { 4372 opp-hz = /bits/ 64 <540000000>; 4373 required-opps = <&rpmhpd_opp_svs>; 4374 }; 4375 4376 opp-675000000 { 4377 opp-hz = /bits/ 64 <675000000>; 4378 required-opps = <&rpmhpd_opp_svs_l1>; 4379 }; 4380 4381 opp-810000000 { 4382 opp-hz = /bits/ 64 <810000000>; 4383 required-opps = <&rpmhpd_opp_nom>; 4384 }; 4385 }; 4386 }; 4387 4388 mdss_dp1: displayport-controller@af5c000 { 4389 compatible = "qcom,glymur-dp"; 4390 reg = <0x0 0xaf5c000 0x0 0x200>, 4391 <0x0 0xaf5c200 0x0 0x200>, 4392 <0x0 0xaf5d000 0x0 0xc00>, 4393 <0x0 0xaf5e000 0x0 0x400>, 4394 <0x0 0xaf5f000 0x0 0x400>, 4395 <0x0 0xaf60000 0x0 0x400>, 4396 <0x0 0xaf61000 0x0 0x400>, 4397 <0x0 0xaf62000 0x0 0x600>, 4398 <0x0 0xaf63000 0x0 0x600>; 4399 4400 interrupts-extended = <&mdss 13>; 4401 4402 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4403 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 4404 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 4405 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4406 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 4407 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 4408 clock-names = "core_iface", 4409 "core_aux", 4410 "ctrl_link", 4411 "ctrl_link_iface", 4412 "stream_pixel", 4413 "stream_1_pixel"; 4414 4415 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4416 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 4417 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 4418 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4419 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4420 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4421 4422 operating-points-v2 = <&mdss_dp0_opp_table>; 4423 4424 power-domains = <&rpmhpd RPMHPD_MMCX>; 4425 4426 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4427 phy-names = "dp"; 4428 4429 #sound-dai-cells = <0>; 4430 4431 status = "disabled"; 4432 4433 ports { 4434 #address-cells = <1>; 4435 #size-cells = <0>; 4436 4437 port@0 { 4438 reg = <0>; 4439 4440 mdss_dp1_in: endpoint { 4441 remote-endpoint = <&mdss_intf4_out>; 4442 }; 4443 }; 4444 4445 port@1 { 4446 reg = <1>; 4447 4448 mdss_dp1_out: endpoint { 4449 remote-endpoint = <&usb_1_qmpphy_dp_in>; 4450 }; 4451 }; 4452 }; 4453 }; 4454 4455 mdss_dp2: displayport-controller@af64000 { 4456 compatible = "qcom,glymur-dp"; 4457 reg = <0x0 0x0af64000 0x0 0x200>, 4458 <0x0 0x0af64200 0x0 0x200>, 4459 <0x0 0x0af65000 0x0 0xc00>, 4460 <0x0 0x0af66000 0x0 0x400>, 4461 <0x0 0x0af67000 0x0 0x400>, 4462 <0x0 0x0af68000 0x0 0x400>, 4463 <0x0 0x0af69000 0x0 0x400>, 4464 <0x0 0x0af6a000 0x0 0x600>, 4465 <0x0 0x0af6b000 0x0 0x600>; 4466 4467 interrupts-extended = <&mdss 14>; 4468 4469 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4470 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 4471 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 4472 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4473 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 4474 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 4475 clock-names = "core_iface", 4476 "core_aux", 4477 "ctrl_link", 4478 "ctrl_link_iface", 4479 "stream_pixel", 4480 "stream_1_pixel"; 4481 4482 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4483 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 4484 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 4485 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4486 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4487 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4488 4489 operating-points-v2 = <&mdss_dp0_opp_table>; 4490 4491 power-domains = <&rpmhpd RPMHPD_MMCX>; 4492 4493 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 4494 phy-names = "dp"; 4495 4496 #sound-dai-cells = <0>; 4497 4498 status = "disabled"; 4499 4500 ports { 4501 #address-cells = <1>; 4502 #size-cells = <0>; 4503 4504 port@0 { 4505 reg = <0>; 4506 mdss_dp2_in: endpoint { 4507 remote-endpoint = <&mdss_intf6_out>; 4508 }; 4509 }; 4510 4511 port@1 { 4512 reg = <1>; 4513 4514 mdss_dp2_out: endpoint { 4515 remote-endpoint = <&usb_2_qmpphy_dp_in>; 4516 }; 4517 }; 4518 }; 4519 }; 4520 4521 mdss_dp3: displayport-controller@af6c000 { 4522 compatible = "qcom,glymur-dp"; 4523 reg = <0x0 0x0af6c000 0x0 0x200>, 4524 <0x0 0x0af6c200 0x0 0x200>, 4525 <0x0 0x0af6d000 0x0 0xc00>, 4526 <0x0 0x0af6e000 0x0 0x400>, 4527 <0x0 0x0af6f000 0x0 0x400>, 4528 <0x0 0x0af70000 0x0 0x400>, 4529 <0x0 0x0af71000 0x0 0x400>, 4530 <0x0 0x0af72000 0x0 0x600>, 4531 <0x0 0x0af73000 0x0 0x600>; 4532 4533 interrupts-extended = <&mdss 15>; 4534 4535 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4536 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 4537 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 4538 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4539 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4540 clock-names = "core_iface", 4541 "core_aux", 4542 "ctrl_link", 4543 "ctrl_link_iface", 4544 "stream_pixel"; 4545 4546 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4547 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4548 assigned-clock-parents = <&mdss_dp3_phy 0>, 4549 <&mdss_dp3_phy 1>; 4550 4551 operating-points-v2 = <&mdss_dp0_opp_table>; 4552 4553 power-domains = <&rpmhpd RPMHPD_MMCX>; 4554 4555 phys = <&mdss_dp3_phy>; 4556 phy-names = "dp"; 4557 4558 #sound-dai-cells = <0>; 4559 4560 status = "disabled"; 4561 4562 ports { 4563 #address-cells = <1>; 4564 #size-cells = <0>; 4565 4566 port@0 { 4567 reg = <0>; 4568 4569 mdss_dp3_in: endpoint { 4570 remote-endpoint = <&mdss_intf5_out>; 4571 }; 4572 }; 4573 4574 port@1 { 4575 reg = <1>; 4576 4577 mdss_dp3_out: endpoint { 4578 }; 4579 }; 4580 }; 4581 }; 4582 }; 4583 4584 dispcc: clock-controller@af00000 { 4585 compatible = "qcom,glymur-dispcc"; 4586 reg = <0x0 0x0af00000 0x0 0x20000>; 4587 clocks = <&rpmhcc RPMH_CXO_CLK>, 4588 <&sleep_clk>, 4589 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 4590 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4591 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 4592 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4593 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 4594 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4595 <&mdss_dp3_phy 0>, /* dp3 */ 4596 <&mdss_dp3_phy 1>, 4597 <0>, /* dsi0 */ 4598 <0>, 4599 <0>, /* dsi1 */ 4600 <0>, 4601 <0>, 4602 <0>, 4603 <0>, 4604 <0>; 4605 power-domains = <&rpmhpd RPMHPD_MMCX>; 4606 required-opps = <&rpmhpd_opp_low_svs>; 4607 #clock-cells = <1>; 4608 #reset-cells = <1>; 4609 #power-domain-cells = <1>; 4610 }; 4611 4612 pdc: interrupt-controller@b220000 { 4613 compatible = "qcom,glymur-pdc", "qcom,pdc"; 4614 reg = <0x0 0x0b220000 0x0 0x10000>; 4615 qcom,pdc-ranges = <0 745 51>, 4616 <51 527 47>, 4617 <98 609 32>, 4618 <130 717 12>, 4619 <142 251 5>, 4620 <147 796 16>, 4621 <171 4104 36>; 4622 #interrupt-cells = <2>; 4623 interrupt-parent = <&intc>; 4624 interrupt-controller; 4625 }; 4626 4627 tsens0: thermal-sensor@c22c000 { 4628 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4629 reg = <0x0 0x0c22c000 0x0 0x1000>, 4630 <0x0 0x0c222000 0x0 0x1000>; 4631 4632 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 4633 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 4634 interrupt-names = "uplow", 4635 "critical"; 4636 4637 #qcom,sensors = <13>; 4638 4639 #thermal-sensor-cells = <1>; 4640 }; 4641 4642 tsens1: thermal-sensor@c22d000 { 4643 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4644 reg = <0x0 0x0c22d000 0x0 0x1000>, 4645 <0x0 0x0c223000 0x0 0x1000>; 4646 4647 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 4648 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 4649 interrupt-names = "uplow", 4650 "critical"; 4651 4652 #qcom,sensors = <9>; 4653 4654 #thermal-sensor-cells = <1>; 4655 }; 4656 4657 tsens2: thermal-sensor@c22e000 { 4658 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4659 reg = <0x0 0x0c22e000 0x0 0x1000>, 4660 <0x0 0x0c224000 0x0 0x1000>; 4661 4662 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 4663 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 4664 interrupt-names = "uplow", 4665 "critical"; 4666 4667 #qcom,sensors = <13>; 4668 4669 #thermal-sensor-cells = <1>; 4670 }; 4671 4672 tsens3: thermal-sensor@c22f000 { 4673 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4674 reg = <0x0 0x0c22f000 0x0 0x1000>, 4675 <0x0 0x0c225000 0x0 0x1000>; 4676 4677 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 4678 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 4679 interrupt-names = "uplow", 4680 "critical"; 4681 4682 #qcom,sensors = <8>; 4683 4684 #thermal-sensor-cells = <1>; 4685 }; 4686 4687 tsens4: thermal-sensor@c230000 { 4688 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4689 reg = <0x0 0x0c230000 0x0 0x1000>, 4690 <0x0 0x0c226000 0x0 0x1000>; 4691 4692 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 4693 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 4694 interrupt-names = "uplow", 4695 "critical"; 4696 4697 #qcom,sensors = <13>; 4698 4699 #thermal-sensor-cells = <1>; 4700 }; 4701 4702 tsens5: thermal-sensor@c231000 { 4703 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4704 reg = <0x0 0x0c231000 0x0 0x1000>, 4705 <0x0 0x0c227000 0x0 0x1000>; 4706 4707 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 4708 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 4709 interrupt-names = "uplow", 4710 "critical"; 4711 4712 #qcom,sensors = <8>; 4713 4714 #thermal-sensor-cells = <1>; 4715 }; 4716 4717 tsens6: thermal-sensor@c232000 { 4718 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4719 reg = <0x0 0x0c232000 0x0 0x1000>, 4720 <0x0 0x0c228000 0x0 0x1000>; 4721 4722 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 4723 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 4724 interrupt-names = "uplow", 4725 "critical"; 4726 4727 #qcom,sensors = <13>; 4728 4729 #thermal-sensor-cells = <1>; 4730 }; 4731 4732 tsens7: thermal-sensor@c233000 { 4733 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 4734 reg = <0x0 0x0c233000 0x0 0x1000>, 4735 <0x0 0x0c229000 0x0 0x1000>; 4736 4737 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 4738 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 4739 interrupt-names = "uplow", 4740 "critical"; 4741 4742 #qcom,sensors = <15>; 4743 4744 #thermal-sensor-cells = <1>; 4745 }; 4746 4747 aoss_qmp: power-management@c300000 { 4748 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 4749 reg = <0x0 0x0c300000 0x0 0x400>; 4750 interrupt-parent = <&ipcc>; 4751 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 4752 IRQ_TYPE_EDGE_RISING>; 4753 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4754 4755 #clock-cells = <0>; 4756 }; 4757 4758 sram@c30f000 { 4759 compatible = "qcom,rpmh-stats"; 4760 reg = <0x0 0x0c30f000 0x0 0x400>; 4761 }; 4762 4763 arbiter@c400000 { 4764 compatible = "qcom,glymur-spmi-pmic-arb"; 4765 reg = <0x0 0x0c400000 0x0 0x3000>, 4766 <0x0 0x0c900000 0x0 0x400000>, 4767 <0x0 0x0c4c0000 0x0 0x400000>, 4768 <0x0 0x0c403000 0x0 0x8000>; 4769 reg-names = "core", 4770 "chnls", 4771 "obsrvr", 4772 "chnl_map"; 4773 #address-cells = <2>; 4774 #size-cells = <2>; 4775 ranges; 4776 qcom,channel = <0>; 4777 qcom,ee = <0>; 4778 4779 spmi_bus0: spmi@c426000 { 4780 reg = <0x0 0x0c426000 0x0 0x4000>, 4781 <0x0 0x0c8c0000 0x0 0x10000>, 4782 <0x0 0x0c42a000 0x0 0x8000>; 4783 reg-names = "cnfg", 4784 "intr", 4785 "chnl_owner"; 4786 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4787 interrupt-names = "periph_irq"; 4788 interrupt-controller; 4789 #interrupt-cells = <4>; 4790 #address-cells = <2>; 4791 #size-cells = <0>; 4792 }; 4793 4794 spmi_bus1: spmi@c437000 { 4795 reg = <0x0 0x0c437000 0x0 0x4000>, 4796 <0x0 0x0c8d0000 0x0 0x10000>, 4797 <0x0 0x0c43b000 0x0 0x8000>; 4798 reg-names = "cnfg", 4799 "intr", 4800 "chnl_owner"; 4801 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 4802 interrupt-names = "periph_irq"; 4803 interrupt-controller; 4804 #interrupt-cells = <4>; 4805 #address-cells = <2>; 4806 #size-cells = <0>; 4807 }; 4808 4809 spmi_bus2: spmi@c48000 { 4810 reg = <0x0 0x0c448000 0x0 0x4000>, 4811 <0x0 0x0c8e0000 0x0 0x10000>, 4812 <0x0 0x0c44c000 0x0 0x8000>; 4813 reg-names = "cnfg", 4814 "intr", 4815 "chnl_owner"; 4816 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 4817 interrupt-names = "periph_irq"; 4818 interrupt-controller; 4819 #interrupt-cells = <4>; 4820 #address-cells = <2>; 4821 #size-cells = <0>; 4822 }; 4823 }; 4824 4825 tlmm: pinctrl@f100000 { 4826 compatible = "qcom,glymur-tlmm"; 4827 reg = <0x0 0x0f100000 0x0 0xf00000>; 4828 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4829 gpio-controller; 4830 #gpio-cells = <2>; 4831 interrupt-controller; 4832 #interrupt-cells = <2>; 4833 gpio-ranges = <&tlmm 0 0 249>; 4834 wakeup-parent = <&pdc>; 4835 4836 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4837 /* SDA, SCL */ 4838 pins = "gpio0", "gpio1"; 4839 function = "qup0_se0"; 4840 drive-strength = <2>; 4841 bias-pull-up = <2200>; 4842 }; 4843 4844 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4845 /* SDA, SCL */ 4846 pins = "gpio4", "gpio5"; 4847 function = "qup0_se1"; 4848 drive-strength = <2>; 4849 bias-pull-up = <2200>; 4850 }; 4851 4852 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4853 /* SDA, SCL */ 4854 pins = "gpio8", "gpio9"; 4855 function = "qup0_se2"; 4856 drive-strength = <2>; 4857 bias-pull-up = <2200>; 4858 }; 4859 4860 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4861 /* SDA, SCL */ 4862 pins = "gpio12", "gpio13"; 4863 function = "qup0_se3"; 4864 drive-strength = <2>; 4865 bias-pull-up = <2200>; 4866 }; 4867 4868 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4869 /* SDA, SCL */ 4870 pins = "gpio16", "gpio17"; 4871 function = "qup0_se4"; 4872 drive-strength = <2>; 4873 bias-pull-up = <2200>; 4874 }; 4875 4876 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4877 /* SDA, SCL */ 4878 pins = "gpio20", "gpio21"; 4879 function = "qup0_se5"; 4880 drive-strength = <2>; 4881 bias-pull-up = <2200>; 4882 }; 4883 4884 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4885 /* SDA, SCL */ 4886 pins = "gpio6", "gpio7"; 4887 function = "qup0_se6"; 4888 drive-strength = <2>; 4889 bias-pull-up = <2200>; 4890 }; 4891 4892 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 4893 /* SDA, SCL */ 4894 pins = "gpio14", "gpio15"; 4895 function = "qup0_se7"; 4896 drive-strength = <2>; 4897 bias-pull-up = <2200>; 4898 }; 4899 4900 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4901 /* SDA, SCL */ 4902 pins = "gpio32", "gpio33"; 4903 function = "qup1_se0"; 4904 drive-strength = <2>; 4905 bias-pull-up = <2200>; 4906 }; 4907 4908 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4909 /* SDA, SCL */ 4910 pins = "gpio36", "gpio37"; 4911 function = "qup1_se1"; 4912 drive-strength = <2>; 4913 bias-pull-up = <2200>; 4914 }; 4915 4916 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4917 /* SDA, SCL */ 4918 pins = "gpio40", "gpio41"; 4919 function = "qup1_se2"; 4920 drive-strength = <2>; 4921 bias-pull-up = <2200>; 4922 }; 4923 4924 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4925 /* SDA, SCL */ 4926 pins = "gpio44", "gpio45"; 4927 function = "qup1_se3"; 4928 drive-strength = <2>; 4929 bias-pull-up = <2200>; 4930 }; 4931 4932 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 4933 /* SDA, SCL */ 4934 pins = "gpio48", "gpio49"; 4935 function = "qup1_se4"; 4936 drive-strength = <2>; 4937 bias-pull-up = <2200>; 4938 }; 4939 4940 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 4941 /* SDA, SCL */ 4942 pins = "gpio52", "gpio53"; 4943 function = "qup1_se5"; 4944 drive-strength = <2>; 4945 bias-pull-up = <2200>; 4946 }; 4947 4948 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 4949 /* SDA, SCL */ 4950 pins = "gpio56", "gpio57"; 4951 function = "qup1_se6"; 4952 drive-strength = <2>; 4953 bias-pull-up = <2200>; 4954 }; 4955 4956 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 4957 /* SDA, SCL */ 4958 pins = "gpio54", "gpio55"; 4959 function = "qup1_se7"; 4960 drive-strength = <2>; 4961 bias-pull-up = <2200>; 4962 }; 4963 4964 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 4965 /* SDA, SCL */ 4966 pins = "gpio64", "gpio65"; 4967 function = "qup2_se0"; 4968 drive-strength = <2>; 4969 bias-pull-up = <2200>; 4970 }; 4971 4972 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 4973 /* SDA, SCL */ 4974 pins = "gpio68", "gpio69"; 4975 function = "qup2_se1"; 4976 drive-strength = <2>; 4977 bias-pull-up = <2200>; 4978 }; 4979 4980 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 4981 /* SDA, SCL */ 4982 pins = "gpio72", "gpio73"; 4983 function = "qup2_se2"; 4984 drive-strength = <2>; 4985 bias-pull-up = <2200>; 4986 }; 4987 4988 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 4989 /* SDA, SCL */ 4990 pins = "gpio76", "gpio77"; 4991 function = "qup2_se3"; 4992 drive-strength = <2>; 4993 bias-pull-up = <2200>; 4994 }; 4995 4996 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 4997 /* SDA, SCL */ 4998 pins = "gpio80", "gpio81"; 4999 function = "qup2_se4"; 5000 drive-strength = <2>; 5001 bias-pull-up = <2200>; 5002 }; 5003 5004 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 5005 /* SDA, SCL */ 5006 pins = "gpio84", "gpio85"; 5007 function = "qup2_se5"; 5008 drive-strength = <2>; 5009 bias-pull-up = <2200>; 5010 }; 5011 5012 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 5013 /* SDA, SCL */ 5014 pins = "gpio88", "gpio89"; 5015 function = "qup2_se6"; 5016 drive-strength = <2>; 5017 bias-pull-up = <2200>; 5018 }; 5019 5020 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 5021 /* SDA, SCL */ 5022 pins = "gpio80", "gpio81"; 5023 function = "qup2_se7"; 5024 drive-strength = <2>; 5025 bias-pull-up = <2200>; 5026 }; 5027 5028 qup_spi0_cs: qup-spi0-cs-state { 5029 pins = "gpio3"; 5030 function = "qup0_se0"; 5031 drive-strength = <6>; 5032 bias-disable; 5033 }; 5034 5035 qup_spi0_data_clk: qup-spi0-data-clk-state { 5036 /* MISO, MOSI, CLK */ 5037 pins = "gpio0", "gpio1", "gpio2"; 5038 function = "qup0_se0"; 5039 drive-strength = <6>; 5040 bias-disable; 5041 }; 5042 5043 qup_spi1_cs: qup-spi1-cs-state { 5044 pins = "gpio7"; 5045 function = "qup0_se1"; 5046 drive-strength = <6>; 5047 bias-disable; 5048 }; 5049 5050 qup_spi1_data_clk: qup-spi1-data-clk-state { 5051 /* MISO, MOSI, CLK */ 5052 pins = "gpio4", "gpio5", "gpio6"; 5053 function = "qup0_se1"; 5054 drive-strength = <6>; 5055 bias-disable; 5056 }; 5057 5058 qup_spi2_cs: qup-spi2-cs-state { 5059 pins = "gpio11"; 5060 function = "qup0_se2"; 5061 drive-strength = <6>; 5062 bias-disable; 5063 }; 5064 5065 qup_spi2_data_clk: qup-spi2-data-clk-state { 5066 /* MISO, MOSI, CLK */ 5067 pins = "gpio8", "gpio9", "gpio10"; 5068 function = "qup0_se2"; 5069 drive-strength = <6>; 5070 bias-disable; 5071 }; 5072 5073 qup_spi3_cs: qup-spi3-cs-state { 5074 pins = "gpio15"; 5075 function = "qup0_se3"; 5076 drive-strength = <6>; 5077 bias-disable; 5078 }; 5079 5080 qup_spi3_data_clk: qup-spi3-data-clk-state { 5081 /* MISO, MOSI, CLK */ 5082 pins = "gpio12", "gpio13", "gpio14"; 5083 function = "qup0_se3"; 5084 drive-strength = <6>; 5085 bias-disable; 5086 }; 5087 5088 qup_spi4_cs: qup-spi4-cs-state { 5089 pins = "gpio19"; 5090 function = "qup0_se4"; 5091 drive-strength = <6>; 5092 bias-disable; 5093 }; 5094 5095 qup_spi4_data_clk: qup-spi4-data-clk-state { 5096 /* MISO, MOSI, CLK */ 5097 pins = "gpio16", "gpio17", "gpio18"; 5098 function = "qup0_se4"; 5099 drive-strength = <6>; 5100 bias-disable; 5101 }; 5102 5103 qup_spi5_cs: qup-spi5-cs-state { 5104 pins = "gpio23"; 5105 function = "qup0_se5"; 5106 drive-strength = <6>; 5107 bias-disable; 5108 }; 5109 5110 qup_spi5_data_clk: qup-spi5-data-clk-state { 5111 /* MISO, MOSI, CLK */ 5112 pins = "gpio20", "gpio21", "gpio22"; 5113 function = "qup0_se5"; 5114 drive-strength = <6>; 5115 bias-disable; 5116 }; 5117 5118 qup_spi6_cs: qup-spi6-cs-state { 5119 pins = "gpio5"; 5120 function = "qup0_se6"; 5121 drive-strength = <6>; 5122 bias-disable; 5123 }; 5124 5125 qup_spi6_data_clk: qup-spi6-data-clk-state { 5126 /* MISO, MOSI, CLK */ 5127 pins = "gpio6", "gpio7", "gpio4"; 5128 function = "qup0_se6"; 5129 drive-strength = <6>; 5130 bias-disable; 5131 }; 5132 5133 qup_spi7_cs: qup-spi7-cs-state { 5134 pins = "gpio13"; 5135 function = "qup0_se7"; 5136 drive-strength = <6>; 5137 bias-disable; 5138 }; 5139 5140 qup_spi7_data_clk: qup-spi7-data-clk-state { 5141 /* MISO, MOSI, CLK */ 5142 pins = "gpio14", "gpio15", "gpio12"; 5143 function = "qup0_se7"; 5144 drive-strength = <6>; 5145 bias-disable; 5146 }; 5147 5148 qup_spi8_cs: qup-spi8-cs-state { 5149 pins = "gpio35"; 5150 function = "qup1_se0"; 5151 drive-strength = <6>; 5152 bias-disable; 5153 }; 5154 5155 qup_spi8_data_clk: qup-spi8-data-clk-state { 5156 /* MISO, MOSI, CLK */ 5157 pins = "gpio32", "gpio33", "gpio34"; 5158 function = "qup1_se0"; 5159 drive-strength = <6>; 5160 bias-disable; 5161 }; 5162 5163 qup_spi9_cs: qup-spi9-cs-state { 5164 pins = "gpio39"; 5165 function = "qup1_se1"; 5166 drive-strength = <6>; 5167 bias-disable; 5168 }; 5169 5170 qup_spi9_data_clk: qup-spi9-data-clk-state { 5171 /* MISO, MOSI, CLK */ 5172 pins = "gpio36", "gpio37", "gpio38"; 5173 function = "qup1_se1"; 5174 drive-strength = <6>; 5175 bias-disable; 5176 }; 5177 5178 qup_spi10_cs: qup-spi10-cs-state { 5179 pins = "gpio43"; 5180 function = "qup1_se2"; 5181 drive-strength = <6>; 5182 bias-disable; 5183 }; 5184 5185 qup_spi10_data_clk: qup-spi10-data-clk-state { 5186 /* MISO, MOSI, CLK */ 5187 pins = "gpio40", "gpio41", "gpio42"; 5188 function = "qup1_se2"; 5189 drive-strength = <6>; 5190 bias-disable; 5191 }; 5192 5193 qup_spi11_cs: qup-spi11-cs-state { 5194 pins = "gpio47"; 5195 function = "qup1_se3"; 5196 drive-strength = <6>; 5197 bias-disable; 5198 }; 5199 5200 qup_spi11_data_clk: qup-spi11-data-clk-state { 5201 pins = "gpio44", "gpio45", "gpio46"; 5202 function = "qup1_se3"; 5203 drive-strength = <6>; 5204 bias-disable; 5205 }; 5206 5207 qup_spi12_cs: qup-spi12-cs-state { 5208 pins = "gpio51"; 5209 function = "qup1_se4"; 5210 drive-strength = <6>; 5211 bias-disable; 5212 }; 5213 5214 qup_spi12_data_clk: qup-spi12-data-clk-state { 5215 /* MISO, MOSI, CLK */ 5216 pins = "gpio48", "gpio49", "gpio50"; 5217 function = "qup1_se4"; 5218 drive-strength = <6>; 5219 bias-disable; 5220 }; 5221 5222 qup_spi13_cs: qup-spi13-cs-state { 5223 pins = "gpio55"; 5224 function = "qup1_se5"; 5225 drive-strength = <6>; 5226 bias-disable; 5227 }; 5228 5229 qup_spi13_data_clk: qup-spi13-data-clk-state { 5230 /* MISO, MOSI, CLK */ 5231 pins = "gpio52", "gpio53", "gpio54"; 5232 function = "qup1_se5"; 5233 drive-strength = <6>; 5234 bias-disable; 5235 }; 5236 5237 qup_spi14_cs: qup-spi14-cs-state { 5238 pins = "gpio59"; 5239 function = "qup1_se6"; 5240 drive-strength = <6>; 5241 bias-disable; 5242 }; 5243 5244 qup_spi14_data_clk: qup-spi14-data-clk-state { 5245 /* MISO, MOSI, CLK */ 5246 pins = "gpio56", "gpio57", "gpio58"; 5247 function = "qup1_se6"; 5248 drive-strength = <6>; 5249 bias-disable; 5250 }; 5251 5252 qup_spi15_cs: qup-spi15-cs-state { 5253 pins = "gpio53"; 5254 function = "qup1_se7"; 5255 drive-strength = <6>; 5256 bias-disable; 5257 }; 5258 5259 qup_spi15_data_clk: qup-spi15-data-clk-state { 5260 /* MISO, MOSI, CLK */ 5261 pins = "gpio54", "gpio55", "gpio52"; 5262 function = "qup1_se7"; 5263 drive-strength = <6>; 5264 bias-disable; 5265 }; 5266 5267 qup_spi16_cs: qup-spi16-cs-state { 5268 pins = "gpio67"; 5269 function = "qup2_se0"; 5270 drive-strength = <6>; 5271 bias-disable; 5272 }; 5273 5274 qup_spi16_data_clk: qup-spi16-data-clk-state { 5275 /* MISO, MOSI, CLK */ 5276 pins = "gpio64", "gpio65", "gpio66"; 5277 function = "qup2_se0"; 5278 drive-strength = <6>; 5279 bias-disable; 5280 }; 5281 5282 qup_spi17_cs: qup-spi17-cs-state { 5283 pins = "gpio71"; 5284 function = "qup2_se1"; 5285 drive-strength = <6>; 5286 bias-disable; 5287 }; 5288 5289 qup_spi17_data_clk: qup-spi17-data-clk-state { 5290 /* MISO, MOSI, CLK */ 5291 pins = "gpio68", "gpio69", "gpio70"; 5292 function = "qup2_se1"; 5293 drive-strength = <6>; 5294 bias-disable; 5295 }; 5296 5297 qup_spi18_cs: qup-spi18-cs-state { 5298 pins = "gpio75"; 5299 function = "qup2_se2"; 5300 drive-strength = <6>; 5301 bias-disable; 5302 }; 5303 5304 qup_spi18_data_clk: qup-spi18-data-clk-state { 5305 /* MISO, MOSI, CLK */ 5306 pins = "gpio72", "gpio73", "gpio74"; 5307 function = "qup2_se2"; 5308 drive-strength = <6>; 5309 bias-disable; 5310 }; 5311 5312 qup_spi19_cs: qup-spi19-cs-state { 5313 pins = "gpio79"; 5314 function = "qup2_se3"; 5315 drive-strength = <6>; 5316 bias-disable; 5317 }; 5318 5319 qup_spi19_data_clk: qup-spi19-data-clk-state { 5320 /* MISO, MOSI, CLK */ 5321 pins = "gpio76", "gpio77", "gpio78"; 5322 function = "qup2_se3"; 5323 drive-strength = <6>; 5324 bias-disable; 5325 }; 5326 5327 qup_spi20_cs: qup-spi20-cs-state { 5328 pins = "gpio83"; 5329 function = "qup2_se4"; 5330 drive-strength = <6>; 5331 bias-disable; 5332 }; 5333 5334 qup_spi20_data_clk: qup-spi20-data-clk-state { 5335 /* MISO, MOSI, CLK */ 5336 pins = "gpio80", "gpio81", "gpio82"; 5337 function = "qup2_se4"; 5338 drive-strength = <6>; 5339 bias-disable; 5340 }; 5341 5342 qup_spi21_cs: qup-spi21-cs-state { 5343 pins = "gpio87"; 5344 function = "qup2_se5"; 5345 drive-strength = <6>; 5346 bias-disable; 5347 }; 5348 5349 qup_spi21_data_clk: qup-spi21-data-clk-state { 5350 /* MISO, MOSI, CLK */ 5351 pins = "gpio84", "gpio85", "gpio86"; 5352 function = "qup2_se5"; 5353 drive-strength = <6>; 5354 bias-disable; 5355 }; 5356 5357 qup_spi22_cs: qup-spi22-cs-state { 5358 pins = "gpio91"; 5359 function = "qup2_se6"; 5360 drive-strength = <6>; 5361 bias-disable; 5362 }; 5363 5364 qup_spi22_data_clk: qup-spi22-data-clk-state { 5365 /* MISO, MOSI, CLK */ 5366 pins = "gpio88", "gpio89", "gpio90"; 5367 function = "qup2_se6"; 5368 drive-strength = <6>; 5369 bias-disable; 5370 }; 5371 5372 qup_spi23_cs: qup-spi23-cs-state { 5373 pins = "gpio83"; 5374 function = "qup2_se7"; 5375 drive-strength = <6>; 5376 bias-disable; 5377 }; 5378 5379 qup_spi23_data_clk: qup-spi23-data-clk-state { 5380 /* MISO, MOSI, CLK */ 5381 pins = "gpio80", "gpio81", "gpio82"; 5382 function = "qup2_se7"; 5383 drive-strength = <6>; 5384 bias-disable; 5385 }; 5386 5387 qup_uart2_default: qup-uart2-default-state { 5388 tx-pins { 5389 pins = "gpio10"; 5390 function = "qup0_se2"; 5391 drive-strength = <2>; 5392 bias-disable; 5393 }; 5394 5395 rx-pins { 5396 pins = "gpio11"; 5397 function = "qup0_se2"; 5398 drive-strength = <2>; 5399 bias-disable; 5400 }; 5401 }; 5402 5403 qup_uart14_default: qup-uart14-default-state { 5404 cts-pins { 5405 pins = "gpio56"; 5406 function = "qup1_se6"; 5407 drive-strength = <2>; 5408 bias-disable; 5409 }; 5410 5411 rts-pins { 5412 pins = "gpio57"; 5413 function = "qup1_se6"; 5414 drive-strength = <2>; 5415 bias-disable; 5416 }; 5417 5418 tx-pins { 5419 pins = "gpio58"; 5420 function = "qup1_se6"; 5421 drive-strength = <2>; 5422 bias-disable; 5423 }; 5424 5425 rx-pins { 5426 pins = "gpio59"; 5427 function = "qup1_se6"; 5428 drive-strength = <2>; 5429 bias-disable; 5430 }; 5431 }; 5432 5433 qup_uart19_default: qup-uart19-default-state { 5434 cts-pins { 5435 pins = "gpio76"; 5436 function = "qup2_se3"; 5437 drive-strength = <2>; 5438 bias-disable; 5439 }; 5440 5441 rts-pins { 5442 pins = "gpio77"; 5443 function = "qup2_se3"; 5444 drive-strength = <2>; 5445 bias-disable; 5446 }; 5447 5448 tx-pins { 5449 pins = "gpio78"; 5450 function = "qup2_se3"; 5451 drive-strength = <2>; 5452 bias-disable; 5453 }; 5454 5455 rx-pins { 5456 pins = "gpio79"; 5457 function = "qup2_se3"; 5458 drive-strength = <2>; 5459 bias-disable; 5460 }; 5461 }; 5462 5463 qup_uart21_default: qup-uart21-default-state { 5464 tx-pins { 5465 pins = "gpio86"; 5466 function = "qup2_se5"; 5467 drive-strength = <2>; 5468 bias-disable; 5469 }; 5470 5471 rx-pins { 5472 pins = "gpio87"; 5473 function = "qup2_se5"; 5474 drive-strength = <2>; 5475 bias-disable; 5476 }; 5477 }; 5478 5479 qup_uart22_default: qup-uart22-default-state { 5480 tx-pins { 5481 pins = "gpio90"; 5482 function = "qup2_se6"; 5483 drive-strength = <2>; 5484 bias-disable; 5485 }; 5486 5487 rx-pins { 5488 pins = "gpio91"; 5489 function = "qup2_se6"; 5490 drive-strength = <2>; 5491 bias-disable; 5492 }; 5493 }; 5494 }; 5495 5496 apps_smmu: iommu@15000000 { 5497 compatible = "qcom,glymur-smmu-500", 5498 "qcom,smmu-500", 5499 "arm,mmu-500"; 5500 reg = <0x0 0x15000000 0x0 0x100000>; 5501 5502 #iommu-cells = <2>; 5503 #global-interrupts = <1>; 5504 5505 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5506 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5507 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5508 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5509 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5510 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5511 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5512 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5513 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5514 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5515 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5516 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5517 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5518 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5519 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5520 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5521 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5522 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5523 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5524 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5525 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5526 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5527 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5528 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5529 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5530 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5531 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5532 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5533 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5534 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5535 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5536 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5537 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5538 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5539 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5540 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5541 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5542 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5543 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5544 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5545 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5546 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5547 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5548 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5549 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5550 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5551 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5552 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5553 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5554 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5555 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5556 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5557 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5558 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5559 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5560 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5561 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5562 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5563 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5564 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5565 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5566 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5567 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5568 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5569 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5570 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5571 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5572 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5573 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5574 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5575 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5576 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5577 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5578 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5579 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5580 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5581 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5582 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5583 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5584 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5585 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5586 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5587 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5588 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5589 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5590 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5591 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5592 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5593 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5594 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5595 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5596 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5597 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5598 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5599 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5600 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5601 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5602 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5603 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5604 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5605 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5606 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5607 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5608 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5609 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5610 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5611 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5612 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5613 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5614 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5615 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5616 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5617 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5618 5619 dma-coherent; 5620 }; 5621 5622 pcie_smmu: iommu@15480000 { 5623 compatible = "arm,smmu-v3"; 5624 reg = <0x0 0x15480000 0x0 0x20000>; 5625 interrupts = <GIC_SPI 964 IRQ_TYPE_LEVEL_HIGH>, 5626 <GIC_SPI 962 IRQ_TYPE_LEVEL_HIGH>, 5627 <GIC_SPI 960 IRQ_TYPE_LEVEL_HIGH>; 5628 interrupt-names = "eventq", "cmdq-sync", "gerror"; 5629 dma-coherent; 5630 #iommu-cells = <1>; 5631 }; 5632 5633 intc: interrupt-controller@17000000 { 5634 compatible = "arm,gic-v3"; 5635 reg = <0x0 0x17000000 0x0 0x10000>, 5636 <0x0 0x17080000 0x0 0x480000>; 5637 5638 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5639 5640 #interrupt-cells = <3>; 5641 interrupt-controller; 5642 5643 #address-cells = <2>; 5644 #size-cells = <2>; 5645 ranges; 5646 5647 gic_its: msi-controller@17040000 { 5648 compatible = "arm,gic-v3-its"; 5649 reg = <0x0 0x17040000 0x0 0x40000>; 5650 5651 msi-controller; 5652 #msi-cells = <1>; 5653 }; 5654 }; 5655 5656 watchdog@17600000 { 5657 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 5658 reg = <0x0 0x17600000 0x0 0x1000>; 5659 clocks = <&sleep_clk>; 5660 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5661 }; 5662 5663 pdp0_mbox: mailbox@17610000 { 5664 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5665 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 5666 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 5667 #mbox-cells = <1>; 5668 }; 5669 5670 timer@17810000 { 5671 compatible = "arm,armv7-timer-mem"; 5672 reg = <0x0 0x17810000 0x0 0x1000>; 5673 #address-cells = <2>; 5674 #size-cells = <1>; 5675 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 5676 5677 frame@17811000 { 5678 reg = <0x0 0x17811000 0x1000>, 5679 <0x0 0x17812000 0x1000>; 5680 5681 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5683 5684 frame-number = <0>; 5685 }; 5686 5687 frame@17813000 { 5688 reg = <0x0 0x17813000 0x1000>; 5689 5690 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5691 5692 frame-number = <1>; 5693 5694 status = "disabled"; 5695 }; 5696 5697 frame@17815000 { 5698 reg = <0x0 0x17815000 0x1000>; 5699 5700 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5701 5702 frame-number = <2>; 5703 5704 status = "disabled"; 5705 }; 5706 5707 frame@17817000 { 5708 reg = <0x0 0x17817000 0x1000>; 5709 5710 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5711 5712 frame-number = <3>; 5713 5714 status = "disabled"; 5715 }; 5716 5717 frame@17819000 { 5718 reg = <0x0 0x17819000 0x1000>; 5719 5720 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5721 5722 frame-number = <4>; 5723 5724 status = "disabled"; 5725 }; 5726 5727 frame@1781b000 { 5728 reg = <0x0 0x1781b000 0x1000>; 5729 5730 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5731 5732 frame-number = <5>; 5733 5734 status = "disabled"; 5735 }; 5736 5737 frame@1781d000 { 5738 reg = <0x0 0x1781d000 0x1000>; 5739 5740 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5741 5742 frame-number = <6>; 5743 5744 status = "disabled"; 5745 }; 5746 }; 5747 5748 apps_rsc: rsc@18900000 { 5749 compatible = "qcom,rpmh-rsc"; 5750 label = "apps_rsc"; 5751 reg = <0x0 0x18900000 0x0 0x10000>, 5752 <0x0 0x18910000 0x0 0x10000>, 5753 <0x0 0x18920000 0x0 0x10000>; 5754 reg-names = "drv-0", 5755 "drv-1", 5756 "drv-2"; 5757 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5760 qcom,tcs-offset = <0xd00>; 5761 qcom,drv-id = <2>; 5762 qcom,tcs-config = <ACTIVE_TCS 2>, 5763 <SLEEP_TCS 3>, 5764 <WAKE_TCS 3>, 5765 <CONTROL_TCS 0>; 5766 power-domains = <&system_pd>; 5767 5768 apps_bcm_voter: bcm-voter { 5769 compatible = "qcom,bcm-voter"; 5770 }; 5771 5772 rpmhcc: clock-controller { 5773 compatible = "qcom,glymur-rpmh-clk"; 5774 5775 clocks = <&xo_board>; 5776 clock-names = "xo"; 5777 5778 #clock-cells = <1>; 5779 }; 5780 5781 rpmhpd: power-controller { 5782 compatible = "qcom,glymur-rpmhpd"; 5783 5784 operating-points-v2 = <&rpmhpd_opp_table>; 5785 5786 #power-domain-cells = <1>; 5787 5788 rpmhpd_opp_table: opp-table { 5789 compatible = "operating-points-v2"; 5790 5791 rpmhpd_opp_ret: opp-16 { 5792 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5793 }; 5794 5795 rpmhpd_opp_min_svs: opp-48 { 5796 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5797 }; 5798 5799 rpmhpd_opp_low_svs_d2: opp-52 { 5800 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5801 }; 5802 5803 rpmhpd_opp_low_svs_d1: opp-56 { 5804 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5805 }; 5806 5807 rpmhpd_opp_low_svs_d0: opp-60 { 5808 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5809 }; 5810 5811 rpmhpd_opp_low_svs: opp-64 { 5812 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5813 }; 5814 5815 rpmhpd_opp_low_svs_l1: opp-80 { 5816 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5817 }; 5818 5819 rpmhpd_opp_svs: opp-128 { 5820 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5821 }; 5822 5823 rpmhpd_opp_svs_l0: opp-144 { 5824 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5825 }; 5826 5827 rpmhpd_opp_svs_l1: opp-192 { 5828 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5829 }; 5830 5831 rpmhpd_opp_nom: opp-256 { 5832 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5833 }; 5834 5835 rpmhpd_opp_nom_l1: opp-320 { 5836 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5837 }; 5838 5839 rpmhpd_opp_nom_l2: opp-336 { 5840 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5841 }; 5842 5843 rpmhpd_opp_turbo: opp-384 { 5844 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5845 }; 5846 5847 rpmhpd_opp_turbo_l1: opp-416 { 5848 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5849 }; 5850 }; 5851 }; 5852 }; 5853 5854 nsi_noc: interconnect@1d600000 { 5855 compatible = "qcom,glymur-nsinoc"; 5856 reg = <0x0 0x1d600000 0x0 0x14080>; 5857 qcom,bcm-voters = <&apps_bcm_voter>; 5858 #interconnect-cells = <2>; 5859 }; 5860 5861 oobm_ss_noc: interconnect@1f300000 { 5862 compatible = "qcom,glymur-oobm-ss-noc"; 5863 reg = <0x0 0x1f300000 0x0 0x49a00>; 5864 qcom,bcm-voters = <&apps_bcm_voter>; 5865 #interconnect-cells = <2>; 5866 }; 5867 5868 system-cache-controller@20400000 { 5869 compatible = "qcom,glymur-llcc"; 5870 reg = <0x0 0x21800000 0x0 0x100000>, 5871 <0x0 0x21a00000 0x0 0x100000>, 5872 <0x0 0x21c00000 0x0 0x100000>, 5873 <0x0 0x21e00000 0x0 0x100000>, 5874 <0x0 0x22800000 0x0 0x100000>, 5875 <0x0 0x22a00000 0x0 0x100000>, 5876 <0x0 0x22c00000 0x0 0x100000>, 5877 <0x0 0x22e00000 0x0 0x100000>, 5878 <0x0 0x23800000 0x0 0x100000>, 5879 <0x0 0x23a00000 0x0 0x100000>, 5880 <0x0 0x23c00000 0x0 0x100000>, 5881 <0x0 0x23e00000 0x0 0x100000>, 5882 <0x0 0x20400000 0x0 0x100000>, 5883 <0x0 0x20600000 0x0 0x100000>; 5884 reg-names = "llcc0_base", 5885 "llcc1_base", 5886 "llcc2_base", 5887 "llcc3_base", 5888 "llcc4_base", 5889 "llcc5_base", 5890 "llcc6_base", 5891 "llcc7_base", 5892 "llcc8_base", 5893 "llcc9_base", 5894 "llcc10_base", 5895 "llcc11_base", 5896 "llcc_broadcast_base", 5897 "llcc_broadcast_and_base"; 5898 5899 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5900 }; 5901 5902 nsp_noc: interconnect@320c0000 { 5903 compatible = "qcom,glymur-nsp-noc"; 5904 reg = <0x0 0x320c0000 0x0 0x21280>; 5905 qcom,bcm-voters = <&apps_bcm_voter>; 5906 #interconnect-cells = <2>; 5907 }; 5908 5909 imem: sram@81e08000 { 5910 compatible = "mmio-sram"; 5911 reg = <0x0 0x81e08600 0x0 0x300>; 5912 5913 #address-cells = <1>; 5914 #size-cells = <1>; 5915 ranges = <0x0 0x0 0x81e08600 0x300>; 5916 5917 cpu_scp_lpri0: scp-sram-section@0 { 5918 compatible = "arm,scmi-shmem"; 5919 reg = <0x0 0x180>; 5920 }; 5921 5922 cpu_scp_lpri1: scp-sram-section@180 { 5923 compatible = "arm,scmi-shmem"; 5924 reg = <0x180 0x180>; 5925 }; 5926 }; 5927 }; 5928 5929 timer { 5930 compatible = "arm,armv8-timer"; 5931 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 5932 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 5933 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 5934 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 5935 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 5936 }; 5937 5938 thermal_zones: thermal-zones { 5939 aoss-0-thermal { 5940 thermal-sensors = <&tsens0 0>; 5941 5942 trips { 5943 aoss-0-critical { 5944 temperature = <115000>; 5945 hysteresis = <1000>; 5946 type = "critical"; 5947 }; 5948 }; 5949 }; 5950 5951 cpu-0-0-0-thermal { 5952 thermal-sensors = <&tsens0 1>; 5953 5954 trips { 5955 cpu-0-0-0-critical { 5956 temperature = <115000>; 5957 hysteresis = <1000>; 5958 type = "critical"; 5959 }; 5960 }; 5961 }; 5962 5963 cpu-0-0-1-thermal { 5964 thermal-sensors = <&tsens0 2>; 5965 5966 trips { 5967 cpu-0-0-1-critical { 5968 temperature = <115000>; 5969 hysteresis = <1000>; 5970 type = "critical"; 5971 }; 5972 }; 5973 }; 5974 5975 cpu-0-1-0-thermal { 5976 thermal-sensors = <&tsens0 3>; 5977 5978 trips { 5979 cpu-0-1-0-critical { 5980 temperature = <115000>; 5981 hysteresis = <1000>; 5982 type = "critical"; 5983 }; 5984 }; 5985 }; 5986 5987 cpu-0-1-1-thermal { 5988 thermal-sensors = <&tsens0 4>; 5989 5990 trips { 5991 cpu-0-1-1-critical { 5992 temperature = <115000>; 5993 hysteresis = <1000>; 5994 type = "critical"; 5995 }; 5996 }; 5997 }; 5998 5999 cpu-0-2-0-thermal { 6000 thermal-sensors = <&tsens0 5>; 6001 6002 trips { 6003 cpu-0-2-0-critical { 6004 temperature = <115000>; 6005 hysteresis = <1000>; 6006 type = "critical"; 6007 }; 6008 }; 6009 }; 6010 6011 cpu-0-2-1-thermal { 6012 thermal-sensors = <&tsens0 6>; 6013 6014 trips { 6015 cpu-0-2-1-critical { 6016 temperature = <115000>; 6017 hysteresis = <1000>; 6018 type = "critical"; 6019 }; 6020 }; 6021 }; 6022 6023 cpu-0-3-0-thermal { 6024 thermal-sensors = <&tsens0 7>; 6025 6026 trips { 6027 cpu-0-3-0-critical { 6028 temperature = <115000>; 6029 hysteresis = <1000>; 6030 type = "critical"; 6031 }; 6032 }; 6033 }; 6034 6035 cpu-0-3-1-thermal { 6036 thermal-sensors = <&tsens0 8>; 6037 6038 trips { 6039 cpu-0-3-1-critical { 6040 temperature = <115000>; 6041 hysteresis = <1000>; 6042 type = "critical"; 6043 }; 6044 }; 6045 }; 6046 6047 cpu-0-4-0-thermal { 6048 thermal-sensors = <&tsens0 9>; 6049 6050 trips { 6051 cpu-0-4-0-critical { 6052 temperature = <115000>; 6053 hysteresis = <1000>; 6054 type = "critical"; 6055 }; 6056 }; 6057 }; 6058 6059 cpu-0-4-1-thermal { 6060 thermal-sensors = <&tsens0 10>; 6061 6062 trips { 6063 cpu-0-4-1-critical { 6064 temperature = <115000>; 6065 hysteresis = <1000>; 6066 type = "critical"; 6067 }; 6068 }; 6069 }; 6070 6071 cpu-0-5-0-thermal { 6072 thermal-sensors = <&tsens0 11>; 6073 6074 trips { 6075 cpu-0-5-0-critical { 6076 temperature = <115000>; 6077 hysteresis = <1000>; 6078 type = "critical"; 6079 }; 6080 }; 6081 }; 6082 6083 cpu-0-5-1-thermal { 6084 thermal-sensors = <&tsens0 12>; 6085 6086 trips { 6087 cpu-0-5-1-critical { 6088 temperature = <115000>; 6089 hysteresis = <1000>; 6090 type = "critical"; 6091 }; 6092 }; 6093 }; 6094 6095 aoss-1-thermal { 6096 thermal-sensors = <&tsens1 0>; 6097 6098 trips { 6099 aoss-1-critical { 6100 temperature = <115000>; 6101 hysteresis = <1000>; 6102 type = "critical"; 6103 }; 6104 }; 6105 }; 6106 6107 cpullc-0-0-thermal { 6108 thermal-sensors = <&tsens1 1>; 6109 6110 trips { 6111 cpullc-0-0-critical { 6112 temperature = <115000>; 6113 hysteresis = <1000>; 6114 type = "critical"; 6115 }; 6116 }; 6117 }; 6118 6119 cpullc-0-1-thermal { 6120 thermal-sensors = <&tsens1 2>; 6121 6122 trips { 6123 cpullc-0-1-critical { 6124 temperature = <115000>; 6125 hysteresis = <1000>; 6126 type = "critical"; 6127 }; 6128 }; 6129 }; 6130 6131 qmx-0-0-thermal { 6132 thermal-sensors = <&tsens1 3>; 6133 6134 trips { 6135 qmx-0-0-critical { 6136 temperature = <115000>; 6137 hysteresis = <1000>; 6138 type = "critical"; 6139 }; 6140 }; 6141 }; 6142 6143 qmx-0-1-thermal { 6144 thermal-sensors = <&tsens1 4>; 6145 6146 trips { 6147 qmx-0-1-critical { 6148 temperature = <115000>; 6149 hysteresis = <1000>; 6150 type = "critical"; 6151 }; 6152 }; 6153 }; 6154 6155 qmx-0-2-thermal { 6156 thermal-sensors = <&tsens1 5>; 6157 6158 trips { 6159 qmx-0-2-critical { 6160 temperature = <115000>; 6161 hysteresis = <1000>; 6162 type = "critical"; 6163 }; 6164 }; 6165 }; 6166 6167 ddr-0-thermal { 6168 thermal-sensors = <&tsens1 6>; 6169 6170 trips { 6171 ddr-0-critical { 6172 temperature = <115000>; 6173 hysteresis = <1000>; 6174 type = "critical"; 6175 }; 6176 }; 6177 }; 6178 6179 thermal_video_0: video-0-thermal { 6180 thermal-sensors = <&tsens1 7>; 6181 6182 trips { 6183 video-0-critical { 6184 temperature = <115000>; 6185 hysteresis = <1000>; 6186 type = "critical"; 6187 }; 6188 }; 6189 }; 6190 6191 thermal_video_1: video-1-thermal { 6192 thermal-sensors = <&tsens1 8>; 6193 6194 trips { 6195 video-1-critical { 6196 temperature = <115000>; 6197 hysteresis = <1000>; 6198 type = "critical"; 6199 }; 6200 }; 6201 }; 6202 6203 aoss-2-thermal { 6204 thermal-sensors = <&tsens2 0>; 6205 6206 trips { 6207 aoss-2-critical { 6208 temperature = <115000>; 6209 hysteresis = <1000>; 6210 type = "critical"; 6211 }; 6212 }; 6213 }; 6214 6215 cpu-1-0-0-thermal { 6216 thermal-sensors = <&tsens2 1>; 6217 6218 trips { 6219 cpu-1-0-0-critical { 6220 temperature = <115000>; 6221 hysteresis = <1000>; 6222 type = "critical"; 6223 }; 6224 }; 6225 }; 6226 6227 cpu-1-0-1-thermal { 6228 thermal-sensors = <&tsens2 2>; 6229 6230 trips { 6231 cpu-1-0-1-critical { 6232 temperature = <115000>; 6233 hysteresis = <1000>; 6234 type = "critical"; 6235 }; 6236 }; 6237 }; 6238 6239 cpu-1-1-0-thermal { 6240 thermal-sensors = <&tsens2 3>; 6241 6242 trips { 6243 cpu-1-1-0-critical { 6244 temperature = <115000>; 6245 hysteresis = <1000>; 6246 type = "critical"; 6247 }; 6248 }; 6249 }; 6250 6251 cpu-1-1-1-thermal { 6252 thermal-sensors = <&tsens2 4>; 6253 6254 trips { 6255 cpu-1-1-1-critical { 6256 temperature = <115000>; 6257 hysteresis = <1000>; 6258 type = "critical"; 6259 }; 6260 }; 6261 }; 6262 6263 cpu-1-2-0-thermal { 6264 thermal-sensors = <&tsens2 5>; 6265 6266 trips { 6267 cpu-1-2-0-critical { 6268 temperature = <115000>; 6269 hysteresis = <1000>; 6270 type = "critical"; 6271 }; 6272 }; 6273 }; 6274 6275 cpu-1-2-1-thermal { 6276 thermal-sensors = <&tsens2 6>; 6277 6278 trips { 6279 cpu-1-2-1-critical { 6280 temperature = <115000>; 6281 hysteresis = <1000>; 6282 type = "critical"; 6283 }; 6284 }; 6285 }; 6286 6287 cpu-1-3-0-thermal { 6288 thermal-sensors = <&tsens2 7>; 6289 6290 trips { 6291 cpu-1-3-0-critical { 6292 temperature = <115000>; 6293 hysteresis = <1000>; 6294 type = "critical"; 6295 }; 6296 }; 6297 }; 6298 6299 cpu-1-3-1-thermal { 6300 thermal-sensors = <&tsens2 8>; 6301 6302 trips { 6303 cpu-1-3-1-critical { 6304 temperature = <115000>; 6305 hysteresis = <1000>; 6306 type = "critical"; 6307 }; 6308 }; 6309 }; 6310 6311 cpu-1-4-0-thermal { 6312 thermal-sensors = <&tsens2 9>; 6313 6314 trips { 6315 cpu-1-4-0-critical { 6316 temperature = <115000>; 6317 hysteresis = <1000>; 6318 type = "critical"; 6319 }; 6320 }; 6321 }; 6322 6323 cpu-1-4-1-thermal { 6324 thermal-sensors = <&tsens2 10>; 6325 6326 trips { 6327 cpu-1-4-1-critical { 6328 temperature = <115000>; 6329 hysteresis = <1000>; 6330 type = "critical"; 6331 }; 6332 }; 6333 }; 6334 6335 cpu-1-5-0-thermal { 6336 thermal-sensors = <&tsens2 11>; 6337 6338 trips { 6339 cpu-1-5-0-critical { 6340 temperature = <115000>; 6341 hysteresis = <1000>; 6342 type = "critical"; 6343 }; 6344 }; 6345 }; 6346 6347 cpu-1-5-1-thermal { 6348 thermal-sensors = <&tsens2 12>; 6349 6350 trips { 6351 cpu-1-5-1-critical { 6352 temperature = <115000>; 6353 hysteresis = <1000>; 6354 type = "critical"; 6355 }; 6356 }; 6357 }; 6358 6359 aoss-3-thermal { 6360 thermal-sensors = <&tsens3 0>; 6361 6362 trips { 6363 aoss-3-critical { 6364 temperature = <115000>; 6365 hysteresis = <1000>; 6366 type = "critical"; 6367 }; 6368 }; 6369 }; 6370 6371 cpullc-1-0-thermal { 6372 thermal-sensors = <&tsens3 1>; 6373 6374 trips { 6375 cpullc-1-0-critical { 6376 temperature = <115000>; 6377 hysteresis = <1000>; 6378 type = "critical"; 6379 }; 6380 }; 6381 }; 6382 6383 cpullc-1-1-thermal { 6384 thermal-sensors = <&tsens3 2>; 6385 6386 trips { 6387 cpullc-1-1-critical { 6388 temperature = <115000>; 6389 hysteresis = <1000>; 6390 type = "critical"; 6391 }; 6392 }; 6393 }; 6394 6395 qmx-1-0-thermal { 6396 thermal-sensors = <&tsens3 3>; 6397 6398 trips { 6399 qmx-1-0-critical { 6400 temperature = <115000>; 6401 hysteresis = <1000>; 6402 type = "critical"; 6403 }; 6404 }; 6405 }; 6406 6407 qmx-1-1-thermal { 6408 thermal-sensors = <&tsens3 4>; 6409 6410 trips { 6411 qmx-1-1-critical { 6412 temperature = <115000>; 6413 hysteresis = <1000>; 6414 type = "critical"; 6415 }; 6416 }; 6417 }; 6418 6419 qmx-1-2-thermal { 6420 thermal-sensors = <&tsens3 5>; 6421 6422 trips { 6423 qmx-1-2-critical { 6424 temperature = <115000>; 6425 hysteresis = <1000>; 6426 type = "critical"; 6427 }; 6428 }; 6429 }; 6430 6431 qmx-1-3-thermal { 6432 thermal-sensors = <&tsens3 6>; 6433 6434 trips { 6435 qmx-1-3-critical { 6436 temperature = <115000>; 6437 hysteresis = <1000>; 6438 type = "critical"; 6439 }; 6440 }; 6441 }; 6442 6443 qmx-1-4-thermal { 6444 thermal-sensors = <&tsens3 7>; 6445 6446 trips { 6447 qmx-1-4-critical { 6448 temperature = <115000>; 6449 hysteresis = <1000>; 6450 type = "critical"; 6451 }; 6452 }; 6453 }; 6454 6455 aoss-4-thermal { 6456 thermal-sensors = <&tsens4 0>; 6457 6458 trips { 6459 aoss-4-critical { 6460 temperature = <115000>; 6461 hysteresis = <1000>; 6462 type = "critical"; 6463 }; 6464 }; 6465 }; 6466 6467 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 6468 thermal-sensors = <&tsens4 1>; 6469 6470 trips { 6471 cpu-2-0-0-critical { 6472 temperature = <115000>; 6473 hysteresis = <1000>; 6474 type = "critical"; 6475 }; 6476 }; 6477 }; 6478 6479 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 6480 thermal-sensors = <&tsens4 2>; 6481 6482 trips { 6483 cpu-2-0-1-critical { 6484 temperature = <115000>; 6485 hysteresis = <1000>; 6486 type = "critical"; 6487 }; 6488 }; 6489 }; 6490 6491 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 6492 thermal-sensors = <&tsens4 3>; 6493 6494 trips { 6495 cpu-2-1-0-critical { 6496 temperature = <115000>; 6497 hysteresis = <1000>; 6498 type = "critical"; 6499 }; 6500 }; 6501 }; 6502 6503 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 6504 thermal-sensors = <&tsens4 4>; 6505 6506 trips { 6507 cpu-2-1-1-critical { 6508 temperature = <115000>; 6509 hysteresis = <1000>; 6510 type = "critical"; 6511 }; 6512 }; 6513 }; 6514 6515 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 6516 thermal-sensors = <&tsens4 5>; 6517 6518 trips { 6519 cpu-2-2-0-critical { 6520 temperature = <115000>; 6521 hysteresis = <1000>; 6522 type = "critical"; 6523 }; 6524 }; 6525 }; 6526 6527 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 6528 thermal-sensors = <&tsens4 6>; 6529 6530 trips { 6531 cpu-2-2-1-critical { 6532 temperature = <115000>; 6533 hysteresis = <1000>; 6534 type = "critical"; 6535 }; 6536 }; 6537 }; 6538 6539 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 6540 thermal-sensors = <&tsens4 7>; 6541 6542 trips { 6543 cpu-2-3-0-critical { 6544 temperature = <115000>; 6545 hysteresis = <1000>; 6546 type = "critical"; 6547 }; 6548 }; 6549 }; 6550 6551 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 6552 thermal-sensors = <&tsens4 8>; 6553 6554 trips { 6555 cpu-2-3-1-critical { 6556 temperature = <115000>; 6557 hysteresis = <1000>; 6558 type = "critical"; 6559 }; 6560 }; 6561 }; 6562 6563 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 6564 thermal-sensors = <&tsens4 9>; 6565 6566 trips { 6567 cpu-2-4-0-critical { 6568 temperature = <115000>; 6569 hysteresis = <1000>; 6570 type = "critical"; 6571 }; 6572 }; 6573 }; 6574 6575 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 6576 thermal-sensors = <&tsens4 10>; 6577 6578 trips { 6579 cpu-2-4-1-critical { 6580 temperature = <115000>; 6581 hysteresis = <1000>; 6582 type = "critical"; 6583 }; 6584 }; 6585 }; 6586 6587 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 6588 thermal-sensors = <&tsens4 11>; 6589 6590 trips { 6591 cpu-2-5-0-critical { 6592 temperature = <115000>; 6593 hysteresis = <1000>; 6594 type = "critical"; 6595 }; 6596 }; 6597 }; 6598 6599 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 6600 thermal-sensors = <&tsens4 12>; 6601 6602 trips { 6603 cpu-2-5-1-critical { 6604 temperature = <115000>; 6605 hysteresis = <1000>; 6606 type = "critical"; 6607 }; 6608 }; 6609 }; 6610 6611 aoss-5-thermal { 6612 thermal-sensors = <&tsens5 0>; 6613 6614 trips { 6615 aoss-5-critical { 6616 temperature = <115000>; 6617 hysteresis = <1000>; 6618 type = "critical"; 6619 }; 6620 }; 6621 }; 6622 6623 thermal_cpullc_2_0: cpullc-2-0-thermal { 6624 thermal-sensors = <&tsens5 1>; 6625 6626 trips { 6627 cpullc-2-0-critical { 6628 temperature = <115000>; 6629 hysteresis = <1000>; 6630 type = "critical"; 6631 }; 6632 }; 6633 }; 6634 6635 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 6636 thermal-sensors = <&tsens5 2>; 6637 6638 trips { 6639 cpullc-2-1-critical { 6640 temperature = <115000>; 6641 hysteresis = <1000>; 6642 type = "critical"; 6643 }; 6644 }; 6645 }; 6646 6647 thermal_qmx_2_0: qmx-2-0-thermal { 6648 thermal-sensors = <&tsens5 3>; 6649 6650 trips { 6651 qmx-2-0-critical { 6652 temperature = <115000>; 6653 hysteresis = <1000>; 6654 type = "critical"; 6655 }; 6656 }; 6657 }; 6658 6659 thermal_qmx_2_1: qmx-2-1-thermal { 6660 thermal-sensors = <&tsens5 4>; 6661 6662 trips { 6663 qmx-2-1-critical { 6664 temperature = <115000>; 6665 hysteresis = <1000>; 6666 type = "critical"; 6667 }; 6668 }; 6669 }; 6670 6671 thermal_qmx_2_2: qmx-2-2-thermal { 6672 thermal-sensors = <&tsens5 5>; 6673 6674 trips { 6675 qmx-2-2-critical { 6676 temperature = <115000>; 6677 hysteresis = <1000>; 6678 type = "critical"; 6679 }; 6680 }; 6681 }; 6682 6683 thermal_qmx_2_3: qmx-2-3-thermal { 6684 thermal-sensors = <&tsens5 6>; 6685 6686 trips { 6687 qmx-2-3-critical { 6688 temperature = <115000>; 6689 hysteresis = <1000>; 6690 type = "critical"; 6691 }; 6692 }; 6693 }; 6694 6695 thermal_qmx_2_4: qmx-2-4-thermal { 6696 thermal-sensors = <&tsens5 7>; 6697 6698 trips { 6699 qmx-2-4-critical { 6700 temperature = <115000>; 6701 hysteresis = <1000>; 6702 type = "critical"; 6703 }; 6704 }; 6705 }; 6706 6707 thermal_aoss_6: aoss-6-thermal { 6708 thermal-sensors = <&tsens6 0>; 6709 6710 trips { 6711 aoss-6-critical { 6712 temperature = <115000>; 6713 hysteresis = <1000>; 6714 type = "critical"; 6715 }; 6716 }; 6717 }; 6718 6719 thermal_nsphvx_0: nsphvx-0-thermal { 6720 thermal-sensors = <&tsens6 1>; 6721 6722 trips { 6723 nsphvx-0-critical { 6724 temperature = <115000>; 6725 hysteresis = <1000>; 6726 type = "critical"; 6727 }; 6728 }; 6729 }; 6730 6731 thermal_nsphvx_1: nsphvx-1-thermal { 6732 thermal-sensors = <&tsens6 2>; 6733 6734 trips { 6735 nsphvx-1-critical { 6736 temperature = <115000>; 6737 hysteresis = <1000>; 6738 type = "critical"; 6739 }; 6740 }; 6741 }; 6742 6743 thermal_nsphvx_2: nsphvx-2-thermal { 6744 thermal-sensors = <&tsens6 3>; 6745 6746 trips { 6747 nsphvx-2-critical { 6748 temperature = <115000>; 6749 hysteresis = <1000>; 6750 type = "critical"; 6751 }; 6752 }; 6753 }; 6754 6755 thermal_nsphvx_3: nsphvx-3-thermal { 6756 thermal-sensors = <&tsens6 4>; 6757 6758 trips { 6759 nsphvx-3-critical { 6760 temperature = <115000>; 6761 hysteresis = <1000>; 6762 type = "critical"; 6763 }; 6764 }; 6765 }; 6766 6767 thermal_nsphmx_0: nsphmx-0-thermal { 6768 thermal-sensors = <&tsens6 5>; 6769 6770 trips { 6771 nsphmx-0-critical { 6772 temperature = <115000>; 6773 hysteresis = <1000>; 6774 type = "critical"; 6775 }; 6776 }; 6777 }; 6778 6779 thermal_nsphmx_1: nsphmx-1-thermal { 6780 thermal-sensors = <&tsens6 6>; 6781 6782 trips { 6783 nsphmx-1-critical { 6784 temperature = <115000>; 6785 hysteresis = <1000>; 6786 type = "critical"; 6787 }; 6788 }; 6789 }; 6790 6791 thermal_nsphmx_2: nsphmx-2-thermal { 6792 thermal-sensors = <&tsens6 7>; 6793 6794 trips { 6795 nsphmx-2-critical { 6796 temperature = <115000>; 6797 hysteresis = <1000>; 6798 type = "critical"; 6799 }; 6800 }; 6801 }; 6802 6803 thermal_nsphmx_3: nsphmx-3-thermal { 6804 thermal-sensors = <&tsens6 8>; 6805 6806 trips { 6807 nsphmx-3-critical { 6808 temperature = <115000>; 6809 hysteresis = <1000>; 6810 type = "critical"; 6811 }; 6812 }; 6813 }; 6814 6815 thermal_camera_0: camera-0-thermal { 6816 thermal-sensors = <&tsens6 9>; 6817 6818 trips { 6819 camera-0-critical { 6820 temperature = <115000>; 6821 hysteresis = <1000>; 6822 type = "critical"; 6823 }; 6824 }; 6825 }; 6826 6827 thermal_camera_1: camera-1-thermal { 6828 thermal-sensors = <&tsens6 10>; 6829 6830 trips { 6831 camera-1-critical { 6832 temperature = <115000>; 6833 hysteresis = <1000>; 6834 type = "critical"; 6835 }; 6836 }; 6837 }; 6838 6839 thermal_ddr_1: ddr-1-thermal { 6840 thermal-sensors = <&tsens6 11>; 6841 6842 trips { 6843 ddr-1-critical { 6844 temperature = <115000>; 6845 hysteresis = <1000>; 6846 type = "critical"; 6847 }; 6848 }; 6849 }; 6850 6851 thermal_ddr_2: ddr-2-thermal { 6852 thermal-sensors = <&tsens6 12>; 6853 6854 trips { 6855 ddr-2-critical { 6856 temperature = <115000>; 6857 hysteresis = <1000>; 6858 type = "critical"; 6859 }; 6860 }; 6861 }; 6862 6863 thermal_aoss_7: aoss-7-thermal { 6864 thermal-sensors = <&tsens7 0>; 6865 6866 trips { 6867 aoss-7-critical { 6868 temperature = <115000>; 6869 hysteresis = <1000>; 6870 type = "critical"; 6871 }; 6872 }; 6873 }; 6874 6875 thermal_gpu_0_0: gpu-0-0-thermal { 6876 thermal-sensors = <&tsens7 1>; 6877 6878 trips { 6879 trip-point0 { 6880 temperature = <90000>; 6881 hysteresis = <5000>; 6882 type = "hot"; 6883 }; 6884 6885 gpu-0-0-critical { 6886 temperature = <115000>; 6887 hysteresis = <1000>; 6888 type = "critical"; 6889 }; 6890 }; 6891 }; 6892 6893 thermal_gpu_0_1: gpu-0-1-thermal { 6894 thermal-sensors = <&tsens7 2>; 6895 6896 trips { 6897 trip-point0 { 6898 temperature = <90000>; 6899 hysteresis = <5000>; 6900 type = "hot"; 6901 }; 6902 6903 gpu-0-1-critical { 6904 temperature = <115000>; 6905 hysteresis = <1000>; 6906 type = "critical"; 6907 }; 6908 }; 6909 }; 6910 6911 thermal_gpu_0_2: gpu-0-2-thermal { 6912 thermal-sensors = <&tsens7 3>; 6913 6914 trips { 6915 trip-point0 { 6916 temperature = <90000>; 6917 hysteresis = <5000>; 6918 type = "hot"; 6919 }; 6920 6921 gpu-0-2-critical { 6922 temperature = <115000>; 6923 hysteresis = <1000>; 6924 type = "critical"; 6925 }; 6926 }; 6927 }; 6928 6929 thermal_gpu_1_0: gpu-1-0-thermal { 6930 thermal-sensors = <&tsens7 4>; 6931 6932 trips { 6933 trip-point0 { 6934 temperature = <90000>; 6935 hysteresis = <5000>; 6936 type = "hot"; 6937 }; 6938 6939 gpu-1-0-critical { 6940 temperature = <115000>; 6941 hysteresis = <1000>; 6942 type = "critical"; 6943 }; 6944 }; 6945 }; 6946 6947 thermal_gpu_1_1: gpu-1-1-thermal { 6948 thermal-sensors = <&tsens7 5>; 6949 6950 trips { 6951 trip-point0 { 6952 temperature = <90000>; 6953 hysteresis = <5000>; 6954 type = "hot"; 6955 }; 6956 6957 gpu-1-1-critical { 6958 temperature = <115000>; 6959 hysteresis = <1000>; 6960 type = "critical"; 6961 }; 6962 }; 6963 }; 6964 6965 thermal_gpu_1_2: gpu-1-2-thermal { 6966 thermal-sensors = <&tsens7 6>; 6967 6968 trips { 6969 trip-point0 { 6970 temperature = <90000>; 6971 hysteresis = <5000>; 6972 type = "hot"; 6973 }; 6974 6975 gpu-1-2-critical { 6976 temperature = <115000>; 6977 hysteresis = <1000>; 6978 type = "critical"; 6979 }; 6980 }; 6981 }; 6982 6983 thermal_gpu_2_0: gpu-2-0-thermal { 6984 thermal-sensors = <&tsens7 7>; 6985 6986 trips { 6987 trip-point0 { 6988 temperature = <90000>; 6989 hysteresis = <5000>; 6990 type = "hot"; 6991 }; 6992 6993 gpu-2-0-critical { 6994 temperature = <115000>; 6995 hysteresis = <1000>; 6996 type = "critical"; 6997 }; 6998 }; 6999 }; 7000 7001 thermal_gpu_2_1: gpu-2-1-thermal { 7002 thermal-sensors = <&tsens7 8>; 7003 7004 trips { 7005 trip-point0 { 7006 temperature = <90000>; 7007 hysteresis = <5000>; 7008 type = "hot"; 7009 }; 7010 7011 gpu-2-1-critical { 7012 temperature = <115000>; 7013 hysteresis = <1000>; 7014 type = "critical"; 7015 }; 7016 }; 7017 }; 7018 7019 thermal_gpu_2_2: gpu-2-2-thermal { 7020 thermal-sensors = <&tsens7 9>; 7021 7022 trips { 7023 trip-point0 { 7024 temperature = <90000>; 7025 hysteresis = <5000>; 7026 type = "hot"; 7027 }; 7028 7029 gpu-2-2-critical { 7030 temperature = <115000>; 7031 hysteresis = <1000>; 7032 type = "critical"; 7033 }; 7034 }; 7035 }; 7036 7037 thermal_gpu_3_0: gpu-3-0-thermal { 7038 thermal-sensors = <&tsens7 10>; 7039 7040 trips { 7041 trip-point0 { 7042 temperature = <90000>; 7043 hysteresis = <5000>; 7044 type = "hot"; 7045 }; 7046 7047 gpu-3-0-critical { 7048 temperature = <115000>; 7049 hysteresis = <1000>; 7050 type = "critical"; 7051 }; 7052 }; 7053 }; 7054 7055 thermal_gpu_3_1: gpu-3-1-thermal { 7056 thermal-sensors = <&tsens7 11>; 7057 7058 trips { 7059 trip-point0 { 7060 temperature = <90000>; 7061 hysteresis = <5000>; 7062 type = "hot"; 7063 }; 7064 7065 gpu-3-1-critical { 7066 temperature = <115000>; 7067 hysteresis = <1000>; 7068 type = "critical"; 7069 }; 7070 }; 7071 }; 7072 7073 thermal_gpu_3_2: gpu-3-2-thermal { 7074 thermal-sensors = <&tsens7 12>; 7075 7076 trips { 7077 trip-point0 { 7078 temperature = <90000>; 7079 hysteresis = <5000>; 7080 type = "hot"; 7081 }; 7082 7083 gpu-3-2-critical { 7084 temperature = <115000>; 7085 hysteresis = <1000>; 7086 type = "critical"; 7087 }; 7088 }; 7089 }; 7090 7091 thermal_gpuss_0: gpuss-0-thermal { 7092 thermal-sensors = <&tsens7 13>; 7093 7094 trips { 7095 trip-point0 { 7096 temperature = <90000>; 7097 hysteresis = <5000>; 7098 type = "hot"; 7099 }; 7100 7101 gpuss-0-critical { 7102 temperature = <115000>; 7103 hysteresis = <1000>; 7104 type = "critical"; 7105 }; 7106 }; 7107 }; 7108 7109 thermal_gpuss_1: gpuss-1-thermal { 7110 thermal-sensors = <&tsens7 14>; 7111 7112 trips { 7113 trip-point0 { 7114 temperature = <90000>; 7115 hysteresis = <5000>; 7116 type = "hot"; 7117 }; 7118 7119 gpuss-1-critical { 7120 temperature = <115000>; 7121 hysteresis = <1000>; 7122 type = "critical"; 7123 }; 7124 }; 7125 }; 7126 }; 7127}; 7128