1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 12#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a78c"; 53 reg = <0x0 0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 capacity-dmips-mhz = <1946>; 59 dynamic-power-coefficient = <472>; 60 #cooling-cells = <2>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 64 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 65 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 66 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 67 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78c"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_1>; 82 power-domains = <&cpu_pd1>; 83 power-domain-names = "psci"; 84 capacity-dmips-mhz = <1946>; 85 #cooling-cells = <2>; 86 dynamic-power-coefficient = <472>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 90 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 91 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 92 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 93 94 l2_1: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_0>; 99 }; 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a78c"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 next-level-cache = <&l2_2>; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 capacity-dmips-mhz = <1946>; 111 #cooling-cells = <2>; 112 dynamic-power-coefficient = <507>; 113 qcom,freq-domain = <&cpufreq_hw 2>; 114 operating-points-v2 = <&cpu2_opp_table>; 115 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 116 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 117 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 118 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 119 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78c"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 next-level-cache = <&l2_3>; 134 power-domains = <&cpu_pd3>; 135 power-domain-names = "psci"; 136 capacity-dmips-mhz = <1946>; 137 #cooling-cells = <2>; 138 dynamic-power-coefficient = <507>; 139 qcom,freq-domain = <&cpufreq_hw 2>; 140 operating-points-v2 = <&cpu2_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 146 l2_3: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu4: cpu@10000 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a55"; 157 reg = <0x0 0x10000>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_4>; 160 power-domains = <&cpu_pd4>; 161 power-domain-names = "psci"; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 operating-points-v2 = <&cpu4_opp_table>; 167 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 168 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 170 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 171 172 l2_4: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_1>; 177 }; 178 }; 179 180 cpu5: cpu@10100 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a55"; 183 reg = <0x0 0x10100>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_5>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 capacity-dmips-mhz = <1024>; 189 #cooling-cells = <2>; 190 dynamic-power-coefficient = <100>; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 operating-points-v2 = <&cpu4_opp_table>; 193 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 195 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 196 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 197 198 l2_5: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_1>; 203 }; 204 }; 205 206 cpu6: cpu@10200 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a55"; 209 reg = <0x0 0x10200>; 210 enable-method = "psci"; 211 next-level-cache = <&l2_6>; 212 power-domains = <&cpu_pd6>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <1024>; 215 #cooling-cells = <2>; 216 dynamic-power-coefficient = <100>; 217 qcom,freq-domain = <&cpufreq_hw 1>; 218 operating-points-v2 = <&cpu4_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 221 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 222 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 223 224 l2_6: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_1>; 229 }; 230 }; 231 232 cpu7: cpu@10300 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a55"; 235 reg = <0x0 0x10300>; 236 enable-method = "psci"; 237 next-level-cache = <&l2_7>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 capacity-dmips-mhz = <1024>; 241 #cooling-cells = <2>; 242 dynamic-power-coefficient = <100>; 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 operating-points-v2 = <&cpu4_opp_table>; 245 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 247 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 248 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 249 250 l2_7: l2-cache { 251 compatible = "cache"; 252 cache-level = <2>; 253 cache-unified; 254 next-level-cache = <&l3_1>; 255 }; 256 }; 257 258 cpu-map { 259 cluster0 { 260 core0 { 261 cpu = <&cpu0>; 262 }; 263 264 core1 { 265 cpu = <&cpu1>; 266 }; 267 268 core2 { 269 cpu = <&cpu2>; 270 }; 271 272 core3 { 273 cpu = <&cpu3>; 274 }; 275 }; 276 277 cluster1 { 278 core0 { 279 cpu = <&cpu4>; 280 }; 281 282 core1 { 283 cpu = <&cpu5>; 284 }; 285 286 core2 { 287 cpu = <&cpu6>; 288 }; 289 290 core3 { 291 cpu = <&cpu7>; 292 }; 293 }; 294 }; 295 296 l3_0: l3-cache-0 { 297 compatible = "cache"; 298 cache-level = <3>; 299 cache-unified; 300 }; 301 302 l3_1: l3-cache-1 { 303 compatible = "cache"; 304 cache-level = <3>; 305 cache-unified; 306 }; 307 308 idle-states { 309 entry-method = "psci"; 310 311 little_cpu_sleep_0: cpu-sleep-0-0 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "silver-rail-power-collapse"; 314 arm,psci-suspend-param = <0x40000004>; 315 entry-latency-us = <602>; 316 exit-latency-us = <961>; 317 min-residency-us = <4288>; 318 local-timer-stop; 319 }; 320 321 big_cpu_sleep_0: cpu-sleep-1-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "gold-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <702>; 326 exit-latency-us = <1061>; 327 min-residency-us = <4488>; 328 local-timer-stop; 329 }; 330 }; 331 332 domain-idle-states { 333 silver_cluster_sleep: cluster-sleep-0 { 334 compatible = "domain-idle-state"; 335 arm,psci-suspend-param = <0x41000044>; 336 entry-latency-us = <2552>; 337 exit-latency-us = <2848>; 338 min-residency-us = <5908>; 339 }; 340 341 gold_cluster_sleep: cluster-sleep-1 { 342 compatible = "domain-idle-state"; 343 arm,psci-suspend-param = <0x41000044>; 344 entry-latency-us = <2752>; 345 exit-latency-us = <3048>; 346 min-residency-us = <6118>; 347 }; 348 349 system_sleep: domain-sleep { 350 compatible = "domain-idle-state"; 351 arm,psci-suspend-param = <0x42000144>; 352 entry-latency-us = <3263>; 353 exit-latency-us = <6562>; 354 min-residency-us = <9987>; 355 }; 356 }; 357 }; 358 359 cpu0_opp_table: opp-table-cpu0 { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-902400000 { 364 opp-hz = /bits/ 64 <902400000>; 365 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 366 }; 367 368 opp-1017600000 { 369 opp-hz = /bits/ 64 <1017600000>; 370 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 371 }; 372 373 opp-1190400000 { 374 opp-hz = /bits/ 64 <1190400000>; 375 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 376 }; 377 378 opp-1267200000 { 379 opp-hz = /bits/ 64 <1267200000>; 380 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 381 }; 382 383 opp-1344000000 { 384 opp-hz = /bits/ 64 <1344000000>; 385 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 386 }; 387 388 opp-1420800000 { 389 opp-hz = /bits/ 64 <1420800000>; 390 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 391 }; 392 393 opp-1497600000 { 394 opp-hz = /bits/ 64 <1497600000>; 395 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 396 }; 397 398 opp-1574400000 { 399 opp-hz = /bits/ 64 <1574400000>; 400 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 401 }; 402 403 opp-1670400000 { 404 opp-hz = /bits/ 64 <1670400000>; 405 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 406 }; 407 408 opp-1747200000 { 409 opp-hz = /bits/ 64 <1747200000>; 410 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 411 }; 412 413 opp-1824000000 { 414 opp-hz = /bits/ 64 <1824000000>; 415 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 416 }; 417 418 opp-1900800000 { 419 opp-hz = /bits/ 64 <1900800000>; 420 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 421 }; 422 423 opp-1977600000 { 424 opp-hz = /bits/ 64 <1977600000>; 425 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 426 }; 427 428 opp-2054400000 { 429 opp-hz = /bits/ 64 <2054400000>; 430 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 431 }; 432 433 opp-2112000000 { 434 opp-hz = /bits/ 64 <2112000000>; 435 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 436 }; 437 438 }; 439 440 cpu2_opp_table: opp-table-cpu2 { 441 compatible = "operating-points-v2"; 442 opp-shared; 443 444 opp-940800000 { 445 opp-hz = /bits/ 64 <940800000>; 446 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 447 }; 448 449 opp-1094400000 { 450 opp-hz = /bits/ 64 <1094400000>; 451 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 452 }; 453 454 opp-1267200000 { 455 opp-hz = /bits/ 64 <1267200000>; 456 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 457 }; 458 459 opp-1344000000 { 460 opp-hz = /bits/ 64 <1344000000>; 461 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 462 }; 463 464 opp-1420800000 { 465 opp-hz = /bits/ 64 <1420800000>; 466 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 467 }; 468 469 opp-1497600000 { 470 opp-hz = /bits/ 64 <1497600000>; 471 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 472 }; 473 474 opp-1574400000 { 475 opp-hz = /bits/ 64 <1574400000>; 476 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 477 }; 478 479 opp-1632000000 { 480 opp-hz = /bits/ 64 <1632000000>; 481 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 482 }; 483 484 opp-1708800000 { 485 opp-hz = /bits/ 64 <1708800000>; 486 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 487 }; 488 489 opp-1804800000 { 490 opp-hz = /bits/ 64 <1804800000>; 491 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 492 }; 493 494 opp-1900800000 { 495 opp-hz = /bits/ 64 <1900800000>; 496 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 497 }; 498 499 opp-1977600000 { 500 opp-hz = /bits/ 64 <1977600000>; 501 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 502 }; 503 504 opp-2054400000 { 505 opp-hz = /bits/ 64 <2054400000>; 506 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 507 }; 508 509 opp-2131200000 { 510 opp-hz = /bits/ 64 <2131200000>; 511 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 512 }; 513 514 opp-2208000000 { 515 opp-hz = /bits/ 64 <2208000000>; 516 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 517 }; 518 519 opp-2284800000 { 520 opp-hz = /bits/ 64 <2284800000>; 521 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 522 }; 523 524 opp-2361600000 { 525 opp-hz = /bits/ 64 <2361600000>; 526 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 527 }; 528 529 }; 530 531 cpu4_opp_table: opp-table-cpu4 { 532 compatible = "operating-points-v2"; 533 opp-shared; 534 535 opp-844800000 { 536 opp-hz = /bits/ 64 <844800000>; 537 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 538 }; 539 540 opp-1113600000 { 541 opp-hz = /bits/ 64 <1113600000>; 542 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 543 }; 544 545 opp-1209600000 { 546 opp-hz = /bits/ 64 <1209600000>; 547 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 548 }; 549 550 opp-1305600000 { 551 opp-hz = /bits/ 64 <1305600000>; 552 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 553 }; 554 555 opp-1382400000 { 556 opp-hz = /bits/ 64 <1382400000>; 557 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 558 }; 559 560 opp-1459200000 { 561 opp-hz = /bits/ 64 <1459200000>; 562 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 563 }; 564 565 opp-1497600000 { 566 opp-hz = /bits/ 64 <1497600000>; 567 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 568 }; 569 570 opp-1574400000 { 571 opp-hz = /bits/ 64 <1574400000>; 572 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 573 }; 574 575 opp-1651200000 { 576 opp-hz = /bits/ 64 <1651200000>; 577 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 578 }; 579 580 opp-1728000000 { 581 opp-hz = /bits/ 64 <1728000000>; 582 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 583 }; 584 585 opp-1804800000 { 586 opp-hz = /bits/ 64 <1804800000>; 587 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 588 }; 589 590 opp-1881600000 { 591 opp-hz = /bits/ 64 <1881600000>; 592 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 593 }; 594 595 opp-1958400000 { 596 opp-hz = /bits/ 64 <1958400000>; 597 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 598 }; 599 }; 600 601 dummy_eud: dummy-sink { 602 compatible = "arm,coresight-dummy-sink"; 603 604 in-ports { 605 port { 606 eud_in: endpoint { 607 remote-endpoint = <&swao_rep_out1>; 608 }; 609 }; 610 }; 611 }; 612 613 firmware { 614 scm: scm { 615 compatible = "qcom,scm-qcs8300", "qcom,scm"; 616 qcom,dload-mode = <&tcsr 0x13000>; 617 sram = <&minidump_config>; 618 }; 619 }; 620 621 memory@80000000 { 622 device_type = "memory"; 623 /* We expect the bootloader to fill in the size */ 624 reg = <0x0 0x80000000 0x0 0x0>; 625 }; 626 627 clk_virt: interconnect-0 { 628 compatible = "qcom,qcs8300-clk-virt"; 629 #interconnect-cells = <2>; 630 qcom,bcm-voters = <&apps_bcm_voter>; 631 }; 632 633 mc_virt: interconnect-1 { 634 compatible = "qcom,qcs8300-mc-virt"; 635 #interconnect-cells = <2>; 636 qcom,bcm-voters = <&apps_bcm_voter>; 637 }; 638 639 qup_opp_table: opp-table-qup { 640 compatible = "operating-points-v2"; 641 642 opp-120000000 { 643 opp-hz = /bits/ 64 <120000000>; 644 required-opps = <&rpmhpd_opp_svs_l1>; 645 }; 646 }; 647 648 pmu-a55 { 649 compatible = "arm,cortex-a55-pmu"; 650 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 651 }; 652 653 pmu-a78 { 654 compatible = "arm,cortex-a78-pmu"; 655 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 656 }; 657 658 psci { 659 compatible = "arm,psci-1.0"; 660 method = "smc"; 661 662 cpu_pd0: power-domain-cpu0 { 663 #power-domain-cells = <0>; 664 power-domains = <&cluster_pd0>; 665 domain-idle-states = <&big_cpu_sleep_0>; 666 }; 667 668 cpu_pd1: power-domain-cpu1 { 669 #power-domain-cells = <0>; 670 power-domains = <&cluster_pd0>; 671 domain-idle-states = <&big_cpu_sleep_0>; 672 }; 673 674 cpu_pd2: power-domain-cpu2 { 675 #power-domain-cells = <0>; 676 power-domains = <&cluster_pd0>; 677 domain-idle-states = <&big_cpu_sleep_0>; 678 }; 679 680 cpu_pd3: power-domain-cpu3 { 681 #power-domain-cells = <0>; 682 power-domains = <&cluster_pd0>; 683 domain-idle-states = <&big_cpu_sleep_0>; 684 }; 685 686 cpu_pd4: power-domain-cpu4 { 687 #power-domain-cells = <0>; 688 power-domains = <&cluster_pd1>; 689 domain-idle-states = <&little_cpu_sleep_0>; 690 }; 691 692 cpu_pd5: power-domain-cpu5 { 693 #power-domain-cells = <0>; 694 power-domains = <&cluster_pd1>; 695 domain-idle-states = <&little_cpu_sleep_0>; 696 }; 697 698 cpu_pd6: power-domain-cpu6 { 699 #power-domain-cells = <0>; 700 power-domains = <&cluster_pd1>; 701 domain-idle-states = <&little_cpu_sleep_0>; 702 }; 703 704 cpu_pd7: power-domain-cpu7 { 705 #power-domain-cells = <0>; 706 power-domains = <&cluster_pd1>; 707 domain-idle-states = <&little_cpu_sleep_0>; 708 }; 709 710 cluster_pd0: power-domain-cluster0 { 711 #power-domain-cells = <0>; 712 power-domains = <&system_pd>; 713 domain-idle-states = <&gold_cluster_sleep>; 714 }; 715 716 cluster_pd1: power-domain-cluster1 { 717 #power-domain-cells = <0>; 718 power-domains = <&system_pd>; 719 domain-idle-states = <&silver_cluster_sleep>; 720 }; 721 722 system_pd: power-domain-system { 723 #power-domain-cells = <0>; 724 domain-idle-states = <&system_sleep>; 725 }; 726 }; 727 728 reserved-memory { 729 #address-cells = <2>; 730 #size-cells = <2>; 731 ranges; 732 733 aop_image_mem: aop-image-region@90800000 { 734 reg = <0x0 0x90800000 0x0 0x60000>; 735 no-map; 736 }; 737 738 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 739 compatible = "qcom,cmd-db"; 740 reg = <0x0 0x90860000 0x0 0x20000>; 741 no-map; 742 }; 743 744 smem_mem: smem@90900000 { 745 compatible = "qcom,smem"; 746 reg = <0x0 0x90900000 0x0 0x200000>; 747 no-map; 748 hwlocks = <&tcsr_mutex 3>; 749 }; 750 751 gunyah_md_mem: gunyah-md-region@91a80000 { 752 reg = <0x0 0x91a80000 0x0 0x80000>; 753 no-map; 754 }; 755 756 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 757 reg = <0x0 0x93b00000 0x0 0xf00000>; 758 no-map; 759 }; 760 761 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 762 reg = <0x0 0x94a00000 0x0 0x800000>; 763 no-map; 764 }; 765 766 camera_mem: camera-region@95200000 { 767 reg = <0x0 0x95200000 0x0 0x500000>; 768 no-map; 769 }; 770 771 adsp_mem: adsp-region@95c00000 { 772 no-map; 773 reg = <0x0 0x95c00000 0x0 0x1e00000>; 774 }; 775 776 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 777 reg = <0x0 0x97a00000 0x0 0x80000>; 778 no-map; 779 }; 780 781 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 782 reg = <0x0 0x97a80000 0x0 0x80000>; 783 no-map; 784 }; 785 786 gpdsp_mem: gpdsp-region@97b00000 { 787 reg = <0x0 0x97b00000 0x0 0x1e00000>; 788 no-map; 789 }; 790 791 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 792 reg = <0x0 0x99900000 0x0 0x80000>; 793 no-map; 794 }; 795 796 cdsp_mem: cdsp-region@99980000 { 797 reg = <0x0 0x99980000 0x0 0x1e00000>; 798 no-map; 799 }; 800 801 gpu_microcode_mem: gpu-microcode-region@9b780000 { 802 reg = <0x0 0x9b780000 0x0 0x2000>; 803 no-map; 804 }; 805 806 cvp_mem: cvp-region@9b782000 { 807 reg = <0x0 0x9b782000 0x0 0x700000>; 808 no-map; 809 }; 810 811 video_mem: video-region@9be82000 { 812 reg = <0x0 0x9be82000 0x0 0x700000>; 813 no-map; 814 }; 815 }; 816 817 smp2p-adsp { 818 compatible = "qcom,smp2p"; 819 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 820 IPCC_MPROC_SIGNAL_SMP2P 821 IRQ_TYPE_EDGE_RISING>; 822 mboxes = <&ipcc IPCC_CLIENT_LPASS 823 IPCC_MPROC_SIGNAL_SMP2P>; 824 825 qcom,smem = <443>, <429>; 826 qcom,local-pid = <0>; 827 qcom,remote-pid = <2>; 828 829 smp2p_adsp_in: slave-kernel { 830 qcom,entry-name = "slave-kernel"; 831 interrupt-controller; 832 #interrupt-cells = <2>; 833 }; 834 835 smp2p_adsp_out: master-kernel { 836 qcom,entry-name = "master-kernel"; 837 #qcom,smem-state-cells = <1>; 838 }; 839 }; 840 841 smp2p-cdsp { 842 compatible = "qcom,smp2p"; 843 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 844 IPCC_MPROC_SIGNAL_SMP2P 845 IRQ_TYPE_EDGE_RISING>; 846 mboxes = <&ipcc IPCC_CLIENT_CDSP 847 IPCC_MPROC_SIGNAL_SMP2P>; 848 849 qcom,smem = <94>, <432>; 850 qcom,local-pid = <0>; 851 qcom,remote-pid = <5>; 852 853 smp2p_cdsp_in: slave-kernel { 854 qcom,entry-name = "slave-kernel"; 855 interrupt-controller; 856 #interrupt-cells = <2>; 857 }; 858 859 smp2p_cdsp_out: master-kernel { 860 qcom,entry-name = "master-kernel"; 861 #qcom,smem-state-cells = <1>; 862 }; 863 }; 864 865 smp2p-gpdsp { 866 compatible = "qcom,smp2p"; 867 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 868 IPCC_MPROC_SIGNAL_SMP2P 869 IRQ_TYPE_EDGE_RISING>; 870 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 871 IPCC_MPROC_SIGNAL_SMP2P>; 872 873 qcom,smem = <617>, <616>; 874 qcom,local-pid = <0>; 875 qcom,remote-pid = <17>; 876 877 smp2p_gpdsp_in: slave-kernel { 878 qcom,entry-name = "slave-kernel"; 879 interrupt-controller; 880 #interrupt-cells = <2>; 881 }; 882 883 smp2p_gpdsp_out: master-kernel { 884 qcom,entry-name = "master-kernel"; 885 #qcom,smem-state-cells = <1>; 886 }; 887 }; 888 889 soc: soc@0 { 890 compatible = "simple-bus"; 891 ranges = <0 0 0 0 0x10 0>; 892 #address-cells = <2>; 893 #size-cells = <2>; 894 895 gcc: clock-controller@100000 { 896 compatible = "qcom,qcs8300-gcc"; 897 reg = <0x0 0x00100000 0x0 0xc7018>; 898 #clock-cells = <1>; 899 #reset-cells = <1>; 900 #power-domain-cells = <1>; 901 clocks = <&rpmhcc RPMH_CXO_CLK>, 902 <&sleep_clk>, 903 <&pcie0_phy>, 904 <&pcie1_phy>, 905 <0>, 906 <0>, 907 <0>, 908 <0>, 909 <0>, 910 <0>; 911 }; 912 913 ipcc: mailbox@408000 { 914 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 915 reg = <0x0 0x408000 0x0 0x1000>; 916 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 917 interrupt-controller; 918 #interrupt-cells = <3>; 919 #mbox-cells = <2>; 920 }; 921 922 qfprom: efuse@784000 { 923 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 924 reg = <0x0 0x00784000 0x0 0x2410>; 925 #address-cells = <1>; 926 #size-cells = <1>; 927 928 gpu_speed_bin: gpu-speed-bin@240c { 929 reg = <0x240c 0x1>; 930 bits = <0 8>; 931 }; 932 }; 933 934 gpi_dma0: dma-controller@900000 { 935 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 936 reg = <0x0 0x900000 0x0 0x60000>; 937 #dma-cells = <3>; 938 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 950 iommus = <&apps_smmu 0x416 0x0>; 951 dma-channels = <12>; 952 dma-channel-mask = <0xfff>; 953 dma-coherent; 954 status = "disabled"; 955 }; 956 957 qupv3_id_0: geniqup@9c0000 { 958 compatible = "qcom,geni-se-qup"; 959 reg = <0x0 0x9c0000 0x0 0x2000>; 960 ranges; 961 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 962 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 963 clock-names = "m-ahb", 964 "s-ahb"; 965 #address-cells = <2>; 966 #size-cells = <2>; 967 iommus = <&apps_smmu 0x403 0x0>; 968 dma-coherent; 969 status = "disabled"; 970 971 i2c0: i2c@980000 { 972 compatible = "qcom,geni-i2c"; 973 reg = <0x0 0x980000 0x0 0x4000>; 974 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 975 clock-names = "se"; 976 pinctrl-0 = <&qup_i2c0_data_clk>; 977 pinctrl-names = "default"; 978 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 982 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 983 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 984 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 985 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 986 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 987 interconnect-names = "qup-core", 988 "qup-config", 989 "qup-memory"; 990 power-domains = <&rpmhpd RPMHPD_CX>; 991 required-opps = <&rpmhpd_opp_low_svs>; 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 993 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 994 dma-names = "tx", 995 "rx"; 996 status = "disabled"; 997 }; 998 999 spi0: spi@980000 { 1000 compatible = "qcom,geni-spi"; 1001 reg = <0x0 0x980000 0x0 0x4000>; 1002 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1003 clock-names = "se"; 1004 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1005 pinctrl-names = "default"; 1006 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1010 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1011 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1012 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1013 interconnect-names = "qup-core", 1014 "qup-config"; 1015 power-domains = <&rpmhpd RPMHPD_CX>; 1016 operating-points-v2 = <&qup_opp_table>; 1017 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1018 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1019 dma-names = "tx", 1020 "rx"; 1021 status = "disabled"; 1022 }; 1023 1024 uart0: serial@980000 { 1025 compatible = "qcom,geni-uart"; 1026 reg = <0x0 0x980000 0x0 0x4000>; 1027 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1028 clock-names = "se"; 1029 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1030 <&qup_uart0_tx>, <&qup_uart0_rx>; 1031 pinctrl-names = "default"; 1032 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1033 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1034 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1035 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1036 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1037 interconnect-names = "qup-core", 1038 "qup-config"; 1039 power-domains = <&rpmhpd RPMHPD_CX>; 1040 operating-points-v2 = <&qup_opp_table>; 1041 status = "disabled"; 1042 }; 1043 1044 i2c1: i2c@984000 { 1045 compatible = "qcom,geni-i2c"; 1046 reg = <0x0 0x984000 0x0 0x4000>; 1047 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1048 clock-names = "se"; 1049 pinctrl-0 = <&qup_i2c1_data_clk>; 1050 pinctrl-names = "default"; 1051 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1055 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1056 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1057 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1058 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1059 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1060 interconnect-names = "qup-core", 1061 "qup-config", 1062 "qup-memory"; 1063 power-domains = <&rpmhpd RPMHPD_CX>; 1064 required-opps = <&rpmhpd_opp_low_svs>; 1065 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1066 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1067 dma-names = "tx", 1068 "rx"; 1069 status = "disabled"; 1070 }; 1071 1072 spi1: spi@984000 { 1073 compatible = "qcom,geni-spi"; 1074 reg = <0x0 0x984000 0x0 0x4000>; 1075 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1076 clock-names = "se"; 1077 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1078 pinctrl-names = "default"; 1079 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1083 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1084 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1085 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1086 interconnect-names = "qup-core", 1087 "qup-config"; 1088 power-domains = <&rpmhpd RPMHPD_CX>; 1089 operating-points-v2 = <&qup_opp_table>; 1090 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1091 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1092 dma-names = "tx", 1093 "rx"; 1094 status = "disabled"; 1095 }; 1096 1097 uart1: serial@984000 { 1098 compatible = "qcom,geni-uart"; 1099 reg = <0x0 0x984000 0x0 0x4000>; 1100 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1101 clock-names = "se"; 1102 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1103 <&qup_uart1_tx>, <&qup_uart1_rx>; 1104 pinctrl-names = "default"; 1105 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1106 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1107 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1108 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1109 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1110 interconnect-names = "qup-core", 1111 "qup-config"; 1112 power-domains = <&rpmhpd RPMHPD_CX>; 1113 operating-points-v2 = <&qup_opp_table>; 1114 status = "disabled"; 1115 }; 1116 1117 i2c2: i2c@988000 { 1118 compatible = "qcom,geni-i2c"; 1119 reg = <0x0 0x988000 0x0 0x4000>; 1120 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1121 clock-names = "se"; 1122 pinctrl-0 = <&qup_i2c2_data_clk>; 1123 pinctrl-names = "default"; 1124 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1125 #address-cells = <1>; 1126 #size-cells = <0>; 1127 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1130 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1131 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 power-domains = <&rpmhpd RPMHPD_CX>; 1137 required-opps = <&rpmhpd_opp_low_svs>; 1138 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1139 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1140 dma-names = "tx", 1141 "rx"; 1142 status = "disabled"; 1143 }; 1144 1145 spi2: spi@988000 { 1146 compatible = "qcom,geni-spi"; 1147 reg = <0x0 0x988000 0x0 0x4000>; 1148 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1149 clock-names = "se"; 1150 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1151 pinctrl-names = "default"; 1152 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1156 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1157 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1158 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1159 interconnect-names = "qup-core", 1160 "qup-config"; 1161 power-domains = <&rpmhpd RPMHPD_CX>; 1162 operating-points-v2 = <&qup_opp_table>; 1163 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1164 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1165 dma-names = "tx", 1166 "rx"; 1167 status = "disabled"; 1168 }; 1169 1170 uart2: serial@988000 { 1171 compatible = "qcom,geni-uart"; 1172 reg = <0x0 0x988000 0x0 0x4000>; 1173 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1174 clock-names = "se"; 1175 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1176 <&qup_uart2_tx>, <&qup_uart2_rx>; 1177 pinctrl-names = "default"; 1178 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1179 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1180 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1181 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1182 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1183 interconnect-names = "qup-core", 1184 "qup-config"; 1185 power-domains = <&rpmhpd RPMHPD_CX>; 1186 operating-points-v2 = <&qup_opp_table>; 1187 status = "disabled"; 1188 }; 1189 1190 i2c3: i2c@98c000 { 1191 compatible = "qcom,geni-i2c"; 1192 reg = <0x0 0x98c000 0x0 0x4000>; 1193 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1194 clock-names = "se"; 1195 pinctrl-0 = <&qup_i2c3_data_clk>; 1196 pinctrl-names = "default"; 1197 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1201 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1202 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1203 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1204 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1205 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1206 interconnect-names = "qup-core", 1207 "qup-config", 1208 "qup-memory"; 1209 power-domains = <&rpmhpd RPMHPD_CX>; 1210 required-opps = <&rpmhpd_opp_low_svs>; 1211 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1212 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1213 dma-names = "tx", 1214 "rx"; 1215 status = "disabled"; 1216 }; 1217 1218 spi3: spi@98c000 { 1219 compatible = "qcom,geni-spi"; 1220 reg = <0x0 0x98c000 0x0 0x4000>; 1221 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1222 clock-names = "se"; 1223 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1224 pinctrl-names = "default"; 1225 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1229 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1230 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1231 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1232 interconnect-names = "qup-core", 1233 "qup-config"; 1234 power-domains = <&rpmhpd RPMHPD_CX>; 1235 operating-points-v2 = <&qup_opp_table>; 1236 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1237 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1238 dma-names = "tx", 1239 "rx"; 1240 status = "disabled"; 1241 }; 1242 1243 uart3: serial@98c000 { 1244 compatible = "qcom,geni-uart"; 1245 reg = <0x0 0x98c000 0x0 0x4000>; 1246 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1247 clock-names = "se"; 1248 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1249 <&qup_uart3_tx>, <&qup_uart3_rx>; 1250 pinctrl-names = "default"; 1251 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1252 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1253 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1254 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1255 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1256 interconnect-names = "qup-core", 1257 "qup-config"; 1258 power-domains = <&rpmhpd RPMHPD_CX>; 1259 operating-points-v2 = <&qup_opp_table>; 1260 status = "disabled"; 1261 }; 1262 1263 i2c4: i2c@990000 { 1264 compatible = "qcom,geni-i2c"; 1265 reg = <0x0 0x990000 0x0 0x4000>; 1266 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1267 clock-names = "se"; 1268 pinctrl-0 = <&qup_i2c4_data_clk>; 1269 pinctrl-names = "default"; 1270 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1274 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1275 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1276 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1277 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1278 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1279 interconnect-names = "qup-core", 1280 "qup-config", 1281 "qup-memory"; 1282 power-domains = <&rpmhpd RPMHPD_CX>; 1283 required-opps = <&rpmhpd_opp_low_svs>; 1284 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1285 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1286 dma-names = "tx", 1287 "rx"; 1288 status = "disabled"; 1289 }; 1290 1291 spi4: spi@990000 { 1292 compatible = "qcom,geni-spi"; 1293 reg = <0x0 0x990000 0x0 0x4000>; 1294 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1295 clock-names = "se"; 1296 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1297 pinctrl-names = "default"; 1298 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1299 #address-cells = <1>; 1300 #size-cells = <0>; 1301 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1302 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1303 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1304 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1305 interconnect-names = "qup-core", 1306 "qup-config"; 1307 power-domains = <&rpmhpd RPMHPD_CX>; 1308 operating-points-v2 = <&qup_opp_table>; 1309 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1310 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1311 dma-names = "tx", 1312 "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 uart4: serial@990000 { 1317 compatible = "qcom,geni-uart"; 1318 reg = <0x0 0x990000 0x0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1320 clock-names = "se"; 1321 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1322 <&qup_uart4_tx>, <&qup_uart4_rx>; 1323 pinctrl-names = "default"; 1324 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1325 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1326 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1327 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1328 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1329 interconnect-names = "qup-core", 1330 "qup-config"; 1331 power-domains = <&rpmhpd RPMHPD_CX>; 1332 operating-points-v2 = <&qup_opp_table>; 1333 status = "disabled"; 1334 }; 1335 1336 i2c5: i2c@994000 { 1337 compatible = "qcom,geni-i2c"; 1338 reg = <0x0 0x994000 0x0 0x4000>; 1339 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1340 clock-names = "se"; 1341 pinctrl-0 = <&qup_i2c5_data_clk>; 1342 pinctrl-names = "default"; 1343 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1347 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1348 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1349 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1350 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1351 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1352 interconnect-names = "qup-core", 1353 "qup-config", 1354 "qup-memory"; 1355 power-domains = <&rpmhpd RPMHPD_CX>; 1356 required-opps = <&rpmhpd_opp_low_svs>; 1357 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1358 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1359 dma-names = "tx", 1360 "rx"; 1361 status = "disabled"; 1362 }; 1363 1364 spi5: spi@994000 { 1365 compatible = "qcom,geni-spi"; 1366 reg = <0x0 0x994000 0x0 0x4000>; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1368 clock-names = "se"; 1369 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1370 pinctrl-names = "default"; 1371 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1375 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1376 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1377 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1378 interconnect-names = "qup-core", 1379 "qup-config"; 1380 power-domains = <&rpmhpd RPMHPD_CX>; 1381 operating-points-v2 = <&qup_opp_table>; 1382 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1383 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1384 dma-names = "tx", 1385 "rx"; 1386 status = "disabled"; 1387 }; 1388 1389 uart5: serial@994000 { 1390 compatible = "qcom,geni-uart"; 1391 reg = <0x0 0x994000 0x0 0x4000>; 1392 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1393 clock-names = "se"; 1394 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1395 <&qup_uart5_tx>, <&qup_uart5_rx>; 1396 pinctrl-names = "default"; 1397 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1399 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1400 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1401 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1402 interconnect-names = "qup-core", 1403 "qup-config"; 1404 power-domains = <&rpmhpd RPMHPD_CX>; 1405 operating-points-v2 = <&qup_opp_table>; 1406 status = "disabled"; 1407 }; 1408 1409 i2c6: i2c@998000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0x0 0x998000 0x0 0x4000>; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1413 clock-names = "se"; 1414 pinctrl-0 = <&qup_i2c6_data_clk>; 1415 pinctrl-names = "default"; 1416 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1417 #address-cells = <1>; 1418 #size-cells = <0>; 1419 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1420 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1421 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1422 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1423 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1424 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1425 interconnect-names = "qup-core", 1426 "qup-config", 1427 "qup-memory"; 1428 power-domains = <&rpmhpd RPMHPD_CX>; 1429 required-opps = <&rpmhpd_opp_low_svs>; 1430 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1431 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1432 dma-names = "tx", 1433 "rx"; 1434 status = "disabled"; 1435 }; 1436 1437 spi6: spi@998000 { 1438 compatible = "qcom,geni-spi"; 1439 reg = <0x0 0x998000 0x0 0x4000>; 1440 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1441 clock-names = "se"; 1442 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1443 pinctrl-names = "default"; 1444 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1445 #address-cells = <1>; 1446 #size-cells = <0>; 1447 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1448 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1449 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1450 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1451 interconnect-names = "qup-core", 1452 "qup-config"; 1453 power-domains = <&rpmhpd RPMHPD_CX>; 1454 operating-points-v2 = <&qup_opp_table>; 1455 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1456 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1457 dma-names = "tx", 1458 "rx"; 1459 status = "disabled"; 1460 }; 1461 1462 uart6: serial@998000 { 1463 compatible = "qcom,geni-uart"; 1464 reg = <0x0 0x998000 0x0 0x4000>; 1465 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1466 clock-names = "se"; 1467 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1468 <&qup_uart6_tx>, <&qup_uart6_rx>; 1469 pinctrl-names = "default"; 1470 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1471 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1472 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1473 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1474 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1475 interconnect-names = "qup-core", 1476 "qup-config"; 1477 power-domains = <&rpmhpd RPMHPD_CX>; 1478 operating-points-v2 = <&qup_opp_table>; 1479 status = "disabled"; 1480 }; 1481 1482 uart7: serial@99c000 { 1483 compatible = "qcom,geni-debug-uart"; 1484 reg = <0x0 0x0099c000 0x0 0x4000>; 1485 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1486 clock-names = "se"; 1487 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1488 pinctrl-names = "default"; 1489 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1491 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1493 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1494 interconnect-names = "qup-core", 1495 "qup-config"; 1496 power-domains = <&rpmhpd RPMHPD_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 status = "disabled"; 1499 }; 1500 }; 1501 1502 gpi_dma1: dma-controller@a00000 { 1503 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1504 reg = <0x0 0xa00000 0x0 0x60000>; 1505 #dma-cells = <3>; 1506 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1513 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1514 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1515 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1518 iommus = <&apps_smmu 0x456 0x0>; 1519 dma-channels = <12>; 1520 dma-channel-mask = <0xfff>; 1521 dma-coherent; 1522 status = "disabled"; 1523 }; 1524 1525 qupv3_id_1: geniqup@ac0000 { 1526 compatible = "qcom,geni-se-qup"; 1527 reg = <0x0 0xac0000 0x0 0x2000>; 1528 ranges; 1529 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1530 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1531 clock-names = "m-ahb", 1532 "s-ahb"; 1533 #address-cells = <2>; 1534 #size-cells = <2>; 1535 iommus = <&apps_smmu 0x443 0x0>; 1536 dma-coherent; 1537 status = "disabled"; 1538 1539 i2c8: i2c@a80000 { 1540 compatible = "qcom,geni-i2c"; 1541 reg = <0x0 0xa80000 0x0 0x4000>; 1542 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1543 clock-names = "se"; 1544 pinctrl-0 = <&qup_i2c8_data_clk>; 1545 pinctrl-names = "default"; 1546 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1547 #address-cells = <1>; 1548 #size-cells = <0>; 1549 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1550 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1551 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1552 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1553 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1554 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1555 interconnect-names = "qup-core", 1556 "qup-config", 1557 "qup-memory"; 1558 power-domains = <&rpmhpd RPMHPD_CX>; 1559 required-opps = <&rpmhpd_opp_low_svs>; 1560 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1561 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1562 dma-names = "tx", 1563 "rx"; 1564 status = "disabled"; 1565 }; 1566 1567 spi8: spi@a80000 { 1568 compatible = "qcom,geni-spi"; 1569 reg = <0x0 0xa80000 0x0 0x4000>; 1570 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1571 clock-names = "se"; 1572 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1573 pinctrl-names = "default"; 1574 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1578 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1579 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1580 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1581 interconnect-names = "qup-core", 1582 "qup-config"; 1583 power-domains = <&rpmhpd RPMHPD_CX>; 1584 operating-points-v2 = <&qup_opp_table>; 1585 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1586 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1587 dma-names = "tx", 1588 "rx"; 1589 status = "disabled"; 1590 }; 1591 1592 uart8: serial@a80000 { 1593 compatible = "qcom,geni-uart"; 1594 reg = <0x0 0xa80000 0x0 0x4000>; 1595 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1596 clock-names = "se"; 1597 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1598 <&qup_uart8_tx>, <&qup_uart8_rx>; 1599 pinctrl-names = "default"; 1600 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1601 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1602 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1603 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1604 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1605 interconnect-names = "qup-core", 1606 "qup-config"; 1607 power-domains = <&rpmhpd RPMHPD_CX>; 1608 operating-points-v2 = <&qup_opp_table>; 1609 status = "disabled"; 1610 }; 1611 1612 i2c9: i2c@a84000 { 1613 compatible = "qcom,geni-i2c"; 1614 reg = <0x0 0xa84000 0x0 0x4000>; 1615 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1616 clock-names = "se"; 1617 pinctrl-0 = <&qup_i2c9_data_clk>; 1618 pinctrl-names = "default"; 1619 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1620 #address-cells = <1>; 1621 #size-cells = <0>; 1622 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1623 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1624 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1625 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1626 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1627 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1628 interconnect-names = "qup-core", 1629 "qup-config", 1630 "qup-memory"; 1631 power-domains = <&rpmhpd RPMHPD_CX>; 1632 required-opps = <&rpmhpd_opp_low_svs>; 1633 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1634 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1635 dma-names = "tx", 1636 "rx"; 1637 status = "disabled"; 1638 }; 1639 1640 spi9: spi@a84000 { 1641 compatible = "qcom,geni-spi"; 1642 reg = <0x0 0xa84000 0x0 0x4000>; 1643 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1644 clock-names = "se"; 1645 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1646 pinctrl-names = "default"; 1647 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1648 #address-cells = <1>; 1649 #size-cells = <0>; 1650 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1651 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1652 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1653 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1654 interconnect-names = "qup-core", 1655 "qup-config"; 1656 power-domains = <&rpmhpd RPMHPD_CX>; 1657 operating-points-v2 = <&qup_opp_table>; 1658 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1659 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1660 dma-names = "tx", 1661 "rx"; 1662 status = "disabled"; 1663 }; 1664 1665 uart9: serial@a84000 { 1666 compatible = "qcom,geni-uart"; 1667 reg = <0x0 0xa84000 0x0 0x4000>; 1668 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1669 clock-names = "se"; 1670 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1671 <&qup_uart9_tx>, <&qup_uart9_rx>; 1672 pinctrl-names = "default"; 1673 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1674 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1675 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1676 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1677 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1678 interconnect-names = "qup-core", 1679 "qup-config"; 1680 power-domains = <&rpmhpd RPMHPD_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 status = "disabled"; 1683 }; 1684 1685 i2c10: i2c@a88000 { 1686 compatible = "qcom,geni-i2c"; 1687 reg = <0x0 0xa88000 0x0 0x4000>; 1688 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1689 clock-names = "se"; 1690 pinctrl-0 = <&qup_i2c10_data_clk>; 1691 pinctrl-names = "default"; 1692 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1693 #address-cells = <1>; 1694 #size-cells = <0>; 1695 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1696 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1697 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1698 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1699 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1700 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1701 interconnect-names = "qup-core", 1702 "qup-config", 1703 "qup-memory"; 1704 power-domains = <&rpmhpd RPMHPD_CX>; 1705 required-opps = <&rpmhpd_opp_low_svs>; 1706 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1707 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1708 dma-names = "tx", 1709 "rx"; 1710 status = "disabled"; 1711 }; 1712 1713 spi10: spi@a88000 { 1714 compatible = "qcom,geni-spi"; 1715 reg = <0x0 0xa88000 0x0 0x4000>; 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1717 clock-names = "se"; 1718 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1719 pinctrl-names = "default"; 1720 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1724 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1725 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1726 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1727 interconnect-names = "qup-core", 1728 "qup-config"; 1729 power-domains = <&rpmhpd RPMHPD_CX>; 1730 operating-points-v2 = <&qup_opp_table>; 1731 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1732 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1733 dma-names = "tx", 1734 "rx"; 1735 status = "disabled"; 1736 }; 1737 1738 uart10: serial@a88000 { 1739 compatible = "qcom,geni-uart"; 1740 reg = <0x0 0xa88000 0x0 0x4000>; 1741 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1742 clock-names = "se"; 1743 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1744 <&qup_uart10_tx>, <&qup_uart10_rx>; 1745 pinctrl-names = "default"; 1746 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1747 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1748 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1750 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1751 interconnect-names = "qup-core", 1752 "qup-config"; 1753 power-domains = <&rpmhpd RPMHPD_CX>; 1754 operating-points-v2 = <&qup_opp_table>; 1755 status = "disabled"; 1756 }; 1757 1758 i2c11: i2c@a8c000 { 1759 compatible = "qcom,geni-i2c"; 1760 reg = <0x0 0xa8c000 0x0 0x4000>; 1761 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1762 clock-names = "se"; 1763 pinctrl-0 = <&qup_i2c11_data_clk>; 1764 pinctrl-names = "default"; 1765 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1766 #address-cells = <1>; 1767 #size-cells = <0>; 1768 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1769 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1770 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1771 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1772 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1773 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1774 interconnect-names = "qup-core", 1775 "qup-config", 1776 "qup-memory"; 1777 power-domains = <&rpmhpd RPMHPD_CX>; 1778 required-opps = <&rpmhpd_opp_low_svs>; 1779 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1780 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1781 dma-names = "tx", 1782 "rx"; 1783 status = "disabled"; 1784 }; 1785 1786 uart11: serial@a8c000 { 1787 compatible = "qcom,geni-uart"; 1788 reg = <0x0 0xa8c000 0x0 0x4000>; 1789 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1790 clock-names = "se"; 1791 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1792 pinctrl-names = "default"; 1793 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1794 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1795 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1796 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1797 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1798 interconnect-names = "qup-core", 1799 "qup-config"; 1800 power-domains = <&rpmhpd RPMHPD_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 status = "disabled"; 1803 }; 1804 1805 i2c12: i2c@a90000 { 1806 compatible = "qcom,geni-i2c"; 1807 reg = <0x0 0xa90000 0x0 0x4000>; 1808 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1809 clock-names = "se"; 1810 pinctrl-0 = <&qup_i2c12_data_clk>; 1811 pinctrl-names = "default"; 1812 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1813 #address-cells = <1>; 1814 #size-cells = <0>; 1815 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1816 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1817 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1818 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1819 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1820 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1821 interconnect-names = "qup-core", 1822 "qup-config", 1823 "qup-memory"; 1824 power-domains = <&rpmhpd RPMHPD_CX>; 1825 required-opps = <&rpmhpd_opp_low_svs>; 1826 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1827 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1828 dma-names = "tx", 1829 "rx"; 1830 status = "disabled"; 1831 }; 1832 1833 spi12: spi@a90000 { 1834 compatible = "qcom,geni-spi"; 1835 reg = <0x0 0xa90000 0x0 0x4000>; 1836 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1837 clock-names = "se"; 1838 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1839 pinctrl-names = "default"; 1840 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1844 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1845 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1846 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1847 interconnect-names = "qup-core", 1848 "qup-config"; 1849 power-domains = <&rpmhpd RPMHPD_CX>; 1850 operating-points-v2 = <&qup_opp_table>; 1851 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1852 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1853 dma-names = "tx", 1854 "rx"; 1855 status = "disabled"; 1856 }; 1857 1858 uart12: serial@a90000 { 1859 compatible = "qcom,geni-uart"; 1860 reg = <0x0 0xa90000 0x0 0x4000>; 1861 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1862 clock-names = "se"; 1863 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1864 <&qup_uart12_tx>, <&qup_uart12_rx>; 1865 pinctrl-names = "default"; 1866 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1867 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1868 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1869 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1870 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1871 interconnect-names = "qup-core", 1872 "qup-config"; 1873 power-domains = <&rpmhpd RPMHPD_CX>; 1874 operating-points-v2 = <&qup_opp_table>; 1875 status = "disabled"; 1876 }; 1877 1878 i2c13: i2c@a94000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0x0 0xa94000 0x0 0x4000>; 1881 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1882 clock-names = "se"; 1883 pinctrl-0 = <&qup_i2c13_data_clk>; 1884 pinctrl-names = "default"; 1885 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1889 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1890 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1891 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1892 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1893 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1894 interconnect-names = "qup-core", 1895 "qup-config", 1896 "qup-memory"; 1897 power-domains = <&rpmhpd RPMHPD_CX>; 1898 required-opps = <&rpmhpd_opp_low_svs>; 1899 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1900 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1901 dma-names = "tx", 1902 "rx"; 1903 status = "disabled"; 1904 }; 1905 1906 spi13: spi@a94000 { 1907 compatible = "qcom,geni-spi"; 1908 reg = <0x0 0xa94000 0x0 0x4000>; 1909 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1910 clock-names = "se"; 1911 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1912 pinctrl-names = "default"; 1913 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1914 #address-cells = <1>; 1915 #size-cells = <0>; 1916 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1917 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1918 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1919 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1920 interconnect-names = "qup-core", 1921 "qup-config"; 1922 power-domains = <&rpmhpd RPMHPD_CX>; 1923 operating-points-v2 = <&qup_opp_table>; 1924 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1925 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1926 dma-names = "tx", 1927 "rx"; 1928 status = "disabled"; 1929 }; 1930 1931 uart13: serial@a94000 { 1932 compatible = "qcom,geni-uart"; 1933 reg = <0x0 0xa94000 0x0 0x4000>; 1934 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1935 clock-names = "se"; 1936 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1937 <&qup_uart13_tx>, <&qup_uart13_rx>; 1938 pinctrl-names = "default"; 1939 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1940 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1941 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1942 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1943 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1944 interconnect-names = "qup-core", 1945 "qup-config"; 1946 power-domains = <&rpmhpd RPMHPD_CX>; 1947 operating-points-v2 = <&qup_opp_table>; 1948 status = "disabled"; 1949 }; 1950 1951 i2c14: i2c@a98000 { 1952 compatible = "qcom,geni-i2c"; 1953 reg = <0x0 0xa98000 0x0 0x4000>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1955 clock-names = "se"; 1956 pinctrl-0 = <&qup_i2c14_data_clk>; 1957 pinctrl-names = "default"; 1958 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1962 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1963 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1964 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1965 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1967 interconnect-names = "qup-core", 1968 "qup-config", 1969 "qup-memory"; 1970 power-domains = <&rpmhpd RPMHPD_CX>; 1971 required-opps = <&rpmhpd_opp_low_svs>; 1972 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1973 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1974 dma-names = "tx", 1975 "rx"; 1976 status = "disabled"; 1977 }; 1978 1979 spi14: spi@a98000 { 1980 compatible = "qcom,geni-spi"; 1981 reg = <0x0 0xa98000 0x0 0x4000>; 1982 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1983 clock-names = "se"; 1984 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1985 pinctrl-names = "default"; 1986 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1987 #address-cells = <1>; 1988 #size-cells = <0>; 1989 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1990 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1991 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1992 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1993 interconnect-names = "qup-core", 1994 "qup-config"; 1995 power-domains = <&rpmhpd RPMHPD_CX>; 1996 operating-points-v2 = <&qup_opp_table>; 1997 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1998 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1999 dma-names = "tx", 2000 "rx"; 2001 status = "disabled"; 2002 }; 2003 2004 uart14: serial@a98000 { 2005 compatible = "qcom,geni-uart"; 2006 reg = <0x0 0xa98000 0x0 0x4000>; 2007 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2008 clock-names = "se"; 2009 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2010 <&qup_uart14_tx>, <&qup_uart14_rx>; 2011 pinctrl-names = "default"; 2012 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2013 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2014 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2015 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2016 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2017 interconnect-names = "qup-core", 2018 "qup-config"; 2019 power-domains = <&rpmhpd RPMHPD_CX>; 2020 operating-points-v2 = <&qup_opp_table>; 2021 status = "disabled"; 2022 }; 2023 2024 i2c15: i2c@a9c000 { 2025 compatible = "qcom,geni-i2c"; 2026 reg = <0x0 0xa9c000 0x0 0x4000>; 2027 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2028 clock-names = "se"; 2029 pinctrl-0 = <&qup_i2c15_data_clk>; 2030 pinctrl-names = "default"; 2031 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2032 #address-cells = <1>; 2033 #size-cells = <0>; 2034 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2035 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2036 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2037 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2038 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2039 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2040 interconnect-names = "qup-core", 2041 "qup-config", 2042 "qup-memory"; 2043 power-domains = <&rpmhpd RPMHPD_CX>; 2044 required-opps = <&rpmhpd_opp_low_svs>; 2045 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2046 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2047 dma-names = "tx", 2048 "rx"; 2049 status = "disabled"; 2050 }; 2051 2052 spi15: spi@a9c000 { 2053 compatible = "qcom,geni-spi"; 2054 reg = <0x0 0xa9c000 0x0 0x4000>; 2055 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2056 clock-names = "se"; 2057 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2058 pinctrl-names = "default"; 2059 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2060 #address-cells = <1>; 2061 #size-cells = <0>; 2062 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2063 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2064 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2065 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2066 interconnect-names = "qup-core", 2067 "qup-config"; 2068 power-domains = <&rpmhpd RPMHPD_CX>; 2069 operating-points-v2 = <&qup_opp_table>; 2070 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2071 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2072 dma-names = "tx", 2073 "rx"; 2074 status = "disabled"; 2075 }; 2076 2077 uart15: serial@a9c000 { 2078 compatible = "qcom,geni-uart"; 2079 reg = <0x0 0xa9c000 0x0 0x4000>; 2080 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2081 clock-names = "se"; 2082 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2083 <&qup_uart15_tx>, <&qup_uart15_rx>; 2084 pinctrl-names = "default"; 2085 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2086 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2087 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2088 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2089 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2090 interconnect-names = "qup-core", 2091 "qup-config"; 2092 power-domains = <&rpmhpd RPMHPD_CX>; 2093 operating-points-v2 = <&qup_opp_table>; 2094 status = "disabled"; 2095 }; 2096 }; 2097 2098 gpi_dma3: dma-controller@b00000 { 2099 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2100 reg = <0x0 0xb00000 0x0 0x60000>; 2101 #dma-cells = <3>; 2102 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2106 iommus = <&apps_smmu 0x56 0x0>; 2107 dma-channels = <4>; 2108 dma-channel-mask = <0xf>; 2109 dma-coherent; 2110 status = "disabled"; 2111 }; 2112 2113 qupv3_id_3: geniqup@bc0000 { 2114 compatible = "qcom,geni-se-qup"; 2115 reg = <0x0 0xbc0000 0x0 0x2000>; 2116 ranges; 2117 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2118 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2119 clock-names = "m-ahb", 2120 "s-ahb"; 2121 #address-cells = <2>; 2122 #size-cells = <2>; 2123 iommus = <&apps_smmu 0x43 0x0>; 2124 dma-coherent; 2125 status = "disabled"; 2126 2127 i2c16: i2c@b80000 { 2128 compatible = "qcom,geni-i2c"; 2129 reg = <0x0 0xb80000 0x0 0x4000>; 2130 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2131 clock-names = "se"; 2132 pinctrl-0 = <&qup_i2c16_data_clk>; 2133 pinctrl-names = "default"; 2134 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2135 #address-cells = <1>; 2136 #size-cells = <0>; 2137 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2138 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2139 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2140 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2141 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2143 interconnect-names = "qup-core", 2144 "qup-config", 2145 "qup-memory"; 2146 power-domains = <&rpmhpd RPMHPD_CX>; 2147 required-opps = <&rpmhpd_opp_low_svs>; 2148 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2149 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2150 dma-names = "tx", 2151 "rx"; 2152 status = "disabled"; 2153 }; 2154 2155 spi16: spi@b80000 { 2156 compatible = "qcom,geni-spi"; 2157 reg = <0x0 0xb80000 0x0 0x4000>; 2158 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2159 clock-names = "se"; 2160 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2161 pinctrl-names = "default"; 2162 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2166 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2167 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2168 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2169 interconnect-names = "qup-core", 2170 "qup-config"; 2171 power-domains = <&rpmhpd RPMHPD_CX>; 2172 operating-points-v2 = <&qup_opp_table>; 2173 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2174 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2175 dma-names = "tx", 2176 "rx"; 2177 status = "disabled"; 2178 }; 2179 2180 uart16: serial@b80000 { 2181 compatible = "qcom,geni-uart"; 2182 reg = <0x0 0xb80000 0x0 0x4000>; 2183 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2184 clock-names = "se"; 2185 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2186 <&qup_uart16_tx>, <&qup_uart16_rx>; 2187 pinctrl-names = "default"; 2188 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2189 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2190 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2191 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2192 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2193 interconnect-names = "qup-core", 2194 "qup-config"; 2195 power-domains = <&rpmhpd RPMHPD_CX>; 2196 operating-points-v2 = <&qup_opp_table>; 2197 status = "disabled"; 2198 }; 2199 }; 2200 2201 rng: rng@10d2000 { 2202 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2203 reg = <0x0 0x010d2000 0x0 0x1000>; 2204 }; 2205 2206 config_noc: interconnect@14c0000 { 2207 compatible = "qcom,qcs8300-config-noc"; 2208 reg = <0x0 0x014c0000 0x0 0x13080>; 2209 #interconnect-cells = <2>; 2210 qcom,bcm-voters = <&apps_bcm_voter>; 2211 }; 2212 2213 system_noc: interconnect@1680000 { 2214 compatible = "qcom,qcs8300-system-noc"; 2215 reg = <0x0 0x01680000 0x0 0x15080>; 2216 #interconnect-cells = <2>; 2217 qcom,bcm-voters = <&apps_bcm_voter>; 2218 }; 2219 2220 aggre1_noc: interconnect@16c0000 { 2221 compatible = "qcom,qcs8300-aggre1-noc"; 2222 reg = <0x0 0x016c0000 0x0 0x17080>; 2223 #interconnect-cells = <2>; 2224 qcom,bcm-voters = <&apps_bcm_voter>; 2225 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2226 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2227 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2228 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2229 }; 2230 2231 aggre2_noc: interconnect@1700000 { 2232 compatible = "qcom,qcs8300-aggre2-noc"; 2233 reg = <0x0 0x01700000 0x0 0x1a080>; 2234 #interconnect-cells = <2>; 2235 qcom,bcm-voters = <&apps_bcm_voter>; 2236 clocks = <&rpmhcc RPMH_IPA_CLK>; 2237 }; 2238 2239 pcie_anoc: interconnect@1760000 { 2240 compatible = "qcom,qcs8300-pcie-anoc"; 2241 reg = <0x0 0x01760000 0x0 0xc080>; 2242 #interconnect-cells = <2>; 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 }; 2245 2246 gpdsp_anoc: interconnect@1780000 { 2247 compatible = "qcom,qcs8300-gpdsp-anoc"; 2248 reg = <0x0 0x01780000 0x0 0xd080>; 2249 #interconnect-cells = <2>; 2250 qcom,bcm-voters = <&apps_bcm_voter>; 2251 }; 2252 2253 mmss_noc: interconnect@17a0000 { 2254 compatible = "qcom,qcs8300-mmss-noc"; 2255 reg = <0x0 0x017a0000 0x0 0x40000>; 2256 #interconnect-cells = <2>; 2257 qcom,bcm-voters = <&apps_bcm_voter>; 2258 }; 2259 2260 pcie0: pcie@1c00000 { 2261 device_type = "pci"; 2262 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2263 reg = <0x0 0x01c00000 0x0 0x3000>, 2264 <0x0 0x40000000 0x0 0xf20>, 2265 <0x0 0x40000f20 0x0 0xa8>, 2266 <0x0 0x40001000 0x0 0x4000>, 2267 <0x0 0x40100000 0x0 0x100000>, 2268 <0x0 0x01c03000 0x0 0x1000>; 2269 reg-names = "parf", 2270 "dbi", 2271 "elbi", 2272 "atu", 2273 "config", 2274 "mhi"; 2275 #address-cells = <3>; 2276 #size-cells = <2>; 2277 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2278 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2279 bus-range = <0x00 0xff>; 2280 2281 dma-coherent; 2282 2283 linux,pci-domain = <0>; 2284 num-lanes = <2>; 2285 2286 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2295 interrupt-names = "msi0", 2296 "msi1", 2297 "msi2", 2298 "msi3", 2299 "msi4", 2300 "msi5", 2301 "msi6", 2302 "msi7", 2303 "global"; 2304 2305 #interrupt-cells = <1>; 2306 interrupt-map-mask = <0 0 0 0x7>; 2307 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2308 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2309 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2310 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2311 2312 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2313 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2314 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2315 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2316 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2317 clock-names = "aux", 2318 "cfg", 2319 "bus_master", 2320 "bus_slave", 2321 "slave_q2a"; 2322 2323 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2324 assigned-clock-rates = <19200000>; 2325 2326 interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2328 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2329 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2330 interconnect-names = "pcie-mem", 2331 "cpu-pcie"; 2332 2333 iommu-map = <0x0 &pcie_smmu 0x0000 0x0 0x1>, 2334 <0x100 &pcie_smmu 0x0001 0x0 0x1>; 2335 2336 resets = <&gcc GCC_PCIE_0_BCR>, 2337 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2338 reset-names = "pci", 2339 "link_down"; 2340 2341 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2342 2343 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2344 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2345 2346 operating-points-v2 = <&pcie0_opp_table>; 2347 2348 status = "disabled"; 2349 2350 pcie0_opp_table: opp-table { 2351 compatible = "operating-points-v2"; 2352 2353 /* GEN 1 x1 */ 2354 opp-2500000 { 2355 opp-hz = /bits/ 64 <2500000>; 2356 required-opps = <&rpmhpd_opp_svs_l1>; 2357 opp-peak-kBps = <250000 1>; 2358 }; 2359 2360 /* GEN 1 x2 and GEN 2 x1 */ 2361 opp-5000000 { 2362 opp-hz = /bits/ 64 <5000000>; 2363 required-opps = <&rpmhpd_opp_svs_l1>; 2364 opp-peak-kBps = <500000 1>; 2365 }; 2366 2367 /* GEN 2 x2 */ 2368 opp-10000000 { 2369 opp-hz = /bits/ 64 <10000000>; 2370 required-opps = <&rpmhpd_opp_svs_l1>; 2371 opp-peak-kBps = <1000000 1>; 2372 }; 2373 2374 /* GEN 3 x1 */ 2375 opp-8000000 { 2376 opp-hz = /bits/ 64 <8000000>; 2377 required-opps = <&rpmhpd_opp_svs_l1>; 2378 opp-peak-kBps = <984500 1>; 2379 }; 2380 2381 /* GEN 3 x2 and GEN 4 x1 */ 2382 opp-16000000 { 2383 opp-hz = /bits/ 64 <16000000>; 2384 required-opps = <&rpmhpd_opp_nom>; 2385 opp-peak-kBps = <1969000 1>; 2386 }; 2387 2388 /* GEN 4 x2 */ 2389 opp-32000000 { 2390 opp-hz = /bits/ 64 <32000000>; 2391 required-opps = <&rpmhpd_opp_nom>; 2392 opp-peak-kBps = <3938000 1>; 2393 }; 2394 }; 2395 2396 pcieport0: pcie@0 { 2397 device_type = "pci"; 2398 reg = <0x0 0x0 0x0 0x0 0x0>; 2399 bus-range = <0x01 0xff>; 2400 2401 #address-cells = <3>; 2402 #size-cells = <2>; 2403 ranges; 2404 phys = <&pcie0_phy>; 2405 }; 2406 }; 2407 2408 pcie0_phy: phy@1c04000 { 2409 compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; 2410 reg = <0x0 0x01c04000 0x0 0x2000>; 2411 2412 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2413 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2414 <&gcc GCC_PCIE_CLKREF_EN>, 2415 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2416 <&gcc GCC_PCIE_0_PIPE_CLK>, 2417 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2418 clock-names = "aux", 2419 "cfg_ahb", 2420 "ref", 2421 "rchng", 2422 "pipe", 2423 "pipediv2"; 2424 2425 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2426 reset-names = "phy"; 2427 2428 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2429 assigned-clock-rates = <100000000>; 2430 2431 #clock-cells = <0>; 2432 clock-output-names = "pcie_0_pipe_clk"; 2433 2434 #phy-cells = <0>; 2435 2436 status = "disabled"; 2437 }; 2438 2439 pcie1: pcie@1c10000 { 2440 device_type = "pci"; 2441 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2442 reg = <0x0 0x01c10000 0x0 0x3000>, 2443 <0x0 0x60000000 0x0 0xf20>, 2444 <0x0 0x60000f20 0x0 0xa8>, 2445 <0x0 0x60001000 0x0 0x4000>, 2446 <0x0 0x60100000 0x0 0x100000>, 2447 <0x0 0x01c13000 0x0 0x1000>; 2448 reg-names = "parf", 2449 "dbi", 2450 "elbi", 2451 "atu", 2452 "config", 2453 "mhi"; 2454 #address-cells = <3>; 2455 #size-cells = <2>; 2456 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2457 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2458 bus-range = <0x00 0xff>; 2459 2460 dma-coherent; 2461 2462 linux,pci-domain = <1>; 2463 num-lanes = <4>; 2464 2465 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2466 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2467 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2468 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2469 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2470 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2471 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2472 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2473 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2474 interrupt-names = "msi0", 2475 "msi1", 2476 "msi2", 2477 "msi3", 2478 "msi4", 2479 "msi5", 2480 "msi6", 2481 "msi7", 2482 "global"; 2483 #interrupt-cells = <1>; 2484 interrupt-map-mask = <0 0 0 0x7>; 2485 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2486 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2487 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2488 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2489 2490 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2491 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2492 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2493 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2494 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2495 clock-names = "aux", 2496 "cfg", 2497 "bus_master", 2498 "bus_slave", 2499 "slave_q2a"; 2500 2501 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2502 assigned-clock-rates = <19200000>; 2503 2504 interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2505 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2506 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2507 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2508 interconnect-names = "pcie-mem", "cpu-pcie"; 2509 2510 iommu-map = <0x0 &pcie_smmu 0x0080 0x0 0x1>, 2511 <0x100 &pcie_smmu 0x0081 0x0 0x1>; 2512 2513 resets = <&gcc GCC_PCIE_1_BCR>, 2514 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2515 reset-names = "pci", 2516 "link_down"; 2517 2518 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2519 2520 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2521 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2522 2523 operating-points-v2 = <&pcie1_opp_table>; 2524 2525 status = "disabled"; 2526 2527 pcie1_opp_table: opp-table { 2528 compatible = "operating-points-v2"; 2529 2530 /* GEN 1 x1 */ 2531 opp-2500000 { 2532 opp-hz = /bits/ 64 <2500000>; 2533 required-opps = <&rpmhpd_opp_svs_l1>; 2534 opp-peak-kBps = <250000 1>; 2535 }; 2536 2537 /* GEN 1 x2 and GEN 2 x1 */ 2538 opp-5000000 { 2539 opp-hz = /bits/ 64 <5000000>; 2540 required-opps = <&rpmhpd_opp_svs_l1>; 2541 opp-peak-kBps = <500000 1>; 2542 }; 2543 2544 /* GEN 1 x4 and GEN 2 x2 */ 2545 opp-10000000 { 2546 opp-hz = /bits/ 64 <10000000>; 2547 required-opps = <&rpmhpd_opp_svs_l1>; 2548 opp-peak-kBps = <1000000 1>; 2549 }; 2550 2551 /* GEN 2 x4 */ 2552 opp-20000000 { 2553 opp-hz = /bits/ 64 <20000000>; 2554 required-opps = <&rpmhpd_opp_low_svs>; 2555 opp-peak-kBps = <2000000 1>; 2556 }; 2557 2558 /* GEN 3 x1 */ 2559 opp-8000000 { 2560 opp-hz = /bits/ 64 <8000000>; 2561 required-opps = <&rpmhpd_opp_svs_l1>; 2562 opp-peak-kBps = <984500 1>; 2563 }; 2564 2565 /* GEN 3 x2 and GEN 4 x1 */ 2566 opp-16000000 { 2567 opp-hz = /bits/ 64 <16000000>; 2568 required-opps = <&rpmhpd_opp_nom>; 2569 opp-peak-kBps = <1969000 1>; 2570 }; 2571 2572 /* GEN 3 x4 and GEN 4 x2 */ 2573 opp-32000000 { 2574 opp-hz = /bits/ 64 <32000000>; 2575 required-opps = <&rpmhpd_opp_nom>; 2576 opp-peak-kBps = <3938000 1>; 2577 }; 2578 2579 /* GEN 4 x4 */ 2580 opp-64000000 { 2581 opp-hz = /bits/ 64 <64000000>; 2582 required-opps = <&rpmhpd_opp_nom>; 2583 opp-peak-kBps = <7876000 1>; 2584 }; 2585 }; 2586 2587 pcieport1: pcie@0 { 2588 device_type = "pci"; 2589 reg = <0x0 0x0 0x0 0x0 0x0>; 2590 bus-range = <0x01 0xff>; 2591 2592 #address-cells = <3>; 2593 #size-cells = <2>; 2594 ranges; 2595 phys = <&pcie1_phy>; 2596 }; 2597 }; 2598 2599 pcie1_phy: phy@1c14000 { 2600 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2601 reg = <0x0 0x01c14000 0x0 0x4000>; 2602 2603 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2604 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2605 <&gcc GCC_PCIE_CLKREF_EN>, 2606 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2607 <&gcc GCC_PCIE_1_PIPE_CLK>, 2608 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 2609 clock-names = "aux", 2610 "cfg_ahb", 2611 "ref", 2612 "rchng", 2613 "pipe", 2614 "pipediv2"; 2615 2616 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2617 assigned-clock-rates = <100000000>; 2618 2619 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2620 reset-names = "phy"; 2621 2622 #clock-cells = <0>; 2623 clock-output-names = "pcie_1_pipe_clk"; 2624 2625 #phy-cells = <0>; 2626 2627 status = "disabled"; 2628 }; 2629 2630 ufs_mem_hc: ufs@1d84000 { 2631 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2632 reg = <0x0 0x01d84000 0x0 0x3000>; 2633 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2634 phys = <&ufs_mem_phy>; 2635 phy-names = "ufsphy"; 2636 lanes-per-direction = <2>; 2637 #reset-cells = <1>; 2638 resets = <&gcc GCC_UFS_PHY_BCR>; 2639 reset-names = "rst"; 2640 2641 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2642 required-opps = <&rpmhpd_opp_nom>; 2643 2644 iommus = <&apps_smmu 0x100 0x0>; 2645 dma-coherent; 2646 2647 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2650 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2651 interconnect-names = "ufs-ddr", 2652 "cpu-ufs"; 2653 2654 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2655 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2656 <&gcc GCC_UFS_PHY_AHB_CLK>, 2657 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2658 <&rpmhcc RPMH_CXO_CLK>, 2659 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2660 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2661 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2662 clock-names = "core_clk", 2663 "bus_aggr_clk", 2664 "iface_clk", 2665 "core_clk_unipro", 2666 "ref_clk", 2667 "tx_lane0_sync_clk", 2668 "rx_lane0_sync_clk", 2669 "rx_lane1_sync_clk"; 2670 freq-table-hz = <75000000 300000000>, 2671 <0 0>, 2672 <0 0>, 2673 <75000000 300000000>, 2674 <0 0>, 2675 <0 0>, 2676 <0 0>, 2677 <0 0>; 2678 qcom,ice = <&ice>; 2679 status = "disabled"; 2680 }; 2681 2682 ufs_mem_phy: phy@1d87000 { 2683 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2684 reg = <0x0 0x01d87000 0x0 0xe10>; 2685 /* 2686 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2687 * enables the CXO clock to eDP *and* UFS PHY. 2688 */ 2689 clocks = <&rpmhcc RPMH_CXO_CLK>, 2690 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2691 <&gcc GCC_EDP_REF_CLKREF_EN>; 2692 clock-names = "ref", 2693 "ref_aux", 2694 "qref"; 2695 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2696 2697 resets = <&ufs_mem_hc 0>; 2698 reset-names = "ufsphy"; 2699 2700 #phy-cells = <0>; 2701 status = "disabled"; 2702 }; 2703 2704 cryptobam: dma-controller@1dc4000 { 2705 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2706 reg = <0x0 0x01dc4000 0x0 0x28000>; 2707 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2708 #dma-cells = <1>; 2709 qcom,ee = <0>; 2710 qcom,controlled-remotely; 2711 num-channels = <20>; 2712 qcom,num-ees = <4>; 2713 iommus = <&apps_smmu 0x480 0x00>, 2714 <&apps_smmu 0x481 0x00>; 2715 }; 2716 2717 ice: crypto@1d88000 { 2718 compatible = "qcom,qcs8300-inline-crypto-engine", 2719 "qcom,inline-crypto-engine"; 2720 reg = <0x0 0x01d88000 0x0 0x18000>; 2721 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 2722 <&gcc GCC_UFS_PHY_AHB_CLK>; 2723 clock-names = "core", 2724 "iface"; 2725 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2726 }; 2727 2728 crypto: crypto@1dfa000 { 2729 compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; 2730 reg = <0x0 0x01dfa000 0x0 0x6000>; 2731 dmas = <&cryptobam 4>, <&cryptobam 5>; 2732 dma-names = "rx", "tx"; 2733 iommus = <&apps_smmu 0x480 0x0>, 2734 <&apps_smmu 0x481 0x0>; 2735 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2736 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2737 interconnect-names = "memory"; 2738 }; 2739 2740 tcsr_mutex: hwlock@1f40000 { 2741 compatible = "qcom,tcsr-mutex"; 2742 reg = <0x0 0x01f40000 0x0 0x20000>; 2743 #hwlock-cells = <1>; 2744 }; 2745 2746 tcsr: syscon@1fc0000 { 2747 compatible = "qcom,qcs8300-tcsr", "syscon"; 2748 reg = <0x0 0x1fc0000 0x0 0x30000>; 2749 }; 2750 2751 remoteproc_adsp: remoteproc@3000000 { 2752 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2753 reg = <0x0 0x3000000 0x0 0x00100>; 2754 2755 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2756 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2757 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2758 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2759 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2760 interrupt-names = "wdog", 2761 "fatal", 2762 "ready", 2763 "handover", 2764 "stop-ack"; 2765 2766 clocks = <&rpmhcc RPMH_CXO_CLK>; 2767 clock-names = "xo"; 2768 2769 power-domains = <&rpmhpd RPMHPD_LCX>, 2770 <&rpmhpd RPMHPD_LMX>; 2771 power-domain-names = "lcx", 2772 "lmx"; 2773 2774 memory-region = <&adsp_mem>; 2775 2776 qcom,qmp = <&aoss_qmp>; 2777 2778 qcom,smem-states = <&smp2p_adsp_out 0>; 2779 qcom,smem-state-names = "stop"; 2780 2781 status = "disabled"; 2782 2783 glink-edge { 2784 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2785 IPCC_MPROC_SIGNAL_GLINK_QMP 2786 IRQ_TYPE_EDGE_RISING>; 2787 mboxes = <&ipcc IPCC_CLIENT_LPASS 2788 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2789 2790 label = "lpass"; 2791 qcom,remote-pid = <2>; 2792 2793 fastrpc { 2794 compatible = "qcom,fastrpc"; 2795 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2796 label = "adsp"; 2797 memory-region = <&adsp_rpc_remote_heap_mem>; 2798 qcom,vmids = <QCOM_SCM_VMID_LPASS 2799 QCOM_SCM_VMID_ADSP_HEAP>; 2800 #address-cells = <1>; 2801 #size-cells = <0>; 2802 2803 compute-cb@3 { 2804 compatible = "qcom,fastrpc-compute-cb"; 2805 reg = <3>; 2806 iommus = <&apps_smmu 0x2003 0x0>; 2807 dma-coherent; 2808 }; 2809 2810 compute-cb@4 { 2811 compatible = "qcom,fastrpc-compute-cb"; 2812 reg = <4>; 2813 iommus = <&apps_smmu 0x2004 0x0>; 2814 dma-coherent; 2815 }; 2816 2817 compute-cb@5 { 2818 compatible = "qcom,fastrpc-compute-cb"; 2819 reg = <5>; 2820 iommus = <&apps_smmu 0x2005 0x0>; 2821 dma-coherent; 2822 }; 2823 }; 2824 2825 gpr { 2826 compatible = "qcom,gpr"; 2827 qcom,glink-channels = "adsp_apps"; 2828 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2829 qcom,intents = <512 20>; 2830 #address-cells = <1>; 2831 #size-cells = <0>; 2832 2833 q6apm: service@1 { 2834 compatible = "qcom,q6apm"; 2835 reg = <GPR_APM_MODULE_IID>; 2836 #sound-dai-cells = <0>; 2837 qcom,protection-domain = "avs/audio", 2838 "msm/adsp/audio_pd"; 2839 2840 q6apmbedai: bedais { 2841 compatible = "qcom,q6apm-lpass-dais"; 2842 #sound-dai-cells = <1>; 2843 }; 2844 2845 q6apmdai: dais { 2846 compatible = "qcom,q6apm-dais"; 2847 iommus = <&apps_smmu 0x2001 0x0>; 2848 }; 2849 }; 2850 2851 q6prm: service@2 { 2852 compatible = "qcom,q6prm"; 2853 reg = <GPR_PRM_MODULE_IID>; 2854 qcom,protection-domain = "avs/audio", 2855 "msm/adsp/audio_pd"; 2856 2857 q6prmcc: clock-controller { 2858 compatible = "qcom,q6prm-lpass-clocks"; 2859 #clock-cells = <2>; 2860 }; 2861 }; 2862 }; 2863 }; 2864 }; 2865 2866 lpass_tlmm: pinctrl@3440000 { 2867 compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; 2868 reg = <0x0 0x03440000 0x0 0x20000>, 2869 <0x0 0x034d0000 0x0 0x10000>; 2870 2871 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2872 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2873 clock-names = "core", "audio"; 2874 2875 gpio-controller; 2876 #gpio-cells = <2>; 2877 gpio-ranges = <&lpass_tlmm 0 0 23>; 2878 2879 quad_mclk_active: quad-mclk-state { 2880 clk-pins { 2881 pins = "gpio5"; 2882 function = "ext_mclk1_c"; 2883 drive-strength = <8>; 2884 bias-disable; 2885 }; 2886 }; 2887 2888 quad_mi2s_active: quad-active-state { 2889 data-pins { 2890 pins = "gpio2", "gpio3"; 2891 function = "qua_mi2s_data"; 2892 drive-strength = <8>; 2893 bias-disable; 2894 }; 2895 2896 sclk-pins { 2897 pins = "gpio0"; 2898 function = "qua_mi2s_sclk"; 2899 drive-strength = <8>; 2900 bias-disable; 2901 }; 2902 2903 ws-pins { 2904 pins = "gpio1"; 2905 function = "qua_mi2s_ws"; 2906 drive-strength = <8>; 2907 bias-disable; 2908 }; 2909 }; 2910 2911 lpi_i2s4_active: lpi-i2s4-active-state { 2912 data0-pins { 2913 pins = "gpio17"; 2914 function = "i2s4_data"; 2915 drive-strength = <8>; 2916 bias-disable; 2917 }; 2918 2919 clk-pins { 2920 pins = "gpio12"; 2921 function = "i2s4_clk"; 2922 drive-strength = <8>; 2923 bias-disable; 2924 }; 2925 2926 ws-pins { 2927 pins = "gpio13"; 2928 function = "i2s4_ws"; 2929 drive-strength = <8>; 2930 bias-disable; 2931 }; 2932 }; 2933 }; 2934 2935 lpass_ag_noc: interconnect@3c40000 { 2936 compatible = "qcom,qcs8300-lpass-ag-noc"; 2937 reg = <0x0 0x03c40000 0x0 0x17200>; 2938 #interconnect-cells = <2>; 2939 qcom,bcm-voters = <&apps_bcm_voter>; 2940 }; 2941 2942 ctcu@4001000 { 2943 compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; 2944 reg = <0x0 0x04001000 0x0 0x1000>; 2945 2946 clocks = <&aoss_qmp>; 2947 clock-names = "apb"; 2948 2949 in-ports { 2950 #address-cells = <1>; 2951 #size-cells = <0>; 2952 2953 port@0 { 2954 reg = <0>; 2955 2956 ctcu_in0: endpoint { 2957 remote-endpoint = <&etr0_out>; 2958 }; 2959 }; 2960 2961 port@1 { 2962 reg = <1>; 2963 2964 ctcu_in1: endpoint { 2965 remote-endpoint = <&etr1_out>; 2966 }; 2967 }; 2968 }; 2969 }; 2970 2971 stm@4002000 { 2972 compatible = "arm,coresight-stm", "arm,primecell"; 2973 reg = <0x0 0x04002000 0x0 0x1000>, 2974 <0x0 0x16280000 0x0 0x180000>; 2975 reg-names = "stm-base", 2976 "stm-stimulus-base"; 2977 2978 clocks = <&aoss_qmp>; 2979 clock-names = "apb_pclk"; 2980 2981 out-ports { 2982 port { 2983 stm_out: endpoint { 2984 remote-endpoint = <&funnel0_in7>; 2985 }; 2986 }; 2987 }; 2988 }; 2989 2990 tpda@4004000 { 2991 compatible = "qcom,coresight-tpda", "arm,primecell"; 2992 reg = <0x0 0x04004000 0x0 0x1000>; 2993 2994 clocks = <&aoss_qmp>; 2995 clock-names = "apb_pclk"; 2996 2997 in-ports { 2998 #address-cells = <1>; 2999 #size-cells = <0>; 3000 3001 port@1 { 3002 reg = <1>; 3003 3004 qdss_tpda_in1: endpoint { 3005 remote-endpoint = <&qdss_tpdm1_out>; 3006 }; 3007 }; 3008 }; 3009 3010 out-ports { 3011 port { 3012 qdss_tpda_out: endpoint { 3013 remote-endpoint = <&funnel0_in6>; 3014 }; 3015 }; 3016 }; 3017 }; 3018 3019 tpdm@400f000 { 3020 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3021 reg = <0x0 0x0400f000 0x0 0x1000>; 3022 3023 clocks = <&aoss_qmp>; 3024 clock-names = "apb_pclk"; 3025 label = "tpdm_spdm"; 3026 3027 qcom,cmb-element-bits = <32>; 3028 qcom,cmb-msrs-num = <32>; 3029 3030 out-ports { 3031 port { 3032 qdss_tpdm1_out: endpoint { 3033 remote-endpoint = <&qdss_tpda_in1>; 3034 }; 3035 }; 3036 }; 3037 }; 3038 3039 funnel@4041000 { 3040 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3041 reg = <0x0 0x04041000 0x0 0x1000>; 3042 3043 clocks = <&aoss_qmp>; 3044 clock-names = "apb_pclk"; 3045 3046 in-ports { 3047 #address-cells = <1>; 3048 #size-cells = <0>; 3049 3050 port@6 { 3051 reg = <6>; 3052 3053 funnel0_in6: endpoint { 3054 remote-endpoint = <&qdss_tpda_out>; 3055 }; 3056 }; 3057 3058 port@7 { 3059 reg = <7>; 3060 3061 funnel0_in7: endpoint { 3062 remote-endpoint = <&stm_out>; 3063 }; 3064 }; 3065 }; 3066 3067 out-ports { 3068 port { 3069 funnel0_out: endpoint { 3070 remote-endpoint = <&qdss_funnel_in0>; 3071 }; 3072 }; 3073 }; 3074 }; 3075 3076 funnel@4042000 { 3077 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3078 reg = <0x0 0x04042000 0x0 0x1000>; 3079 3080 clocks = <&aoss_qmp>; 3081 clock-names = "apb_pclk"; 3082 3083 in-ports { 3084 #address-cells = <1>; 3085 #size-cells = <0>; 3086 3087 port@4 { 3088 reg = <4>; 3089 3090 funnel1_in4: endpoint { 3091 remote-endpoint = <&apss_funnel1_out>; 3092 }; 3093 }; 3094 3095 port@5 { 3096 reg = <5>; 3097 3098 funnel1_in5: endpoint { 3099 remote-endpoint = <&dlct0_funnel_out>; 3100 }; 3101 }; 3102 3103 port@6 { 3104 reg = <6>; 3105 3106 funnel1_in6: endpoint { 3107 remote-endpoint = <&dlmm_funnel_out>; 3108 }; 3109 }; 3110 3111 port@7 { 3112 reg = <7>; 3113 3114 funnel1_in7: endpoint { 3115 remote-endpoint = <&dlst_ch_funnel_out>; 3116 }; 3117 }; 3118 }; 3119 3120 out-ports { 3121 port { 3122 funnel1_out: endpoint { 3123 remote-endpoint = <&qdss_funnel_in1>; 3124 }; 3125 }; 3126 }; 3127 }; 3128 3129 funnel@4045000 { 3130 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3131 reg = <0x0 0x04045000 0x0 0x1000>; 3132 3133 clocks = <&aoss_qmp>; 3134 clock-names = "apb_pclk"; 3135 3136 in-ports { 3137 #address-cells = <1>; 3138 #size-cells = <0>; 3139 3140 port@0 { 3141 reg = <0>; 3142 3143 qdss_funnel_in0: endpoint { 3144 remote-endpoint = <&funnel0_out>; 3145 }; 3146 }; 3147 3148 port@1 { 3149 reg = <1>; 3150 3151 qdss_funnel_in1: endpoint { 3152 remote-endpoint = <&funnel1_out>; 3153 }; 3154 }; 3155 }; 3156 3157 out-ports { 3158 port { 3159 qdss_funnel_out: endpoint { 3160 remote-endpoint = <&aoss_funnel_in7>; 3161 }; 3162 }; 3163 }; 3164 }; 3165 3166 replicator@4046000 { 3167 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3168 reg = <0x0 0x04046000 0x0 0x1000>; 3169 3170 clocks = <&aoss_qmp>; 3171 clock-names = "apb_pclk"; 3172 3173 in-ports { 3174 port { 3175 qdss_rep_in: endpoint { 3176 remote-endpoint = <&swao_rep_out0>; 3177 }; 3178 }; 3179 }; 3180 3181 out-ports { 3182 port { 3183 qdss_rep_out0: endpoint { 3184 remote-endpoint = <&etr_rep_in>; 3185 }; 3186 }; 3187 }; 3188 }; 3189 3190 tmc@4048000 { 3191 compatible = "arm,coresight-tmc", "arm,primecell"; 3192 reg = <0x0 0x04048000 0x0 0x1000>; 3193 3194 clocks = <&aoss_qmp>; 3195 clock-names = "apb_pclk"; 3196 iommus = <&apps_smmu 0x04c0 0x00>; 3197 3198 arm,scatter-gather; 3199 3200 in-ports { 3201 port { 3202 etr0_in: endpoint { 3203 remote-endpoint = <&etr_rep_out0>; 3204 }; 3205 }; 3206 }; 3207 3208 out-ports { 3209 port { 3210 etr0_out: endpoint { 3211 remote-endpoint = <&ctcu_in0>; 3212 }; 3213 }; 3214 }; 3215 }; 3216 3217 replicator@404e000 { 3218 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3219 reg = <0x0 0x0404e000 0x0 0x1000>; 3220 3221 clocks = <&aoss_qmp>; 3222 clock-names = "apb_pclk"; 3223 3224 in-ports { 3225 port { 3226 etr_rep_in: endpoint { 3227 remote-endpoint = <&qdss_rep_out0>; 3228 }; 3229 }; 3230 }; 3231 3232 out-ports { 3233 #address-cells = <1>; 3234 #size-cells = <0>; 3235 3236 port@0 { 3237 reg = <0>; 3238 3239 etr_rep_out0: endpoint { 3240 remote-endpoint = <&etr0_in>; 3241 }; 3242 }; 3243 3244 port@1 { 3245 reg = <1>; 3246 3247 etr_rep_out1: endpoint { 3248 remote-endpoint = <&etr1_in>; 3249 }; 3250 }; 3251 }; 3252 }; 3253 3254 tmc@404f000 { 3255 compatible = "arm,coresight-tmc", "arm,primecell"; 3256 reg = <0x0 0x0404f000 0x0 0x1000>; 3257 3258 clocks = <&aoss_qmp>; 3259 clock-names = "apb_pclk"; 3260 iommus = <&apps_smmu 0x04a0 0x40>; 3261 3262 arm,scatter-gather; 3263 arm,buffer-size = <0x400000>; 3264 3265 in-ports { 3266 port { 3267 etr1_in: endpoint { 3268 remote-endpoint = <&etr_rep_out1>; 3269 }; 3270 }; 3271 }; 3272 3273 out-ports { 3274 port { 3275 etr1_out: endpoint { 3276 remote-endpoint = <&ctcu_in1>; 3277 }; 3278 }; 3279 }; 3280 }; 3281 3282 tpdm@4841000 { 3283 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3284 reg = <0x0 0x04841000 0x0 0x1000>; 3285 3286 clocks = <&aoss_qmp>; 3287 clock-names = "apb_pclk"; 3288 label = "tpdm_prng"; 3289 3290 qcom,cmb-element-bits = <32>; 3291 qcom,cmb-msrs-num = <32>; 3292 3293 out-ports { 3294 port { 3295 prng_tpdm_out: endpoint { 3296 remote-endpoint = <&dlct0_tpda_in19>; 3297 }; 3298 }; 3299 }; 3300 }; 3301 3302 tpdm@4850000 { 3303 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3304 reg = <0x0 0x04850000 0x0 0x1000>; 3305 3306 clocks = <&aoss_qmp>; 3307 clock-names = "apb_pclk"; 3308 label = "tpdm_pimem"; 3309 3310 qcom,cmb-element-bits = <64>; 3311 qcom,cmb-msrs-num = <32>; 3312 qcom,dsb-element-bits = <32>; 3313 qcom,dsb-msrs-num = <32>; 3314 3315 out-ports { 3316 port { 3317 pimem_tpdm_out: endpoint { 3318 remote-endpoint = <&dlct0_tpda_in25>; 3319 }; 3320 }; 3321 }; 3322 }; 3323 3324 tpdm@4860000 { 3325 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3326 reg = <0x0 0x04860000 0x0 0x1000>; 3327 3328 clocks = <&aoss_qmp>; 3329 clock-names = "apb_pclk"; 3330 label = "tpdm_dl_ch_south"; 3331 3332 qcom,dsb-element-bits = <32>; 3333 qcom,dsb-msrs-num = <32>; 3334 3335 out-ports { 3336 port { 3337 dlst_ch_tpdm0_out: endpoint { 3338 remote-endpoint = <&dlst_ch_tpda_in8>; 3339 }; 3340 }; 3341 }; 3342 }; 3343 3344 tpda@4864000 { 3345 compatible = "qcom,coresight-tpda", "arm,primecell"; 3346 reg = <0x0 0x04864000 0x0 0x1000>; 3347 3348 clocks = <&aoss_qmp>; 3349 clock-names = "apb_pclk"; 3350 3351 in-ports { 3352 #address-cells = <1>; 3353 #size-cells = <0>; 3354 3355 port@8 { 3356 reg = <8>; 3357 3358 dlst_ch_tpda_in8: endpoint { 3359 remote-endpoint = <&dlst_ch_tpdm0_out>; 3360 }; 3361 }; 3362 }; 3363 3364 out-ports { 3365 port { 3366 dlst_ch_tpda_out: endpoint { 3367 remote-endpoint = <&dlst_ch_funnel_in0>; 3368 }; 3369 }; 3370 }; 3371 }; 3372 3373 funnel@4865000 { 3374 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3375 reg = <0x0 0x04865000 0x0 0x1000>; 3376 3377 clocks = <&aoss_qmp>; 3378 clock-names = "apb_pclk"; 3379 3380 in-ports { 3381 #address-cells = <1>; 3382 #size-cells = <0>; 3383 3384 port@0 { 3385 reg = <0>; 3386 3387 dlst_ch_funnel_in0: endpoint { 3388 remote-endpoint = <&dlst_ch_tpda_out>; 3389 }; 3390 }; 3391 3392 port@4 { 3393 reg = <4>; 3394 3395 dlst_ch_funnel_in4: endpoint { 3396 remote-endpoint = <&dlst_funnel_out>; 3397 }; 3398 }; 3399 3400 port@6 { 3401 reg = <6>; 3402 3403 dlst_ch_funnel_in6: endpoint { 3404 remote-endpoint = <&gdsp_funnel_out>; 3405 }; 3406 }; 3407 }; 3408 3409 out-ports { 3410 port { 3411 dlst_ch_funnel_out: endpoint { 3412 remote-endpoint = <&funnel1_in7>; 3413 }; 3414 }; 3415 }; 3416 }; 3417 3418 tpdm@4980000 { 3419 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3420 reg = <0x0 0x04980000 0x0 0x1000>; 3421 3422 clocks = <&aoss_qmp>; 3423 clock-names = "apb_pclk"; 3424 label = "tpdm_cdsp"; 3425 3426 qcom,dsb-element-bits = <32>; 3427 qcom,dsb-msrs-num = <32>; 3428 3429 out-ports { 3430 port { 3431 turing2_tpdm_out: endpoint { 3432 remote-endpoint = <&turing2_funnel_in0>; 3433 }; 3434 }; 3435 }; 3436 }; 3437 3438 funnel@4983000 { 3439 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3440 reg = <0x0 0x04983000 0x0 0x1000>; 3441 3442 clocks = <&aoss_qmp>; 3443 clock-names = "apb_pclk"; 3444 3445 in-ports { 3446 port { 3447 turing2_funnel_in0: endpoint { 3448 remote-endpoint = <&turing2_tpdm_out>; 3449 }; 3450 }; 3451 }; 3452 3453 out-ports { 3454 port { 3455 turing2_funnel_out0: endpoint { 3456 remote-endpoint = <&gdsp_tpda_in5>; 3457 }; 3458 }; 3459 }; 3460 }; 3461 3462 tpdm@4ac0000 { 3463 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3464 reg = <0x0 0x04ac0000 0x0 0x1000>; 3465 3466 clocks = <&aoss_qmp>; 3467 clock-names = "apb_pclk"; 3468 label = "tpdm_mmnoc_0"; 3469 3470 qcom,dsb-element-bits = <32>; 3471 qcom,dsb-msrs-num = <32>; 3472 3473 out-ports { 3474 port { 3475 dlmm_tpdm0_out: endpoint { 3476 remote-endpoint = <&dlmm_tpda_in27>; 3477 }; 3478 }; 3479 }; 3480 }; 3481 3482 tpda@4ac4000 { 3483 compatible = "qcom,coresight-tpda", "arm,primecell"; 3484 reg = <0x0 0x04ac4000 0x0 0x1000>; 3485 3486 clocks = <&aoss_qmp>; 3487 clock-names = "apb_pclk"; 3488 3489 in-ports { 3490 #address-cells = <1>; 3491 #size-cells = <0>; 3492 3493 port@1b { 3494 reg = <27>; 3495 3496 dlmm_tpda_in27: endpoint { 3497 remote-endpoint = <&dlmm_tpdm0_out>; 3498 }; 3499 }; 3500 }; 3501 3502 out-ports { 3503 port { 3504 dlmm_tpda_out: endpoint { 3505 remote-endpoint = <&dlmm_funnel_in0>; 3506 }; 3507 }; 3508 }; 3509 }; 3510 3511 funnel@4ac5000 { 3512 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3513 reg = <0x0 0x04ac5000 0x0 0x1000>; 3514 3515 clocks = <&aoss_qmp>; 3516 clock-names = "apb_pclk"; 3517 3518 in-ports { 3519 port { 3520 dlmm_funnel_in0: endpoint { 3521 remote-endpoint = <&dlmm_tpda_out>; 3522 }; 3523 }; 3524 }; 3525 3526 out-ports { 3527 port { 3528 dlmm_funnel_out: endpoint { 3529 remote-endpoint = <&funnel1_in6>; 3530 }; 3531 }; 3532 }; 3533 }; 3534 3535 tpdm@4ad0000 { 3536 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3537 reg = <0x0 0x04ad0000 0x0 0x1000>; 3538 3539 clocks = <&aoss_qmp>; 3540 clock-names = "apb_pclk"; 3541 label = "tpdm_dlct"; 3542 3543 qcom,dsb-element-bits = <32>; 3544 qcom,dsb-msrs-num = <32>; 3545 3546 out-ports { 3547 port { 3548 dlct0_tpdm0_out: endpoint { 3549 remote-endpoint = <&dlct0_tpda_in26>; 3550 }; 3551 }; 3552 }; 3553 }; 3554 3555 tpda@4ad3000 { 3556 compatible = "qcom,coresight-tpda", "arm,primecell"; 3557 reg = <0x0 0x04ad3000 0x0 0x1000>; 3558 3559 clocks = <&aoss_qmp>; 3560 clock-names = "apb_pclk"; 3561 3562 in-ports { 3563 #address-cells = <1>; 3564 #size-cells = <0>; 3565 3566 port@13 { 3567 reg = <19>; 3568 3569 dlct0_tpda_in19: endpoint { 3570 remote-endpoint = <&prng_tpdm_out>; 3571 }; 3572 }; 3573 3574 port@19 { 3575 reg = <25>; 3576 3577 dlct0_tpda_in25: endpoint { 3578 remote-endpoint = <&pimem_tpdm_out>; 3579 }; 3580 }; 3581 3582 port@1a { 3583 reg = <26>; 3584 3585 dlct0_tpda_in26: endpoint { 3586 remote-endpoint = <&dlct0_tpdm0_out>; 3587 }; 3588 }; 3589 }; 3590 3591 out-ports { 3592 port { 3593 dlct0_tpda_out: endpoint { 3594 remote-endpoint = <&dlct0_funnel_in0>; 3595 }; 3596 }; 3597 }; 3598 }; 3599 3600 funnel@4ad4000 { 3601 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3602 reg = <0x0 0x04ad4000 0x0 0x1000>; 3603 3604 clocks = <&aoss_qmp>; 3605 clock-names = "apb_pclk"; 3606 3607 in-ports { 3608 #address-cells = <1>; 3609 #size-cells = <0>; 3610 3611 port@0 { 3612 reg = <0>; 3613 3614 dlct0_funnel_in0: endpoint { 3615 remote-endpoint = <&dlct0_tpda_out>; 3616 }; 3617 }; 3618 3619 port@4 { 3620 reg = <4>; 3621 3622 dlct0_funnel_in4: endpoint { 3623 remote-endpoint = <&ddr_funnel5_out>; 3624 }; 3625 }; 3626 }; 3627 3628 out-ports { 3629 port { 3630 dlct0_funnel_out: endpoint { 3631 remote-endpoint = <&funnel1_in5>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 funnel@4b04000 { 3638 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3639 reg = <0x0 0x04b04000 0x0 0x1000>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 3644 in-ports { 3645 #address-cells = <1>; 3646 #size-cells = <0>; 3647 3648 port@6 { 3649 reg = <6>; 3650 3651 aoss_funnel_in6: endpoint { 3652 remote-endpoint = <&aoss_tpda_out>; 3653 }; 3654 }; 3655 3656 port@7 { 3657 reg = <7>; 3658 3659 aoss_funnel_in7: endpoint { 3660 remote-endpoint = <&qdss_funnel_out>; 3661 }; 3662 }; 3663 }; 3664 3665 out-ports { 3666 port { 3667 aoss_funnel_out: endpoint { 3668 remote-endpoint = <&etf0_in>; 3669 }; 3670 }; 3671 }; 3672 }; 3673 3674 tmc_etf: tmc@4b05000 { 3675 compatible = "arm,coresight-tmc", "arm,primecell"; 3676 reg = <0x0 0x04b05000 0x0 0x1000>; 3677 3678 clocks = <&aoss_qmp>; 3679 clock-names = "apb_pclk"; 3680 3681 in-ports { 3682 port { 3683 etf0_in: endpoint { 3684 remote-endpoint = <&aoss_funnel_out>; 3685 }; 3686 }; 3687 }; 3688 3689 out-ports { 3690 port { 3691 etf0_out: endpoint { 3692 remote-endpoint = <&swao_rep_in>; 3693 }; 3694 }; 3695 }; 3696 }; 3697 3698 replicator@4b06000 { 3699 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3700 reg = <0x0 0x04b06000 0x0 0x1000>; 3701 3702 clocks = <&aoss_qmp>; 3703 clock-names = "apb_pclk"; 3704 3705 in-ports { 3706 port { 3707 swao_rep_in: endpoint { 3708 remote-endpoint = <&etf0_out>; 3709 }; 3710 }; 3711 }; 3712 3713 out-ports { 3714 #address-cells = <1>; 3715 #size-cells = <0>; 3716 3717 port@0 { 3718 reg = <0>; 3719 3720 swao_rep_out0: endpoint { 3721 remote-endpoint = <&qdss_rep_in>; 3722 }; 3723 }; 3724 3725 port@1 { 3726 reg = <1>; 3727 3728 swao_rep_out1: endpoint { 3729 remote-endpoint = <&eud_in>; 3730 }; 3731 }; 3732 }; 3733 }; 3734 3735 tpda@4b08000 { 3736 compatible = "qcom,coresight-tpda", "arm,primecell"; 3737 reg = <0x0 0x04b08000 0x0 0x1000>; 3738 3739 clocks = <&aoss_qmp>; 3740 clock-names = "apb_pclk"; 3741 3742 in-ports { 3743 #address-cells = <1>; 3744 #size-cells = <0>; 3745 3746 port@0 { 3747 reg = <0>; 3748 3749 aoss_tpda_in0: endpoint { 3750 remote-endpoint = <&aoss_tpdm0_out>; 3751 }; 3752 }; 3753 3754 port@1 { 3755 reg = <1>; 3756 3757 aoss_tpda_in1: endpoint { 3758 remote-endpoint = <&aoss_tpdm1_out>; 3759 }; 3760 }; 3761 3762 port@2 { 3763 reg = <2>; 3764 3765 aoss_tpda_in2: endpoint { 3766 remote-endpoint = <&aoss_tpdm2_out>; 3767 }; 3768 }; 3769 3770 port@3 { 3771 reg = <3>; 3772 3773 aoss_tpda_in3: endpoint { 3774 remote-endpoint = <&aoss_tpdm3_out>; 3775 }; 3776 }; 3777 3778 port@4 { 3779 reg = <4>; 3780 3781 aoss_tpda_in4: endpoint { 3782 remote-endpoint = <&aoss_tpdm4_out>; 3783 }; 3784 }; 3785 }; 3786 3787 out-ports { 3788 port { 3789 aoss_tpda_out: endpoint { 3790 remote-endpoint = <&aoss_funnel_in6>; 3791 }; 3792 }; 3793 }; 3794 }; 3795 3796 tpdm@4b09000 { 3797 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3798 reg = <0x0 0x04b09000 0x0 0x1000>; 3799 3800 clocks = <&aoss_qmp>; 3801 clock-names = "apb_pclk"; 3802 label = "tpdm_swao_prio_0"; 3803 3804 qcom,cmb-element-bits = <64>; 3805 qcom,cmb-msrs-num = <32>; 3806 3807 out-ports { 3808 port { 3809 aoss_tpdm0_out: endpoint { 3810 remote-endpoint = <&aoss_tpda_in0>; 3811 }; 3812 }; 3813 }; 3814 }; 3815 3816 tpdm@4b0a000 { 3817 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3818 reg = <0x0 0x04b0a000 0x0 0x1000>; 3819 3820 clocks = <&aoss_qmp>; 3821 clock-names = "apb_pclk"; 3822 label = "tpdm_swao_prio_1"; 3823 3824 qcom,cmb-element-bits = <64>; 3825 qcom,cmb-msrs-num = <32>; 3826 3827 out-ports { 3828 port { 3829 aoss_tpdm1_out: endpoint { 3830 remote-endpoint = <&aoss_tpda_in1>; 3831 }; 3832 }; 3833 }; 3834 }; 3835 3836 tpdm@4b0b000 { 3837 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3838 reg = <0x0 0x04b0b000 0x0 0x1000>; 3839 3840 clocks = <&aoss_qmp>; 3841 clock-names = "apb_pclk"; 3842 label = "tpdm_swao_prio_2"; 3843 3844 qcom,cmb-element-bits = <64>; 3845 qcom,cmb-msrs-num = <32>; 3846 3847 out-ports { 3848 port { 3849 aoss_tpdm2_out: endpoint { 3850 remote-endpoint = <&aoss_tpda_in2>; 3851 }; 3852 }; 3853 }; 3854 }; 3855 3856 tpdm@4b0c000 { 3857 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3858 reg = <0x0 0x04b0c000 0x0 0x1000>; 3859 3860 clocks = <&aoss_qmp>; 3861 clock-names = "apb_pclk"; 3862 label = "tpdm_swao_prio_3"; 3863 3864 qcom,cmb-element-bits = <64>; 3865 qcom,cmb-msrs-num = <32>; 3866 3867 out-ports { 3868 port { 3869 aoss_tpdm3_out: endpoint { 3870 remote-endpoint = <&aoss_tpda_in3>; 3871 }; 3872 }; 3873 }; 3874 }; 3875 3876 tpdm@4b0d000 { 3877 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3878 reg = <0x0 0x04b0d000 0x0 0x1000>; 3879 3880 clocks = <&aoss_qmp>; 3881 clock-names = "apb_pclk"; 3882 label = "tpdm_swao_1"; 3883 3884 qcom,dsb-element-bits = <32>; 3885 qcom,dsb-msrs-num = <32>; 3886 3887 out-ports { 3888 port { 3889 aoss_tpdm4_out: endpoint { 3890 remote-endpoint = <&aoss_tpda_in4>; 3891 }; 3892 }; 3893 }; 3894 }; 3895 3896 cti@4b13000 { 3897 compatible = "arm,coresight-cti", "arm,primecell"; 3898 reg = <0x0 0x04b13000 0x0 0x1000>; 3899 3900 clocks = <&aoss_qmp>; 3901 clock-names = "apb_pclk"; 3902 label = "cti_aoss"; 3903 }; 3904 3905 tpdm@4b80000 { 3906 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3907 reg = <0x0 0x04b80000 0x0 0x1000>; 3908 3909 clocks = <&aoss_qmp>; 3910 clock-names = "apb_pclk"; 3911 label = "tpdm_cdsp_0"; 3912 3913 qcom,dsb-element-bits = <32>; 3914 qcom,dsb-msrs-num = <32>; 3915 3916 out-ports { 3917 port { 3918 turing0_tpdm0_out: endpoint { 3919 remote-endpoint = <&turing0_tpda_in0>; 3920 }; 3921 }; 3922 }; 3923 }; 3924 3925 tpda@4b86000 { 3926 compatible = "qcom,coresight-tpda", "arm,primecell"; 3927 reg = <0x0 0x04b86000 0x0 0x1000>; 3928 3929 clocks = <&aoss_qmp>; 3930 clock-names = "apb_pclk"; 3931 3932 in-ports { 3933 port { 3934 turing0_tpda_in0: endpoint { 3935 remote-endpoint = <&turing0_tpdm0_out>; 3936 }; 3937 }; 3938 }; 3939 3940 out-ports { 3941 port { 3942 turing0_tpda_out: endpoint { 3943 remote-endpoint = <&turing0_funnel_in0>; 3944 }; 3945 }; 3946 }; 3947 }; 3948 3949 funnel@4b87000 { 3950 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3951 reg = <0x0 0x04b87000 0x0 0x1000>; 3952 3953 clocks = <&aoss_qmp>; 3954 clock-names = "apb_pclk"; 3955 3956 in-ports { 3957 port { 3958 turing0_funnel_in0: endpoint { 3959 remote-endpoint = <&turing0_tpda_out>; 3960 }; 3961 }; 3962 }; 3963 3964 out-ports { 3965 port { 3966 turing0_funnel_out: endpoint { 3967 remote-endpoint = <&gdsp_funnel_in4>; 3968 }; 3969 }; 3970 }; 3971 }; 3972 3973 cti@4b8b000 { 3974 compatible = "arm,coresight-cti", "arm,primecell"; 3975 reg = <0x0 0x04b8b000 0x0 0x1000>; 3976 3977 clocks = <&aoss_qmp>; 3978 clock-names = "apb_pclk"; 3979 label = "cti_cdsp_1"; 3980 }; 3981 3982 tpdm@4c40000 { 3983 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3984 reg = <0x0 0x04c40000 0x0 0x1000>; 3985 3986 clocks = <&aoss_qmp>; 3987 clock-names = "apb_pclk"; 3988 label = "tpdm_gpdsp_0"; 3989 3990 qcom,dsb-element-bits = <32>; 3991 qcom,dsb-msrs-num = <32>; 3992 3993 out-ports { 3994 port { 3995 gdsp_tpdm0_out: endpoint { 3996 remote-endpoint = <&gdsp_tpda_in8>; 3997 }; 3998 }; 3999 }; 4000 }; 4001 4002 tpda@4c44000 { 4003 compatible = "qcom,coresight-tpda", "arm,primecell"; 4004 reg = <0x0 0x04c44000 0x0 0x1000>; 4005 4006 clocks = <&aoss_qmp>; 4007 clock-names = "apb_pclk"; 4008 4009 in-ports { 4010 #address-cells = <1>; 4011 #size-cells = <0>; 4012 4013 port@5 { 4014 reg = <5>; 4015 4016 gdsp_tpda_in5: endpoint { 4017 remote-endpoint = <&turing2_funnel_out0>; 4018 }; 4019 }; 4020 4021 port@8 { 4022 reg = <8>; 4023 4024 gdsp_tpda_in8: endpoint { 4025 remote-endpoint = <&gdsp_tpdm0_out>; 4026 }; 4027 }; 4028 }; 4029 4030 out-ports { 4031 port { 4032 gdsp_tpda_out: endpoint { 4033 remote-endpoint = <&gdsp_funnel_in0>; 4034 }; 4035 }; 4036 }; 4037 }; 4038 4039 funnel@4c45000 { 4040 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4041 reg = <0x0 0x04c45000 0x0 0x1000>; 4042 4043 clocks = <&aoss_qmp>; 4044 clock-names = "apb_pclk"; 4045 4046 in-ports { 4047 #address-cells = <1>; 4048 #size-cells = <0>; 4049 4050 port@0 { 4051 reg = <0>; 4052 4053 gdsp_funnel_in0: endpoint { 4054 remote-endpoint = <&gdsp_tpda_out>; 4055 }; 4056 }; 4057 4058 port@4 { 4059 reg = <4>; 4060 4061 gdsp_funnel_in4: endpoint { 4062 remote-endpoint = <&turing0_funnel_out>; 4063 }; 4064 }; 4065 }; 4066 4067 out-ports { 4068 port { 4069 gdsp_funnel_out: endpoint { 4070 remote-endpoint = <&dlst_ch_funnel_in6>; 4071 }; 4072 }; 4073 }; 4074 }; 4075 4076 tpdm@4c50000 { 4077 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4078 reg = <0x0 0x04c50000 0x0 0x1000>; 4079 4080 clocks = <&aoss_qmp>; 4081 clock-names = "apb_pclk"; 4082 label = "tpdm_dl_south"; 4083 4084 qcom,dsb-element-bits = <32>; 4085 qcom,dsb-msrs-num = <32>; 4086 4087 out-ports { 4088 port { 4089 dlst_tpdm0_out: endpoint { 4090 remote-endpoint = <&dlst_tpda_in8>; 4091 }; 4092 }; 4093 }; 4094 }; 4095 4096 tpda@4c54000 { 4097 compatible = "qcom,coresight-tpda", "arm,primecell"; 4098 reg = <0x0 0x04c54000 0x0 0x1000>; 4099 4100 clocks = <&aoss_qmp>; 4101 clock-names = "apb_pclk"; 4102 4103 in-ports { 4104 #address-cells = <1>; 4105 #size-cells = <0>; 4106 4107 port@8 { 4108 reg = <8>; 4109 4110 dlst_tpda_in8: endpoint { 4111 remote-endpoint = <&dlst_tpdm0_out>; 4112 }; 4113 }; 4114 }; 4115 4116 out-ports { 4117 port { 4118 dlst_tpda_out: endpoint { 4119 remote-endpoint = <&dlst_funnel_in0>; 4120 }; 4121 }; 4122 }; 4123 }; 4124 4125 funnel@4c55000 { 4126 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4127 reg = <0x0 0x04c55000 0x0 0x1000>; 4128 4129 clocks = <&aoss_qmp>; 4130 clock-names = "apb_pclk"; 4131 4132 in-ports { 4133 port { 4134 dlst_funnel_in0: endpoint { 4135 remote-endpoint = <&dlst_tpda_out>; 4136 }; 4137 }; 4138 }; 4139 4140 out-ports { 4141 port { 4142 dlst_funnel_out: endpoint { 4143 remote-endpoint = <&dlst_ch_funnel_in4>; 4144 }; 4145 }; 4146 }; 4147 }; 4148 4149 tpdm@4e00000 { 4150 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4151 reg = <0x0 0x04e00000 0x0 0x1000>; 4152 4153 clocks = <&aoss_qmp>; 4154 clock-names = "apb_pclk"; 4155 label = "tpdm_ddr"; 4156 4157 qcom,dsb-element-bits = <32>; 4158 qcom,dsb-msrs-num = <32>; 4159 qcom,cmb-element-bits = <32>; 4160 qcom,cmb-msrs-num = <32>; 4161 4162 out-ports { 4163 port { 4164 ddr_tpdm3_out: endpoint { 4165 remote-endpoint = <&ddr_tpda_in4>; 4166 }; 4167 }; 4168 }; 4169 }; 4170 4171 tpda@4e03000 { 4172 compatible = "qcom,coresight-tpda", "arm,primecell"; 4173 reg = <0x0 0x04e03000 0x0 0x1000>; 4174 4175 clocks = <&aoss_qmp>; 4176 clock-names = "apb_pclk"; 4177 4178 in-ports { 4179 #address-cells = <1>; 4180 #size-cells = <0>; 4181 4182 port@0 { 4183 reg = <0>; 4184 4185 ddr_tpda_in0: endpoint { 4186 remote-endpoint = <&ddr_funnel0_out0>; 4187 }; 4188 }; 4189 4190 port@1 { 4191 reg = <1>; 4192 4193 ddr_tpda_in1: endpoint { 4194 remote-endpoint = <&ddr_funnel1_out0>; 4195 }; 4196 }; 4197 4198 port@4 { 4199 reg = <4>; 4200 4201 ddr_tpda_in4: endpoint { 4202 remote-endpoint = <&ddr_tpdm3_out>; 4203 }; 4204 }; 4205 }; 4206 4207 out-ports { 4208 port { 4209 ddr_tpda_out: endpoint { 4210 remote-endpoint = <&ddr_funnel5_in0>; 4211 }; 4212 }; 4213 }; 4214 }; 4215 4216 funnel@4e04000 { 4217 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4218 reg = <0x0 0x04e04000 0x0 0x1000>; 4219 4220 clocks = <&aoss_qmp>; 4221 clock-names = "apb_pclk"; 4222 4223 in-ports { 4224 port { 4225 ddr_funnel5_in0: endpoint { 4226 remote-endpoint = <&ddr_tpda_out>; 4227 }; 4228 }; 4229 }; 4230 4231 out-ports { 4232 port { 4233 ddr_funnel5_out: endpoint { 4234 remote-endpoint = <&dlct0_funnel_in4>; 4235 }; 4236 }; 4237 }; 4238 }; 4239 4240 tpdm@4e10000 { 4241 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4242 reg = <0x0 0x04e10000 0x0 0x1000>; 4243 4244 clocks = <&aoss_qmp>; 4245 clock-names = "apb_pclk"; 4246 label = "tpdm_ddr_ch0"; 4247 4248 qcom,dsb-element-bits = <32>; 4249 qcom,dsb-msrs-num = <32>; 4250 4251 out-ports { 4252 port { 4253 ddr_tpdm0_out: endpoint { 4254 remote-endpoint = <&ddr_funnel0_in0>; 4255 }; 4256 }; 4257 }; 4258 }; 4259 4260 funnel@4e12000 { 4261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4262 reg = <0x0 0x04e12000 0x0 0x1000>; 4263 4264 clocks = <&aoss_qmp>; 4265 clock-names = "apb_pclk"; 4266 4267 in-ports { 4268 port { 4269 ddr_funnel0_in0: endpoint { 4270 remote-endpoint = <&ddr_tpdm0_out>; 4271 }; 4272 }; 4273 }; 4274 4275 out-ports { 4276 port { 4277 ddr_funnel0_out0: endpoint { 4278 remote-endpoint = <&ddr_tpda_in0>; 4279 }; 4280 }; 4281 }; 4282 }; 4283 4284 tpdm@4e20000 { 4285 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4286 reg = <0x0 0x04e20000 0x0 0x1000>; 4287 4288 clocks = <&aoss_qmp>; 4289 clock-names = "apb_pclk"; 4290 label = "tpdm_ddr_ch1"; 4291 4292 qcom,dsb-element-bits = <32>; 4293 qcom,dsb-msrs-num = <32>; 4294 4295 out-ports { 4296 port { 4297 ddr_tpdm1_out: endpoint { 4298 remote-endpoint = <&ddr_funnel1_in0>; 4299 }; 4300 }; 4301 }; 4302 }; 4303 4304 funnel@4e22000 { 4305 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4306 reg = <0x0 0x04e22000 0x0 0x1000>; 4307 4308 clocks = <&aoss_qmp>; 4309 clock-names = "apb_pclk"; 4310 4311 in-ports { 4312 port { 4313 ddr_funnel1_in0: endpoint { 4314 remote-endpoint = <&ddr_tpdm1_out>; 4315 }; 4316 }; 4317 }; 4318 4319 out-ports { 4320 port { 4321 ddr_funnel1_out0: endpoint { 4322 remote-endpoint = <&ddr_tpda_in1>; 4323 }; 4324 }; 4325 }; 4326 }; 4327 4328 etm@6040000 { 4329 compatible = "arm,primecell"; 4330 reg = <0x0 0x06040000 0x0 0x1000>; 4331 cpu = <&cpu0>; 4332 4333 clocks = <&aoss_qmp>; 4334 clock-names = "apb_pclk"; 4335 4336 arm,coresight-loses-context-with-cpu; 4337 qcom,skip-power-up; 4338 4339 out-ports { 4340 port { 4341 etm0_out: endpoint { 4342 remote-endpoint = <&apss_funnel0_in0>; 4343 }; 4344 }; 4345 }; 4346 }; 4347 4348 etm@6140000 { 4349 compatible = "arm,primecell"; 4350 reg = <0x0 0x06140000 0x0 0x1000>; 4351 cpu = <&cpu1>; 4352 4353 clocks = <&aoss_qmp>; 4354 clock-names = "apb_pclk"; 4355 4356 arm,coresight-loses-context-with-cpu; 4357 qcom,skip-power-up; 4358 4359 out-ports { 4360 port { 4361 etm1_out: endpoint { 4362 remote-endpoint = <&apss_funnel0_in1>; 4363 }; 4364 }; 4365 }; 4366 }; 4367 4368 etm@6240000 { 4369 compatible = "arm,primecell"; 4370 reg = <0x0 0x06240000 0x0 0x1000>; 4371 cpu = <&cpu2>; 4372 4373 clocks = <&aoss_qmp>; 4374 clock-names = "apb_pclk"; 4375 4376 arm,coresight-loses-context-with-cpu; 4377 qcom,skip-power-up; 4378 4379 out-ports { 4380 port { 4381 etm2_out: endpoint { 4382 remote-endpoint = <&apss_funnel0_in2>; 4383 }; 4384 }; 4385 }; 4386 }; 4387 4388 etm@6340000 { 4389 compatible = "arm,primecell"; 4390 reg = <0x0 0x06340000 0x0 0x1000>; 4391 cpu = <&cpu3>; 4392 4393 clocks = <&aoss_qmp>; 4394 clock-names = "apb_pclk"; 4395 4396 arm,coresight-loses-context-with-cpu; 4397 qcom,skip-power-up; 4398 4399 out-ports { 4400 port { 4401 etm3_out: endpoint { 4402 remote-endpoint = <&apss_funnel0_in3>; 4403 }; 4404 }; 4405 }; 4406 }; 4407 4408 etm@6440000 { 4409 compatible = "arm,primecell"; 4410 reg = <0x0 0x06440000 0x0 0x1000>; 4411 cpu = <&cpu4>; 4412 4413 clocks = <&aoss_qmp>; 4414 clock-names = "apb_pclk"; 4415 4416 arm,coresight-loses-context-with-cpu; 4417 qcom,skip-power-up; 4418 4419 out-ports { 4420 port { 4421 etm4_out: endpoint { 4422 remote-endpoint = <&apss_funnel0_in4>; 4423 }; 4424 }; 4425 }; 4426 }; 4427 4428 etm@6540000 { 4429 compatible = "arm,primecell"; 4430 reg = <0x0 0x06540000 0x0 0x1000>; 4431 cpu = <&cpu5>; 4432 4433 clocks = <&aoss_qmp>; 4434 clock-names = "apb_pclk"; 4435 4436 arm,coresight-loses-context-with-cpu; 4437 qcom,skip-power-up; 4438 4439 out-ports { 4440 port { 4441 etm5_out: endpoint { 4442 remote-endpoint = <&apss_funnel0_in5>; 4443 }; 4444 }; 4445 }; 4446 }; 4447 4448 etm@6640000 { 4449 compatible = "arm,primecell"; 4450 reg = <0x0 0x06640000 0x0 0x1000>; 4451 cpu = <&cpu6>; 4452 4453 clocks = <&aoss_qmp>; 4454 clock-names = "apb_pclk"; 4455 4456 arm,coresight-loses-context-with-cpu; 4457 qcom,skip-power-up; 4458 4459 out-ports { 4460 port { 4461 etm6_out: endpoint { 4462 remote-endpoint = <&apss_funnel0_in6>; 4463 }; 4464 }; 4465 }; 4466 }; 4467 4468 etm@6740000 { 4469 compatible = "arm,primecell"; 4470 reg = <0x0 0x06740000 0x0 0x1000>; 4471 cpu = <&cpu7>; 4472 4473 clocks = <&aoss_qmp>; 4474 clock-names = "apb_pclk"; 4475 4476 arm,coresight-loses-context-with-cpu; 4477 qcom,skip-power-up; 4478 4479 out-ports { 4480 port { 4481 etm7_out: endpoint { 4482 remote-endpoint = <&apss_funnel0_in7>; 4483 }; 4484 }; 4485 }; 4486 }; 4487 4488 funnel@6800000 { 4489 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4490 reg = <0x0 0x06800000 0x0 0x1000>; 4491 4492 clocks = <&aoss_qmp>; 4493 clock-names = "apb_pclk"; 4494 4495 in-ports { 4496 #address-cells = <1>; 4497 #size-cells = <0>; 4498 4499 port@0 { 4500 reg = <0>; 4501 4502 apss_funnel0_in0: endpoint { 4503 remote-endpoint = <&etm0_out>; 4504 }; 4505 }; 4506 4507 port@1 { 4508 reg = <1>; 4509 4510 apss_funnel0_in1: endpoint { 4511 remote-endpoint = <&etm1_out>; 4512 }; 4513 }; 4514 4515 port@2 { 4516 reg = <2>; 4517 4518 apss_funnel0_in2: endpoint { 4519 remote-endpoint = <&etm2_out>; 4520 }; 4521 }; 4522 4523 port@3 { 4524 reg = <3>; 4525 4526 apss_funnel0_in3: endpoint { 4527 remote-endpoint = <&etm3_out>; 4528 }; 4529 }; 4530 4531 port@4 { 4532 reg = <4>; 4533 4534 apss_funnel0_in4: endpoint { 4535 remote-endpoint = <&etm4_out>; 4536 }; 4537 }; 4538 4539 port@5 { 4540 reg = <5>; 4541 4542 apss_funnel0_in5: endpoint { 4543 remote-endpoint = <&etm5_out>; 4544 }; 4545 }; 4546 4547 port@6 { 4548 reg = <6>; 4549 4550 apss_funnel0_in6: endpoint { 4551 remote-endpoint = <&etm6_out>; 4552 }; 4553 }; 4554 4555 port@7 { 4556 reg = <7>; 4557 4558 apss_funnel0_in7: endpoint { 4559 remote-endpoint = <&etm7_out>; 4560 }; 4561 }; 4562 }; 4563 4564 out-ports { 4565 port { 4566 apss_funnel0_out: endpoint { 4567 remote-endpoint = <&apss_funnel1_in0>; 4568 }; 4569 }; 4570 }; 4571 }; 4572 4573 funnel@6810000 { 4574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4575 reg = <0x0 0x06810000 0x0 0x1000>; 4576 4577 clocks = <&aoss_qmp>; 4578 clock-names = "apb_pclk"; 4579 4580 in-ports { 4581 #address-cells = <1>; 4582 #size-cells = <0>; 4583 4584 port@0 { 4585 reg = <0>; 4586 4587 apss_funnel1_in0: endpoint { 4588 remote-endpoint = <&apss_funnel0_out>; 4589 }; 4590 }; 4591 4592 port@3 { 4593 reg = <3>; 4594 4595 apss_funnel1_in3: endpoint { 4596 remote-endpoint = <&apss_tpda_out>; 4597 }; 4598 }; 4599 }; 4600 4601 out-ports { 4602 port { 4603 apss_funnel1_out: endpoint { 4604 remote-endpoint = <&funnel1_in4>; 4605 }; 4606 }; 4607 }; 4608 }; 4609 4610 cti@682b000 { 4611 compatible = "arm,coresight-cti", "arm,primecell"; 4612 reg = <0x0 0x0682b000 0x0 0x1000>; 4613 4614 clocks = <&aoss_qmp>; 4615 clock-names = "apb_pclk"; 4616 label = "cti_apss"; 4617 }; 4618 4619 tpdm@6860000 { 4620 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4621 reg = <0x0 0x06860000 0x0 0x1000>; 4622 4623 clocks = <&aoss_qmp>; 4624 clock-names = "apb_pclk"; 4625 label = "tpdm_actpm"; 4626 4627 qcom,cmb-element-bits = <64>; 4628 qcom,cmb-msrs-num = <32>; 4629 4630 out-ports { 4631 port { 4632 apss_tpdm3_out: endpoint { 4633 remote-endpoint = <&apss_tpda_in3>; 4634 }; 4635 }; 4636 }; 4637 }; 4638 4639 tpdm@6861000 { 4640 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4641 reg = <0x0 0x06861000 0x0 0x1000>; 4642 4643 clocks = <&aoss_qmp>; 4644 clock-names = "apb_pclk"; 4645 label = "tpdm_apss"; 4646 4647 qcom,dsb-element-bits = <32>; 4648 qcom,dsb-msrs-num = <32>; 4649 4650 out-ports { 4651 port { 4652 apss_tpdm4_out: endpoint { 4653 remote-endpoint = <&apss_tpda_in4>; 4654 }; 4655 }; 4656 }; 4657 }; 4658 4659 tpda@6863000 { 4660 compatible = "qcom,coresight-tpda", "arm,primecell"; 4661 reg = <0x0 0x06863000 0x0 0x1000>; 4662 4663 clocks = <&aoss_qmp>; 4664 clock-names = "apb_pclk"; 4665 4666 in-ports { 4667 #address-cells = <1>; 4668 #size-cells = <0>; 4669 4670 port@0 { 4671 reg = <0>; 4672 4673 apss_tpda_in0: endpoint { 4674 remote-endpoint = <&apss_tpdm0_out>; 4675 }; 4676 }; 4677 4678 port@1 { 4679 reg = <1>; 4680 4681 apss_tpda_in1: endpoint { 4682 remote-endpoint = <&apss_tpdm1_out>; 4683 }; 4684 }; 4685 4686 port@2 { 4687 reg = <2>; 4688 4689 apss_tpda_in2: endpoint { 4690 remote-endpoint = <&apss_tpdm2_out>; 4691 }; 4692 }; 4693 4694 port@3 { 4695 reg = <3>; 4696 4697 apss_tpda_in3: endpoint { 4698 remote-endpoint = <&apss_tpdm3_out>; 4699 }; 4700 }; 4701 4702 port@4 { 4703 reg = <4>; 4704 4705 apss_tpda_in4: endpoint { 4706 remote-endpoint = <&apss_tpdm4_out>; 4707 }; 4708 }; 4709 }; 4710 4711 out-ports { 4712 port { 4713 apss_tpda_out: endpoint { 4714 remote-endpoint = <&apss_funnel1_in3>; 4715 }; 4716 }; 4717 }; 4718 }; 4719 4720 tpdm@68a0000 { 4721 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4722 reg = <0x0 0x068a0000 0x0 0x1000>; 4723 4724 clocks = <&aoss_qmp>; 4725 clock-names = "apb_pclk"; 4726 label = "tpdm_llm_gold"; 4727 4728 qcom,cmb-element-bits = <32>; 4729 qcom,cmb-msrs-num = <32>; 4730 4731 out-ports { 4732 port { 4733 apss_tpdm1_out: endpoint { 4734 remote-endpoint = <&apss_tpda_in1>; 4735 }; 4736 }; 4737 }; 4738 }; 4739 4740 tpdm@68b0000 { 4741 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4742 reg = <0x0 0x068b0000 0x0 0x1000>; 4743 4744 clocks = <&aoss_qmp>; 4745 clock-names = "apb_pclk"; 4746 label = "tpdm_llm_silver"; 4747 4748 qcom,cmb-element-bits = <32>; 4749 qcom,cmb-msrs-num = <32>; 4750 4751 out-ports { 4752 port { 4753 apss_tpdm0_out: endpoint { 4754 remote-endpoint = <&apss_tpda_in0>; 4755 }; 4756 }; 4757 }; 4758 }; 4759 4760 tpdm@68c0000 { 4761 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4762 reg = <0x0 0x068c0000 0x0 0x1000>; 4763 4764 clocks = <&aoss_qmp>; 4765 clock-names = "apb_pclk"; 4766 label = "tpdm_ext_dsb"; 4767 4768 qcom,dsb-element-bits = <32>; 4769 qcom,dsb-msrs-num = <32>; 4770 4771 out-ports { 4772 port { 4773 apss_tpdm2_out: endpoint { 4774 remote-endpoint = <&apss_tpda_in2>; 4775 }; 4776 }; 4777 }; 4778 }; 4779 4780 cti@68e0000 { 4781 compatible = "arm,coresight-cti", "arm,primecell"; 4782 reg = <0x0 0x068e0000 0x0 0x1000>; 4783 4784 clocks = <&aoss_qmp>; 4785 clock-names = "apb_pclk"; 4786 label = "cti_llm_gold"; 4787 }; 4788 4789 cti@68f0000 { 4790 compatible = "arm,coresight-cti", "arm,primecell"; 4791 reg = <0x0 0x068f0000 0x0 0x1000>; 4792 4793 clocks = <&aoss_qmp>; 4794 clock-names = "apb_pclk"; 4795 label = "cti_llm_silver"; 4796 }; 4797 4798 cti@6900000 { 4799 compatible = "arm,coresight-cti", "arm,primecell"; 4800 reg = <0x0 0x06900000 0x0 0x1000>; 4801 4802 clocks = <&aoss_qmp>; 4803 clock-names = "apb_pclk"; 4804 label = "cti_ext_dsb"; 4805 }; 4806 4807 sdhc_1: mmc@87c4000 { 4808 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4809 reg = <0x0 0x087c4000 0x0 0x1000>, 4810 <0x0 0x087c5000 0x0 0x1000>; 4811 reg-names = "hc", 4812 "cqhci"; 4813 4814 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4815 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4816 interrupt-names = "hc_irq", 4817 "pwr_irq"; 4818 4819 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4820 <&gcc GCC_SDCC1_APPS_CLK>, 4821 <&rpmhcc RPMH_CXO_CLK>; 4822 clock-names = "iface", 4823 "core", 4824 "xo"; 4825 4826 resets = <&gcc GCC_SDCC1_BCR>; 4827 4828 power-domains = <&rpmhpd RPMHPD_CX>; 4829 operating-points-v2 = <&sdhc1_opp_table>; 4830 iommus = <&apps_smmu 0x0 0x0>; 4831 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4832 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4833 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4834 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4835 interconnect-names = "sdhc-ddr", 4836 "cpu-sdhc"; 4837 4838 pinctrl-names = "default", "sleep"; 4839 pinctrl-0 = <&sdc1_state_on>; 4840 pinctrl-1 = <&sdc1_state_off>; 4841 4842 qcom,dll-config = <0x000f64ee>; 4843 qcom,ddr-config = <0x80040868>; 4844 bus-width = <8>; 4845 supports-cqe; 4846 dma-coherent; 4847 4848 mmc-ddr-1_8v; 4849 mmc-hs200-1_8v; 4850 mmc-hs400-1_8v; 4851 mmc-hs400-enhanced-strobe; 4852 4853 status = "disabled"; 4854 4855 sdhc1_opp_table: opp-table { 4856 compatible = "operating-points-v2"; 4857 4858 opp-50000000 { 4859 opp-hz = /bits/ 64 <50000000>; 4860 required-opps = <&rpmhpd_opp_low_svs>; 4861 }; 4862 4863 opp-100000000 { 4864 opp-hz = /bits/ 64 <100000000>; 4865 required-opps = <&rpmhpd_opp_svs>; 4866 }; 4867 4868 opp-200000000 { 4869 opp-hz = /bits/ 64 <200000000>; 4870 required-opps = <&rpmhpd_opp_svs_l1>; 4871 }; 4872 4873 opp-384000000 { 4874 opp-hz = /bits/ 64 <384000000>; 4875 required-opps = <&rpmhpd_opp_nom>; 4876 }; 4877 }; 4878 }; 4879 4880 usb_1_hsphy: phy@8904000 { 4881 compatible = "qcom,qcs8300-usb-hs-phy", 4882 "qcom,usb-snps-hs-7nm-phy"; 4883 reg = <0x0 0x08904000 0x0 0x400>; 4884 4885 clocks = <&rpmhcc RPMH_CXO_CLK>; 4886 clock-names = "ref"; 4887 4888 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4889 4890 #phy-cells = <0>; 4891 4892 status = "disabled"; 4893 }; 4894 4895 usb_2_hsphy: phy@8906000 { 4896 compatible = "qcom,qcs8300-usb-hs-phy", 4897 "qcom,usb-snps-hs-7nm-phy"; 4898 reg = <0x0 0x08906000 0x0 0x400>; 4899 4900 clocks = <&rpmhcc RPMH_CXO_CLK>; 4901 clock-names = "ref"; 4902 4903 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4904 4905 #phy-cells = <0>; 4906 4907 status = "disabled"; 4908 }; 4909 4910 usb_qmpphy: phy@8907000 { 4911 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4912 reg = <0x0 0x08907000 0x0 0x2000>; 4913 4914 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4915 <&gcc GCC_USB_CLKREF_EN>, 4916 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4917 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4918 clock-names = "aux", 4919 "ref", 4920 "com_aux", 4921 "pipe"; 4922 4923 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4924 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4925 reset-names = "phy", "phy_phy"; 4926 4927 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4928 4929 #clock-cells = <0>; 4930 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4931 4932 #phy-cells = <0>; 4933 4934 status = "disabled"; 4935 }; 4936 4937 serdes0: phy@8909000 { 4938 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4939 reg = <0x0 0x08909000 0x0 0x00000e10>; 4940 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4941 clock-names = "sgmi_ref"; 4942 #phy-cells = <0>; 4943 status = "disabled"; 4944 }; 4945 4946 refgen: regulator@891c000 { 4947 compatible = "qcom,qcs8300-refgen-regulator", 4948 "qcom,sm8250-refgen-regulator"; 4949 reg = <0x0 0x0891c000 0x0 0x84>; 4950 }; 4951 4952 gpu: gpu@3d00000 { 4953 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4954 reg = <0x0 0x03d00000 0x0 0x40000>, 4955 <0x0 0x03d9e000 0x0 0x1000>, 4956 <0x0 0x03d61000 0x0 0x800>; 4957 reg-names = "kgsl_3d0_reg_memory", 4958 "cx_mem", 4959 "cx_dbgc"; 4960 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4961 iommus = <&adreno_smmu 0 0xc00>, 4962 <&adreno_smmu 1 0xc00>; 4963 operating-points-v2 = <&gpu_opp_table>; 4964 qcom,gmu = <&gmu>; 4965 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4966 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4967 interconnect-names = "gfx-mem"; 4968 #cooling-cells = <2>; 4969 4970 nvmem-cells = <&gpu_speed_bin>; 4971 nvmem-cell-names = "speed_bin"; 4972 4973 status = "disabled"; 4974 4975 gpu_zap_shader: zap-shader { 4976 memory-region = <&gpu_microcode_mem>; 4977 }; 4978 4979 gpu_opp_table: opp-table { 4980 compatible = "operating-points-v2"; 4981 4982 opp-877000000 { 4983 opp-hz = /bits/ 64 <877000000>; 4984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4985 opp-peak-kBps = <12484375>; 4986 opp-supported-hw = <0x1>; 4987 }; 4988 4989 opp-780000000 { 4990 opp-hz = /bits/ 64 <780000000>; 4991 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4992 opp-peak-kBps = <10687500>; 4993 opp-supported-hw = <0x1>; 4994 }; 4995 4996 opp-599000000 { 4997 opp-hz = /bits/ 64 <599000000>; 4998 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4999 opp-peak-kBps = <8171875>; 5000 opp-supported-hw = <0x3>; 5001 }; 5002 5003 opp-479000000 { 5004 opp-hz = /bits/ 64 <479000000>; 5005 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5006 opp-peak-kBps = <5285156>; 5007 opp-supported-hw = <0x3>; 5008 }; 5009 }; 5010 }; 5011 5012 gmu: gmu@3d6a000 { 5013 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 5014 reg = <0x0 0x03d6a000 0x0 0x34000>, 5015 <0x0 0x03de0000 0x0 0x10000>, 5016 <0x0 0x0b290000 0x0 0x10000>; 5017 reg-names = "gmu", "rscc", "gmu_pdc"; 5018 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 5020 interrupt-names = "hfi", "gmu"; 5021 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 5022 <&gpucc GPU_CC_CXO_CLK>, 5023 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 5024 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5025 <&gpucc GPU_CC_AHB_CLK>, 5026 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 5027 clock-names = "gmu", 5028 "cxo", 5029 "axi", 5030 "memnoc", 5031 "ahb", 5032 "hub"; 5033 power-domains = <&gpucc GPU_CC_CX_GDSC>, 5034 <&gpucc GPU_CC_GX_GDSC>; 5035 power-domain-names = "cx", 5036 "gx"; 5037 iommus = <&adreno_smmu 5 0xc00>; 5038 operating-points-v2 = <&gmu_opp_table>; 5039 5040 gmu_opp_table: opp-table { 5041 compatible = "operating-points-v2"; 5042 5043 opp-500000000 { 5044 opp-hz = /bits/ 64 <500000000>; 5045 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5046 }; 5047 }; 5048 }; 5049 5050 gpucc: clock-controller@3d90000 { 5051 compatible = "qcom,qcs8300-gpucc"; 5052 reg = <0x0 0x03d90000 0x0 0xa000>; 5053 clocks = <&rpmhcc RPMH_CXO_CLK>, 5054 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 5055 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 5056 clock-names = "bi_tcxo", 5057 "gcc_gpu_gpll0_clk_src", 5058 "gcc_gpu_gpll0_div_clk_src"; 5059 #clock-cells = <1>; 5060 #reset-cells = <1>; 5061 #power-domain-cells = <1>; 5062 }; 5063 5064 adreno_smmu: iommu@3da0000 { 5065 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 5066 "qcom,smmu-500", "arm,mmu-500"; 5067 reg = <0x0 0x3da0000 0x0 0x20000>; 5068 #iommu-cells = <2>; 5069 #global-interrupts = <2>; 5070 5071 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 5073 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 5074 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 5075 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 5076 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 5077 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 5078 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 5079 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 5080 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 5083 5084 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5085 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 5086 <&gpucc GPU_CC_AHB_CLK>, 5087 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 5088 <&gpucc GPU_CC_CX_GMU_CLK>, 5089 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 5090 <&gpucc GPU_CC_HUB_AON_CLK>; 5091 5092 clock-names = "gcc_gpu_memnoc_gfx_clk", 5093 "gcc_gpu_snoc_dvm_gfx_clk", 5094 "gpu_cc_ahb_clk", 5095 "gpu_cc_hlos1_vote_gpu_smmu_clk", 5096 "gpu_cc_cx_gmu_clk", 5097 "gpu_cc_hub_cx_int_clk", 5098 "gpu_cc_hub_aon_clk"; 5099 power-domains = <&gpucc GPU_CC_CX_GDSC>; 5100 dma-coherent; 5101 }; 5102 5103 pmu@9091000 { 5104 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5105 reg = <0x0 0x9091000 0x0 0x1000>; 5106 5107 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 5108 5109 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5110 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5111 5112 operating-points-v2 = <&llcc_bwmon_opp_table>; 5113 5114 llcc_bwmon_opp_table: opp-table { 5115 compatible = "operating-points-v2"; 5116 5117 opp-0 { 5118 opp-peak-kBps = <762000>; 5119 }; 5120 5121 opp-1 { 5122 opp-peak-kBps = <1720000>; 5123 }; 5124 5125 opp-2 { 5126 opp-peak-kBps = <2086000>; 5127 }; 5128 5129 opp-3 { 5130 opp-peak-kBps = <2601000>; 5131 }; 5132 5133 opp-4 { 5134 opp-peak-kBps = <2929000>; 5135 }; 5136 5137 opp-5 { 5138 opp-peak-kBps = <5931000>; 5139 }; 5140 5141 opp-6 { 5142 opp-peak-kBps = <6515000>; 5143 }; 5144 5145 opp-7 { 5146 opp-peak-kBps = <7984000>; 5147 }; 5148 5149 opp-8 { 5150 opp-peak-kBps = <10437000>; 5151 }; 5152 5153 opp-9 { 5154 opp-peak-kBps = <12195000>; 5155 }; 5156 }; 5157 }; 5158 5159 pmu@90b5400 { 5160 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5161 reg = <0x0 0x90b5400 0x0 0x600>; 5162 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5163 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5164 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5165 5166 operating-points-v2 = <&cpu_bwmon_opp_table>; 5167 5168 cpu_bwmon_opp_table: opp-table { 5169 compatible = "operating-points-v2"; 5170 5171 opp-0 { 5172 opp-peak-kBps = <9155000>; 5173 }; 5174 5175 opp-1 { 5176 opp-peak-kBps = <12298000>; 5177 }; 5178 5179 opp-2 { 5180 opp-peak-kBps = <14236000>; 5181 }; 5182 5183 opp-3 { 5184 opp-peak-kBps = <16265000>; 5185 }; 5186 }; 5187 }; 5188 5189 pmu@90b6400 { 5190 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5191 reg = <0x0 0x90b6400 0x0 0x600>; 5192 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5193 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5194 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5195 5196 operating-points-v2 = <&cpu_bwmon_opp_table>; 5197 }; 5198 5199 dc_noc: interconnect@90e0000 { 5200 compatible = "qcom,qcs8300-dc-noc"; 5201 reg = <0x0 0x090e0000 0x0 0x5080>; 5202 #interconnect-cells = <2>; 5203 qcom,bcm-voters = <&apps_bcm_voter>; 5204 }; 5205 5206 gem_noc: interconnect@9100000 { 5207 compatible = "qcom,qcs8300-gem-noc"; 5208 reg = <0x0 0x9100000 0x0 0xf7080>; 5209 #interconnect-cells = <2>; 5210 qcom,bcm-voters = <&apps_bcm_voter>; 5211 clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; 5212 }; 5213 5214 llcc: system-cache-controller@9200000 { 5215 compatible = "qcom,qcs8300-llcc"; 5216 reg = <0x0 0x09200000 0x0 0x80000>, 5217 <0x0 0x09300000 0x0 0x80000>, 5218 <0x0 0x09400000 0x0 0x80000>, 5219 <0x0 0x09500000 0x0 0x80000>, 5220 <0x0 0x09a00000 0x0 0x80000>; 5221 reg-names = "llcc0_base", 5222 "llcc1_base", 5223 "llcc2_base", 5224 "llcc3_base", 5225 "llcc_broadcast_base"; 5226 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 5227 }; 5228 5229 usb_1: usb@a600000 { 5230 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5231 reg = <0x0 0x0a600000 0x0 0xfc100>; 5232 5233 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5234 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5235 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5236 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5237 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 5238 clock-names = "cfg_noc", 5239 "core", 5240 "iface", 5241 "sleep", 5242 "mock_utmi"; 5243 5244 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5245 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5246 assigned-clock-rates = <19200000>, <200000000>; 5247 5248 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 5249 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 5250 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 5251 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5252 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5253 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 5254 interrupt-names = "dwc_usb3", 5255 "pwr_event", 5256 "hs_phy_irq", 5257 "dp_hs_phy_irq", 5258 "dm_hs_phy_irq", 5259 "ss_phy_irq"; 5260 5261 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5262 required-opps = <&rpmhpd_opp_nom>; 5263 5264 resets = <&gcc GCC_USB30_PRIM_BCR>; 5265 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5266 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5267 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5268 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 5269 interconnect-names = "usb-ddr", "apps-usb"; 5270 5271 iommus = <&apps_smmu 0x80 0x0>; 5272 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5273 phy-names = "usb2-phy", "usb3-phy"; 5274 snps,dis_enblslpm_quirk; 5275 snps,dis-u1-entry-quirk; 5276 snps,dis-u2-entry-quirk; 5277 snps,dis_u2_susphy_quirk; 5278 snps,dis_u3_susphy_quirk; 5279 5280 usb-role-switch; 5281 wakeup-source; 5282 5283 status = "disabled"; 5284 5285 ports { 5286 #address-cells = <1>; 5287 #size-cells = <0>; 5288 5289 port@0 { 5290 reg = <0>; 5291 5292 usb_1_dwc3_hs: endpoint { 5293 }; 5294 }; 5295 5296 port@1 { 5297 reg = <1>; 5298 5299 usb_1_dwc3_ss: endpoint { 5300 }; 5301 }; 5302 }; 5303 }; 5304 5305 usb_2: usb@a400000 { 5306 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5307 reg = <0x0 0x0a400000 0x0 0xfc100>; 5308 5309 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5310 <&gcc GCC_USB20_MASTER_CLK>, 5311 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5312 <&gcc GCC_USB20_SLEEP_CLK>, 5313 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5314 clock-names = "cfg_noc", 5315 "core", 5316 "iface", 5317 "sleep", 5318 "mock_utmi"; 5319 5320 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5321 <&gcc GCC_USB20_MASTER_CLK>; 5322 assigned-clock-rates = <19200000>, <120000000>; 5323 5324 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 5325 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 5326 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 5327 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 5328 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 5329 interrupt-names = "dwc_usb3", 5330 "pwr_event", 5331 "hs_phy_irq", 5332 "dp_hs_phy_irq", 5333 "dm_hs_phy_irq"; 5334 5335 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5336 required-opps = <&rpmhpd_opp_nom>; 5337 5338 resets = <&gcc GCC_USB20_PRIM_BCR>; 5339 5340 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5341 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5343 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 5344 interconnect-names = "usb-ddr", "apps-usb"; 5345 5346 iommus = <&apps_smmu 0x20 0x0>; 5347 5348 phys = <&usb_2_hsphy>; 5349 phy-names = "usb2-phy"; 5350 maximum-speed = "high-speed"; 5351 5352 snps,dis-u1-entry-quirk; 5353 snps,dis-u2-entry-quirk; 5354 snps,dis_u2_susphy_quirk; 5355 snps,dis_u3_susphy_quirk; 5356 snps,dis_enblslpm_quirk; 5357 5358 qcom,select-utmi-as-pipe-clk; 5359 wakeup-source; 5360 5361 usb-role-switch; 5362 5363 status = "disabled"; 5364 5365 port { 5366 usb_2_dwc3_hs: endpoint { 5367 }; 5368 }; 5369 }; 5370 5371 iris: video-codec@aa00000 { 5372 compatible = "qcom,qcs8300-iris"; 5373 5374 reg = <0x0 0x0aa00000 0x0 0xf0000>; 5375 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5376 5377 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5378 <&videocc VIDEO_CC_MVS0_GDSC>, 5379 <&rpmhpd RPMHPD_MX>, 5380 <&rpmhpd RPMHPD_MMCX>; 5381 power-domain-names = "venus", 5382 "vcodec0", 5383 "mxc", 5384 "mmcx"; 5385 5386 operating-points-v2 = <&iris_opp_table>; 5387 5388 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5389 <&videocc VIDEO_CC_MVS0C_CLK>, 5390 <&videocc VIDEO_CC_MVS0_CLK>; 5391 clock-names = "iface", 5392 "core", 5393 "vcodec0_core"; 5394 5395 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5396 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5397 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 5398 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5399 interconnect-names = "cpu-cfg", 5400 "video-mem"; 5401 5402 memory-region = <&video_mem>; 5403 5404 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5405 reset-names = "bus"; 5406 5407 iommus = <&apps_smmu 0x0880 0x0400>, 5408 <&apps_smmu 0x0887 0x0400>; 5409 dma-coherent; 5410 5411 status = "disabled"; 5412 5413 iris_opp_table: opp-table { 5414 compatible = "operating-points-v2"; 5415 5416 opp-366000000 { 5417 opp-hz = /bits/ 64 <366000000>; 5418 required-opps = <&rpmhpd_opp_svs_l1>, 5419 <&rpmhpd_opp_svs_l1>; 5420 }; 5421 5422 opp-444000000 { 5423 opp-hz = /bits/ 64 <444000000>; 5424 required-opps = <&rpmhpd_opp_svs_l1>, 5425 <&rpmhpd_opp_nom>; 5426 }; 5427 5428 opp-533000000 { 5429 opp-hz = /bits/ 64 <533000000>; 5430 required-opps = <&rpmhpd_opp_nom>, 5431 <&rpmhpd_opp_turbo>; 5432 }; 5433 5434 opp-560000000 { 5435 opp-hz = /bits/ 64 <560000000>; 5436 required-opps = <&rpmhpd_opp_nom>, 5437 <&rpmhpd_opp_turbo_l1>; 5438 }; 5439 }; 5440 }; 5441 5442 videocc: clock-controller@abf0000 { 5443 compatible = "qcom,qcs8300-videocc"; 5444 reg = <0x0 0x0abf0000 0x0 0x10000>; 5445 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5446 <&rpmhcc RPMH_CXO_CLK>, 5447 <&rpmhcc RPMH_CXO_CLK_A>, 5448 <&sleep_clk>; 5449 power-domains = <&rpmhpd RPMHPD_MMCX>; 5450 #clock-cells = <1>; 5451 #reset-cells = <1>; 5452 #power-domain-cells = <1>; 5453 }; 5454 5455 cci0: cci@ac13000 { 5456 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5457 reg = <0x0 0x0ac13000 0x0 0x1000>; 5458 5459 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5460 5461 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5462 <&camcc CAM_CC_CCI_0_CLK>; 5463 clock-names = "ahb", 5464 "cci"; 5465 5466 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5467 5468 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5469 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5470 pinctrl-names = "default", "sleep"; 5471 5472 #address-cells = <1>; 5473 #size-cells = <0>; 5474 5475 status = "disabled"; 5476 5477 cci0_i2c0: i2c-bus@0 { 5478 reg = <0>; 5479 clock-frequency = <400000>; 5480 #address-cells = <1>; 5481 #size-cells = <0>; 5482 }; 5483 5484 cci0_i2c1: i2c-bus@1 { 5485 reg = <1>; 5486 clock-frequency = <400000>; 5487 #address-cells = <1>; 5488 #size-cells = <0>; 5489 }; 5490 }; 5491 5492 cci1: cci@ac14000 { 5493 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5494 reg = <0x0 0x0ac14000 0x0 0x1000>; 5495 5496 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5497 5498 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5499 <&camcc CAM_CC_CCI_1_CLK>; 5500 clock-names = "ahb", 5501 "cci"; 5502 5503 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5504 5505 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5506 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5507 pinctrl-names = "default", "sleep"; 5508 5509 #address-cells = <1>; 5510 #size-cells = <0>; 5511 5512 status = "disabled"; 5513 5514 cci1_i2c0: i2c-bus@0 { 5515 reg = <0>; 5516 clock-frequency = <400000>; 5517 #address-cells = <1>; 5518 #size-cells = <0>; 5519 }; 5520 5521 cci1_i2c1: i2c-bus@1 { 5522 reg = <1>; 5523 clock-frequency = <400000>; 5524 #address-cells = <1>; 5525 #size-cells = <0>; 5526 }; 5527 }; 5528 5529 cci2: cci@ac15000 { 5530 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5531 reg = <0x0 0x0ac15000 0x0 0x1000>; 5532 5533 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 5534 5535 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5536 <&camcc CAM_CC_CCI_2_CLK>; 5537 clock-names = "ahb", 5538 "cci"; 5539 5540 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5541 5542 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5543 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5544 pinctrl-names = "default", "sleep"; 5545 5546 #address-cells = <1>; 5547 #size-cells = <0>; 5548 5549 status = "disabled"; 5550 5551 cci2_i2c0: i2c-bus@0 { 5552 reg = <0>; 5553 clock-frequency = <400000>; 5554 #address-cells = <1>; 5555 #size-cells = <0>; 5556 }; 5557 5558 cci2_i2c1: i2c-bus@1 { 5559 reg = <1>; 5560 clock-frequency = <400000>; 5561 #address-cells = <1>; 5562 #size-cells = <0>; 5563 }; 5564 }; 5565 5566 camss: isp@ac78000 { 5567 compatible = "qcom,qcs8300-camss"; 5568 5569 reg = <0x0 0xac78000 0x0 0x1000>, 5570 <0x0 0xac7a000 0x0 0xf00>, 5571 <0x0 0xac7c000 0x0 0xf00>, 5572 <0x0 0xac84000 0x0 0xf00>, 5573 <0x0 0xac88000 0x0 0xf00>, 5574 <0x0 0xac8c000 0x0 0xf00>, 5575 <0x0 0xac90000 0x0 0xf00>, 5576 <0x0 0xac94000 0x0 0xf00>, 5577 <0x0 0xac9c000 0x0 0x2000>, 5578 <0x0 0xac9e000 0x0 0x2000>, 5579 <0x0 0xaca0000 0x0 0x2000>, 5580 <0x0 0xacac000 0x0 0x400>, 5581 <0x0 0xacad000 0x0 0x400>, 5582 <0x0 0xacae000 0x0 0x400>, 5583 <0x0 0xac4d000 0x0 0xf000>, 5584 <0x0 0xac60000 0x0 0xf000>, 5585 <0x0 0xac85000 0x0 0xd00>, 5586 <0x0 0xac89000 0x0 0xd00>, 5587 <0x0 0xac8d000 0x0 0xd00>, 5588 <0x0 0xac91000 0x0 0xd00>, 5589 <0x0 0xac95000 0x0 0xd00>; 5590 reg-names = "csid_wrapper", 5591 "csid0", 5592 "csid1", 5593 "csid_lite0", 5594 "csid_lite1", 5595 "csid_lite2", 5596 "csid_lite3", 5597 "csid_lite4", 5598 "csiphy0", 5599 "csiphy1", 5600 "csiphy2", 5601 "tpg0", 5602 "tpg1", 5603 "tpg2", 5604 "vfe0", 5605 "vfe1", 5606 "vfe_lite0", 5607 "vfe_lite1", 5608 "vfe_lite2", 5609 "vfe_lite3", 5610 "vfe_lite4"; 5611 5612 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5613 <&camcc CAM_CC_CORE_AHB_CLK>, 5614 <&camcc CAM_CC_CPAS_AHB_CLK>, 5615 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5616 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5617 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5618 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5619 <&camcc CAM_CC_CSID_CLK>, 5620 <&camcc CAM_CC_CSIPHY0_CLK>, 5621 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5622 <&camcc CAM_CC_CSIPHY1_CLK>, 5623 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5624 <&camcc CAM_CC_CSIPHY2_CLK>, 5625 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5626 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5627 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5628 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5629 <&camcc CAM_CC_ICP_AHB_CLK>, 5630 <&camcc CAM_CC_IFE_0_CLK>, 5631 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5632 <&camcc CAM_CC_IFE_1_CLK>, 5633 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5634 <&camcc CAM_CC_IFE_LITE_CLK>, 5635 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5636 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5637 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5638 clock-names = "camnoc_axi", 5639 "core_ahb", 5640 "cpas_ahb", 5641 "cpas_fast_ahb_clk", 5642 "cpas_vfe_lite", 5643 "cpas_vfe0", 5644 "cpas_vfe1", 5645 "csid", 5646 "csiphy0", 5647 "csiphy0_timer", 5648 "csiphy1", 5649 "csiphy1_timer", 5650 "csiphy2", 5651 "csiphy2_timer", 5652 "csiphy_rx", 5653 "gcc_axi_hf", 5654 "gcc_axi_sf", 5655 "icp_ahb", 5656 "vfe0", 5657 "vfe0_fast_ahb", 5658 "vfe1", 5659 "vfe1_fast_ahb", 5660 "vfe_lite", 5661 "vfe_lite_ahb", 5662 "vfe_lite_cphy_rx", 5663 "vfe_lite_csid"; 5664 5665 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5666 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5667 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5668 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5669 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5670 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5671 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5672 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5673 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5674 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5675 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5676 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5677 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5678 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5679 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5680 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5681 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5682 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5683 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5684 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5685 interrupt-names = "csid0", 5686 "csid1", 5687 "csid_lite0", 5688 "csid_lite1", 5689 "csid_lite2", 5690 "csid_lite3", 5691 "csid_lite4", 5692 "csiphy0", 5693 "csiphy1", 5694 "csiphy2", 5695 "tpg0", 5696 "tpg1", 5697 "tpg2", 5698 "vfe0", 5699 "vfe1", 5700 "vfe_lite0", 5701 "vfe_lite1", 5702 "vfe_lite2", 5703 "vfe_lite3", 5704 "vfe_lite4"; 5705 5706 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5707 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5708 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5709 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5710 interconnect-names = "ahb", 5711 "hf_0"; 5712 5713 iommus = <&apps_smmu 0x2400 0x20>; 5714 5715 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5716 power-domain-names = "top"; 5717 5718 status = "disabled"; 5719 5720 ports { 5721 #address-cells = <1>; 5722 #size-cells = <0>; 5723 5724 port@0 { 5725 reg = <0>; 5726 }; 5727 5728 port@1 { 5729 reg = <1>; 5730 }; 5731 5732 port@2 { 5733 reg = <2>; 5734 }; 5735 }; 5736 }; 5737 5738 camcc: clock-controller@ade0000 { 5739 compatible = "qcom,qcs8300-camcc"; 5740 reg = <0x0 0x0ade0000 0x0 0x20000>; 5741 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5742 <&rpmhcc RPMH_CXO_CLK>, 5743 <&rpmhcc RPMH_CXO_CLK_A>, 5744 <&sleep_clk>; 5745 power-domains = <&rpmhpd RPMHPD_MMCX>; 5746 #clock-cells = <1>; 5747 #reset-cells = <1>; 5748 #power-domain-cells = <1>; 5749 }; 5750 5751 mdss: display-subsystem@ae00000 { 5752 compatible = "qcom,qcs8300-mdss"; 5753 reg = <0x0 0x0ae00000 0x0 0x1000>; 5754 reg-names = "mdss"; 5755 5756 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5757 5758 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5759 <&gcc GCC_DISP_HF_AXI_CLK>, 5760 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; 5761 5762 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; 5763 5764 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5766 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5768 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5769 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5770 interconnect-names = "mdp0-mem", 5771 "mdp1-mem", 5772 "cpu-cfg"; 5773 5774 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; 5775 5776 iommus = <&apps_smmu 0x1000 0x402>; 5777 5778 interrupt-controller; 5779 #interrupt-cells = <1>; 5780 5781 #address-cells = <2>; 5782 #size-cells = <2>; 5783 ranges; 5784 5785 status = "disabled"; 5786 5787 mdss_mdp: display-controller@ae01000 { 5788 compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; 5789 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5790 <0x0 0x0aeb0000 0x0 0x2008>; 5791 reg-names = "mdp", "vbif"; 5792 5793 interrupts-extended = <&mdss 0>; 5794 5795 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5796 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5797 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5798 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, 5799 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5800 clock-names = "nrt_bus", 5801 "iface", 5802 "lut", 5803 "core", 5804 "vsync"; 5805 5806 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5807 assigned-clock-rates = <19200000>; 5808 5809 operating-points-v2 = <&mdp_opp_table>; 5810 power-domains = <&rpmhpd RPMHPD_MMCX>; 5811 5812 ports { 5813 #address-cells = <1>; 5814 #size-cells = <0>; 5815 5816 port@0 { 5817 reg = <0>; 5818 5819 dpu_intf0_out: endpoint { 5820 5821 remote-endpoint = <&mdss_dp0_in>; 5822 }; 5823 }; 5824 5825 port@1 { 5826 reg = <1>; 5827 5828 dpu_intf1_out: endpoint { 5829 5830 remote-endpoint = <&mdss_dsi0_in>; 5831 }; 5832 }; 5833 }; 5834 5835 mdp_opp_table: opp-table { 5836 compatible = "operating-points-v2"; 5837 5838 opp-375000000 { 5839 opp-hz = /bits/ 64 <375000000>; 5840 required-opps = <&rpmhpd_opp_svs_l1>; 5841 }; 5842 5843 opp-500000000 { 5844 opp-hz = /bits/ 64 <500000000>; 5845 required-opps = <&rpmhpd_opp_nom>; 5846 }; 5847 5848 opp-575000000 { 5849 opp-hz = /bits/ 64 <575000000>; 5850 required-opps = <&rpmhpd_opp_turbo>; 5851 }; 5852 5853 opp-650000000 { 5854 opp-hz = /bits/ 64 <650000000>; 5855 required-opps = <&rpmhpd_opp_turbo_l1>; 5856 }; 5857 }; 5858 }; 5859 5860 mdss_dsi0: dsi@ae94000 { 5861 compatible = "qcom,qcs8300-dsi-ctrl", 5862 "qcom,sa8775p-dsi-ctrl", 5863 "qcom,mdss-dsi-ctrl"; 5864 reg = <0x0 0x0ae94000 0x0 0x400>; 5865 reg-names = "dsi_ctrl"; 5866 5867 interrupt-parent = <&mdss>; 5868 interrupts = <4>; 5869 5870 clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5871 <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5872 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5873 <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, 5874 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5875 <&gcc GCC_DISP_HF_AXI_CLK>; 5876 clock-names = "byte", 5877 "byte_intf", 5878 "pixel", 5879 "core", 5880 "iface", 5881 "bus"; 5882 5883 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5884 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5885 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5886 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5887 5888 phys = <&mdss_dsi0_phy>; 5889 5890 operating-points-v2 = <&mdss_dsi_opp_table>; 5891 power-domains = <&rpmhpd RPMHPD_MMCX>; 5892 5893 refgen-supply = <&refgen>; 5894 5895 #address-cells = <1>; 5896 #size-cells = <0>; 5897 5898 status = "disabled"; 5899 5900 ports { 5901 #address-cells = <1>; 5902 #size-cells = <0>; 5903 5904 port@0 { 5905 reg = <0>; 5906 5907 mdss_dsi0_in: endpoint { 5908 5909 remote-endpoint = <&dpu_intf1_out>; 5910 }; 5911 }; 5912 5913 port@1 { 5914 reg = <1>; 5915 5916 mdss_dsi0_out: endpoint { 5917 }; 5918 }; 5919 }; 5920 5921 mdss_dsi_opp_table: opp-table { 5922 compatible = "operating-points-v2"; 5923 5924 opp-358000000 { 5925 opp-hz = /bits/ 64 <358000000>; 5926 required-opps = <&rpmhpd_opp_svs_l1>; 5927 }; 5928 }; 5929 }; 5930 5931 mdss_dsi0_phy: phy@ae94400 { 5932 compatible = "qcom,qcs8300-dsi-phy-5nm", 5933 "qcom,sa8775p-dsi-phy-5nm"; 5934 reg = <0x0 0x0ae94400 0x0 0x200>, 5935 <0x0 0x0ae94600 0x0 0x280>, 5936 <0x0 0x0ae94900 0x0 0x280>; 5937 reg-names = "dsi_phy", 5938 "dsi_phy_lane", 5939 "dsi_pll"; 5940 5941 #clock-cells = <1>; 5942 #phy-cells = <0>; 5943 5944 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5945 <&rpmhcc RPMH_CXO_CLK>; 5946 clock-names = "iface", 5947 "ref"; 5948 5949 status = "disabled"; 5950 }; 5951 5952 mdss_dp0_phy: phy@aec2a00 { 5953 compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; 5954 5955 reg = <0x0 0x0aec2a00 0x0 0x19c>, 5956 <0x0 0x0aec2200 0x0 0xec>, 5957 <0x0 0x0aec2600 0x0 0xec>, 5958 <0x0 0x0aec2000 0x0 0x1c8>; 5959 5960 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5961 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; 5962 clock-names = "aux", 5963 "cfg_ahb"; 5964 5965 power-domains = <&rpmhpd RPMHPD_MX>; 5966 5967 #clock-cells = <1>; 5968 #phy-cells = <0>; 5969 5970 status = "disabled"; 5971 }; 5972 5973 mdss_dp0: displayport-controller@af54000 { 5974 compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; 5975 5976 reg = <0x0 0x0af54000 0x0 0x200>, 5977 <0x0 0x0af54200 0x0 0x200>, 5978 <0x0 0x0af55000 0x0 0xc00>, 5979 <0x0 0x0af56000 0x0 0x09c>, 5980 <0x0 0x0af57000 0x0 0x09c>, 5981 <0x0 0x0af58000 0x0 0x09c>, 5982 <0x0 0x0af59000 0x0 0x09c>, 5983 <0x0 0x0af5a000 0x0 0x23c>, 5984 <0x0 0x0af5b000 0x0 0x23c>; 5985 5986 interrupts-extended = <&mdss 12>; 5987 5988 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5989 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5990 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5991 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5992 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5993 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5994 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5995 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5996 clock-names = "core_iface", 5997 "core_aux", 5998 "ctrl_link", 5999 "ctrl_link_iface", 6000 "stream_pixel", 6001 "stream_1_pixel", 6002 "stream_2_pixel", 6003 "stream_3_pixel"; 6004 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 6005 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 6006 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 6007 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 6008 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 6009 assigned-clock-parents = <&mdss_dp0_phy 0>, 6010 <&mdss_dp0_phy 1>, 6011 <&mdss_dp0_phy 1>, 6012 <&mdss_dp0_phy 1>, 6013 <&mdss_dp0_phy 1>; 6014 phys = <&mdss_dp0_phy>; 6015 phy-names = "dp"; 6016 6017 operating-points-v2 = <&dp_opp_table>; 6018 power-domains = <&rpmhpd RPMHPD_MMCX>; 6019 6020 #sound-dai-cells = <0>; 6021 6022 status = "disabled"; 6023 6024 ports { 6025 #address-cells = <1>; 6026 #size-cells = <0>; 6027 6028 port@0 { 6029 reg = <0>; 6030 6031 mdss_dp0_in: endpoint { 6032 remote-endpoint = <&dpu_intf0_out>; 6033 }; 6034 }; 6035 6036 port@1 { 6037 reg = <1>; 6038 6039 mdss_dp0_out: endpoint { }; 6040 }; 6041 }; 6042 6043 dp_opp_table: opp-table { 6044 compatible = "operating-points-v2"; 6045 6046 opp-162000000 { 6047 opp-hz = /bits/ 64 <162000000>; 6048 required-opps = <&rpmhpd_opp_low_svs>; 6049 }; 6050 6051 opp-270000000 { 6052 opp-hz = /bits/ 64 <270000000>; 6053 required-opps = <&rpmhpd_opp_svs>; 6054 }; 6055 6056 opp-540000000 { 6057 opp-hz = /bits/ 64 <540000000>; 6058 required-opps = <&rpmhpd_opp_svs_l1>; 6059 }; 6060 6061 opp-810000000 { 6062 opp-hz = /bits/ 64 <810000000>; 6063 required-opps = <&rpmhpd_opp_nom>; 6064 }; 6065 }; 6066 }; 6067 }; 6068 6069 dispcc: clock-controller@af00000 { 6070 compatible = "qcom,sa8775p-dispcc0"; 6071 reg = <0x0 0x0af00000 0x0 0x20000>; 6072 clocks = <&gcc GCC_DISP_AHB_CLK>, 6073 <&rpmhcc RPMH_CXO_CLK>, 6074 <&rpmhcc RPMH_CXO_CLK_A>, 6075 <&sleep_clk>, 6076 <&mdss_dp0_phy 0>, 6077 <&mdss_dp0_phy 1>, 6078 <0>, <0>, 6079 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 6080 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 6081 <0>, <0>; 6082 power-domains = <&rpmhpd RPMHPD_MMCX>; 6083 #clock-cells = <1>; 6084 #reset-cells = <1>; 6085 #power-domain-cells = <1>; 6086 }; 6087 6088 pdc: interrupt-controller@b220000 { 6089 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 6090 reg = <0x0 0xb220000 0x0 0x10000>, 6091 <0x0 0x17c000f0 0x0 0x64>; 6092 interrupt-parent = <&intc>; 6093 #interrupt-cells = <2>; 6094 interrupt-controller; 6095 qcom,pdc-ranges = <0 480 40>, 6096 <40 140 14>, 6097 <54 263 1>, 6098 <55 306 4>, 6099 <59 312 3>, 6100 <62 374 2>, 6101 <64 434 2>, 6102 <66 438 2>, 6103 <70 520 1>, 6104 <73 523 1>, 6105 <118 568 6>, 6106 <124 609 3>, 6107 <159 638 1>, 6108 <160 720 3>, 6109 <169 728 30>, 6110 <199 416 2>, 6111 <201 449 1>, 6112 <202 89 1>, 6113 <203 451 1>, 6114 <204 462 1>, 6115 <205 264 1>, 6116 <206 579 1>, 6117 <207 653 1>, 6118 <208 656 1>, 6119 <209 659 1>, 6120 <210 122 1>, 6121 <211 699 1>, 6122 <212 705 1>, 6123 <213 450 1>, 6124 <214 643 2>, 6125 <216 646 5>, 6126 <221 390 5>, 6127 <226 700 2>, 6128 <228 440 1>, 6129 <229 663 1>, 6130 <230 524 2>, 6131 <232 612 3>, 6132 <235 723 5>; 6133 }; 6134 6135 tsens2: thermal-sensor@c251000 { 6136 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6137 reg = <0x0 0x0c251000 0x0 0x1000>, 6138 <0x0 0x0c224000 0x0 0x1000>; 6139 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 6140 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 6141 interrupt-names = "uplow", "critical"; 6142 #qcom,sensors = <10>; 6143 #thermal-sensor-cells = <1>; 6144 }; 6145 6146 tsens3: thermal-sensor@c252000 { 6147 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6148 reg = <0x0 0x0c252000 0x0 0x1000>, 6149 <0x0 0x0c225000 0x0 0x1000>; 6150 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 6151 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 6152 interrupt-names = "uplow", "critical"; 6153 #qcom,sensors = <10>; 6154 #thermal-sensor-cells = <1>; 6155 }; 6156 6157 tsens0: thermal-sensor@c263000 { 6158 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6159 reg = <0x0 0x0c263000 0x0 0x1000>, 6160 <0x0 0x0c222000 0x0 0x1000>; 6161 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 6162 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 6163 interrupt-names = "uplow", "critical"; 6164 #qcom,sensors = <10>; 6165 #thermal-sensor-cells = <1>; 6166 }; 6167 6168 tsens1: thermal-sensor@c265000 { 6169 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6170 reg = <0x0 0x0c265000 0x0 0x1000>, 6171 <0x0 0x0c223000 0x0 0x1000>; 6172 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 6173 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 6174 interrupt-names = "uplow", "critical"; 6175 #qcom,sensors = <10>; 6176 #thermal-sensor-cells = <1>; 6177 }; 6178 6179 aoss_qmp: power-management@c300000 { 6180 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 6181 reg = <0x0 0x0c300000 0x0 0x400>; 6182 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 6183 IPCC_MPROC_SIGNAL_GLINK_QMP 6184 IRQ_TYPE_EDGE_RISING>; 6185 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6186 #clock-cells = <0>; 6187 }; 6188 6189 sram@c3f0000 { 6190 compatible = "qcom,rpmh-stats"; 6191 reg = <0x0 0x0c3f0000 0x0 0x400>; 6192 }; 6193 6194 spmi_bus: spmi@c440000 { 6195 compatible = "qcom,spmi-pmic-arb"; 6196 reg = <0x0 0x0c440000 0x0 0x1100>, 6197 <0x0 0x0c600000 0x0 0x2000000>, 6198 <0x0 0x0e600000 0x0 0x100000>, 6199 <0x0 0x0e700000 0x0 0xa0000>, 6200 <0x0 0x0c40a000 0x0 0x26000>; 6201 reg-names = "core", 6202 "chnls", 6203 "obsrvr", 6204 "intr", 6205 "cnfg"; 6206 qcom,channel = <0>; 6207 qcom,ee = <0>; 6208 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6209 interrupt-names = "periph_irq"; 6210 interrupt-controller; 6211 #interrupt-cells = <4>; 6212 #address-cells = <2>; 6213 #size-cells = <0>; 6214 }; 6215 6216 tlmm: pinctrl@f100000 { 6217 compatible = "qcom,qcs8300-tlmm"; 6218 reg = <0x0 0x0f100000 0x0 0x300000>; 6219 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6220 gpio-controller; 6221 #gpio-cells = <2>; 6222 gpio-ranges = <&tlmm 0 0 134>; 6223 interrupt-controller; 6224 #interrupt-cells = <2>; 6225 wakeup-parent = <&pdc>; 6226 6227 cam0_default: cam0-default-state { 6228 pins = "gpio67"; 6229 function = "cam_mclk"; 6230 drive-strength = <2>; 6231 bias-disable; 6232 }; 6233 6234 cam1_default: cam1-default-state { 6235 pins = "gpio68"; 6236 function = "cam_mclk"; 6237 drive-strength = <2>; 6238 bias-disable; 6239 }; 6240 6241 cam2_default: cam2-default-state { 6242 pins = "gpio69"; 6243 function = "cam_mclk"; 6244 drive-strength = <2>; 6245 bias-disable; 6246 }; 6247 6248 cci0_0_default: cci0-0-default-state { 6249 sda-pins { 6250 pins = "gpio57"; 6251 function = "cci_i2c_sda"; 6252 drive-strength = <2>; 6253 bias-pull-up = <2200>; 6254 }; 6255 6256 scl-pins { 6257 pins = "gpio58"; 6258 function = "cci_i2c_scl"; 6259 drive-strength = <2>; 6260 bias-pull-up = <2200>; 6261 }; 6262 }; 6263 6264 cci0_0_sleep: cci0-0-sleep-state { 6265 sda-pins { 6266 pins = "gpio57"; 6267 function = "cci_i2c_sda"; 6268 drive-strength = <2>; 6269 bias-pull-down; 6270 }; 6271 6272 scl-pins { 6273 pins = "gpio58"; 6274 function = "cci_i2c_scl"; 6275 drive-strength = <2>; 6276 bias-pull-down; 6277 }; 6278 }; 6279 6280 cci0_1_default: cci0-1-default-state { 6281 sda-pins { 6282 pins = "gpio29"; 6283 function = "cci_i2c_sda"; 6284 drive-strength = <2>; 6285 bias-pull-up = <2200>; 6286 }; 6287 6288 scl-pins { 6289 pins = "gpio30"; 6290 function = "cci_i2c_scl"; 6291 drive-strength = <2>; 6292 bias-pull-up = <2200>; 6293 }; 6294 }; 6295 6296 cci0_1_sleep: cci0-1-sleep-state { 6297 sda-pins { 6298 pins = "gpio29"; 6299 function = "cci_i2c_sda"; 6300 drive-strength = <2>; 6301 bias-pull-down; 6302 }; 6303 6304 scl-pins { 6305 pins = "gpio30"; 6306 function = "cci_i2c_scl"; 6307 drive-strength = <2>; 6308 bias-pull-down; 6309 }; 6310 }; 6311 6312 cci1_0_default: cci1-0-default-state { 6313 sda-pins { 6314 pins = "gpio59"; 6315 function = "cci_i2c_sda"; 6316 drive-strength = <2>; 6317 bias-pull-up = <2200>; 6318 }; 6319 6320 scl-pins { 6321 pins = "gpio60"; 6322 function = "cci_i2c_scl"; 6323 drive-strength = <2>; 6324 bias-pull-up = <2200>; 6325 }; 6326 }; 6327 6328 cci1_0_sleep: cci1-0-sleep-state { 6329 sda-pins { 6330 pins = "gpio59"; 6331 function = "cci_i2c_sda"; 6332 drive-strength = <2>; 6333 bias-pull-down; 6334 }; 6335 6336 scl-pins { 6337 pins = "gpio60"; 6338 function = "cci_i2c_scl"; 6339 drive-strength = <2>; 6340 bias-pull-down; 6341 }; 6342 }; 6343 6344 cci1_1_default: cci1-1-default-state { 6345 sda-pins { 6346 pins = "gpio31"; 6347 function = "cci_i2c_sda"; 6348 drive-strength = <2>; 6349 bias-pull-up = <2200>; 6350 }; 6351 6352 scl-pins { 6353 pins = "gpio32"; 6354 function = "cci_i2c_scl"; 6355 drive-strength = <2>; 6356 bias-pull-up = <2200>; 6357 }; 6358 }; 6359 6360 cci1_1_sleep: cci1-1-sleep-state { 6361 sda-pins { 6362 pins = "gpio31"; 6363 function = "cci_i2c_sda"; 6364 drive-strength = <2>; 6365 bias-pull-down; 6366 }; 6367 6368 scl-pins { 6369 pins = "gpio32"; 6370 function = "cci_i2c_scl"; 6371 drive-strength = <2>; 6372 bias-pull-down; 6373 }; 6374 }; 6375 6376 cci2_0_default: cci2-0-default-state { 6377 sda-pins { 6378 pins = "gpio61"; 6379 function = "cci_i2c_sda"; 6380 drive-strength = <2>; 6381 bias-pull-up = <2200>; 6382 }; 6383 6384 scl-pins { 6385 pins = "gpio62"; 6386 function = "cci_i2c_scl"; 6387 drive-strength = <2>; 6388 bias-pull-up = <2200>; 6389 }; 6390 }; 6391 6392 cci2_0_sleep: cci2-0-sleep-state { 6393 sda-pins { 6394 pins = "gpio61"; 6395 function = "cci_i2c_sda"; 6396 drive-strength = <2>; 6397 bias-pull-down; 6398 }; 6399 6400 scl-pins { 6401 pins = "gpio62"; 6402 function = "cci_i2c_scl"; 6403 drive-strength = <2>; 6404 bias-pull-down; 6405 }; 6406 }; 6407 6408 cci2_1_default: cci2-1-default-state { 6409 sda-pins { 6410 pins = "gpio54"; 6411 function = "cci_i2c_sda"; 6412 drive-strength = <2>; 6413 bias-pull-up = <2200>; 6414 }; 6415 6416 scl-pins { 6417 pins = "gpio55"; 6418 function = "cci_i2c_scl"; 6419 drive-strength = <2>; 6420 bias-pull-up = <2200>; 6421 }; 6422 }; 6423 6424 cci2_1_sleep: cci2-1-sleep-state { 6425 sda-pins { 6426 pins = "gpio54"; 6427 function = "cci_i2c_sda"; 6428 drive-strength = <2>; 6429 bias-pull-down; 6430 }; 6431 6432 scl-pins { 6433 pins = "gpio55"; 6434 function = "cci_i2c_scl"; 6435 drive-strength = <2>; 6436 bias-pull-down; 6437 }; 6438 }; 6439 6440 dp_hot_plug_det: dp-hot-plug-det-state { 6441 pins = "gpio94"; 6442 function = "edp0_hot"; 6443 bias-disable; 6444 }; 6445 6446 hs0_mi2s_active: hs0-mi2s-active-state { 6447 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 6448 function = "hs0_mi2s"; 6449 drive-strength = <8>; 6450 bias-disable; 6451 }; 6452 6453 mi2s1_active: mi2s1-active-state { 6454 data0-pins { 6455 pins = "gpio100"; 6456 function = "mi2s1_data0"; 6457 drive-strength = <8>; 6458 bias-disable; 6459 }; 6460 6461 data1-pins { 6462 pins = "gpio101"; 6463 function = "mi2s1_data1"; 6464 drive-strength = <8>; 6465 bias-disable; 6466 }; 6467 6468 sclk-pins { 6469 pins = "gpio98"; 6470 function = "mi2s1_sck"; 6471 drive-strength = <8>; 6472 bias-disable; 6473 }; 6474 6475 ws-pins { 6476 pins = "gpio99"; 6477 function = "mi2s1_ws"; 6478 drive-strength = <8>; 6479 bias-disable; 6480 }; 6481 }; 6482 6483 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6484 pins = "gpio17", "gpio18"; 6485 function = "qup0_se0"; 6486 }; 6487 6488 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6489 pins = "gpio19", "gpio20"; 6490 function = "qup0_se1"; 6491 }; 6492 6493 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6494 pins = "gpio33", "gpio34"; 6495 function = "qup0_se2"; 6496 }; 6497 6498 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6499 pins = "gpio25", "gpio26"; 6500 function = "qup0_se3"; 6501 }; 6502 6503 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6504 pins = "gpio29", "gpio30"; 6505 function = "qup0_se4"; 6506 }; 6507 6508 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6509 pins = "gpio21", "gpio22"; 6510 function = "qup0_se5"; 6511 }; 6512 6513 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6514 pins = "gpio80", "gpio81"; 6515 function = "qup0_se6"; 6516 }; 6517 6518 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6519 pins = "gpio37", "gpio38"; 6520 function = "qup1_se0"; 6521 }; 6522 6523 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6524 pins = "gpio39", "gpio40"; 6525 function = "qup1_se1"; 6526 }; 6527 6528 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6529 pins = "gpio84", "gpio85"; 6530 function = "qup1_se2"; 6531 }; 6532 6533 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6534 pins = "gpio41", "gpio42"; 6535 function = "qup1_se3"; 6536 }; 6537 6538 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6539 pins = "gpio45", "gpio46"; 6540 function = "qup1_se4"; 6541 }; 6542 6543 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6544 pins = "gpio49", "gpio50"; 6545 function = "qup1_se5"; 6546 }; 6547 6548 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6549 pins = "gpio89", "gpio90"; 6550 function = "qup1_se6"; 6551 }; 6552 6553 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6554 pins = "gpio91", "gpio92"; 6555 function = "qup1_se7"; 6556 }; 6557 6558 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6559 pins = "gpio10", "gpio11"; 6560 function = "qup2_se0"; 6561 }; 6562 6563 qup_spi0_data_clk: qup-spi0-data-clk-state { 6564 pins = "gpio17", "gpio18", "gpio19"; 6565 function = "qup0_se0"; 6566 }; 6567 6568 qup_spi0_cs: qup-spi0-cs-state { 6569 pins = "gpio20"; 6570 function = "qup0_se0"; 6571 }; 6572 6573 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6574 pins = "gpio20"; 6575 function = "gpio"; 6576 }; 6577 6578 qup_spi1_data_clk: qup-spi1-data-clk-state { 6579 pins = "gpio19", "gpio20", "gpio17"; 6580 function = "qup0_se1"; 6581 }; 6582 6583 qup_spi1_cs: qup-spi1-cs-state { 6584 pins = "gpio18"; 6585 function = "qup0_se1"; 6586 }; 6587 6588 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6589 pins = "gpio18"; 6590 function = "gpio"; 6591 }; 6592 6593 qup_spi2_data_clk: qup-spi2-data-clk-state { 6594 pins = "gpio33", "gpio34", "gpio35"; 6595 function = "qup0_se2"; 6596 }; 6597 6598 qup_spi2_cs: qup-spi2-cs-state { 6599 pins = "gpio36"; 6600 function = "qup0_se2"; 6601 }; 6602 6603 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6604 pins = "gpio36"; 6605 function = "gpio"; 6606 }; 6607 6608 qup_spi3_data_clk: qup-spi3-data-clk-state { 6609 pins = "gpio25", "gpio26", "gpio27"; 6610 function = "qup0_se3"; 6611 }; 6612 6613 qup_spi3_cs: qup-spi3-cs-state { 6614 pins = "gpio28"; 6615 function = "qup0_se3"; 6616 }; 6617 6618 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6619 pins = "gpio28"; 6620 function = "gpio"; 6621 }; 6622 6623 qup_spi4_data_clk: qup-spi4-data-clk-state { 6624 pins = "gpio29", "gpio30", "gpio31"; 6625 function = "qup0_se4"; 6626 }; 6627 6628 qup_spi4_cs: qup-spi4-cs-state { 6629 pins = "gpio32"; 6630 function = "qup0_se4"; 6631 }; 6632 6633 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6634 pins = "gpio32"; 6635 function = "gpio"; 6636 }; 6637 6638 qup_spi5_data_clk: qup-spi5-data-clk-state { 6639 pins = "gpio21", "gpio22", "gpio23"; 6640 function = "qup0_se5"; 6641 }; 6642 6643 qup_spi5_cs: qup-spi5-cs-state { 6644 pins = "gpio24"; 6645 function = "qup0_se5"; 6646 }; 6647 6648 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6649 pins = "gpio24"; 6650 function = "gpio"; 6651 }; 6652 6653 qup_spi6_data_clk: qup-spi6-data-clk-state { 6654 pins = "gpio80", "gpio81", "gpio82"; 6655 function = "qup0_se6"; 6656 }; 6657 6658 qup_spi6_cs: qup-spi6-cs-state { 6659 pins = "gpio83"; 6660 function = "qup0_se6"; 6661 }; 6662 6663 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6664 pins = "gpio83"; 6665 function = "gpio"; 6666 }; 6667 6668 qup_spi8_data_clk: qup-spi8-data-clk-state { 6669 pins = "gpio37", "gpio38", "gpio39"; 6670 function = "qup1_se0"; 6671 }; 6672 6673 qup_spi8_cs: qup-spi8-cs-state { 6674 pins = "gpio40"; 6675 function = "qup1_se0"; 6676 }; 6677 6678 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6679 pins = "gpio40"; 6680 function = "gpio"; 6681 }; 6682 6683 qup_spi9_data_clk: qup-spi9-data-clk-state { 6684 pins = "gpio39", "gpio40", "gpio37"; 6685 function = "qup1_se1"; 6686 }; 6687 6688 qup_spi9_cs: qup-spi9-cs-state { 6689 pins = "gpio38"; 6690 function = "qup1_se1"; 6691 }; 6692 6693 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6694 pins = "gpio38"; 6695 function = "gpio"; 6696 }; 6697 6698 qup_spi10_data_clk: qup-spi10-data-clk-state { 6699 pins = "gpio84", "gpio85", "gpio86"; 6700 function = "qup1_se2"; 6701 }; 6702 6703 qup_spi10_cs: qup-spi10-cs-state { 6704 pins = "gpio87"; 6705 function = "qup1_se2"; 6706 }; 6707 6708 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6709 pins = "gpio87"; 6710 function = "gpio"; 6711 }; 6712 6713 qup_spi12_data_clk: qup-spi12-data-clk-state { 6714 pins = "gpio45", "gpio46", "gpio47"; 6715 function = "qup1_se4"; 6716 }; 6717 6718 qup_spi12_cs: qup-spi12-cs-state { 6719 pins = "gpio48"; 6720 function = "qup1_se4"; 6721 }; 6722 6723 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6724 pins = "gpio48"; 6725 function = "gpio"; 6726 }; 6727 6728 qup_spi13_data_clk: qup-spi13-data-clk-state { 6729 pins = "gpio49", "gpio50", "gpio51"; 6730 function = "qup1_se5"; 6731 }; 6732 6733 qup_spi13_cs: qup-spi13-cs-state { 6734 pins = "gpio52"; 6735 function = "qup1_se5"; 6736 }; 6737 6738 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6739 pins = "gpio52"; 6740 function = "gpio"; 6741 }; 6742 6743 qup_spi14_data_clk: qup-spi14-data-clk-state { 6744 pins = "gpio89", "gpio90", "gpio91"; 6745 function = "qup1_se6"; 6746 }; 6747 6748 qup_spi14_cs: qup-spi14-cs-state { 6749 pins = "gpio92"; 6750 function = "qup1_se6"; 6751 }; 6752 6753 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6754 pins = "gpio92"; 6755 function = "gpio"; 6756 }; 6757 6758 qup_spi15_data_clk: qup-spi15-data-clk-state { 6759 pins = "gpio91", "gpio92", "gpio89"; 6760 function = "qup1_se7"; 6761 }; 6762 6763 qup_spi15_cs: qup-spi15-cs-state { 6764 pins = "gpio90"; 6765 function = "qup1_se7"; 6766 }; 6767 6768 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6769 pins = "gpio90"; 6770 function = "gpio"; 6771 }; 6772 6773 qup_spi16_data_clk: qup-spi16-data-clk-state { 6774 pins = "gpio10", "gpio11", "gpio12"; 6775 function = "qup2_se0"; 6776 }; 6777 6778 qup_spi16_cs: qup-spi16-cs-state { 6779 pins = "gpio13"; 6780 function = "qup2_se0"; 6781 }; 6782 6783 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 6784 pins = "gpio13"; 6785 function = "gpio"; 6786 }; 6787 6788 qup_uart0_cts: qup-uart0-cts-state { 6789 pins = "gpio17"; 6790 function = "qup0_se0"; 6791 }; 6792 6793 qup_uart0_rts: qup-uart0-rts-state { 6794 pins = "gpio18"; 6795 function = "qup0_se0"; 6796 }; 6797 6798 qup_uart0_tx: qup-uart0-tx-state { 6799 pins = "gpio19"; 6800 function = "qup0_se0"; 6801 }; 6802 6803 qup_uart0_rx: qup-uart0-rx-state { 6804 pins = "gpio20"; 6805 function = "qup0_se0"; 6806 }; 6807 6808 qup_uart1_cts: qup-uart1-cts-state { 6809 pins = "gpio19"; 6810 function = "qup0_se1"; 6811 }; 6812 6813 qup_uart1_rts: qup-uart1-rts-state { 6814 pins = "gpio20"; 6815 function = "qup0_se1"; 6816 }; 6817 6818 qup_uart1_tx: qup-uart1-tx-state { 6819 pins = "gpio17"; 6820 function = "qup0_se1"; 6821 }; 6822 6823 qup_uart1_rx: qup-uart1-rx-state { 6824 pins = "gpio18"; 6825 function = "qup0_se1"; 6826 }; 6827 6828 qup_uart2_cts: qup-uart2-cts-state { 6829 pins = "gpio33"; 6830 function = "qup0_se2"; 6831 }; 6832 6833 qup_uart2_rts: qup-uart2-rts-state { 6834 pins = "gpio34"; 6835 function = "qup0_se2"; 6836 }; 6837 6838 qup_uart2_tx: qup-uart2-tx-state { 6839 pins = "gpio35"; 6840 function = "qup0_se2"; 6841 }; 6842 6843 qup_uart2_rx: qup-uart2-rx-state { 6844 pins = "gpio36"; 6845 function = "qup0_se2"; 6846 }; 6847 6848 qup_uart3_cts: qup-uart3-cts-state { 6849 pins = "gpio25"; 6850 function = "qup0_se3"; 6851 }; 6852 6853 qup_uart3_rts: qup-uart3-rts-state { 6854 pins = "gpio26"; 6855 function = "qup0_se3"; 6856 }; 6857 6858 qup_uart3_tx: qup-uart3-tx-state { 6859 pins = "gpio27"; 6860 function = "qup0_se3"; 6861 }; 6862 6863 qup_uart3_rx: qup-uart3-rx-state { 6864 pins = "gpio28"; 6865 function = "qup0_se3"; 6866 }; 6867 6868 qup_uart4_cts: qup-uart4-cts-state { 6869 pins = "gpio29"; 6870 function = "qup0_se4"; 6871 }; 6872 6873 qup_uart4_rts: qup-uart4-rts-state { 6874 pins = "gpio30"; 6875 function = "qup0_se4"; 6876 }; 6877 6878 qup_uart4_tx: qup-uart4-tx-state { 6879 pins = "gpio31"; 6880 function = "qup0_se4"; 6881 }; 6882 6883 qup_uart4_rx: qup-uart4-rx-state { 6884 pins = "gpio32"; 6885 function = "qup0_se4"; 6886 }; 6887 6888 qup_uart5_cts: qup-uart5-cts-state { 6889 pins = "gpio21"; 6890 function = "qup0_se5"; 6891 }; 6892 6893 qup_uart5_rts: qup-uart5-rts-state { 6894 pins = "gpio22"; 6895 function = "qup0_se5"; 6896 }; 6897 6898 qup_uart5_tx: qup-uart5-tx-state { 6899 pins = "gpio23"; 6900 function = "qup0_se5"; 6901 }; 6902 6903 qup_uart5_rx: qup-uart5-rx-state { 6904 pins = "gpio23"; 6905 function = "qup0_se5"; 6906 }; 6907 6908 qup_uart6_cts: qup-uart6-cts-state { 6909 pins = "gpio80"; 6910 function = "qup0_se6"; 6911 }; 6912 6913 qup_uart6_rts: qup-uart6-rts-state { 6914 pins = "gpio81"; 6915 function = "qup0_se6"; 6916 }; 6917 6918 qup_uart6_tx: qup-uart6-tx-state { 6919 pins = "gpio82"; 6920 function = "qup0_se6"; 6921 }; 6922 6923 qup_uart6_rx: qup-uart6-rx-state { 6924 pins = "gpio83"; 6925 function = "qup0_se6"; 6926 }; 6927 6928 qup_uart7_tx: qup-uart7-tx-state { 6929 pins = "gpio43"; 6930 function = "qup0_se7"; 6931 }; 6932 6933 qup_uart7_rx: qup-uart7-rx-state { 6934 pins = "gpio44"; 6935 function = "qup0_se7"; 6936 }; 6937 6938 qup_uart8_cts: qup-uart8-cts-state { 6939 pins = "gpio37"; 6940 function = "qup1_se0"; 6941 }; 6942 6943 qup_uart8_rts: qup-uart8-rts-state { 6944 pins = "gpio38"; 6945 function = "qup1_se0"; 6946 }; 6947 6948 qup_uart8_tx: qup-uart8-tx-state { 6949 pins = "gpio39"; 6950 function = "qup1_se0"; 6951 }; 6952 6953 qup_uart8_rx: qup-uart8-rx-state { 6954 pins = "gpio40"; 6955 function = "qup1_se0"; 6956 }; 6957 6958 qup_uart9_cts: qup-uart9-cts-state { 6959 pins = "gpio39"; 6960 function = "qup1_se1"; 6961 }; 6962 6963 qup_uart9_rts: qup-uart9-rts-state { 6964 pins = "gpio40"; 6965 function = "qup1_se1"; 6966 }; 6967 6968 qup_uart9_tx: qup-uart9-tx-state { 6969 pins = "gpio37"; 6970 function = "qup1_se1"; 6971 }; 6972 6973 qup_uart9_rx: qup-uart9-rx-state { 6974 pins = "gpio38"; 6975 function = "qup1_se1"; 6976 }; 6977 6978 qup_uart10_cts: qup-uart10-cts-state { 6979 pins = "gpio84"; 6980 function = "qup1_se2"; 6981 }; 6982 6983 qup_uart10_rts: qup-uart10-rts-state { 6984 pins = "gpio85"; 6985 function = "qup1_se2"; 6986 }; 6987 6988 qup_uart10_tx: qup-uart10-tx-state { 6989 pins = "gpio86"; 6990 function = "qup1_se2"; 6991 }; 6992 6993 qup_uart10_rx: qup-uart10-rx-state { 6994 pins = "gpio87"; 6995 function = "qup1_se2"; 6996 }; 6997 6998 qup_uart11_tx: qup-uart11-tx-state { 6999 pins = "gpio41"; 7000 function = "qup1_se3"; 7001 }; 7002 7003 qup_uart11_rx: qup-uart11-rx-state { 7004 pins = "gpio42"; 7005 function = "qup1_se3"; 7006 }; 7007 7008 qup_uart12_cts: qup-uart12-cts-state { 7009 pins = "gpio45"; 7010 function = "qup1_se4"; 7011 }; 7012 7013 qup_uart12_rts: qup-uart12-rts-state { 7014 pins = "gpio46"; 7015 function = "qup1_se4"; 7016 }; 7017 7018 qup_uart12_tx: qup-uart12-tx-state { 7019 pins = "gpio47"; 7020 function = "qup1_se4"; 7021 }; 7022 7023 qup_uart12_rx: qup-uart12-rx-state { 7024 pins = "gpio48"; 7025 function = "qup1_se4"; 7026 }; 7027 7028 qup_uart13_cts: qup-uart13-cts-state { 7029 pins = "gpio49"; 7030 function = "qup1_se5"; 7031 }; 7032 7033 qup_uart13_rts: qup-uart13-rts-state { 7034 pins = "gpio50"; 7035 function = "qup1_se5"; 7036 }; 7037 7038 qup_uart13_tx: qup-uart13-tx-state { 7039 pins = "gpio51"; 7040 function = "qup1_se5"; 7041 }; 7042 7043 qup_uart13_rx: qup-uart13-rx-state { 7044 pins = "gpio52"; 7045 function = "qup1_se5"; 7046 }; 7047 7048 qup_uart14_cts: qup-uart14-cts-state { 7049 pins = "gpio89"; 7050 function = "qup1_se6"; 7051 }; 7052 7053 qup_uart14_rts: qup-uart14-rts-state { 7054 pins = "gpio90"; 7055 function = "qup1_se6"; 7056 }; 7057 7058 qup_uart14_tx: qup-uart14-tx-state { 7059 pins = "gpio91"; 7060 function = "qup1_se6"; 7061 }; 7062 7063 qup_uart14_rx: qup-uart14-rx-state { 7064 pins = "gpio92"; 7065 function = "qup1_se6"; 7066 }; 7067 7068 qup_uart15_cts: qup-uart15-cts-state { 7069 pins = "gpio91"; 7070 function = "qup1_se7"; 7071 }; 7072 7073 qup_uart15_rts: qup-uart15-rts-state { 7074 pins = "gpio92"; 7075 function = "qup1_se7"; 7076 }; 7077 7078 qup_uart15_tx: qup-uart15-tx-state { 7079 pins = "gpio89"; 7080 function = "qup1_se7"; 7081 }; 7082 7083 qup_uart15_rx: qup-uart15-rx-state { 7084 pins = "gpio90"; 7085 function = "qup1_se7"; 7086 }; 7087 7088 qup_uart16_cts: qup-uart16-cts-state { 7089 pins = "gpio10"; 7090 function = "qup2_se0"; 7091 }; 7092 7093 qup_uart16_rts: qup-uart16-rts-state { 7094 pins = "gpio11"; 7095 function = "qup2_se0"; 7096 }; 7097 7098 qup_uart16_tx: qup-uart16-tx-state { 7099 pins = "gpio12"; 7100 function = "qup2_se0"; 7101 }; 7102 7103 qup_uart16_rx: qup-uart16-rx-state { 7104 pins = "gpio13"; 7105 function = "qup2_se0"; 7106 }; 7107 7108 sdc1_state_on: sdc1-on-state { 7109 clk-pins { 7110 pins = "sdc1_clk"; 7111 drive-strength = <16>; 7112 bias-disable; 7113 }; 7114 7115 cmd-pins { 7116 pins = "sdc1_cmd"; 7117 drive-strength = <10>; 7118 bias-pull-up; 7119 }; 7120 7121 data-pins { 7122 pins = "sdc1_data"; 7123 drive-strength = <10>; 7124 bias-pull-up; 7125 }; 7126 7127 rclk-pins { 7128 pins = "sdc1_rclk"; 7129 bias-pull-down; 7130 }; 7131 }; 7132 7133 sdc1_state_off: sdc1-off-state { 7134 clk-pins { 7135 pins = "sdc1_clk"; 7136 drive-strength = <2>; 7137 bias-bus-hold; 7138 }; 7139 7140 cmd-pins { 7141 pins = "sdc1_cmd"; 7142 drive-strength = <2>; 7143 bias-bus-hold; 7144 }; 7145 7146 data-pins { 7147 pins = "sdc1_data"; 7148 drive-strength = <2>; 7149 bias-bus-hold; 7150 }; 7151 7152 rclk-pins { 7153 pins = "sdc1_rclk"; 7154 bias-bus-hold; 7155 }; 7156 }; 7157 }; 7158 7159 sram: sram@146d8000 { 7160 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 7161 reg = <0x0 0x146d8000 0x0 0x1000>; 7162 ranges = <0x0 0x0 0x146d8000 0x1000>; 7163 7164 #address-cells = <1>; 7165 #size-cells = <1>; 7166 7167 minidump_config: minidump-sram@1c { 7168 reg = <0x1c 0x4>; 7169 }; 7170 7171 pil-reloc@94c { 7172 compatible = "qcom,pil-reloc-info"; 7173 reg = <0x94c 0xc8>; 7174 }; 7175 }; 7176 7177 apps_smmu: iommu@15000000 { 7178 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7179 7180 reg = <0x0 0x15000000 0x0 0x100000>; 7181 #iommu-cells = <2>; 7182 #global-interrupts = <2>; 7183 dma-coherent; 7184 7185 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 7186 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 7187 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7188 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7189 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7190 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7191 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7192 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7193 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7194 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7195 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7196 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7197 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7198 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7199 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7200 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7201 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7202 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7203 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7204 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7205 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7206 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7207 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7208 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7209 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7210 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7211 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7212 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7213 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7214 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7215 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7216 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7217 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7218 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7219 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7220 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7221 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7222 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7223 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7224 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7225 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7226 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7227 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7228 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7229 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7230 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7231 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7232 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7233 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7234 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7235 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7236 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7237 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7238 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7239 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7240 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7241 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7242 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7243 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7244 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7245 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7246 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7247 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7248 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7249 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7250 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7251 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7252 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7253 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7254 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7255 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7256 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7257 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7258 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7259 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7260 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7261 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7262 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7263 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7264 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7265 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7266 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7267 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7268 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7269 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7270 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 7271 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7272 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7273 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7274 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 7275 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7276 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7277 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7278 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7279 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7280 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7281 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7282 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 7283 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 7284 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 7285 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 7286 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 7287 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7288 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 7289 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 7290 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 7291 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 7292 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 7293 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 7294 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 7295 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 7296 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 7297 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 7298 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 7299 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 7300 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 7301 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 7302 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 7303 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 7304 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 7305 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 7306 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 7307 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 7308 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 7309 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 7310 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 7311 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 7312 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 7313 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 7314 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 7315 }; 7316 7317 pcie_smmu: iommu@15200000 { 7318 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7319 reg = <0x0 0x15200000 0x0 0x80000>; 7320 #iommu-cells = <2>; 7321 #global-interrupts = <2>; 7322 dma-coherent; 7323 7324 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 7325 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 7326 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 7327 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 7328 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 7329 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 7330 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 7331 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 7332 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 7333 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 7334 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 7335 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 7336 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 7337 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 7338 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 7339 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 7340 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 7341 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 7342 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 7343 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 7344 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 7345 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 7346 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 7347 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 7348 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 7349 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 7350 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 7351 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 7352 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 7353 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 7354 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 7355 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 7356 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 7357 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 7358 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 7359 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 7360 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 7361 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 7362 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 7363 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 7364 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 7365 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 7366 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 7367 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 7368 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 7369 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 7370 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 7371 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 7372 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 7373 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 7374 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 7375 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 7376 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 7377 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 7378 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 7379 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 7380 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 7381 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 7382 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 7383 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 7384 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 7385 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 7386 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 7387 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 7388 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 7389 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 7390 }; 7391 7392 intc: interrupt-controller@17a00000 { 7393 compatible = "arm,gic-v3"; 7394 reg = <0x0 0x17a00000 0x0 0x10000>, 7395 <0x0 0x17a60000 0x0 0x100000>; 7396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7397 #interrupt-cells = <3>; 7398 interrupt-controller; 7399 #redistributor-regions = <1>; 7400 redistributor-stride = <0x0 0x20000>; 7401 #address-cells = <0>; 7402 }; 7403 7404 watchdog@17c10000 { 7405 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 7406 reg = <0x0 0x17c10000 0x0 0x1000>; 7407 clocks = <&sleep_clk>; 7408 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7409 }; 7410 7411 timer@17c20000 { 7412 compatible = "arm,armv7-timer-mem"; 7413 reg = <0x0 0x17c20000 0x0 0x1000>; 7414 ranges = <0x0 0x0 0x0 0x20000000>; 7415 #address-cells = <1>; 7416 #size-cells = <1>; 7417 7418 frame@17c21000 { 7419 reg = <0x17c21000 0x1000>, 7420 <0x17c22000 0x1000>; 7421 frame-number = <0>; 7422 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7423 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7424 }; 7425 7426 frame@17c23000 { 7427 reg = <0x17c23000 0x1000>; 7428 frame-number = <1>; 7429 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7430 status = "disabled"; 7431 }; 7432 7433 frame@17c25000 { 7434 reg = <0x17c25000 0x1000>; 7435 frame-number = <2>; 7436 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7437 status = "disabled"; 7438 }; 7439 7440 frame@17c27000 { 7441 reg = <0x17c27000 0x1000>; 7442 frame-number = <3>; 7443 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7444 status = "disabled"; 7445 }; 7446 7447 frame@17c29000 { 7448 reg = <0x17c29000 0x1000>; 7449 frame-number = <4>; 7450 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7451 status = "disabled"; 7452 }; 7453 7454 frame@17c2b000 { 7455 reg = <0x17c2b000 0x1000>; 7456 frame-number = <5>; 7457 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7458 status = "disabled"; 7459 }; 7460 7461 frame@17c2d000 { 7462 reg = <0x17c2d000 0x1000>; 7463 frame-number = <6>; 7464 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7465 status = "disabled"; 7466 }; 7467 }; 7468 7469 apps_rsc: rsc@18200000 { 7470 compatible = "qcom,rpmh-rsc"; 7471 reg = <0x0 0x18200000 0x0 0x10000>, 7472 <0x0 0x18210000 0x0 0x10000>, 7473 <0x0 0x18220000 0x0 0x10000>; 7474 reg-names = "drv-0", 7475 "drv-1", 7476 "drv-2"; 7477 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7478 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7479 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7480 7481 power-domains = <&system_pd>; 7482 label = "apps_rsc"; 7483 7484 qcom,tcs-offset = <0xd00>; 7485 qcom,drv-id = <2>; 7486 qcom,tcs-config = <ACTIVE_TCS 2>, 7487 <SLEEP_TCS 3>, 7488 <WAKE_TCS 3>, 7489 <CONTROL_TCS 0>; 7490 7491 apps_bcm_voter: bcm-voter { 7492 compatible = "qcom,bcm-voter"; 7493 }; 7494 7495 rpmhcc: clock-controller { 7496 compatible = "qcom,sa8775p-rpmh-clk"; 7497 #clock-cells = <1>; 7498 clocks = <&xo_board_clk>; 7499 clock-names = "xo"; 7500 }; 7501 7502 rpmhpd: power-controller { 7503 compatible = "qcom,qcs8300-rpmhpd"; 7504 #power-domain-cells = <1>; 7505 operating-points-v2 = <&rpmhpd_opp_table>; 7506 7507 rpmhpd_opp_table: opp-table { 7508 compatible = "operating-points-v2"; 7509 7510 rpmhpd_opp_ret: opp-0 { 7511 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7512 }; 7513 7514 rpmhpd_opp_min_svs: opp-1 { 7515 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7516 }; 7517 7518 rpmhpd_opp_low_svs: opp-2 { 7519 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7520 }; 7521 7522 rpmhpd_opp_svs: opp-3 { 7523 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7524 }; 7525 7526 rpmhpd_opp_svs_l1: opp-4 { 7527 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7528 }; 7529 7530 rpmhpd_opp_nom: opp-5 { 7531 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7532 }; 7533 7534 rpmhpd_opp_nom_l1: opp-6 { 7535 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7536 }; 7537 7538 rpmhpd_opp_nom_l2: opp-7 { 7539 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7540 }; 7541 7542 rpmhpd_opp_turbo: opp-8 { 7543 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7544 }; 7545 7546 rpmhpd_opp_turbo_l1: opp-9 { 7547 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7548 }; 7549 }; 7550 }; 7551 }; 7552 7553 epss_l3_cl0: interconnect@18590000 { 7554 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7555 "qcom,epss-l3"; 7556 reg = <0x0 0x18590000 0x0 0x1000>; 7557 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7558 clock-names = "xo", "alternate"; 7559 #interconnect-cells = <1>; 7560 }; 7561 7562 cpufreq_hw: cpufreq@18591000 { 7563 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 7564 reg = <0x0 0x18591000 0x0 0x1000>, 7565 <0x0 0x18593000 0x0 0x1000>, 7566 <0x0 0x18594000 0x0 0x1000>; 7567 reg-names = "freq-domain0", 7568 "freq-domain1", 7569 "freq-domain2"; 7570 7571 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7572 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 7573 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 7574 interrupt-names = "dcvsh-irq-0", 7575 "dcvsh-irq-1", 7576 "dcvsh-irq-2"; 7577 7578 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7579 clock-names = "xo", "alternate"; 7580 7581 #freq-domain-cells = <1>; 7582 }; 7583 7584 epss_l3_cl1: interconnect@18592000 { 7585 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7586 "qcom,epss-l3"; 7587 reg = <0x0 0x18592000 0x0 0x1000>; 7588 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7589 clock-names = "xo", "alternate"; 7590 #interconnect-cells = <1>; 7591 }; 7592 7593 remoteproc_gpdsp: remoteproc@20c00000 { 7594 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 7595 reg = <0x0 0x20c00000 0x0 0x10000>; 7596 7597 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7598 <&smp2p_gpdsp_in 0 0>, 7599 <&smp2p_gpdsp_in 1 0>, 7600 <&smp2p_gpdsp_in 2 0>, 7601 <&smp2p_gpdsp_in 3 0>; 7602 interrupt-names = "wdog", 7603 "fatal", 7604 "ready", 7605 "handover", 7606 "stop-ack"; 7607 7608 clocks = <&rpmhcc RPMH_CXO_CLK>; 7609 clock-names = "xo"; 7610 7611 power-domains = <&rpmhpd RPMHPD_CX>, 7612 <&rpmhpd RPMHPD_MXC>; 7613 power-domain-names = "cx", 7614 "mxc"; 7615 7616 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 7617 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 7618 7619 memory-region = <&gpdsp_mem>; 7620 7621 qcom,qmp = <&aoss_qmp>; 7622 7623 qcom,smem-states = <&smp2p_gpdsp_out 0>; 7624 qcom,smem-state-names = "stop"; 7625 7626 status = "disabled"; 7627 7628 glink-edge { 7629 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7630 IPCC_MPROC_SIGNAL_GLINK_QMP 7631 IRQ_TYPE_EDGE_RISING>; 7632 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7633 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7634 7635 label = "gpdsp"; 7636 qcom,remote-pid = <17>; 7637 7638 fastrpc { 7639 compatible = "qcom,fastrpc"; 7640 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7641 label = "gdsp0"; 7642 #address-cells = <1>; 7643 #size-cells = <0>; 7644 7645 compute-cb@1 { 7646 compatible = "qcom,fastrpc-compute-cb"; 7647 reg = <1>; 7648 iommus = <&apps_smmu 0x28a1 0x0>; 7649 dma-coherent; 7650 }; 7651 7652 compute-cb@2 { 7653 compatible = "qcom,fastrpc-compute-cb"; 7654 reg = <2>; 7655 iommus = <&apps_smmu 0x28a2 0x0>; 7656 dma-coherent; 7657 }; 7658 7659 compute-cb@3 { 7660 compatible = "qcom,fastrpc-compute-cb"; 7661 reg = <3>; 7662 iommus = <&apps_smmu 0x28a3 0x0>; 7663 dma-coherent; 7664 }; 7665 }; 7666 }; 7667 }; 7668 7669 ethernet0: ethernet@23040000 { 7670 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 7671 reg = <0x0 0x23040000 0x0 0x00010000>, 7672 <0x0 0x23056000 0x0 0x00000100>; 7673 reg-names = "stmmaceth", "rgmii"; 7674 7675 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7676 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 7677 interrupt-names = "macirq", "sfty"; 7678 7679 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7680 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7681 <&gcc GCC_EMAC0_PTP_CLK>, 7682 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7683 clock-names = "stmmaceth", 7684 "pclk", 7685 "ptp_ref", 7686 "phyaux"; 7687 power-domains = <&gcc GCC_EMAC0_GDSC>; 7688 7689 phys = <&serdes0>; 7690 phy-names = "serdes"; 7691 7692 iommus = <&apps_smmu 0x120 0xf>; 7693 dma-coherent; 7694 7695 snps,tso; 7696 snps,pbl = <32>; 7697 rx-fifo-depth = <16384>; 7698 tx-fifo-depth = <20480>; 7699 7700 status = "disabled"; 7701 }; 7702 7703 nspa_noc: interconnect@260c0000 { 7704 compatible = "qcom,qcs8300-nspa-noc"; 7705 reg = <0x0 0x260c0000 0x0 0x16080>; 7706 #interconnect-cells = <2>; 7707 qcom,bcm-voters = <&apps_bcm_voter>; 7708 }; 7709 7710 remoteproc_cdsp: remoteproc@26300000 { 7711 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 7712 reg = <0x0 0x26300000 0x0 0x10000>; 7713 7714 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7715 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7716 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7717 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7718 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7719 interrupt-names = "wdog", 7720 "fatal", 7721 "ready", 7722 "handover", 7723 "stop-ack"; 7724 7725 clocks = <&rpmhcc RPMH_CXO_CLK>; 7726 clock-names = "xo"; 7727 7728 power-domains = <&rpmhpd RPMHPD_CX>, 7729 <&rpmhpd RPMHPD_MXC>, 7730 <&rpmhpd RPMHPD_NSP0>; 7731 7732 power-domain-names = "cx", 7733 "mxc", 7734 "nsp"; 7735 7736 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7737 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7738 7739 memory-region = <&cdsp_mem>; 7740 7741 qcom,qmp = <&aoss_qmp>; 7742 7743 qcom,smem-states = <&smp2p_cdsp_out 0>; 7744 qcom,smem-state-names = "stop"; 7745 7746 status = "disabled"; 7747 7748 glink-edge { 7749 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7750 IPCC_MPROC_SIGNAL_GLINK_QMP 7751 IRQ_TYPE_EDGE_RISING>; 7752 mboxes = <&ipcc IPCC_CLIENT_CDSP 7753 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7754 7755 label = "cdsp"; 7756 qcom,remote-pid = <5>; 7757 7758 fastrpc { 7759 compatible = "qcom,fastrpc"; 7760 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7761 label = "cdsp"; 7762 #address-cells = <1>; 7763 #size-cells = <0>; 7764 7765 compute-cb@1 { 7766 compatible = "qcom,fastrpc-compute-cb"; 7767 reg = <1>; 7768 iommus = <&apps_smmu 0x19c1 0x0440>, 7769 <&apps_smmu 0x1961 0x0400>; 7770 dma-coherent; 7771 }; 7772 7773 compute-cb@2 { 7774 compatible = "qcom,fastrpc-compute-cb"; 7775 reg = <2>; 7776 iommus = <&apps_smmu 0x19c2 0x0440>, 7777 <&apps_smmu 0x1962 0x0400>; 7778 dma-coherent; 7779 }; 7780 7781 compute-cb@3 { 7782 compatible = "qcom,fastrpc-compute-cb"; 7783 reg = <3>; 7784 iommus = <&apps_smmu 0x19c3 0x0440>, 7785 <&apps_smmu 0x1963 0x0400>; 7786 dma-coherent; 7787 }; 7788 7789 compute-cb@4 { 7790 compatible = "qcom,fastrpc-compute-cb"; 7791 reg = <4>; 7792 iommus = <&apps_smmu 0x19c4 0x0440>, 7793 <&apps_smmu 0x1964 0x0400>; 7794 dma-coherent; 7795 }; 7796 7797 compute-cb@5 { 7798 compatible = "qcom,fastrpc-compute-cb"; 7799 reg = <5>; 7800 iommus = <&apps_smmu 0x19c5 0x0400>; 7801 dma-coherent; 7802 }; 7803 7804 compute-cb@6 { 7805 compatible = "qcom,fastrpc-compute-cb"; 7806 reg = <6>; 7807 iommus = <&apps_smmu 0x19c6 0x0400>; 7808 dma-coherent; 7809 }; 7810 7811 compute-cb@7 { 7812 compatible = "qcom,fastrpc-compute-cb"; 7813 reg = <7>; 7814 iommus = <&apps_smmu 0x19c7 0x0400>; 7815 dma-coherent; 7816 }; 7817 7818 compute-cb@8 { 7819 compatible = "qcom,fastrpc-compute-cb"; 7820 reg = <8>; 7821 iommus = <&apps_smmu 0x19c8 0x0400>; 7822 dma-coherent; 7823 }; 7824 7825 compute-cb@9 { 7826 compatible = "qcom,fastrpc-compute-cb"; 7827 reg = <9>; 7828 iommus = <&apps_smmu 0x19c9 0x0400>; 7829 dma-coherent; 7830 }; 7831 7832 compute-cb@11 { 7833 compatible = "qcom,fastrpc-compute-cb"; 7834 reg = <0xb>; 7835 iommus = <&apps_smmu 0x19cb 0x0400>; 7836 dma-coherent; 7837 }; 7838 7839 compute-cb@12 { 7840 compatible = "qcom,fastrpc-compute-cb"; 7841 reg = <0xc>; 7842 iommus = <&apps_smmu 0x19cc 0x000>; 7843 dma-coherent; 7844 }; 7845 }; 7846 }; 7847 }; 7848 }; 7849 7850 thermal_zones: thermal-zones { 7851 aoss-0-thermal { 7852 thermal-sensors = <&tsens0 0>; 7853 7854 trips { 7855 aoss0-critical { 7856 temperature = <125000>; 7857 hysteresis = <1000>; 7858 type = "critical"; 7859 }; 7860 }; 7861 }; 7862 7863 cpu-0-0-0-thermal { 7864 thermal-sensors = <&tsens0 1>; 7865 7866 trips { 7867 cpu-critical { 7868 temperature = <125000>; 7869 hysteresis = <1000>; 7870 type = "critical"; 7871 }; 7872 }; 7873 }; 7874 7875 cpu-0-1-0-thermal { 7876 thermal-sensors = <&tsens0 2>; 7877 7878 trips { 7879 cpu-critical { 7880 temperature = <125000>; 7881 hysteresis = <1000>; 7882 type = "critical"; 7883 }; 7884 }; 7885 }; 7886 7887 cpu-0-2-0-thermal { 7888 thermal-sensors = <&tsens0 3>; 7889 7890 trips { 7891 cpu-critical { 7892 temperature = <125000>; 7893 hysteresis = <1000>; 7894 type = "critical"; 7895 }; 7896 }; 7897 }; 7898 7899 cpu-0-3-0-thermal { 7900 thermal-sensors = <&tsens0 4>; 7901 7902 trips { 7903 cpu-critical { 7904 temperature = <125000>; 7905 hysteresis = <1000>; 7906 type = "critical"; 7907 }; 7908 }; 7909 }; 7910 7911 gpuss-0-thermal { 7912 thermal-sensors = <&tsens0 5>; 7913 7914 trips { 7915 gpuss0_alert0: trip-point0 { 7916 temperature = <115000>; 7917 hysteresis = <5000>; 7918 type = "passive"; 7919 }; 7920 7921 gpuss0-critical { 7922 temperature = <125000>; 7923 hysteresis = <1000>; 7924 type = "critical"; 7925 }; 7926 }; 7927 7928 cooling-maps { 7929 map0 { 7930 trip = <&gpuss0_alert0>; 7931 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7932 }; 7933 }; 7934 }; 7935 7936 audio-thermal { 7937 thermal-sensors = <&tsens0 6>; 7938 7939 trips { 7940 audio-critical { 7941 temperature = <125000>; 7942 hysteresis = <1000>; 7943 type = "critical"; 7944 }; 7945 }; 7946 }; 7947 7948 camss-0-thermal { 7949 thermal-sensors = <&tsens0 7>; 7950 7951 trips { 7952 camss-critical { 7953 temperature = <125000>; 7954 hysteresis = <1000>; 7955 type = "critical"; 7956 }; 7957 }; 7958 }; 7959 7960 pcie-0-thermal { 7961 thermal-sensors = <&tsens0 8>; 7962 7963 trips { 7964 pcie-critical { 7965 temperature = <125000>; 7966 hysteresis = <1000>; 7967 type = "critical"; 7968 }; 7969 }; 7970 }; 7971 7972 cpuss-0-0-thermal { 7973 thermal-sensors = <&tsens0 9>; 7974 7975 trips { 7976 cpuss0-critical { 7977 temperature = <125000>; 7978 hysteresis = <1000>; 7979 type = "critical"; 7980 }; 7981 }; 7982 }; 7983 7984 aoss-1-thermal { 7985 thermal-sensors = <&tsens1 0>; 7986 7987 trips { 7988 aoss1-critical { 7989 temperature = <125000>; 7990 hysteresis = <1000>; 7991 type = "critical"; 7992 }; 7993 }; 7994 }; 7995 7996 cpu-0-0-1-thermal { 7997 thermal-sensors = <&tsens1 1>; 7998 7999 trips { 8000 cpu-critical { 8001 temperature = <125000>; 8002 hysteresis = <1000>; 8003 type = "critical"; 8004 }; 8005 }; 8006 }; 8007 8008 cpu-0-1-1-thermal { 8009 thermal-sensors = <&tsens1 2>; 8010 8011 trips { 8012 cpu-critical { 8013 temperature = <125000>; 8014 hysteresis = <1000>; 8015 type = "critical"; 8016 }; 8017 }; 8018 }; 8019 8020 cpu-0-2-1-thermal { 8021 thermal-sensors = <&tsens1 3>; 8022 8023 trips { 8024 cpu-critical { 8025 temperature = <125000>; 8026 hysteresis = <1000>; 8027 type = "critical"; 8028 }; 8029 }; 8030 }; 8031 8032 cpu-0-3-1-thermal { 8033 thermal-sensors = <&tsens1 4>; 8034 8035 trips { 8036 cpu-critical { 8037 temperature = <125000>; 8038 hysteresis = <1000>; 8039 type = "critical"; 8040 }; 8041 }; 8042 }; 8043 8044 gpuss-1-thermal { 8045 thermal-sensors = <&tsens1 5>; 8046 8047 trips { 8048 gpuss1_alert0: trip-point0 { 8049 temperature = <115000>; 8050 hysteresis = <5000>; 8051 type = "passive"; 8052 }; 8053 8054 gpuss1-critical { 8055 temperature = <125000>; 8056 hysteresis = <1000>; 8057 type = "critical"; 8058 }; 8059 }; 8060 8061 cooling-maps { 8062 map0 { 8063 trip = <&gpuss1_alert0>; 8064 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8065 }; 8066 }; 8067 }; 8068 8069 video-thermal { 8070 thermal-sensors = <&tsens1 6>; 8071 8072 trips { 8073 video-critical { 8074 temperature = <125000>; 8075 hysteresis = <1000>; 8076 type = "critical"; 8077 }; 8078 }; 8079 }; 8080 8081 camss-1-thermal { 8082 thermal-sensors = <&tsens1 7>; 8083 8084 trips { 8085 camss1-critical { 8086 temperature = <125000>; 8087 hysteresis = <1000>; 8088 type = "critical"; 8089 }; 8090 }; 8091 }; 8092 8093 pcie-1-thermal { 8094 thermal-sensors = <&tsens1 8>; 8095 8096 trips { 8097 pcie-critical { 8098 temperature = <125000>; 8099 hysteresis = <1000>; 8100 type = "critical"; 8101 }; 8102 }; 8103 }; 8104 8105 cpuss-0-1-thermal { 8106 thermal-sensors = <&tsens1 9>; 8107 8108 trips { 8109 cpuss0-critical { 8110 temperature = <125000>; 8111 hysteresis = <1000>; 8112 type = "critical"; 8113 }; 8114 }; 8115 }; 8116 8117 aoss-2-thermal { 8118 thermal-sensors = <&tsens2 0>; 8119 8120 trips { 8121 aoss2-critical { 8122 temperature = <125000>; 8123 hysteresis = <1000>; 8124 type = "critical"; 8125 }; 8126 }; 8127 }; 8128 8129 cpu-1-0-0-thermal { 8130 thermal-sensors = <&tsens2 1>; 8131 8132 trips { 8133 cpu-critical { 8134 temperature = <125000>; 8135 hysteresis = <1000>; 8136 type = "critical"; 8137 }; 8138 }; 8139 }; 8140 8141 cpu-1-1-0-thermal { 8142 thermal-sensors = <&tsens2 2>; 8143 8144 trips { 8145 cpu-critical { 8146 temperature = <125000>; 8147 hysteresis = <1000>; 8148 type = "critical"; 8149 }; 8150 }; 8151 }; 8152 8153 cpu-1-2-0-thermal { 8154 thermal-sensors = <&tsens2 3>; 8155 8156 trips { 8157 cpu-critical { 8158 temperature = <125000>; 8159 hysteresis = <1000>; 8160 type = "critical"; 8161 }; 8162 }; 8163 }; 8164 8165 cpu-1-3-0-thermal { 8166 thermal-sensors = <&tsens2 4>; 8167 8168 trips { 8169 cpu-critical { 8170 temperature = <125000>; 8171 hysteresis = <1000>; 8172 type = "critical"; 8173 }; 8174 }; 8175 }; 8176 8177 nsp-0-0-0-thermal { 8178 thermal-sensors = <&tsens2 5>; 8179 8180 trips { 8181 nsp-critical { 8182 temperature = <125000>; 8183 hysteresis = <1000>; 8184 type = "critical"; 8185 }; 8186 }; 8187 }; 8188 8189 nsp-0-1-0-thermal { 8190 thermal-sensors = <&tsens2 6>; 8191 8192 trips { 8193 nsp-critical { 8194 temperature = <125000>; 8195 hysteresis = <1000>; 8196 type = "critical"; 8197 }; 8198 }; 8199 }; 8200 8201 nsp-0-2-0-thermal { 8202 thermal-sensors = <&tsens2 7>; 8203 8204 trips { 8205 nsp-critical { 8206 temperature = <125000>; 8207 hysteresis = <1000>; 8208 type = "critical"; 8209 }; 8210 }; 8211 }; 8212 8213 ddrss-0-thermal { 8214 thermal-sensors = <&tsens2 8>; 8215 8216 trips { 8217 ddrss-critical { 8218 temperature = <125000>; 8219 hysteresis = <1000>; 8220 type = "critical"; 8221 }; 8222 }; 8223 }; 8224 8225 cpuss-1-0-thermal { 8226 thermal-sensors = <&tsens2 9>; 8227 8228 trips { 8229 cpuss1-critical { 8230 temperature = <125000>; 8231 hysteresis = <1000>; 8232 type = "critical"; 8233 }; 8234 }; 8235 }; 8236 8237 aoss-3-thermal { 8238 thermal-sensors = <&tsens3 0>; 8239 8240 trips { 8241 aoss3-critical { 8242 temperature = <125000>; 8243 hysteresis = <1000>; 8244 type = "critical"; 8245 }; 8246 }; 8247 }; 8248 8249 cpu-1-0-1-thermal { 8250 thermal-sensors = <&tsens3 1>; 8251 8252 trips { 8253 cpu-critical { 8254 temperature = <125000>; 8255 hysteresis = <1000>; 8256 type = "critical"; 8257 }; 8258 }; 8259 }; 8260 8261 cpu-1-1-1-thermal { 8262 thermal-sensors = <&tsens3 2>; 8263 8264 trips { 8265 cpu-critical { 8266 temperature = <125000>; 8267 hysteresis = <1000>; 8268 type = "critical"; 8269 }; 8270 }; 8271 }; 8272 8273 cpu-1-2-1-thermal { 8274 thermal-sensors = <&tsens3 3>; 8275 8276 trips { 8277 cpu-critical { 8278 temperature = <125000>; 8279 hysteresis = <1000>; 8280 type = "critical"; 8281 }; 8282 }; 8283 }; 8284 8285 cpu-1-3-1-thermal { 8286 thermal-sensors = <&tsens3 4>; 8287 8288 trips { 8289 cpu-critical { 8290 temperature = <125000>; 8291 hysteresis = <1000>; 8292 type = "critical"; 8293 }; 8294 }; 8295 }; 8296 8297 nsp-0-0-1-thermal { 8298 thermal-sensors = <&tsens3 5>; 8299 8300 trips { 8301 nsp-critical { 8302 temperature = <125000>; 8303 hysteresis = <1000>; 8304 type = "critical"; 8305 }; 8306 }; 8307 }; 8308 8309 nsp-0-1-1-thermal { 8310 thermal-sensors = <&tsens3 6>; 8311 8312 trips { 8313 nsp-critical { 8314 temperature = <125000>; 8315 hysteresis = <1000>; 8316 type = "critical"; 8317 }; 8318 }; 8319 }; 8320 8321 nsp-0-2-1-thermal { 8322 thermal-sensors = <&tsens3 7>; 8323 8324 trips { 8325 nsp-critical { 8326 temperature = <125000>; 8327 hysteresis = <1000>; 8328 type = "critical"; 8329 }; 8330 }; 8331 }; 8332 8333 ddrss-1-thermal { 8334 thermal-sensors = <&tsens3 8>; 8335 8336 trips { 8337 ddrss-critical { 8338 temperature = <125000>; 8339 hysteresis = <1000>; 8340 type = "critical"; 8341 }; 8342 }; 8343 }; 8344 8345 cpuss-1-1-thermal { 8346 thermal-sensors = <&tsens3 9>; 8347 8348 trips { 8349 cpuss1-critical { 8350 temperature = <125000>; 8351 hysteresis = <1000>; 8352 type = "critical"; 8353 }; 8354 }; 8355 }; 8356 }; 8357 8358 timer { 8359 compatible = "arm,armv8-timer"; 8360 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8361 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8362 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8363 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8364 }; 8365}; 8366