1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com> 4 */ 5 6#include <dt-bindings/clock/sophgo,sg2044-pll.h> 7#include <dt-bindings/clock/sophgo,sg2044-clk.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/pinctrl/pinctrl-sg2044.h> 11 12#include "sg2044-cpus.dtsi" 13#include "sg2044-reset.h" 14 15/ { 16 compatible = "sophgo,sg2044"; 17 18 memory@80000000 { 19 device_type = "memory"; 20 reg = <0x00000000 0x80000000 0x00000010 0x00000000>; 21 }; 22 23 osc: oscillator { 24 compatible = "fixed-clock"; 25 clock-output-names = "osc"; 26 #clock-cells = <0>; 27 }; 28 29 soc { 30 compatible = "simple-bus"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 pcie0: pcie@6c00000000 { 36 compatible = "sophgo,sg2044-pcie"; 37 reg = <0x6c 0x00000000 0x0 0x00001000>, 38 <0x6c 0x00300000 0x0 0x00004000>, 39 <0x48 0x00000000 0x0 0x00001000>, 40 <0x6c 0x000c0000 0x0 0x00001000>; 41 reg-names = "dbi", "atu", "config", "app"; 42 #address-cells = <3>; 43 #size-cells = <2>; 44 #interrupt-cells = <1>; 45 clocks = <&clk CLK_GATE_PCIE_1G>; 46 clock-names = "core"; 47 device_type = "pci"; 48 interrupt-map-mask = <0 0 0 7>; 49 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 50 <0 0 0 2 &pcie_intc0 1>, 51 <0 0 0 3 &pcie_intc0 2>, 52 <0 0 0 4 &pcie_intc0 3>; 53 msi-parent = <&msi>; 54 ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00200000>, 55 <0x42000000 0x0 0x10000000 0x0 0x10000000 0x0 0x04000000>, 56 <0x02000000 0x0 0x14000000 0x0 0x14000000 0x0 0x04000000>, 57 <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, 58 <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; 59 status = "disabled"; 60 61 pcie_intc0: interrupt-controller { 62 #address-cells = <0>; 63 #interrupt-cells = <1>; 64 interrupt-parent = <&intc>; 65 interrupts = <65 IRQ_TYPE_LEVEL_HIGH>; 66 interrupt-controller; 67 }; 68 }; 69 70 pcie1: pcie@6c00400000 { 71 compatible = "sophgo,sg2044-pcie"; 72 reg = <0x6c 0x00400000 0x0 0x00001000>, 73 <0x6c 0x00700000 0x0 0x00004000>, 74 <0x40 0x00000000 0x0 0x00001000>, 75 <0x6c 0x00780000 0x0 0x00001000>; 76 reg-names = "dbi", "atu", "config", "app"; 77 #address-cells = <3>; 78 #size-cells = <2>; 79 #interrupt-cells = <1>; 80 clocks = <&clk CLK_GATE_PCIE_1G>; 81 clock-names = "core"; 82 device_type = "pci"; 83 interrupt-map-mask = <0 0 0 7>; 84 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 85 <0 0 0 2 &pcie_intc1 1>, 86 <0 0 0 3 &pcie_intc1 2>, 87 <0 0 0 4 &pcie_intc1 3>; 88 msi-parent = <&msi>; 89 ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00200000>, 90 <0x42000000 0x0 0x00000000 0x0 0x00000000 0x0 0x04000000>, 91 <0x02000000 0x0 0x04000000 0x0 0x04000000 0x0 0x04000000>, 92 <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, 93 <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; 94 status = "disabled"; 95 96 pcie_intc1: interrupt-controller { 97 #address-cells = <0>; 98 #interrupt-cells = <1>; 99 interrupt-parent = <&intc>; 100 interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; 101 interrupt-controller; 102 }; 103 }; 104 105 pcie2: pcie@6c04000000 { 106 compatible = "sophgo,sg2044-pcie"; 107 reg = <0x6c 0x04000000 0x0 0x00001000>, 108 <0x6c 0x04300000 0x0 0x00004000>, 109 <0x58 0x00000000 0x0 0x00001000>, 110 <0x6c 0x040c0000 0x0 0x00001000>; 111 reg-names = "dbi", "atu", "config", "app"; 112 #address-cells = <3>; 113 #size-cells = <2>; 114 #interrupt-cells = <1>; 115 clocks = <&clk CLK_GATE_PCIE_1G>; 116 clock-names = "core"; 117 device_type = "pci"; 118 interrupt-map-mask = <0 0 0 7>; 119 interrupt-map = <0 0 0 1 &pcie_intc2 0>, 120 <0 0 0 2 &pcie_intc2 1>, 121 <0 0 0 3 &pcie_intc2 2>, 122 <0 0 0 4 &pcie_intc2 3>; 123 msi-parent = <&msi>; 124 ranges = <0x01000000 0x0 0x00000000 0x58 0x10000000 0x0 0x00200000>, 125 <0x42000000 0x0 0x30000000 0x0 0x30000000 0x0 0x04000000>, 126 <0x02000000 0x0 0x34000000 0x0 0x34000000 0x0 0x04000000>, 127 <0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>, 128 <0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>; 129 status = "disabled"; 130 131 pcie_intc2: interrupt-controller { 132 #address-cells = <0>; 133 #interrupt-cells = <1>; 134 interrupt-parent = <&intc>; 135 interrupts = <74 IRQ_TYPE_LEVEL_HIGH>; 136 interrupt-controller; 137 }; 138 }; 139 140 pcie3: pcie@6c04400000 { 141 compatible = "sophgo,sg2044-pcie"; 142 reg = <0x6c 0x04400000 0x0 0x00001000>, 143 <0x6c 0x04700000 0x0 0x00004000>, 144 <0x50 0x00000000 0x0 0x00001000>, 145 <0x6c 0x04780000 0x0 0x00001000>; 146 reg-names = "dbi", "atu", "config", "app"; 147 #address-cells = <3>; 148 #size-cells = <2>; 149 #interrupt-cells = <1>; 150 clocks = <&clk CLK_GATE_PCIE_1G>; 151 clock-names = "core"; 152 device_type = "pci"; 153 interrupt-map-mask = <0 0 0 7>; 154 interrupt-map = <0 0 0 1 &pcie_intc3 0>, 155 <0 0 0 2 &pcie_intc3 1>, 156 <0 0 0 3 &pcie_intc3 2>, 157 <0 0 0 4 &pcie_intc3 3>; 158 msi-parent = <&msi>; 159 ranges = <0x01000000 0x0 0x00000000 0x50 0x10000000 0x0 0x00200000>, 160 <0x42000000 0x0 0x20000000 0x0 0x20000000 0x0 0x04000000>, 161 <0x02000000 0x0 0x24000000 0x0 0x24000000 0x0 0x04000000>, 162 <0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>, 163 <0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>; 164 status = "disabled"; 165 166 pcie_intc3: interrupt-controller { 167 #address-cells = <0>; 168 #interrupt-cells = <1>; 169 interrupt-parent = <&intc>; 170 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-controller; 172 }; 173 }; 174 175 pcie4: pcie@6c08400000 { 176 compatible = "sophgo,sg2044-pcie"; 177 reg = <0x6c 0x08400000 0x0 0x00001000>, 178 <0x6c 0x08700000 0x0 0x00004000>, 179 <0x60 0x00000000 0x0 0x00001000>, 180 <0x6c 0x08780000 0x0 0x00001000>; 181 reg-names = "dbi", "atu", "config", "app"; 182 #address-cells = <3>; 183 #size-cells = <2>; 184 #interrupt-cells = <1>; 185 clocks = <&clk CLK_GATE_PCIE_1G>; 186 clock-names = "core"; 187 device_type = "pci"; 188 interrupt-map-mask = <0 0 0 7>; 189 interrupt-map = <0 0 0 1 &pcie_intc4 0>, 190 <0 0 0 2 &pcie_intc4 1>, 191 <0 0 0 3 &pcie_intc4 2>, 192 <0 0 0 4 &pcie_intc4 3>; 193 msi-parent = <&msi>; 194 ranges = <0x01000000 0x0 0x00000000 0x60 0x10000000 0x0 0x00200000>, 195 <0x42000000 0x0 0x40000000 0x0 0x40000000 0x0 0x04000000>, 196 <0x02000000 0x0 0x44000000 0x0 0x44000000 0x0 0x04000000>, 197 <0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>, 198 <0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>; 199 status = "disabled"; 200 201 pcie_intc4: interrupt-controller { 202 #address-cells = <0>; 203 #interrupt-cells = <1>; 204 interrupt-parent = <&intc>; 205 interrupts = <125 IRQ_TYPE_LEVEL_HIGH>; 206 interrupt-controller; 207 }; 208 }; 209 210 msi: msi-controller@6d50000000 { 211 compatible = "sophgo,sg2044-msi"; 212 reg = <0x6d 0x50000000 0x0 0x800>, 213 <0x0 0x7ee00000 0x0 0x40>; 214 reg-names = "clr", "doorbell"; 215 #msi-cells = <0>; 216 msi-controller; 217 msi-ranges = <&intc 352 IRQ_TYPE_EDGE_RISING 512>; 218 status = "disabled"; 219 }; 220 221 spifmc0: spi@7001000000 { 222 compatible = "sophgo,sg2044-spifmc-nor"; 223 reg = <0x70 0x01000000 0x0 0x4000000>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 clocks = <&clk CLK_GATE_AHB_SPIFMC>; 227 interrupt-parent = <&intc>; 228 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 229 resets = <&rst RST_SPIFMC0>; 230 status = "disabled"; 231 }; 232 233 spifmc1: spi@7005000000 { 234 compatible = "sophgo,sg2044-spifmc-nor"; 235 reg = <0x70 0x05000000 0x0 0x4000000>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 clocks = <&clk CLK_GATE_AHB_SPIFMC>; 239 interrupt-parent = <&intc>; 240 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 241 resets = <&rst RST_SPIFMC1>; 242 status = "disabled"; 243 }; 244 245 dmac0: dma-controller@7020000000 { 246 compatible = "snps,axi-dma-1.01a"; 247 reg = <0x70 0x20000000 0x0 0x10000>; 248 #dma-cells = <1>; 249 clock-names = "core-clk", "cfgr-clk"; 250 clocks = <&clk CLK_GATE_SYSDMA_AXI>, 251 <&clk CLK_GATE_SYSDMA_AXI>; 252 dma-noncoherent; 253 interrupt-parent = <&intc>; 254 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 255 dma-channels = <8>; 256 snps,priority = <0 1 2 3 4 5 6 7>; 257 snps,block-size = <4096 4096 4096 4096 258 4096 4096 4096 4096>; 259 snps,dma-masters = <2>; 260 snps,data-width = <2>; 261 snps,axi-max-burst-len = <4>; 262 status = "disabled"; 263 }; 264 265 uart0: serial@7030000000 { 266 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 267 reg = <0x70 0x30000000 0x0 0x1000>; 268 clock-frequency = <500000000>; 269 clocks = <&clk CLK_GATE_UART_500M>, 270 <&clk CLK_GATE_APB_UART>; 271 clock-names = "baudclk", "apb_pclk"; 272 interrupt-parent = <&intc>; 273 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 274 reg-shift = <2>; 275 reg-io-width = <4>; 276 resets = <&rst RST_UART0>; 277 status = "disabled"; 278 }; 279 280 uart1: serial@7030001000 { 281 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 282 reg = <0x70 0x30001000 0x0 0x1000>; 283 clock-frequency = <500000000>; 284 clocks = <&clk CLK_GATE_UART_500M>, 285 <&clk CLK_GATE_APB_UART>; 286 clock-names = "baudclk", "apb_pclk"; 287 interrupt-parent = <&intc>; 288 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 289 reg-shift = <2>; 290 reg-io-width = <4>; 291 resets = <&rst RST_UART1>; 292 status = "disabled"; 293 }; 294 295 uart2: serial@7030002000 { 296 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 297 reg = <0x70 0x30002000 0x0 0x1000>; 298 clock-frequency = <500000000>; 299 clocks = <&clk CLK_GATE_UART_500M>, 300 <&clk CLK_GATE_APB_UART>; 301 clock-names = "baudclk", "apb_pclk"; 302 interrupt-parent = <&intc>; 303 interrupts = <43 IRQ_TYPE_LEVEL_HIGH>; 304 reg-shift = <2>; 305 reg-io-width = <4>; 306 resets = <&rst RST_UART2>; 307 status = "disabled"; 308 }; 309 310 uart3: serial@7030003000 { 311 compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart"; 312 reg = <0x70 0x30003000 0x0 0x1000>; 313 clock-frequency = <500000000>; 314 clocks = <&clk CLK_GATE_UART_500M>, 315 <&clk CLK_GATE_APB_UART>; 316 clock-names = "baudclk", "apb_pclk"; 317 interrupt-parent = <&intc>; 318 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 319 reg-shift = <2>; 320 reg-io-width = <4>; 321 resets = <&rst RST_UART3>; 322 status = "disabled"; 323 }; 324 325 gmac0: ethernet@7030006000 { 326 compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a"; 327 reg = <0x70 0x30006000 0x0 0x4000>; 328 clocks = <&clk CLK_GATE_AXI_ETH0>, 329 <&clk CLK_GATE_PTP_REF_I_ETH0>, 330 <&clk CLK_GATE_TX_ETH0>; 331 clock-names = "stmmaceth", "ptp_ref", "tx"; 332 dma-noncoherent; 333 interrupt-parent = <&intc>; 334 interrupts = <296 IRQ_TYPE_LEVEL_HIGH>; 335 interrupt-names = "macirq"; 336 resets = <&rst RST_ETH0>; 337 reset-names = "stmmaceth"; 338 snps,multicast-filter-bins = <0>; 339 snps,perfect-filter-entries = <1>; 340 snps,aal; 341 snps,tso; 342 snps,txpbl = <32>; 343 snps,rxpbl = <32>; 344 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 345 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 346 snps,axi-config = <&gmac0_stmmac_axi_setup>; 347 status = "disabled"; 348 349 mdio { 350 compatible = "snps,dwmac-mdio"; 351 #address-cells = <1>; 352 #size-cells = <0>; 353 }; 354 355 gmac0_mtl_rx_setup: rx-queues-config { 356 snps,rx-queues-to-use = <8>; 357 snps,rx-sched-wsp; 358 queue0 {}; 359 queue1 {}; 360 queue2 {}; 361 queue3 {}; 362 queue4 {}; 363 queue5 {}; 364 queue6 {}; 365 queue7 {}; 366 }; 367 368 gmac0_mtl_tx_setup: tx-queues-config { 369 snps,tx-queues-to-use = <8>; 370 queue0 {}; 371 queue1 {}; 372 queue2 {}; 373 queue3 {}; 374 queue4 {}; 375 queue5 {}; 376 queue6 {}; 377 queue7 {}; 378 }; 379 380 gmac0_stmmac_axi_setup: stmmac-axi-config { 381 snps,blen = <16 8 4 0 0 0 0>; 382 snps,wr_osr_lmt = <1>; 383 snps,rd_osr_lmt = <2>; 384 }; 385 }; 386 387 emmc: mmc@703000a000 { 388 compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; 389 reg = <0x70 0x3000a000 0x0 0x1000>; 390 clocks = <&clk CLK_GATE_EMMC>, 391 <&clk CLK_GATE_AXI_EMMC>, 392 <&clk CLK_GATE_EMMC_100K>; 393 clock-names = "core", "bus", "timer"; 394 interrupt-parent = <&intc>; 395 interrupts = <298 IRQ_TYPE_LEVEL_HIGH>; 396 status = "disabled"; 397 }; 398 399 sd: mmc@703000b000 { 400 compatible = "sophgo,sg2044-dwcmshc", "sophgo,sg2042-dwcmshc"; 401 reg = <0x70 0x3000b000 0x0 0x1000>; 402 clocks = <&clk CLK_GATE_SD>, 403 <&clk CLK_GATE_AXI_SD>, 404 <&clk CLK_GATE_SD_100K>; 405 clock-names = "core", "bus", "timer"; 406 interrupt-parent = <&intc>; 407 interrupts = <300 IRQ_TYPE_LEVEL_HIGH>; 408 status = "disabled"; 409 }; 410 411 i2c0: i2c@7040005000 { 412 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; 413 reg = <0x70 0x40005000 0x0 0x1000>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 clock-frequency = <100000>; 417 clocks = <&clk CLK_GATE_APB_I2C>; 418 clock-names = "ref"; 419 interrupt-parent = <&intc>; 420 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; 421 resets = <&rst RST_I2C0>; 422 status = "disabled"; 423 }; 424 425 i2c1: i2c@7040006000 { 426 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; 427 reg = <0x70 0x40006000 0x0 0x1000>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clock-frequency = <100000>; 431 clocks = <&clk CLK_GATE_APB_I2C>; 432 clock-names = "ref"; 433 interrupt-parent = <&intc>; 434 interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; 435 resets = <&rst RST_I2C1>; 436 status = "disabled"; 437 }; 438 439 i2c2: i2c@7040007000 { 440 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; 441 reg = <0x70 0x40007000 0x0 0x1000>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 clock-frequency = <100000>; 445 clocks = <&clk CLK_GATE_APB_I2C>; 446 clock-names = "ref"; 447 interrupt-parent = <&intc>; 448 interrupts = <33 IRQ_TYPE_LEVEL_HIGH>; 449 resets = <&rst RST_I2C2>; 450 status = "disabled"; 451 }; 452 453 i2c3: i2c@7040008000 { 454 compatible = "sophgo,sg2044-i2c", "snps,designware-i2c"; 455 reg = <0x70 0x40008000 0x0 0x1000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 clock-frequency = <100000>; 459 clocks = <&clk CLK_GATE_APB_I2C>; 460 clock-names = "ref"; 461 interrupt-parent = <&intc>; 462 interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; 463 resets = <&rst RST_I2C3>; 464 status = "disabled"; 465 }; 466 467 gpio0: gpio@7040009000 { 468 compatible = "snps,dw-apb-gpio"; 469 reg = <0x70 0x40009000 0x0 0x1000>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 clocks = <&clk CLK_GATE_APB_GPIO>, 473 <&clk CLK_GATE_GPIO_DB>; 474 clock-names = "bus", "db"; 475 resets = <&rst RST_GPIO0>; 476 477 porta: gpio-controller@0 { 478 compatible = "snps,dw-apb-gpio-port"; 479 reg = <0>; 480 gpio-controller; 481 #gpio-cells = <2>; 482 ngpios = <32>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 interrupt-parent = <&intc>; 486 interrupts = <26 IRQ_TYPE_LEVEL_HIGH>; 487 }; 488 }; 489 490 gpio1: gpio@704000a000 { 491 compatible = "snps,dw-apb-gpio"; 492 reg = <0x70 0x4000a000 0x0 0x1000>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 clocks = <&clk CLK_GATE_APB_GPIO>, 496 <&clk CLK_GATE_GPIO_DB>; 497 clock-names = "bus", "db"; 498 resets = <&rst RST_GPIO1>; 499 500 portb: gpio-controller@0 { 501 compatible = "snps,dw-apb-gpio-port"; 502 reg = <0>; 503 gpio-controller; 504 #gpio-cells = <2>; 505 ngpios = <32>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 interrupt-parent = <&intc>; 509 interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; 510 }; 511 }; 512 513 gpio2: gpio@704000b000 { 514 compatible = "snps,dw-apb-gpio"; 515 reg = <0x70 0x4000b000 0x0 0x1000>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 clocks = <&clk CLK_GATE_APB_GPIO>, 519 <&clk CLK_GATE_GPIO_DB>; 520 clock-names = "bus", "db"; 521 resets = <&rst RST_GPIO2>; 522 523 portc: gpio-controller@0 { 524 compatible = "snps,dw-apb-gpio-port"; 525 reg = <0>; 526 gpio-controller; 527 #gpio-cells = <2>; 528 ngpios = <32>; 529 interrupt-controller; 530 #interrupt-cells = <2>; 531 interrupt-parent = <&intc>; 532 interrupts = <28 IRQ_TYPE_LEVEL_HIGH>; 533 }; 534 }; 535 536 pwm: pwm@704000c000 { 537 compatible = "sophgo,sg2044-pwm"; 538 reg = <0x70 0x4000c000 0x0 0x1000>; 539 #pwm-cells = <3>; 540 clocks = <&clk CLK_GATE_APB_PWM>; 541 clock-names = "apb"; 542 resets = <&rst RST_PWM>; 543 status = "disabled"; 544 }; 545 546 syscon: syscon@7050000000 { 547 compatible = "sophgo,sg2044-top-syscon", "syscon"; 548 reg = <0x70 0x50000000 0x0 0x1000>; 549 #clock-cells = <1>; 550 clocks = <&osc>; 551 }; 552 553 pinctrl: pinctrl@7050001000 { 554 compatible = "sophgo,sg2044-pinctrl"; 555 reg = <0x70 0x50001000 0x0 0x1000>; 556 }; 557 558 clk: clock-controller@7050002000 { 559 compatible = "sophgo,sg2044-clk"; 560 reg = <0x70 0x50002000 0x0 0x1000>; 561 #clock-cells = <1>; 562 clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>, 563 <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>, 564 <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>, 565 <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>, 566 <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>, 567 <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>, 568 <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>, 569 <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>, 570 <&syscon CLK_MPLL5>; 571 clock-names = "fpll0", "fpll1", "fpll2", "dpll0", 572 "dpll1", "dpll2", "dpll3", "dpll4", 573 "dpll5", "dpll6", "dpll7", "mpll0", 574 "mpll1", "mpll2", "mpll3", "mpll4", 575 "mpll5"; 576 }; 577 578 rst: reset-controller@7050003000 { 579 compatible = "sophgo,sg2044-reset", 580 "sophgo,sg2042-reset"; 581 reg = <0x70 0x50003000 0x0 0x1000>; 582 #reset-cells = <1>; 583 }; 584 }; 585}; 586