1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68 #define SMU11_VOLTAGE_SCALE 4
69
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81
smu_v11_0_poll_baco_exit(struct smu_context * smu)82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
83 {
84 struct amdgpu_device *adev = smu->adev;
85 uint32_t data, loop = 0;
86
87 do {
88 usleep_range(1000, 1100);
89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
90 } while ((data & 0x100) && (++loop < 100));
91 }
92
smu_v11_0_init_microcode(struct smu_context * smu)93 int smu_v11_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[25];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 if (amdgpu_sriov_vf(adev) &&
103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) ||
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7))))
105 return 0;
106
107 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
108 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
109 "amdgpu/%s.bin", ucode_prefix);
110 if (err)
111 goto out;
112
113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
114 amdgpu_ucode_print_smc_hdr(&hdr->header);
115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
120 ucode->fw = adev->pm.fw;
121 header = (const struct common_firmware_header *)ucode->fw->data;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
124 }
125
126 out:
127 if (err)
128 amdgpu_ucode_release(&adev->pm.fw);
129 return err;
130 }
131
smu_v11_0_fini_microcode(struct smu_context * smu)132 void smu_v11_0_fini_microcode(struct smu_context *smu)
133 {
134 struct amdgpu_device *adev = smu->adev;
135
136 amdgpu_ucode_release(&adev->pm.fw);
137 adev->pm.fw_version = 0;
138 }
139
smu_v11_0_load_microcode(struct smu_context * smu)140 int smu_v11_0_load_microcode(struct smu_context *smu)
141 {
142 struct amdgpu_device *adev = smu->adev;
143 const uint32_t *src;
144 const struct smc_firmware_header_v1_0 *hdr;
145 uint32_t addr_start = MP1_SRAM;
146 uint32_t i;
147 uint32_t smc_fw_size;
148 uint32_t mp1_fw_flags;
149
150 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
151 src = (const uint32_t *)(adev->pm.fw->data +
152 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
153 smc_fw_size = hdr->header.ucode_size_bytes;
154
155 for (i = 1; i < smc_fw_size/4 - 1; i++) {
156 WREG32_PCIE(addr_start, src[i]);
157 addr_start += 4;
158 }
159
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
164
165 for (i = 0; i < adev->usec_timeout; i++) {
166 mp1_fw_flags = RREG32_PCIE(MP1_Public |
167 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
168 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
169 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
170 break;
171 udelay(1);
172 }
173
174 if (i == adev->usec_timeout)
175 return -ETIME;
176
177 return 0;
178 }
179
smu_v11_0_check_fw_status(struct smu_context * smu)180 int smu_v11_0_check_fw_status(struct smu_context *smu)
181 {
182 struct amdgpu_device *adev = smu->adev;
183 uint32_t mp1_fw_flags;
184
185 mp1_fw_flags = RREG32_PCIE(MP1_Public |
186 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
187
188 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
189 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
190 return 0;
191
192 return -EIO;
193 }
194
smu_v11_0_check_fw_version(struct smu_context * smu)195 int smu_v11_0_check_fw_version(struct smu_context *smu)
196 {
197 struct amdgpu_device *adev = smu->adev;
198 uint32_t if_version = 0xff, smu_version = 0xff;
199 uint8_t smu_program, smu_major, smu_minor, smu_debug;
200 int ret = 0;
201
202 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
203 if (ret)
204 return ret;
205
206 smu_program = (smu_version >> 24) & 0xff;
207 smu_major = (smu_version >> 16) & 0xff;
208 smu_minor = (smu_version >> 8) & 0xff;
209 smu_debug = (smu_version >> 0) & 0xff;
210 if (smu->is_apu)
211 adev->pm.fw_version = smu_version;
212
213 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
214 case IP_VERSION(11, 0, 0):
215 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
216 break;
217 case IP_VERSION(11, 0, 9):
218 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
219 break;
220 case IP_VERSION(11, 0, 5):
221 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
222 break;
223 case IP_VERSION(11, 0, 7):
224 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
225 break;
226 case IP_VERSION(11, 0, 11):
227 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
228 break;
229 case IP_VERSION(11, 5, 0):
230 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
231 break;
232 case IP_VERSION(11, 0, 12):
233 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
234 break;
235 case IP_VERSION(11, 0, 13):
236 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
237 break;
238 case IP_VERSION(11, 0, 8):
239 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
240 break;
241 case IP_VERSION(11, 0, 2):
242 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
243 break;
244 default:
245 dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
246 amdgpu_ip_version(adev, MP1_HWIP, 0));
247 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
248 break;
249 }
250
251 /*
252 * 1. if_version mismatch is not critical as our fw is designed
253 * to be backward compatible.
254 * 2. New fw usually brings some optimizations. But that's visible
255 * only on the paired driver.
256 * Considering above, we just leave user a verbal message instead
257 * of halt driver loading.
258 */
259 if (if_version != smu->smc_driver_if_version) {
260 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
261 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
262 smu->smc_driver_if_version, if_version,
263 smu_program, smu_version, smu_major, smu_minor, smu_debug);
264 dev_info(smu->adev->dev, "SMU driver if version not matched\n");
265 }
266
267 return ret;
268 }
269
smu_v11_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)270 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
271 {
272 struct amdgpu_device *adev = smu->adev;
273 uint32_t ppt_offset_bytes;
274 const struct smc_firmware_header_v2_0 *v2;
275
276 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
277
278 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
279 *size = le32_to_cpu(v2->ppt_size_bytes);
280 *table = (uint8_t *)v2 + ppt_offset_bytes;
281
282 return 0;
283 }
284
smu_v11_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)285 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
286 uint32_t *size, uint32_t pptable_id)
287 {
288 struct amdgpu_device *adev = smu->adev;
289 const struct smc_firmware_header_v2_1 *v2_1;
290 struct smc_soft_pptable_entry *entries;
291 uint32_t pptable_count = 0;
292 int i = 0;
293
294 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
295 entries = (struct smc_soft_pptable_entry *)
296 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
297 pptable_count = le32_to_cpu(v2_1->pptable_count);
298 for (i = 0; i < pptable_count; i++) {
299 if (le32_to_cpu(entries[i].id) == pptable_id) {
300 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
301 *size = le32_to_cpu(entries[i].ppt_size_bytes);
302 break;
303 }
304 }
305
306 if (i == pptable_count)
307 return -EINVAL;
308
309 return 0;
310 }
311
smu_v11_0_setup_pptable(struct smu_context * smu)312 int smu_v11_0_setup_pptable(struct smu_context *smu)
313 {
314 struct amdgpu_device *adev = smu->adev;
315 const struct smc_firmware_header_v1_0 *hdr;
316 int ret, index;
317 uint32_t size = 0;
318 uint16_t atom_table_size;
319 uint8_t frev, crev;
320 void *table;
321 uint16_t version_major, version_minor;
322
323 if (!amdgpu_sriov_vf(adev)) {
324 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
325 version_major = le16_to_cpu(hdr->header.header_version_major);
326 version_minor = le16_to_cpu(hdr->header.header_version_minor);
327 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
328 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
329 switch (version_minor) {
330 case 0:
331 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
332 break;
333 case 1:
334 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
335 smu->smu_table.boot_values.pp_table_id);
336 break;
337 default:
338 ret = -EINVAL;
339 break;
340 }
341 if (ret)
342 return ret;
343 goto out;
344 }
345 }
346
347 dev_info(adev->dev, "use vbios provided pptable\n");
348 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
349 powerplayinfo);
350
351 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
352 (uint8_t **)&table);
353 if (ret)
354 return ret;
355 size = atom_table_size;
356
357 out:
358 if (!smu->smu_table.power_play_table)
359 smu->smu_table.power_play_table = table;
360 if (!smu->smu_table.power_play_table_size)
361 smu->smu_table.power_play_table_size = size;
362
363 return 0;
364 }
365
smu_v11_0_init_smc_tables(struct smu_context * smu)366 int smu_v11_0_init_smc_tables(struct smu_context *smu)
367 {
368 struct smu_table_context *smu_table = &smu->smu_table;
369 struct smu_table *tables = smu_table->tables;
370 int ret = 0;
371
372 smu_table->driver_pptable =
373 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
374 if (!smu_table->driver_pptable) {
375 ret = -ENOMEM;
376 goto err0_out;
377 }
378
379 smu_table->max_sustainable_clocks =
380 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
381 if (!smu_table->max_sustainable_clocks) {
382 ret = -ENOMEM;
383 goto err1_out;
384 }
385
386 /* Arcturus does not support OVERDRIVE */
387 if (tables[SMU_TABLE_OVERDRIVE].size) {
388 smu_table->overdrive_table =
389 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
390 if (!smu_table->overdrive_table) {
391 ret = -ENOMEM;
392 goto err2_out;
393 }
394
395 smu_table->boot_overdrive_table =
396 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
397 if (!smu_table->boot_overdrive_table) {
398 ret = -ENOMEM;
399 goto err3_out;
400 }
401
402 smu_table->user_overdrive_table =
403 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
404 if (!smu_table->user_overdrive_table) {
405 ret = -ENOMEM;
406 goto err4_out;
407 }
408
409 }
410
411 return 0;
412
413 err4_out:
414 kfree(smu_table->boot_overdrive_table);
415 err3_out:
416 kfree(smu_table->overdrive_table);
417 err2_out:
418 kfree(smu_table->max_sustainable_clocks);
419 err1_out:
420 kfree(smu_table->driver_pptable);
421 err0_out:
422 return ret;
423 }
424
smu_v11_0_fini_smc_tables(struct smu_context * smu)425 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
426 {
427 struct smu_table_context *smu_table = &smu->smu_table;
428 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
429
430 kfree(smu_table->gpu_metrics_table);
431 kfree(smu_table->user_overdrive_table);
432 kfree(smu_table->boot_overdrive_table);
433 kfree(smu_table->overdrive_table);
434 kfree(smu_table->max_sustainable_clocks);
435 kfree(smu_table->driver_pptable);
436 kfree(smu_table->clocks_table);
437 smu_table->gpu_metrics_table = NULL;
438 smu_table->user_overdrive_table = NULL;
439 smu_table->boot_overdrive_table = NULL;
440 smu_table->overdrive_table = NULL;
441 smu_table->max_sustainable_clocks = NULL;
442 smu_table->driver_pptable = NULL;
443 smu_table->clocks_table = NULL;
444 kfree(smu_table->hardcode_pptable);
445 smu_table->hardcode_pptable = NULL;
446
447 kfree(smu_table->driver_smu_config_table);
448 kfree(smu_table->ecc_table);
449 kfree(smu_table->metrics_table);
450 kfree(smu_table->watermarks_table);
451 smu_table->driver_smu_config_table = NULL;
452 smu_table->ecc_table = NULL;
453 smu_table->metrics_table = NULL;
454 smu_table->watermarks_table = NULL;
455 smu_table->metrics_time = 0;
456
457 kfree(smu_dpm->dpm_context);
458 kfree(smu_dpm->golden_dpm_context);
459 kfree(smu_dpm->dpm_current_power_state);
460 kfree(smu_dpm->dpm_request_power_state);
461 smu_dpm->dpm_context = NULL;
462 smu_dpm->golden_dpm_context = NULL;
463 smu_dpm->dpm_context_size = 0;
464 smu_dpm->dpm_current_power_state = NULL;
465 smu_dpm->dpm_request_power_state = NULL;
466
467 return 0;
468 }
469
smu_v11_0_init_power(struct smu_context * smu)470 int smu_v11_0_init_power(struct smu_context *smu)
471 {
472 struct amdgpu_device *adev = smu->adev;
473 struct smu_power_context *smu_power = &smu->smu_power;
474 size_t size = amdgpu_ip_version(adev, MP1_HWIP, 0) ==
475 IP_VERSION(11, 5, 0) ?
476 sizeof(struct smu_11_5_power_context) :
477 sizeof(struct smu_11_0_power_context);
478
479 smu_power->power_context = kzalloc(size, GFP_KERNEL);
480 if (!smu_power->power_context)
481 return -ENOMEM;
482 smu_power->power_context_size = size;
483
484 return 0;
485 }
486
smu_v11_0_fini_power(struct smu_context * smu)487 int smu_v11_0_fini_power(struct smu_context *smu)
488 {
489 struct smu_power_context *smu_power = &smu->smu_power;
490
491 kfree(smu_power->power_context);
492 smu_power->power_context = NULL;
493 smu_power->power_context_size = 0;
494
495 return 0;
496 }
497
smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)498 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
499 uint8_t clk_id,
500 uint8_t syspll_id,
501 uint32_t *clk_freq)
502 {
503 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
504 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
505 int ret, index;
506
507 input.clk_id = clk_id;
508 input.syspll_id = syspll_id;
509 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
510 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
511 getsmuclockinfo);
512
513 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
514 (uint32_t *)&input, sizeof(input));
515 if (ret)
516 return -EINVAL;
517
518 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
519 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
520
521 return 0;
522 }
523
smu_v11_0_get_vbios_bootup_values(struct smu_context * smu)524 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
525 {
526 int ret, index;
527 uint16_t size;
528 uint8_t frev, crev;
529 struct atom_common_table_header *header;
530 struct atom_firmware_info_v3_3 *v_3_3;
531 struct atom_firmware_info_v3_1 *v_3_1;
532
533 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
534 firmwareinfo);
535
536 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
537 (uint8_t **)&header);
538 if (ret)
539 return ret;
540
541 if (header->format_revision != 3) {
542 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
543 return -EINVAL;
544 }
545
546 switch (header->content_revision) {
547 case 0:
548 case 1:
549 case 2:
550 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
551 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
552 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
553 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
554 smu->smu_table.boot_values.socclk = 0;
555 smu->smu_table.boot_values.dcefclk = 0;
556 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
557 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
558 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
559 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
560 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
561 smu->smu_table.boot_values.pp_table_id = 0;
562 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
563 break;
564 case 3:
565 case 4:
566 default:
567 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
568 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
569 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
570 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
571 smu->smu_table.boot_values.socclk = 0;
572 smu->smu_table.boot_values.dcefclk = 0;
573 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
574 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
575 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
576 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
577 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
578 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
579 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
580 }
581
582 smu->smu_table.boot_values.format_revision = header->format_revision;
583 smu->smu_table.boot_values.content_revision = header->content_revision;
584
585 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
586 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
587 (uint8_t)0,
588 &smu->smu_table.boot_values.socclk);
589
590 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
591 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
592 (uint8_t)0,
593 &smu->smu_table.boot_values.dcefclk);
594
595 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
596 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
597 (uint8_t)0,
598 &smu->smu_table.boot_values.eclk);
599
600 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
601 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
602 (uint8_t)0,
603 &smu->smu_table.boot_values.vclk);
604
605 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
606 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
607 (uint8_t)0,
608 &smu->smu_table.boot_values.dclk);
609
610 if ((smu->smu_table.boot_values.format_revision == 3) &&
611 (smu->smu_table.boot_values.content_revision >= 2))
612 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
613 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
614 (uint8_t)SMU11_SYSPLL1_2_ID,
615 &smu->smu_table.boot_values.fclk);
616
617 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
618 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
619 (uint8_t)SMU11_SYSPLL3_1_ID,
620 &smu->smu_table.boot_values.lclk);
621
622 return 0;
623 }
624
smu_v11_0_notify_memory_pool_location(struct smu_context * smu)625 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
626 {
627 struct smu_table_context *smu_table = &smu->smu_table;
628 struct smu_table *memory_pool = &smu_table->memory_pool;
629 int ret = 0;
630 uint64_t address;
631 uint32_t address_low, address_high;
632
633 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
634 return ret;
635
636 address = (uintptr_t)memory_pool->cpu_addr;
637 address_high = (uint32_t)upper_32_bits(address);
638 address_low = (uint32_t)lower_32_bits(address);
639
640 ret = smu_cmn_send_smc_msg_with_param(smu,
641 SMU_MSG_SetSystemVirtualDramAddrHigh,
642 address_high,
643 NULL);
644 if (ret)
645 return ret;
646 ret = smu_cmn_send_smc_msg_with_param(smu,
647 SMU_MSG_SetSystemVirtualDramAddrLow,
648 address_low,
649 NULL);
650 if (ret)
651 return ret;
652
653 address = memory_pool->mc_address;
654 address_high = (uint32_t)upper_32_bits(address);
655 address_low = (uint32_t)lower_32_bits(address);
656
657 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
658 address_high, NULL);
659 if (ret)
660 return ret;
661 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
662 address_low, NULL);
663 if (ret)
664 return ret;
665 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
666 (uint32_t)memory_pool->size, NULL);
667 if (ret)
668 return ret;
669
670 return ret;
671 }
672
smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)673 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
674 {
675 int ret;
676
677 ret = smu_cmn_send_smc_msg_with_param(smu,
678 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
679 if (ret)
680 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
681
682 return ret;
683 }
684
smu_v11_0_set_driver_table_location(struct smu_context * smu)685 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
686 {
687 struct smu_table *driver_table = &smu->smu_table.driver_table;
688 int ret = 0;
689
690 if (driver_table->mc_address) {
691 ret = smu_cmn_send_smc_msg_with_param(smu,
692 SMU_MSG_SetDriverDramAddrHigh,
693 upper_32_bits(driver_table->mc_address),
694 NULL);
695 if (!ret)
696 ret = smu_cmn_send_smc_msg_with_param(smu,
697 SMU_MSG_SetDriverDramAddrLow,
698 lower_32_bits(driver_table->mc_address),
699 NULL);
700 }
701
702 return ret;
703 }
704
smu_v11_0_set_tool_table_location(struct smu_context * smu)705 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
706 {
707 int ret = 0;
708 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
709
710 if (tool_table->mc_address) {
711 ret = smu_cmn_send_smc_msg_with_param(smu,
712 SMU_MSG_SetToolsDramAddrHigh,
713 upper_32_bits(tool_table->mc_address),
714 NULL);
715 if (!ret)
716 ret = smu_cmn_send_smc_msg_with_param(smu,
717 SMU_MSG_SetToolsDramAddrLow,
718 lower_32_bits(tool_table->mc_address),
719 NULL);
720 }
721
722 return ret;
723 }
724
smu_v11_0_init_display_count(struct smu_context * smu,uint32_t count)725 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
726 {
727 struct amdgpu_device *adev = smu->adev;
728
729 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
730 * display num currently
731 */
732 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) ||
733 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
734 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) ||
735 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
736 return 0;
737
738 return smu_cmn_send_smc_msg_with_param(smu,
739 SMU_MSG_NumOfDisplays,
740 count,
741 NULL);
742 }
743
744
smu_v11_0_set_allowed_mask(struct smu_context * smu)745 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
746 {
747 struct smu_feature *feature = &smu->smu_feature;
748 int ret = 0;
749 uint32_t feature_mask[2];
750
751 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64) {
752 ret = -EINVAL;
753 goto failed;
754 }
755
756 bitmap_to_arr32(feature_mask, feature->allowed, 64);
757
758 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
759 feature_mask[1], NULL);
760 if (ret)
761 goto failed;
762
763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
764 feature_mask[0], NULL);
765 if (ret)
766 goto failed;
767
768 failed:
769 return ret;
770 }
771
smu_v11_0_system_features_control(struct smu_context * smu,bool en)772 int smu_v11_0_system_features_control(struct smu_context *smu,
773 bool en)
774 {
775 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
776 SMU_MSG_DisableAllSmuFeatures), NULL);
777 }
778
smu_v11_0_notify_display_change(struct smu_context * smu)779 int smu_v11_0_notify_display_change(struct smu_context *smu)
780 {
781 int ret = 0;
782
783 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
784 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
785 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
786
787 return ret;
788 }
789
790 static int
smu_v11_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)791 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
792 enum smu_clk_type clock_select)
793 {
794 int ret = 0;
795 int clk_id;
796
797 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
798 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
799 return 0;
800
801 clk_id = smu_cmn_to_asic_specific_index(smu,
802 CMN2ASIC_MAPPING_CLK,
803 clock_select);
804 if (clk_id < 0)
805 return -EINVAL;
806
807 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
808 clk_id << 16, clock);
809 if (ret) {
810 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
811 return ret;
812 }
813
814 if (*clock != 0)
815 return 0;
816
817 /* if DC limit is zero, return AC limit */
818 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
819 clk_id << 16, clock);
820 if (ret) {
821 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
822 return ret;
823 }
824
825 return 0;
826 }
827
smu_v11_0_init_max_sustainable_clocks(struct smu_context * smu)828 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
829 {
830 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
831 smu->smu_table.max_sustainable_clocks;
832 int ret = 0;
833
834 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
835 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
836 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
837 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
838 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
839 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
840
841 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
842 ret = smu_v11_0_get_max_sustainable_clock(smu,
843 &(max_sustainable_clocks->uclock),
844 SMU_UCLK);
845 if (ret) {
846 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
847 __func__);
848 return ret;
849 }
850 }
851
852 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
853 ret = smu_v11_0_get_max_sustainable_clock(smu,
854 &(max_sustainable_clocks->soc_clock),
855 SMU_SOCCLK);
856 if (ret) {
857 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
858 __func__);
859 return ret;
860 }
861 }
862
863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
864 ret = smu_v11_0_get_max_sustainable_clock(smu,
865 &(max_sustainable_clocks->dcef_clock),
866 SMU_DCEFCLK);
867 if (ret) {
868 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
869 __func__);
870 return ret;
871 }
872
873 ret = smu_v11_0_get_max_sustainable_clock(smu,
874 &(max_sustainable_clocks->display_clock),
875 SMU_DISPCLK);
876 if (ret) {
877 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
878 __func__);
879 return ret;
880 }
881 ret = smu_v11_0_get_max_sustainable_clock(smu,
882 &(max_sustainable_clocks->phy_clock),
883 SMU_PHYCLK);
884 if (ret) {
885 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
886 __func__);
887 return ret;
888 }
889 ret = smu_v11_0_get_max_sustainable_clock(smu,
890 &(max_sustainable_clocks->pixel_clock),
891 SMU_PIXCLK);
892 if (ret) {
893 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
894 __func__);
895 return ret;
896 }
897 }
898
899 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
900 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
901
902 return 0;
903 }
904
smu_v11_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)905 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
906 uint32_t *power_limit)
907 {
908 int power_src;
909 int ret = 0;
910
911 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
912 return -EINVAL;
913
914 power_src = smu_cmn_to_asic_specific_index(smu,
915 CMN2ASIC_MAPPING_PWR,
916 smu->adev->pm.ac_power ?
917 SMU_POWER_SOURCE_AC :
918 SMU_POWER_SOURCE_DC);
919 if (power_src < 0)
920 return -EINVAL;
921
922 /*
923 * BIT 24-31: ControllerId (only PPT0 is supported for now)
924 * BIT 16-23: PowerSource
925 */
926 ret = smu_cmn_send_smc_msg_with_param(smu,
927 SMU_MSG_GetPptLimit,
928 (0 << 24) | (power_src << 16),
929 power_limit);
930 if (ret)
931 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
932
933 return ret;
934 }
935
smu_v11_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)936 int smu_v11_0_set_power_limit(struct smu_context *smu,
937 enum smu_ppt_limit_type limit_type,
938 uint32_t limit)
939 {
940 int power_src;
941 int ret = 0;
942 uint32_t limit_param;
943
944 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
945 return -EINVAL;
946
947 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
948 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
949 return -EOPNOTSUPP;
950 }
951
952 power_src = smu_cmn_to_asic_specific_index(smu,
953 CMN2ASIC_MAPPING_PWR,
954 smu->adev->pm.ac_power ?
955 SMU_POWER_SOURCE_AC :
956 SMU_POWER_SOURCE_DC);
957 if (power_src < 0)
958 return -EINVAL;
959
960 /*
961 * BIT 24-31: ControllerId (only PPT0 is supported for now)
962 * BIT 16-23: PowerSource
963 * BIT 0-15: PowerLimit
964 */
965 limit_param = (limit & 0xFFFF);
966 limit_param |= 0 << 24;
967 limit_param |= (power_src) << 16;
968 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
969 if (ret) {
970 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
971 return ret;
972 }
973
974 smu->current_power_limit = limit;
975
976 return 0;
977 }
978
smu_v11_0_ack_ac_dc_interrupt(struct smu_context * smu)979 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
980 {
981 return smu_cmn_send_smc_msg(smu,
982 SMU_MSG_ReenableAcDcInterrupt,
983 NULL);
984 }
985
smu_v11_0_process_pending_interrupt(struct smu_context * smu)986 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
987 {
988 int ret = 0;
989
990 if (smu->dc_controlled_by_gpio &&
991 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
992 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
993
994 return ret;
995 }
996
smu_v11_0_interrupt_work(struct smu_context * smu)997 void smu_v11_0_interrupt_work(struct smu_context *smu)
998 {
999 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1000 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1001 }
1002
smu_v11_0_enable_thermal_alert(struct smu_context * smu)1003 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1004 {
1005 int ret = 0;
1006
1007 if (smu->smu_table.thermal_controller_type) {
1008 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1009 if (ret)
1010 return ret;
1011 }
1012
1013 /*
1014 * After init there might have been missed interrupts triggered
1015 * before driver registers for interrupt (Ex. AC/DC).
1016 */
1017 return smu_v11_0_process_pending_interrupt(smu);
1018 }
1019
smu_v11_0_disable_thermal_alert(struct smu_context * smu)1020 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1021 {
1022 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1023 }
1024
convert_to_vddc(uint8_t vid)1025 static uint16_t convert_to_vddc(uint8_t vid)
1026 {
1027 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1028 }
1029
smu_v11_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1030 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1031 {
1032 struct amdgpu_device *adev = smu->adev;
1033 uint32_t vdd = 0, val_vid = 0;
1034
1035 if (!value)
1036 return -EINVAL;
1037 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1038 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1039 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1040
1041 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1042
1043 *value = vdd;
1044
1045 return 0;
1046
1047 }
1048
1049 int
smu_v11_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1050 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1051 struct pp_display_clock_request
1052 *clock_req)
1053 {
1054 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1055 int ret = 0;
1056 enum smu_clk_type clk_select = 0;
1057 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1058
1059 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1060 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1061 switch (clk_type) {
1062 case amd_pp_dcef_clock:
1063 clk_select = SMU_DCEFCLK;
1064 break;
1065 case amd_pp_disp_clock:
1066 clk_select = SMU_DISPCLK;
1067 break;
1068 case amd_pp_pixel_clock:
1069 clk_select = SMU_PIXCLK;
1070 break;
1071 case amd_pp_phy_clock:
1072 clk_select = SMU_PHYCLK;
1073 break;
1074 case amd_pp_mem_clock:
1075 clk_select = SMU_UCLK;
1076 break;
1077 default:
1078 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1079 ret = -EINVAL;
1080 break;
1081 }
1082
1083 if (ret)
1084 goto failed;
1085
1086 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1087 return 0;
1088
1089 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1090
1091 if(clk_select == SMU_UCLK)
1092 smu->hard_min_uclk_req_from_dal = clk_freq;
1093 }
1094
1095 failed:
1096 return ret;
1097 }
1098
smu_v11_0_gfx_off_control(struct smu_context * smu,bool enable)1099 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1100 {
1101 int ret = 0;
1102 struct amdgpu_device *adev = smu->adev;
1103
1104 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1105 case IP_VERSION(11, 0, 0):
1106 case IP_VERSION(11, 0, 5):
1107 case IP_VERSION(11, 0, 9):
1108 case IP_VERSION(11, 0, 7):
1109 case IP_VERSION(11, 0, 11):
1110 case IP_VERSION(11, 0, 12):
1111 case IP_VERSION(11, 0, 13):
1112 case IP_VERSION(11, 5, 0):
1113 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1114 return 0;
1115 if (enable)
1116 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1117 else
1118 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1119 break;
1120 default:
1121 break;
1122 }
1123
1124 return ret;
1125 }
1126
1127 uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context * smu)1128 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1129 {
1130 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1131 return AMD_FAN_CTRL_AUTO;
1132 else
1133 return smu->user_dpm_profile.fan_mode;
1134 }
1135
1136 static int
smu_v11_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1137 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1138 {
1139 int ret = 0;
1140
1141 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1142 return 0;
1143
1144 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1145 if (ret)
1146 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1147 __func__, (auto_fan_control ? "Start" : "Stop"));
1148
1149 return ret;
1150 }
1151
1152 static int
smu_v11_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1153 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1154 {
1155 struct amdgpu_device *adev = smu->adev;
1156
1157 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1158 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1159 CG_FDO_CTRL2, TMIN, 0));
1160 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1161 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1162 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1163
1164 return 0;
1165 }
1166
1167 int
smu_v11_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1168 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1169 {
1170 struct amdgpu_device *adev = smu->adev;
1171 uint32_t duty100, duty;
1172 uint64_t tmp64;
1173
1174 speed = min_t(uint32_t, speed, 255);
1175
1176 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1177 CG_FDO_CTRL1, FMAX_DUTY100);
1178 if (!duty100)
1179 return -EINVAL;
1180
1181 tmp64 = (uint64_t)speed * duty100;
1182 do_div(tmp64, 255);
1183 duty = (uint32_t)tmp64;
1184
1185 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1186 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1187 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1188
1189 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1190 }
1191
smu_v11_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1192 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1193 uint32_t speed)
1194 {
1195 struct amdgpu_device *adev = smu->adev;
1196 /*
1197 * crystal_clock_freq used for fan speed rpm calculation is
1198 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1199 */
1200 uint32_t crystal_clock_freq = 2500;
1201 uint32_t tach_period;
1202
1203 if (speed == 0)
1204 return -EINVAL;
1205 /*
1206 * To prevent from possible overheat, some ASICs may have requirement
1207 * for minimum fan speed:
1208 * - For some NV10 SKU, the fan speed cannot be set lower than
1209 * 700 RPM.
1210 * - For some Sienna Cichlid SKU, the fan speed cannot be set
1211 * lower than 500 RPM.
1212 */
1213 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1214 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1215 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1216 CG_TACH_CTRL, TARGET_PERIOD,
1217 tach_period));
1218
1219 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1220 }
1221
smu_v11_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1222 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1223 uint32_t *speed)
1224 {
1225 struct amdgpu_device *adev = smu->adev;
1226 uint32_t duty100, duty;
1227 uint64_t tmp64;
1228
1229 /*
1230 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1231 * detected via register retrieving. To workaround this, we will
1232 * report the fan speed as 0 PWM if user just requested such.
1233 */
1234 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1235 && !smu->user_dpm_profile.fan_speed_pwm) {
1236 *speed = 0;
1237 return 0;
1238 }
1239
1240 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1241 CG_FDO_CTRL1, FMAX_DUTY100);
1242 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1243 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1244 if (!duty100)
1245 return -EINVAL;
1246
1247 tmp64 = (uint64_t)duty * 255;
1248 do_div(tmp64, duty100);
1249 *speed = min_t(uint32_t, tmp64, 255);
1250
1251 return 0;
1252 }
1253
smu_v11_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1254 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1255 uint32_t *speed)
1256 {
1257 struct amdgpu_device *adev = smu->adev;
1258 uint32_t crystal_clock_freq = 2500;
1259 uint32_t tach_status;
1260 uint64_t tmp64;
1261
1262 /*
1263 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1264 * detected via register retrieving. To workaround this, we will
1265 * report the fan speed as 0 RPM if user just requested such.
1266 */
1267 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1268 && !smu->user_dpm_profile.fan_speed_rpm) {
1269 *speed = 0;
1270 return 0;
1271 }
1272
1273 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1274
1275 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
1276 if (tach_status) {
1277 do_div(tmp64, tach_status);
1278 *speed = (uint32_t)tmp64;
1279 } else {
1280 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
1281 *speed = 0;
1282 }
1283
1284 return 0;
1285 }
1286
1287 int
smu_v11_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1288 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1289 uint32_t mode)
1290 {
1291 int ret = 0;
1292
1293 switch (mode) {
1294 case AMD_FAN_CTRL_NONE:
1295 ret = smu_v11_0_auto_fan_control(smu, 0);
1296 if (!ret)
1297 ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1298 break;
1299 case AMD_FAN_CTRL_MANUAL:
1300 ret = smu_v11_0_auto_fan_control(smu, 0);
1301 break;
1302 case AMD_FAN_CTRL_AUTO:
1303 ret = smu_v11_0_auto_fan_control(smu, 1);
1304 break;
1305 default:
1306 break;
1307 }
1308
1309 if (ret) {
1310 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1311 return -EINVAL;
1312 }
1313
1314 return ret;
1315 }
1316
smu_v11_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1317 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1318 uint32_t pstate)
1319 {
1320 return smu_cmn_send_smc_msg_with_param(smu,
1321 SMU_MSG_SetXgmiMode,
1322 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1323 NULL);
1324 }
1325
smu_v11_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1326 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1327 struct amdgpu_irq_src *source,
1328 unsigned tyep,
1329 enum amdgpu_interrupt_state state)
1330 {
1331 struct smu_context *smu = adev->powerplay.pp_handle;
1332 uint32_t low, high;
1333 uint32_t val = 0;
1334
1335 switch (state) {
1336 case AMDGPU_IRQ_STATE_DISABLE:
1337 /* For THM irqs */
1338 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1339 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1340 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1341 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1342
1343 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1344
1345 /* For MP1 SW irqs */
1346 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1347 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1348 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1349
1350 break;
1351 case AMDGPU_IRQ_STATE_ENABLE:
1352 /* For THM irqs */
1353 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1354 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1355 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1356 smu->thermal_range.software_shutdown_temp);
1357
1358 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1359 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1360 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1361 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1362 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1363 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1364 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1365 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1366 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1367
1368 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1369 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1370 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1371 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1372
1373 /* For MP1 SW irqs */
1374 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1375 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1376 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1377 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1378
1379 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1380 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1381 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1382
1383 break;
1384 default:
1385 break;
1386 }
1387
1388 return 0;
1389 }
1390
1391 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1392 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1393
1394 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1395
smu_v11_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1396 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1397 struct amdgpu_irq_src *source,
1398 struct amdgpu_iv_entry *entry)
1399 {
1400 struct smu_context *smu = adev->powerplay.pp_handle;
1401 uint32_t client_id = entry->client_id;
1402 uint32_t src_id = entry->src_id;
1403 /*
1404 * ctxid is used to distinguish different
1405 * events for SMCToHost interrupt.
1406 */
1407 uint32_t ctxid = entry->src_data[0];
1408 uint32_t data;
1409
1410 if (client_id == SOC15_IH_CLIENTID_THM) {
1411 switch (src_id) {
1412 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1413 schedule_delayed_work(&smu->swctf_delayed_work,
1414 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1415 break;
1416 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1417 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1418 break;
1419 default:
1420 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1421 src_id);
1422 break;
1423 }
1424 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1425 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1426 /*
1427 * HW CTF just occurred. Shutdown to prevent further damage.
1428 */
1429 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1430 orderly_poweroff(true);
1431 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1432 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1433 /* ACK SMUToHost interrupt */
1434 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1435 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1436 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1437
1438 switch (ctxid) {
1439 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1440 dev_dbg(adev->dev, "Switched to AC mode!\n");
1441 schedule_work(&smu->interrupt_work);
1442 adev->pm.ac_power = true;
1443 break;
1444 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1445 dev_dbg(adev->dev, "Switched to DC mode!\n");
1446 schedule_work(&smu->interrupt_work);
1447 adev->pm.ac_power = false;
1448 break;
1449 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1450 /*
1451 * Increment the throttle interrupt counter
1452 */
1453 atomic64_inc(&smu->throttle_int_counter);
1454
1455 if (!atomic_read(&adev->throttling_logging_enabled))
1456 return 0;
1457
1458 if (__ratelimit(&adev->throttling_logging_rs))
1459 schedule_work(&smu->throttling_logging_work);
1460
1461 break;
1462 default:
1463 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1464 ctxid, client_id);
1465 break;
1466 }
1467 }
1468 }
1469
1470 return 0;
1471 }
1472
1473 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1474 {
1475 .set = smu_v11_0_set_irq_state,
1476 .process = smu_v11_0_irq_process,
1477 };
1478
smu_v11_0_register_irq_handler(struct smu_context * smu)1479 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1480 {
1481 struct amdgpu_device *adev = smu->adev;
1482 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1483 int ret = 0;
1484
1485 irq_src->num_types = 1;
1486 irq_src->funcs = &smu_v11_0_irq_funcs;
1487
1488 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1489 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1490 irq_src);
1491 if (ret)
1492 return ret;
1493
1494 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1495 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1496 irq_src);
1497 if (ret)
1498 return ret;
1499
1500 /* Register CTF(GPIO_19) interrupt */
1501 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1502 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1503 irq_src);
1504 if (ret)
1505 return ret;
1506
1507 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1508 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1509 irq_src);
1510 if (ret)
1511 return ret;
1512
1513 return ret;
1514 }
1515
smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1516 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1517 struct pp_smu_nv_clock_table *max_clocks)
1518 {
1519 struct smu_table_context *table_context = &smu->smu_table;
1520 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1521
1522 if (!max_clocks || !table_context->max_sustainable_clocks)
1523 return -EINVAL;
1524
1525 sustainable_clocks = table_context->max_sustainable_clocks;
1526
1527 max_clocks->dcfClockInKhz =
1528 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1529 max_clocks->displayClockInKhz =
1530 (unsigned int) sustainable_clocks->display_clock * 1000;
1531 max_clocks->phyClockInKhz =
1532 (unsigned int) sustainable_clocks->phy_clock * 1000;
1533 max_clocks->pixelClockInKhz =
1534 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1535 max_clocks->uClockInKhz =
1536 (unsigned int) sustainable_clocks->uclock * 1000;
1537 max_clocks->socClockInKhz =
1538 (unsigned int) sustainable_clocks->soc_clock * 1000;
1539 max_clocks->dscClockInKhz = 0;
1540 max_clocks->dppClockInKhz = 0;
1541 max_clocks->fabricClockInKhz = 0;
1542
1543 return 0;
1544 }
1545
smu_v11_0_set_azalia_d3_pme(struct smu_context * smu)1546 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1547 {
1548 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1549 }
1550
smu_v11_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1551 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1552 enum smu_baco_seq baco_seq)
1553 {
1554 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1555 }
1556
smu_v11_0_get_bamaco_support(struct smu_context * smu)1557 int smu_v11_0_get_bamaco_support(struct smu_context *smu)
1558 {
1559 struct smu_baco_context *smu_baco = &smu->smu_baco;
1560 int bamaco_support = 0;
1561
1562 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1563 return 0;
1564
1565 if (smu_baco->maco_support)
1566 bamaco_support |= MACO_SUPPORT;
1567
1568 /* return true if ASIC is in BACO state already */
1569 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1570 return bamaco_support |= BACO_SUPPORT;
1571
1572 /* Arcturus does not support this bit mask */
1573 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1574 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1575 return 0;
1576
1577 return (bamaco_support |= BACO_SUPPORT);
1578 }
1579
smu_v11_0_baco_get_state(struct smu_context * smu)1580 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1581 {
1582 struct smu_baco_context *smu_baco = &smu->smu_baco;
1583
1584 return smu_baco->state;
1585 }
1586
1587 #define D3HOT_BACO_SEQUENCE 0
1588 #define D3HOT_BAMACO_SEQUENCE 2
1589
smu_v11_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1590 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1591 {
1592 struct smu_baco_context *smu_baco = &smu->smu_baco;
1593 struct amdgpu_device *adev = smu->adev;
1594 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1595 uint32_t data;
1596 int ret = 0;
1597
1598 if (smu_v11_0_baco_get_state(smu) == state)
1599 return 0;
1600
1601 if (state == SMU_BACO_STATE_ENTER) {
1602 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1603 case IP_VERSION(11, 0, 7):
1604 case IP_VERSION(11, 0, 11):
1605 case IP_VERSION(11, 0, 12):
1606 case IP_VERSION(11, 0, 13):
1607 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
1608 ret = smu_cmn_send_smc_msg_with_param(smu,
1609 SMU_MSG_EnterBaco,
1610 D3HOT_BAMACO_SEQUENCE,
1611 NULL);
1612 else
1613 ret = smu_cmn_send_smc_msg_with_param(smu,
1614 SMU_MSG_EnterBaco,
1615 D3HOT_BACO_SEQUENCE,
1616 NULL);
1617 break;
1618 default:
1619 if (!ras || !adev->ras_enabled ||
1620 (adev->init_lvl->level ==
1621 AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) {
1622 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1623 IP_VERSION(11, 0, 2)) {
1624 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1625 data |= 0x80000000;
1626 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1627 } else {
1628 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1629 data |= 0x80000000;
1630 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1631 }
1632
1633 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1634 } else {
1635 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1636 }
1637 break;
1638 }
1639
1640 } else {
1641 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1642 if (ret)
1643 return ret;
1644
1645 /* clear vbios scratch 6 and 7 for coming asic reinit */
1646 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1647 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1648 }
1649
1650 if (!ret)
1651 smu_baco->state = state;
1652
1653 return ret;
1654 }
1655
smu_v11_0_baco_enter(struct smu_context * smu)1656 int smu_v11_0_baco_enter(struct smu_context *smu)
1657 {
1658 int ret = 0;
1659
1660 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1661 if (ret)
1662 return ret;
1663
1664 msleep(10);
1665
1666 return ret;
1667 }
1668
smu_v11_0_baco_exit(struct smu_context * smu)1669 int smu_v11_0_baco_exit(struct smu_context *smu)
1670 {
1671 int ret;
1672
1673 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1674 if (!ret) {
1675 /*
1676 * Poll BACO exit status to ensure FW has completed
1677 * BACO exit process to avoid timing issues.
1678 */
1679 smu_v11_0_poll_baco_exit(smu);
1680 }
1681
1682 return ret;
1683 }
1684
smu_v11_0_mode1_reset(struct smu_context * smu)1685 int smu_v11_0_mode1_reset(struct smu_context *smu)
1686 {
1687 int ret = 0;
1688
1689 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1690 if (!ret)
1691 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1692
1693 return ret;
1694 }
1695
smu_v11_0_handle_passthrough_sbr(struct smu_context * smu,bool enable)1696 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1697 {
1698 int ret = 0;
1699
1700 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1701
1702 return ret;
1703 }
1704
1705
smu_v11_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1706 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1707 uint32_t *min, uint32_t *max)
1708 {
1709 int ret = 0, clk_id = 0;
1710 uint32_t param = 0;
1711 uint32_t clock_limit;
1712
1713 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1714 switch (clk_type) {
1715 case SMU_MCLK:
1716 case SMU_UCLK:
1717 clock_limit = smu->smu_table.boot_values.uclk;
1718 break;
1719 case SMU_GFXCLK:
1720 case SMU_SCLK:
1721 clock_limit = smu->smu_table.boot_values.gfxclk;
1722 break;
1723 case SMU_SOCCLK:
1724 clock_limit = smu->smu_table.boot_values.socclk;
1725 break;
1726 default:
1727 clock_limit = 0;
1728 break;
1729 }
1730
1731 /* clock in Mhz unit */
1732 if (min)
1733 *min = clock_limit / 100;
1734 if (max)
1735 *max = clock_limit / 100;
1736
1737 return 0;
1738 }
1739
1740 clk_id = smu_cmn_to_asic_specific_index(smu,
1741 CMN2ASIC_MAPPING_CLK,
1742 clk_type);
1743 if (clk_id < 0) {
1744 ret = -EINVAL;
1745 goto failed;
1746 }
1747 param = (clk_id & 0xffff) << 16;
1748
1749 if (max) {
1750 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1751 if (ret)
1752 goto failed;
1753 }
1754
1755 if (min) {
1756 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1757 if (ret)
1758 goto failed;
1759 }
1760
1761 failed:
1762 return ret;
1763 }
1764
smu_v11_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1765 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1766 enum smu_clk_type clk_type,
1767 uint32_t min,
1768 uint32_t max,
1769 bool automatic)
1770 {
1771 int ret = 0, clk_id = 0;
1772 uint32_t param;
1773
1774 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1775 return 0;
1776
1777 clk_id = smu_cmn_to_asic_specific_index(smu,
1778 CMN2ASIC_MAPPING_CLK,
1779 clk_type);
1780 if (clk_id < 0)
1781 return clk_id;
1782
1783 if (max > 0) {
1784 if (automatic)
1785 param = (uint32_t)((clk_id << 16) | 0xffff);
1786 else
1787 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1788 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1789 param, NULL);
1790 if (ret)
1791 goto out;
1792 }
1793
1794 if (min > 0) {
1795 if (automatic)
1796 param = (uint32_t)((clk_id << 16) | 0);
1797 else
1798 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1799 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1800 param, NULL);
1801 if (ret)
1802 goto out;
1803 }
1804
1805 out:
1806 return ret;
1807 }
1808
smu_v11_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1809 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1810 enum smu_clk_type clk_type,
1811 uint32_t min,
1812 uint32_t max)
1813 {
1814 int ret = 0, clk_id = 0;
1815 uint32_t param;
1816
1817 if (min <= 0 && max <= 0)
1818 return -EINVAL;
1819
1820 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1821 return 0;
1822
1823 clk_id = smu_cmn_to_asic_specific_index(smu,
1824 CMN2ASIC_MAPPING_CLK,
1825 clk_type);
1826 if (clk_id < 0)
1827 return clk_id;
1828
1829 if (max > 0) {
1830 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1831 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1832 param, NULL);
1833 if (ret)
1834 return ret;
1835 }
1836
1837 if (min > 0) {
1838 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1839 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1840 param, NULL);
1841 if (ret)
1842 return ret;
1843 }
1844
1845 return ret;
1846 }
1847
smu_v11_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1848 int smu_v11_0_set_performance_level(struct smu_context *smu,
1849 enum amd_dpm_forced_level level)
1850 {
1851 struct smu_11_0_dpm_context *dpm_context =
1852 smu->smu_dpm.dpm_context;
1853 struct smu_11_0_dpm_table *gfx_table =
1854 &dpm_context->dpm_tables.gfx_table;
1855 struct smu_11_0_dpm_table *mem_table =
1856 &dpm_context->dpm_tables.uclk_table;
1857 struct smu_11_0_dpm_table *soc_table =
1858 &dpm_context->dpm_tables.soc_table;
1859 struct smu_umd_pstate_table *pstate_table =
1860 &smu->pstate_table;
1861 struct amdgpu_device *adev = smu->adev;
1862 uint32_t sclk_min = 0, sclk_max = 0;
1863 uint32_t mclk_min = 0, mclk_max = 0;
1864 uint32_t socclk_min = 0, socclk_max = 0;
1865 int ret = 0;
1866 bool auto_level = false;
1867
1868 switch (level) {
1869 case AMD_DPM_FORCED_LEVEL_HIGH:
1870 sclk_min = sclk_max = gfx_table->max;
1871 mclk_min = mclk_max = mem_table->max;
1872 socclk_min = socclk_max = soc_table->max;
1873 break;
1874 case AMD_DPM_FORCED_LEVEL_LOW:
1875 sclk_min = sclk_max = gfx_table->min;
1876 mclk_min = mclk_max = mem_table->min;
1877 socclk_min = socclk_max = soc_table->min;
1878 break;
1879 case AMD_DPM_FORCED_LEVEL_AUTO:
1880 sclk_min = gfx_table->min;
1881 sclk_max = gfx_table->max;
1882 mclk_min = mem_table->min;
1883 mclk_max = mem_table->max;
1884 socclk_min = soc_table->min;
1885 socclk_max = soc_table->max;
1886 auto_level = true;
1887 break;
1888 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1889 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1890 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1891 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1892 break;
1893 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1894 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1895 break;
1896 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1897 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1898 break;
1899 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1900 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1901 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1902 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1903 break;
1904 case AMD_DPM_FORCED_LEVEL_MANUAL:
1905 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1906 return 0;
1907 default:
1908 dev_err(adev->dev, "Invalid performance level %d\n", level);
1909 return -EINVAL;
1910 }
1911
1912 /*
1913 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1914 * on Arcturus.
1915 */
1916 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1917 mclk_min = mclk_max = 0;
1918 socclk_min = socclk_max = 0;
1919 auto_level = false;
1920 }
1921
1922 if (sclk_min && sclk_max) {
1923 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1924 SMU_GFXCLK,
1925 sclk_min,
1926 sclk_max,
1927 auto_level);
1928 if (ret)
1929 return ret;
1930 }
1931
1932 if (mclk_min && mclk_max) {
1933 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1934 SMU_MCLK,
1935 mclk_min,
1936 mclk_max,
1937 auto_level);
1938 if (ret)
1939 return ret;
1940 }
1941
1942 if (socclk_min && socclk_max) {
1943 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1944 SMU_SOCCLK,
1945 socclk_min,
1946 socclk_max,
1947 auto_level);
1948 if (ret)
1949 return ret;
1950 }
1951
1952 return ret;
1953 }
1954
smu_v11_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1955 int smu_v11_0_set_power_source(struct smu_context *smu,
1956 enum smu_power_src_type power_src)
1957 {
1958 int pwr_source;
1959
1960 pwr_source = smu_cmn_to_asic_specific_index(smu,
1961 CMN2ASIC_MAPPING_PWR,
1962 (uint32_t)power_src);
1963 if (pwr_source < 0)
1964 return -EINVAL;
1965
1966 return smu_cmn_send_smc_msg_with_param(smu,
1967 SMU_MSG_NotifyPowerSource,
1968 pwr_source,
1969 NULL);
1970 }
1971
smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1972 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1973 enum smu_clk_type clk_type,
1974 uint16_t level,
1975 uint32_t *value)
1976 {
1977 int ret = 0, clk_id = 0;
1978 uint32_t param;
1979
1980 if (!value)
1981 return -EINVAL;
1982
1983 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1984 return 0;
1985
1986 clk_id = smu_cmn_to_asic_specific_index(smu,
1987 CMN2ASIC_MAPPING_CLK,
1988 clk_type);
1989 if (clk_id < 0)
1990 return clk_id;
1991
1992 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1993
1994 ret = smu_cmn_send_smc_msg_with_param(smu,
1995 SMU_MSG_GetDpmFreqByIndex,
1996 param,
1997 value);
1998 if (ret)
1999 return ret;
2000
2001 /*
2002 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
2003 * now, we un-support it
2004 */
2005 *value = *value & 0x7fffffff;
2006
2007 return ret;
2008 }
2009
smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)2010 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
2011 enum smu_clk_type clk_type,
2012 uint32_t *value)
2013 {
2014 return smu_v11_0_get_dpm_freq_by_index(smu,
2015 clk_type,
2016 0xff,
2017 value);
2018 }
2019
smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_11_0_dpm_table * single_dpm_table)2020 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2021 enum smu_clk_type clk_type,
2022 struct smu_11_0_dpm_table *single_dpm_table)
2023 {
2024 int ret = 0;
2025 uint32_t clk;
2026 int i;
2027
2028 ret = smu_v11_0_get_dpm_level_count(smu,
2029 clk_type,
2030 &single_dpm_table->count);
2031 if (ret) {
2032 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2033 return ret;
2034 }
2035
2036 for (i = 0; i < single_dpm_table->count; i++) {
2037 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2038 clk_type,
2039 i,
2040 &clk);
2041 if (ret) {
2042 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2043 return ret;
2044 }
2045
2046 single_dpm_table->dpm_levels[i].value = clk;
2047 single_dpm_table->dpm_levels[i].enabled = true;
2048
2049 if (i == 0)
2050 single_dpm_table->min = clk;
2051 else if (i == single_dpm_table->count - 1)
2052 single_dpm_table->max = clk;
2053 }
2054
2055 return 0;
2056 }
2057
smu_v11_0_get_dpm_level_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min_value,uint32_t * max_value)2058 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
2059 enum smu_clk_type clk_type,
2060 uint32_t *min_value,
2061 uint32_t *max_value)
2062 {
2063 uint32_t level_count = 0;
2064 int ret = 0;
2065
2066 if (!min_value && !max_value)
2067 return -EINVAL;
2068
2069 if (min_value) {
2070 /* by default, level 0 clock value as min value */
2071 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2072 clk_type,
2073 0,
2074 min_value);
2075 if (ret)
2076 return ret;
2077 }
2078
2079 if (max_value) {
2080 ret = smu_v11_0_get_dpm_level_count(smu,
2081 clk_type,
2082 &level_count);
2083 if (ret)
2084 return ret;
2085
2086 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2087 clk_type,
2088 level_count - 1,
2089 max_value);
2090 if (ret)
2091 return ret;
2092 }
2093
2094 return ret;
2095 }
2096
smu_v11_0_get_current_pcie_link_width_level(struct smu_context * smu)2097 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2098 {
2099 struct amdgpu_device *adev = smu->adev;
2100
2101 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2102 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2103 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2104 }
2105
smu_v11_0_get_current_pcie_link_width(struct smu_context * smu)2106 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2107 {
2108 uint32_t width_level;
2109
2110 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2111 if (width_level > LINK_WIDTH_MAX)
2112 width_level = 0;
2113
2114 return link_width[width_level];
2115 }
2116
smu_v11_0_get_current_pcie_link_speed_level(struct smu_context * smu)2117 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2118 {
2119 struct amdgpu_device *adev = smu->adev;
2120
2121 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2122 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2123 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2124 }
2125
smu_v11_0_get_current_pcie_link_speed(struct smu_context * smu)2126 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2127 {
2128 uint32_t speed_level;
2129
2130 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2131 if (speed_level > LINK_SPEED_MAX)
2132 speed_level = 0;
2133
2134 return link_speed[speed_level];
2135 }
2136
smu_v11_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2137 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2138 bool enablement)
2139 {
2140 int ret = 0;
2141
2142 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2143 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2144
2145 return ret;
2146 }
2147
smu_v11_0_deep_sleep_control(struct smu_context * smu,bool enablement)2148 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2149 bool enablement)
2150 {
2151 struct amdgpu_device *adev = smu->adev;
2152 int ret = 0;
2153
2154 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2155 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2156 if (ret) {
2157 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2158 return ret;
2159 }
2160 }
2161
2162 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2163 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2164 if (ret) {
2165 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2166 return ret;
2167 }
2168 }
2169
2170 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2171 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2172 if (ret) {
2173 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2174 return ret;
2175 }
2176 }
2177
2178 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2179 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2180 if (ret) {
2181 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2182 return ret;
2183 }
2184 }
2185
2186 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2187 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2188 if (ret) {
2189 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2190 return ret;
2191 }
2192 }
2193
2194 return ret;
2195 }
2196
smu_v11_0_restore_user_od_settings(struct smu_context * smu)2197 int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2198 {
2199 struct smu_table_context *table_context = &smu->smu_table;
2200 void *user_od_table = table_context->user_overdrive_table;
2201 int ret = 0;
2202
2203 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2204 if (ret)
2205 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2206
2207 return ret;
2208 }
2209
smu_v11_0_set_smu_mailbox_registers(struct smu_context * smu)2210 void smu_v11_0_set_smu_mailbox_registers(struct smu_context *smu)
2211 {
2212 struct amdgpu_device *adev = smu->adev;
2213
2214 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2215 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2216 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2217 }
2218