1 // SPDX-License-Identifier: GPL-2.0 2 /* Renesas Ethernet AVB device driver 3 * 4 * Copyright (C) 2014-2019 Renesas Electronics Corporation 5 * Copyright (C) 2015 Renesas Solutions Corp. 6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com> 7 * 8 * Based on the SuperH Ethernet driver 9 */ 10 11 #include <linux/cache.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/err.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_vlan.h> 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/module.h> 22 #include <linux/net_tstamp.h> 23 #include <linux/of.h> 24 #include <linux/of_mdio.h> 25 #include <linux/of_net.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/slab.h> 29 #include <linux/spinlock.h> 30 #include <linux/reset.h> 31 #include <linux/math64.h> 32 #include <net/ip.h> 33 #include <net/page_pool/helpers.h> 34 35 #include "ravb.h" 36 37 #define RAVB_DEF_MSG_ENABLE \ 38 (NETIF_MSG_LINK | \ 39 NETIF_MSG_TIMER | \ 40 NETIF_MSG_RX_ERR | \ 41 NETIF_MSG_TX_ERR) 42 43 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear, 44 u32 set) 45 { 46 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg); 47 } 48 49 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value) 50 { 51 int i; 52 53 for (i = 0; i < 10000; i++) { 54 if ((ravb_read(ndev, reg) & mask) == value) 55 return 0; 56 udelay(10); 57 } 58 return -ETIMEDOUT; 59 } 60 61 static int ravb_set_opmode(struct net_device *ndev, u32 opmode) 62 { 63 u32 csr_ops = 1U << (opmode & CCC_OPC); 64 u32 ccc_mask = CCC_OPC; 65 int error; 66 67 /* If gPTP active in config mode is supported it needs to be configured 68 * along with CSEL and operating mode in the same access. This is a 69 * hardware limitation. 70 */ 71 if (opmode & CCC_GAC) 72 ccc_mask |= CCC_GAC | CCC_CSEL; 73 74 /* Set operating mode */ 75 ravb_modify(ndev, CCC, ccc_mask, opmode); 76 /* Check if the operating mode is changed to the requested one */ 77 error = ravb_wait(ndev, CSR, CSR_OPS, csr_ops); 78 if (error) { 79 netdev_err(ndev, "failed to switch device to requested mode (%u)\n", 80 opmode & CCC_OPC); 81 } 82 83 return error; 84 } 85 86 static void ravb_set_rate_gbeth(struct net_device *ndev) 87 { 88 struct ravb_private *priv = netdev_priv(ndev); 89 90 switch (priv->speed) { 91 case 10: /* 10BASE */ 92 ravb_write(ndev, GBETH_GECMR_SPEED_10, GECMR); 93 break; 94 case 100: /* 100BASE */ 95 ravb_write(ndev, GBETH_GECMR_SPEED_100, GECMR); 96 break; 97 case 1000: /* 1000BASE */ 98 ravb_write(ndev, GBETH_GECMR_SPEED_1000, GECMR); 99 break; 100 } 101 } 102 103 static void ravb_set_rate_rcar(struct net_device *ndev) 104 { 105 struct ravb_private *priv = netdev_priv(ndev); 106 107 switch (priv->speed) { 108 case 100: /* 100BASE */ 109 ravb_write(ndev, GECMR_SPEED_100, GECMR); 110 break; 111 case 1000: /* 1000BASE */ 112 ravb_write(ndev, GECMR_SPEED_1000, GECMR); 113 break; 114 } 115 } 116 117 /* Get MAC address from the MAC address registers 118 * 119 * Ethernet AVB device doesn't have ROM for MAC address. 120 * This function gets the MAC address that was used by a bootloader. 121 */ 122 static void ravb_read_mac_address(struct device_node *np, 123 struct net_device *ndev) 124 { 125 int ret; 126 127 ret = of_get_ethdev_address(np, ndev); 128 if (ret) { 129 u32 mahr = ravb_read(ndev, MAHR); 130 u32 malr = ravb_read(ndev, MALR); 131 u8 addr[ETH_ALEN]; 132 133 addr[0] = (mahr >> 24) & 0xFF; 134 addr[1] = (mahr >> 16) & 0xFF; 135 addr[2] = (mahr >> 8) & 0xFF; 136 addr[3] = (mahr >> 0) & 0xFF; 137 addr[4] = (malr >> 8) & 0xFF; 138 addr[5] = (malr >> 0) & 0xFF; 139 eth_hw_addr_set(ndev, addr); 140 } 141 } 142 143 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set) 144 { 145 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 146 mdiobb); 147 148 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0); 149 } 150 151 /* MDC pin control */ 152 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level) 153 { 154 ravb_mdio_ctrl(ctrl, PIR_MDC, level); 155 } 156 157 /* Data I/O pin control */ 158 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 159 { 160 ravb_mdio_ctrl(ctrl, PIR_MMD, output); 161 } 162 163 /* Set data bit */ 164 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 165 { 166 ravb_mdio_ctrl(ctrl, PIR_MDO, value); 167 } 168 169 /* Get data bit */ 170 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl) 171 { 172 struct ravb_private *priv = container_of(ctrl, struct ravb_private, 173 mdiobb); 174 175 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0; 176 } 177 178 /* MDIO bus control struct */ 179 static const struct mdiobb_ops bb_ops = { 180 .owner = THIS_MODULE, 181 .set_mdc = ravb_set_mdc, 182 .set_mdio_dir = ravb_set_mdio_dir, 183 .set_mdio_data = ravb_set_mdio_data, 184 .get_mdio_data = ravb_get_mdio_data, 185 }; 186 187 static struct ravb_rx_desc * 188 ravb_rx_get_desc(struct ravb_private *priv, unsigned int q, 189 unsigned int i) 190 { 191 return priv->rx_ring[q].raw + priv->info->rx_desc_size * i; 192 } 193 194 /* Free TX skb function for AVB-IP */ 195 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only) 196 { 197 struct ravb_private *priv = netdev_priv(ndev); 198 struct net_device_stats *stats = &priv->stats[q]; 199 unsigned int num_tx_desc = priv->num_tx_desc; 200 struct ravb_tx_desc *desc; 201 unsigned int entry; 202 int free_num = 0; 203 u32 size; 204 205 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) { 206 bool txed; 207 208 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] * 209 num_tx_desc); 210 desc = &priv->tx_ring[q][entry]; 211 txed = desc->die_dt == DT_FEMPTY; 212 if (free_txed_only && !txed) 213 break; 214 /* Descriptor type must be checked before all other reads */ 215 dma_rmb(); 216 size = le16_to_cpu(desc->ds_tagl) & TX_DS; 217 /* Free the original skb. */ 218 if (priv->tx_skb[q][entry / num_tx_desc]) { 219 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 220 size, DMA_TO_DEVICE); 221 /* Last packet descriptor? */ 222 if (entry % num_tx_desc == num_tx_desc - 1) { 223 entry /= num_tx_desc; 224 dev_kfree_skb_any(priv->tx_skb[q][entry]); 225 priv->tx_skb[q][entry] = NULL; 226 if (txed) 227 stats->tx_packets++; 228 } 229 free_num++; 230 } 231 if (txed) 232 stats->tx_bytes += size; 233 desc->die_dt = DT_EEMPTY; 234 } 235 return free_num; 236 } 237 238 static void ravb_rx_ring_free(struct net_device *ndev, int q) 239 { 240 struct ravb_private *priv = netdev_priv(ndev); 241 unsigned int ring_size; 242 243 if (!priv->rx_ring[q].raw) 244 return; 245 246 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 247 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q].raw, 248 priv->rx_desc_dma[q]); 249 priv->rx_ring[q].raw = NULL; 250 } 251 252 /* Free skb's and DMA buffers for Ethernet AVB */ 253 static void ravb_ring_free(struct net_device *ndev, int q) 254 { 255 struct ravb_private *priv = netdev_priv(ndev); 256 unsigned int num_tx_desc = priv->num_tx_desc; 257 unsigned int ring_size; 258 unsigned int i; 259 260 ravb_rx_ring_free(ndev, q); 261 262 if (priv->tx_ring[q]) { 263 ravb_tx_free(ndev, q, false); 264 265 ring_size = sizeof(struct ravb_tx_desc) * 266 (priv->num_tx_ring[q] * num_tx_desc + 1); 267 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q], 268 priv->tx_desc_dma[q]); 269 priv->tx_ring[q] = NULL; 270 } 271 272 /* Free RX buffers */ 273 for (i = 0; i < priv->num_rx_ring[q]; i++) { 274 if (priv->rx_buffers[q][i].page) 275 page_pool_put_page(priv->rx_pool[q], 276 priv->rx_buffers[q][i].page, 277 0, true); 278 } 279 kfree(priv->rx_buffers[q]); 280 priv->rx_buffers[q] = NULL; 281 page_pool_destroy(priv->rx_pool[q]); 282 283 /* Free aligned TX buffers */ 284 kfree(priv->tx_align[q]); 285 priv->tx_align[q] = NULL; 286 287 /* Free TX skb ringbuffer. 288 * SKBs are freed by ravb_tx_free() call above. 289 */ 290 kfree(priv->tx_skb[q]); 291 priv->tx_skb[q] = NULL; 292 } 293 294 static int 295 ravb_alloc_rx_buffer(struct net_device *ndev, int q, u32 entry, gfp_t gfp_mask, 296 struct ravb_rx_desc *rx_desc) 297 { 298 struct ravb_private *priv = netdev_priv(ndev); 299 const struct ravb_hw_info *info = priv->info; 300 struct ravb_rx_buffer *rx_buff; 301 dma_addr_t dma_addr; 302 unsigned int size; 303 304 rx_buff = &priv->rx_buffers[q][entry]; 305 size = info->rx_buffer_size; 306 rx_buff->page = page_pool_alloc(priv->rx_pool[q], &rx_buff->offset, 307 &size, gfp_mask); 308 if (unlikely(!rx_buff->page)) { 309 /* We just set the data size to 0 for a failed mapping which 310 * should prevent DMA from happening... 311 */ 312 rx_desc->ds_cc = cpu_to_le16(0); 313 return -ENOMEM; 314 } 315 316 dma_addr = page_pool_get_dma_addr(rx_buff->page) + rx_buff->offset; 317 dma_sync_single_for_device(ndev->dev.parent, dma_addr, 318 info->rx_buffer_size, DMA_FROM_DEVICE); 319 rx_desc->dptr = cpu_to_le32(dma_addr); 320 321 /* The end of the RX buffer is used to store skb shared data, so we need 322 * to ensure that the hardware leaves enough space for this. 323 */ 324 rx_desc->ds_cc = cpu_to_le16(info->rx_buffer_size - 325 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) - 326 ETH_FCS_LEN + sizeof(__sum16)); 327 return 0; 328 } 329 330 static u32 331 ravb_rx_ring_refill(struct net_device *ndev, int q, u32 count, gfp_t gfp_mask) 332 { 333 struct ravb_private *priv = netdev_priv(ndev); 334 struct ravb_rx_desc *rx_desc; 335 u32 i, entry; 336 337 for (i = 0; i < count; i++) { 338 entry = (priv->dirty_rx[q] + i) % priv->num_rx_ring[q]; 339 rx_desc = ravb_rx_get_desc(priv, q, entry); 340 341 if (!priv->rx_buffers[q][entry].page) { 342 if (unlikely(ravb_alloc_rx_buffer(ndev, q, entry, 343 gfp_mask, rx_desc))) 344 break; 345 } 346 /* Descriptor type must be set after all the above writes */ 347 dma_wmb(); 348 rx_desc->die_dt = DT_FEMPTY; 349 } 350 351 return i; 352 } 353 354 /* Format skb and descriptor buffer for Ethernet AVB */ 355 static void ravb_ring_format(struct net_device *ndev, int q) 356 { 357 struct ravb_private *priv = netdev_priv(ndev); 358 unsigned int num_tx_desc = priv->num_tx_desc; 359 struct ravb_rx_desc *rx_desc; 360 struct ravb_tx_desc *tx_desc; 361 struct ravb_desc *desc; 362 unsigned int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] * 363 num_tx_desc; 364 unsigned int i; 365 366 priv->cur_rx[q] = 0; 367 priv->cur_tx[q] = 0; 368 priv->dirty_rx[q] = 0; 369 priv->dirty_tx[q] = 0; 370 371 /* Regular RX descriptors have already been initialized by 372 * ravb_rx_ring_refill(), we just need to initialize the final link 373 * descriptor. 374 */ 375 rx_desc = ravb_rx_get_desc(priv, q, priv->num_rx_ring[q]); 376 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 377 rx_desc->die_dt = DT_LINKFIX; /* type */ 378 379 memset(priv->tx_ring[q], 0, tx_ring_size); 380 /* Build TX ring buffer */ 381 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q]; 382 i++, tx_desc++) { 383 tx_desc->die_dt = DT_EEMPTY; 384 if (num_tx_desc > 1) { 385 tx_desc++; 386 tx_desc->die_dt = DT_EEMPTY; 387 } 388 } 389 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 390 tx_desc->die_dt = DT_LINKFIX; /* type */ 391 392 /* RX descriptor base address for best effort */ 393 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q]; 394 desc->die_dt = DT_LINKFIX; /* type */ 395 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]); 396 397 /* TX descriptor base address for best effort */ 398 desc = &priv->desc_bat[q]; 399 desc->die_dt = DT_LINKFIX; /* type */ 400 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]); 401 } 402 403 static void *ravb_alloc_rx_desc(struct net_device *ndev, int q) 404 { 405 struct ravb_private *priv = netdev_priv(ndev); 406 unsigned int ring_size; 407 408 ring_size = priv->info->rx_desc_size * (priv->num_rx_ring[q] + 1); 409 410 priv->rx_ring[q].raw = dma_alloc_coherent(ndev->dev.parent, ring_size, 411 &priv->rx_desc_dma[q], 412 GFP_KERNEL); 413 414 return priv->rx_ring[q].raw; 415 } 416 417 /* Init skb and descriptor buffer for Ethernet AVB */ 418 static int ravb_ring_init(struct net_device *ndev, int q) 419 { 420 struct ravb_private *priv = netdev_priv(ndev); 421 unsigned int num_tx_desc = priv->num_tx_desc; 422 struct page_pool_params params = { 423 .order = 0, 424 .flags = PP_FLAG_DMA_MAP, 425 .pool_size = priv->num_rx_ring[q], 426 .nid = NUMA_NO_NODE, 427 .dev = ndev->dev.parent, 428 .dma_dir = DMA_FROM_DEVICE, 429 }; 430 unsigned int ring_size; 431 u32 num_filled; 432 433 /* Allocate RX page pool and buffers */ 434 priv->rx_pool[q] = page_pool_create(¶ms); 435 if (IS_ERR(priv->rx_pool[q])) 436 goto error; 437 438 /* Allocate RX buffers */ 439 priv->rx_buffers[q] = kzalloc_objs(*priv->rx_buffers[q], 440 priv->num_rx_ring[q]); 441 if (!priv->rx_buffers[q]) 442 goto error; 443 444 /* Allocate TX skb rings */ 445 priv->tx_skb[q] = kzalloc_objs(*priv->tx_skb[q], priv->num_tx_ring[q]); 446 if (!priv->tx_skb[q]) 447 goto error; 448 449 /* Allocate all RX descriptors. */ 450 if (!ravb_alloc_rx_desc(ndev, q)) 451 goto error; 452 453 /* Populate RX ring buffer. */ 454 priv->dirty_rx[q] = 0; 455 ring_size = priv->info->rx_desc_size * priv->num_rx_ring[q]; 456 memset(priv->rx_ring[q].raw, 0, ring_size); 457 num_filled = ravb_rx_ring_refill(ndev, q, priv->num_rx_ring[q], 458 GFP_KERNEL); 459 if (num_filled != priv->num_rx_ring[q]) 460 goto error; 461 462 if (num_tx_desc > 1) { 463 /* Allocate rings for the aligned buffers */ 464 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] + 465 DPTR_ALIGN - 1, GFP_KERNEL); 466 if (!priv->tx_align[q]) 467 goto error; 468 } 469 470 /* Allocate all TX descriptors. */ 471 ring_size = sizeof(struct ravb_tx_desc) * 472 (priv->num_tx_ring[q] * num_tx_desc + 1); 473 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size, 474 &priv->tx_desc_dma[q], 475 GFP_KERNEL); 476 if (!priv->tx_ring[q]) 477 goto error; 478 479 return 0; 480 481 error: 482 ravb_ring_free(ndev, q); 483 484 return -ENOMEM; 485 } 486 487 static void ravb_csum_init_gbeth(struct net_device *ndev) 488 { 489 bool tx_enable = ndev->features & NETIF_F_HW_CSUM; 490 bool rx_enable = ndev->features & NETIF_F_RXCSUM; 491 492 if (!(tx_enable || rx_enable)) 493 goto done; 494 495 ravb_write(ndev, 0, CSR0); 496 if (ravb_wait(ndev, CSR0, CSR0_TPE | CSR0_RPE, 0)) { 497 netdev_err(ndev, "Timeout enabling hardware checksum\n"); 498 499 if (tx_enable) 500 ndev->features &= ~NETIF_F_HW_CSUM; 501 502 if (rx_enable) 503 ndev->features &= ~NETIF_F_RXCSUM; 504 } else { 505 if (tx_enable) 506 ravb_write(ndev, CSR1_CSUM_ENABLE, CSR1); 507 508 if (rx_enable) 509 ravb_write(ndev, CSR2_CSUM_ENABLE, CSR2); 510 } 511 512 done: 513 ravb_write(ndev, CSR0_TPE | CSR0_RPE, CSR0); 514 } 515 516 static void ravb_emac_init_gbeth(struct net_device *ndev) 517 { 518 struct ravb_private *priv = netdev_priv(ndev); 519 520 if (priv->phy_interface == PHY_INTERFACE_MODE_MII) { 521 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_MII, CXR35); 522 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 0); 523 } else { 524 ravb_write(ndev, (1000 << 16) | CXR35_SEL_XMII_RGMII, CXR35); 525 ravb_modify(ndev, CXR31, CXR31_SEL_LINK0 | CXR31_SEL_LINK1, 526 CXR31_SEL_LINK0); 527 } 528 529 /* Receive frame limit set register */ 530 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 531 532 /* EMAC Mode: PAUSE prohibition; Duplex; TX; RX; CRC Pass Through */ 533 ravb_write(ndev, ECMR_ZPF | ((priv->duplex > 0) ? ECMR_DM : 0) | 534 ECMR_TE | ECMR_RE | ECMR_RCPT | 535 ECMR_TXF | ECMR_RXF, ECMR); 536 537 ravb_set_rate_gbeth(ndev); 538 539 /* Set MAC address */ 540 ravb_write(ndev, 541 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 542 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 543 ravb_write(ndev, (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 544 545 /* E-MAC status register clear */ 546 ravb_write(ndev, ECSR_ICD | ECSR_LCHNG | ECSR_PFRI, ECSR); 547 548 ravb_csum_init_gbeth(ndev); 549 550 /* E-MAC interrupt enable register */ 551 ravb_write(ndev, ECSIPR_ICDIP, ECSIPR); 552 } 553 554 static void ravb_emac_init_rcar(struct net_device *ndev) 555 { 556 struct ravb_private *priv = netdev_priv(ndev); 557 558 /* Set receive frame length 559 * 560 * The length set here describes the frame from the destination address 561 * up to and including the CRC data. However only the frame data, 562 * excluding the CRC, are transferred to memory. To allow for the 563 * largest frames add the CRC length to the maximum Rx descriptor size. 564 */ 565 ravb_write(ndev, priv->info->rx_max_frame_size + ETH_FCS_LEN, RFLR); 566 567 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */ 568 ravb_write(ndev, ECMR_ZPF | ECMR_DM | 569 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) | 570 ECMR_TE | ECMR_RE, ECMR); 571 572 ravb_set_rate_rcar(ndev); 573 574 /* Set MAC address */ 575 ravb_write(ndev, 576 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 577 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 578 ravb_write(ndev, 579 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 580 581 /* E-MAC status register clear */ 582 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR); 583 584 /* E-MAC interrupt enable register */ 585 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR); 586 } 587 588 static void ravb_emac_init_rcar_gen4(struct net_device *ndev) 589 { 590 struct ravb_private *priv = netdev_priv(ndev); 591 bool mii = priv->phy_interface == PHY_INTERFACE_MODE_MII; 592 593 ravb_modify(ndev, APSR, APSR_MIISELECT, mii ? APSR_MIISELECT : 0); 594 595 ravb_emac_init_rcar(ndev); 596 } 597 598 /* E-MAC init function */ 599 static void ravb_emac_init(struct net_device *ndev) 600 { 601 struct ravb_private *priv = netdev_priv(ndev); 602 const struct ravb_hw_info *info = priv->info; 603 604 info->emac_init(ndev); 605 } 606 607 static int ravb_dmac_init_gbeth(struct net_device *ndev) 608 { 609 struct ravb_private *priv = netdev_priv(ndev); 610 int error; 611 612 error = ravb_ring_init(ndev, RAVB_BE); 613 if (error) 614 return error; 615 616 /* Descriptor format */ 617 ravb_ring_format(ndev, RAVB_BE); 618 619 /* Set DMAC RX */ 620 ravb_write(ndev, 0x60000000, RCR); 621 622 /* Set Max Frame Length (RTC) */ 623 ravb_write(ndev, 0x7ffc0000 | priv->info->rx_max_frame_size, RTC); 624 625 /* Set FIFO size */ 626 ravb_write(ndev, 0x00222200, TGC); 627 628 ravb_write(ndev, 0, TCCR); 629 630 /* Frame receive */ 631 ravb_write(ndev, RIC0_FRE0, RIC0); 632 /* Disable FIFO full warning */ 633 ravb_write(ndev, 0x0, RIC1); 634 /* Receive FIFO full error, descriptor empty */ 635 ravb_write(ndev, RIC2_QFE0 | RIC2_RFFE, RIC2); 636 637 ravb_write(ndev, TIC_FTE0, TIC); 638 639 return 0; 640 } 641 642 static int ravb_dmac_init_rcar(struct net_device *ndev) 643 { 644 struct ravb_private *priv = netdev_priv(ndev); 645 const struct ravb_hw_info *info = priv->info; 646 int error; 647 648 error = ravb_ring_init(ndev, RAVB_BE); 649 if (error) 650 return error; 651 error = ravb_ring_init(ndev, RAVB_NC); 652 if (error) { 653 ravb_ring_free(ndev, RAVB_BE); 654 return error; 655 } 656 657 /* Descriptor format */ 658 ravb_ring_format(ndev, RAVB_BE); 659 ravb_ring_format(ndev, RAVB_NC); 660 661 /* Set AVB RX */ 662 ravb_write(ndev, 663 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR); 664 665 /* Set FIFO size */ 666 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC); 667 668 /* Timestamp enable */ 669 ravb_write(ndev, TCCR_TFEN, TCCR); 670 671 /* Interrupt init: */ 672 if (info->multi_irqs) { 673 /* Clear DIL.DPLx */ 674 ravb_write(ndev, 0, DIL); 675 /* Set queue specific interrupt */ 676 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE); 677 } 678 /* Frame receive */ 679 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0); 680 /* Disable FIFO full warning */ 681 ravb_write(ndev, 0, RIC1); 682 /* Receive FIFO full error, descriptor empty */ 683 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2); 684 /* Frame transmitted, timestamp FIFO updated */ 685 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC); 686 687 return 0; 688 } 689 690 /* Device init function for Ethernet AVB */ 691 static int ravb_dmac_init(struct net_device *ndev) 692 { 693 struct ravb_private *priv = netdev_priv(ndev); 694 const struct ravb_hw_info *info = priv->info; 695 int error; 696 697 /* Clear transmission suspension */ 698 ravb_modify(ndev, CCC, CCC_DTSR, 0); 699 700 /* Set CONFIG mode */ 701 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 702 if (error) 703 return error; 704 705 error = info->dmac_init(ndev); 706 if (error) 707 return error; 708 709 /* Setting the control will start the AVB-DMAC process. */ 710 return ravb_set_opmode(ndev, CCC_OPC_OPERATION); 711 } 712 713 static void ravb_get_tx_tstamp(struct net_device *ndev) 714 { 715 struct ravb_private *priv = netdev_priv(ndev); 716 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 717 struct skb_shared_hwtstamps shhwtstamps; 718 struct sk_buff *skb; 719 struct timespec64 ts; 720 u16 tag, tfa_tag; 721 int count; 722 u32 tfa2; 723 724 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8; 725 while (count--) { 726 tfa2 = ravb_read(ndev, TFA2); 727 tfa_tag = (tfa2 & TFA2_TST) >> 16; 728 ts.tv_nsec = (u64)ravb_read(ndev, TFA0); 729 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) | 730 ravb_read(ndev, TFA1); 731 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 732 shhwtstamps.hwtstamp = timespec64_to_ktime(ts); 733 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, 734 list) { 735 skb = ts_skb->skb; 736 tag = ts_skb->tag; 737 list_del(&ts_skb->list); 738 kfree(ts_skb); 739 if (tag == tfa_tag) { 740 skb_tstamp_tx(skb, &shhwtstamps); 741 dev_consume_skb_any(skb); 742 break; 743 } else { 744 dev_kfree_skb_any(skb); 745 } 746 } 747 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR); 748 } 749 } 750 751 static void ravb_rx_csum_gbeth(struct sk_buff *skb) 752 { 753 struct skb_shared_info *shinfo = skb_shinfo(skb); 754 size_t csum_len; 755 u16 *hw_csum; 756 757 /* The hardware checksum status is contained in 4 bytes appended to 758 * packet data. 759 * 760 * For ipv4, the first 2 bytes are the ip header checksum status. We can 761 * ignore this as it will always be re-checked in inet_gro_receive(). 762 * 763 * The last 2 bytes are the protocol checksum status which will be zero 764 * if the checksum has been validated. 765 */ 766 csum_len = sizeof(*hw_csum) * 2; 767 if (unlikely(skb->len < csum_len)) 768 return; 769 770 if (skb_is_nonlinear(skb)) { 771 skb_frag_t *last_frag = &shinfo->frags[shinfo->nr_frags - 1]; 772 773 hw_csum = (u16 *)(skb_frag_address(last_frag) + 774 skb_frag_size(last_frag)); 775 skb_frag_size_sub(last_frag, csum_len); 776 } else { 777 hw_csum = (u16 *)skb_tail_pointer(skb); 778 skb_trim(skb, skb->len - csum_len); 779 } 780 781 if (!get_unaligned(--hw_csum)) 782 skb->ip_summed = CHECKSUM_UNNECESSARY; 783 } 784 785 static void ravb_rx_csum(struct sk_buff *skb) 786 { 787 u8 *hw_csum; 788 789 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes 790 * appended to packet data 791 */ 792 if (unlikely(skb->len < sizeof(__sum16))) 793 return; 794 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16); 795 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum)); 796 skb->ip_summed = CHECKSUM_COMPLETE; 797 skb_trim(skb, skb->len - sizeof(__sum16)); 798 } 799 800 /* Packet receive function for Gigabit Ethernet */ 801 static int ravb_rx_gbeth(struct net_device *ndev, int budget, int q) 802 { 803 struct ravb_private *priv = netdev_priv(ndev); 804 const struct ravb_hw_info *info = priv->info; 805 struct net_device_stats *stats; 806 struct ravb_rx_desc *desc; 807 int rx_packets = 0; 808 u8 desc_status; 809 u16 desc_len; 810 u8 die_dt; 811 int entry; 812 int limit; 813 int i; 814 815 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 816 stats = &priv->stats[q]; 817 818 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 819 struct sk_buff *skb = NULL; 820 821 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 822 desc = &priv->rx_ring[q].desc[entry]; 823 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 824 break; 825 826 /* Descriptor type must be checked before all other reads */ 827 dma_rmb(); 828 desc_status = desc->msc; 829 desc_len = le16_to_cpu(desc->ds_cc) & RX_DS; 830 831 /* We use 0-byte descriptors to mark the DMA mapping errors */ 832 if (!desc_len) 833 continue; 834 835 if (desc_status & MSC_MC) 836 stats->multicast++; 837 838 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | MSC_CEEF)) { 839 stats->rx_errors++; 840 if (desc_status & MSC_CRC) 841 stats->rx_crc_errors++; 842 if (desc_status & MSC_RFE) 843 stats->rx_frame_errors++; 844 if (desc_status & (MSC_RTLF | MSC_RTSF)) 845 stats->rx_length_errors++; 846 if (desc_status & MSC_CEEF) 847 stats->rx_missed_errors++; 848 } else { 849 struct ravb_rx_buffer *rx_buff; 850 void *rx_addr; 851 852 rx_buff = &priv->rx_buffers[q][entry]; 853 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 854 die_dt = desc->die_dt & 0xF0; 855 dma_sync_single_for_cpu(ndev->dev.parent, 856 le32_to_cpu(desc->dptr), 857 desc_len, DMA_FROM_DEVICE); 858 859 switch (die_dt) { 860 case DT_FSINGLE: 861 case DT_FSTART: 862 /* Start of packet: Set initial data length. */ 863 skb = napi_build_skb(rx_addr, 864 info->rx_buffer_size); 865 if (unlikely(!skb)) { 866 stats->rx_errors++; 867 page_pool_put_page(priv->rx_pool[q], 868 rx_buff->page, 0, 869 true); 870 goto refill; 871 } 872 skb_mark_for_recycle(skb); 873 skb_put(skb, desc_len); 874 875 /* Save this skb if the packet spans multiple 876 * descriptors. 877 */ 878 if (die_dt == DT_FSTART) 879 priv->rx_1st_skb = skb; 880 break; 881 882 case DT_FMID: 883 case DT_FEND: 884 /* Continuing a packet: Add this buffer as an RX 885 * frag. 886 */ 887 888 /* rx_1st_skb will be NULL if napi_build_skb() 889 * failed for the first descriptor of a 890 * multi-descriptor packet. 891 */ 892 if (unlikely(!priv->rx_1st_skb)) { 893 stats->rx_errors++; 894 page_pool_put_page(priv->rx_pool[q], 895 rx_buff->page, 0, 896 true); 897 898 /* We may find a DT_FSINGLE or DT_FSTART 899 * descriptor in the queue which we can 900 * process, so don't give up yet. 901 */ 902 continue; 903 } 904 skb_add_rx_frag(priv->rx_1st_skb, 905 skb_shinfo(priv->rx_1st_skb)->nr_frags, 906 rx_buff->page, rx_buff->offset, 907 desc_len, info->rx_buffer_size); 908 909 /* Set skb to point at the whole packet so that 910 * we only need one code path for finishing a 911 * packet. 912 */ 913 skb = priv->rx_1st_skb; 914 } 915 916 switch (die_dt) { 917 case DT_FSINGLE: 918 case DT_FEND: 919 /* Finishing a packet: Determine protocol & 920 * checksum, hand off to NAPI and update our 921 * stats. 922 */ 923 skb->protocol = eth_type_trans(skb, ndev); 924 if (ndev->features & NETIF_F_RXCSUM) 925 ravb_rx_csum_gbeth(skb); 926 stats->rx_bytes += skb->len; 927 napi_gro_receive(&priv->napi[q], skb); 928 rx_packets++; 929 930 /* Clear rx_1st_skb so that it will only be 931 * non-NULL when valid. 932 */ 933 priv->rx_1st_skb = NULL; 934 } 935 936 /* Mark this RX buffer as consumed. */ 937 rx_buff->page = NULL; 938 } 939 } 940 941 refill: 942 /* Refill the RX ring buffers. */ 943 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 944 priv->cur_rx[q] - priv->dirty_rx[q], 945 GFP_ATOMIC); 946 947 stats->rx_packets += rx_packets; 948 return rx_packets; 949 } 950 951 static void ravb_rx_rcar_hwstamp(struct ravb_private *priv, int q, 952 struct ravb_ex_rx_desc *desc, 953 struct sk_buff *skb) 954 { 955 struct skb_shared_hwtstamps *shhwtstamps; 956 struct timespec64 ts; 957 bool get_ts; 958 959 if (q == RAVB_NC) 960 get_ts = priv->tstamp_rx_ctrl != HWTSTAMP_FILTER_NONE; 961 else 962 get_ts = priv->tstamp_rx_ctrl == HWTSTAMP_FILTER_ALL; 963 964 if (!get_ts) 965 return; 966 967 shhwtstamps = skb_hwtstamps(skb); 968 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 969 ts.tv_sec = ((u64)le16_to_cpu(desc->ts_sh) << 32) 970 | le32_to_cpu(desc->ts_sl); 971 ts.tv_nsec = le32_to_cpu(desc->ts_n); 972 shhwtstamps->hwtstamp = timespec64_to_ktime(ts); 973 } 974 975 /* Packet receive function for Ethernet AVB */ 976 static int ravb_rx_rcar(struct net_device *ndev, int budget, int q) 977 { 978 struct ravb_private *priv = netdev_priv(ndev); 979 const struct ravb_hw_info *info = priv->info; 980 struct net_device_stats *stats = &priv->stats[q]; 981 struct ravb_ex_rx_desc *desc; 982 unsigned int limit, i; 983 struct sk_buff *skb; 984 int rx_packets = 0; 985 u8 desc_status; 986 u16 pkt_len; 987 int entry; 988 989 limit = priv->dirty_rx[q] + priv->num_rx_ring[q] - priv->cur_rx[q]; 990 for (i = 0; i < limit; i++, priv->cur_rx[q]++) { 991 entry = priv->cur_rx[q] % priv->num_rx_ring[q]; 992 desc = &priv->rx_ring[q].ex_desc[entry]; 993 if (rx_packets == budget || desc->die_dt == DT_FEMPTY) 994 break; 995 996 /* Descriptor type must be checked before all other reads */ 997 dma_rmb(); 998 desc_status = desc->msc; 999 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS; 1000 1001 /* We use 0-byte descriptors to mark the DMA mapping errors */ 1002 if (!pkt_len) 1003 continue; 1004 1005 if (desc_status & MSC_MC) 1006 stats->multicast++; 1007 1008 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF | 1009 MSC_CEEF)) { 1010 stats->rx_errors++; 1011 if (desc_status & MSC_CRC) 1012 stats->rx_crc_errors++; 1013 if (desc_status & MSC_RFE) 1014 stats->rx_frame_errors++; 1015 if (desc_status & (MSC_RTLF | MSC_RTSF)) 1016 stats->rx_length_errors++; 1017 if (desc_status & MSC_CEEF) 1018 stats->rx_missed_errors++; 1019 } else { 1020 struct ravb_rx_buffer *rx_buff; 1021 void *rx_addr; 1022 1023 rx_buff = &priv->rx_buffers[q][entry]; 1024 rx_addr = page_address(rx_buff->page) + rx_buff->offset; 1025 dma_sync_single_for_cpu(ndev->dev.parent, 1026 le32_to_cpu(desc->dptr), 1027 pkt_len, DMA_FROM_DEVICE); 1028 1029 skb = napi_build_skb(rx_addr, info->rx_buffer_size); 1030 if (unlikely(!skb)) { 1031 stats->rx_errors++; 1032 page_pool_put_page(priv->rx_pool[q], 1033 rx_buff->page, 0, true); 1034 break; 1035 } 1036 skb_mark_for_recycle(skb); 1037 1038 ravb_rx_rcar_hwstamp(priv, q, desc, skb); 1039 1040 skb_put(skb, pkt_len); 1041 skb->protocol = eth_type_trans(skb, ndev); 1042 if (ndev->features & NETIF_F_RXCSUM) 1043 ravb_rx_csum(skb); 1044 napi_gro_receive(&priv->napi[q], skb); 1045 rx_packets++; 1046 stats->rx_bytes += pkt_len; 1047 1048 /* Mark this RX buffer as consumed. */ 1049 rx_buff->page = NULL; 1050 } 1051 } 1052 1053 /* Refill the RX ring buffers. */ 1054 priv->dirty_rx[q] += ravb_rx_ring_refill(ndev, q, 1055 priv->cur_rx[q] - priv->dirty_rx[q], 1056 GFP_ATOMIC); 1057 1058 stats->rx_packets += rx_packets; 1059 return rx_packets; 1060 } 1061 1062 /* Packet receive function for Ethernet AVB */ 1063 static int ravb_rx(struct net_device *ndev, int budget, int q) 1064 { 1065 struct ravb_private *priv = netdev_priv(ndev); 1066 const struct ravb_hw_info *info = priv->info; 1067 1068 return info->receive(ndev, budget, q); 1069 } 1070 1071 static void ravb_rcv_snd_disable(struct net_device *ndev) 1072 { 1073 /* Disable TX and RX */ 1074 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0); 1075 } 1076 1077 static void ravb_rcv_snd_enable(struct net_device *ndev) 1078 { 1079 /* Enable TX and RX */ 1080 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE); 1081 } 1082 1083 /* function for waiting dma process finished */ 1084 static int ravb_stop_dma(struct net_device *ndev) 1085 { 1086 struct ravb_private *priv = netdev_priv(ndev); 1087 const struct ravb_hw_info *info = priv->info; 1088 int error; 1089 1090 /* Wait for stopping the hardware TX process */ 1091 error = ravb_wait(ndev, TCCR, info->tccr_mask, 0); 1092 1093 if (error) 1094 return error; 1095 1096 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3, 1097 0); 1098 if (error) 1099 return error; 1100 1101 /* Stop the E-MAC's RX/TX processes. */ 1102 ravb_rcv_snd_disable(ndev); 1103 1104 /* Wait for stopping the RX DMA process */ 1105 error = ravb_wait(ndev, CSR, CSR_RPO, 0); 1106 if (error) 1107 return error; 1108 1109 /* Request for transmission suspension */ 1110 ravb_modify(ndev, CCC, CCC_DTSR, CCC_DTSR); 1111 error = ravb_wait(ndev, CSR, CSR_DTS, CSR_DTS); 1112 if (error) 1113 netdev_err(ndev, "failed to stop AXI BUS\n"); 1114 1115 /* Stop AVB-DMAC process */ 1116 return ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1117 } 1118 1119 /* E-MAC interrupt handler */ 1120 static void ravb_emac_interrupt_unlocked(struct net_device *ndev) 1121 { 1122 struct ravb_private *priv = netdev_priv(ndev); 1123 u32 ecsr, psr; 1124 1125 ecsr = ravb_read(ndev, ECSR); 1126 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */ 1127 1128 if (ecsr & ECSR_MPD) 1129 pm_wakeup_event(&priv->pdev->dev, 0); 1130 if (ecsr & ECSR_ICD) 1131 ndev->stats.tx_carrier_errors++; 1132 if (ecsr & ECSR_LCHNG) { 1133 /* Link changed */ 1134 if (priv->no_avb_link) 1135 return; 1136 psr = ravb_read(ndev, PSR); 1137 if (priv->avb_link_active_low) 1138 psr ^= PSR_LMON; 1139 if (!(psr & PSR_LMON)) { 1140 /* DIsable RX and TX */ 1141 ravb_rcv_snd_disable(ndev); 1142 } else { 1143 /* Enable RX and TX */ 1144 ravb_rcv_snd_enable(ndev); 1145 } 1146 } 1147 } 1148 1149 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id) 1150 { 1151 struct net_device *ndev = dev_id; 1152 struct ravb_private *priv = netdev_priv(ndev); 1153 struct device *dev = &priv->pdev->dev; 1154 irqreturn_t result = IRQ_HANDLED; 1155 1156 pm_runtime_get_noresume(dev); 1157 1158 if (unlikely(!pm_runtime_active(dev))) { 1159 result = IRQ_NONE; 1160 goto out_rpm_put; 1161 } 1162 1163 spin_lock(&priv->lock); 1164 ravb_emac_interrupt_unlocked(ndev); 1165 spin_unlock(&priv->lock); 1166 1167 out_rpm_put: 1168 pm_runtime_put_noidle(dev); 1169 return result; 1170 } 1171 1172 /* Error interrupt handler */ 1173 static void ravb_error_interrupt(struct net_device *ndev) 1174 { 1175 struct ravb_private *priv = netdev_priv(ndev); 1176 u32 eis, ris2; 1177 1178 eis = ravb_read(ndev, EIS); 1179 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS); 1180 if (eis & EIS_QFS) { 1181 ris2 = ravb_read(ndev, RIS2); 1182 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_QFF1 | RIS2_RFFF | RIS2_RESERVED), 1183 RIS2); 1184 1185 /* Receive Descriptor Empty int */ 1186 if (ris2 & RIS2_QFF0) 1187 priv->stats[RAVB_BE].rx_over_errors++; 1188 1189 /* Receive Descriptor Empty int */ 1190 if (ris2 & RIS2_QFF1) 1191 priv->stats[RAVB_NC].rx_over_errors++; 1192 1193 /* Receive FIFO Overflow int */ 1194 if (ris2 & RIS2_RFFF) 1195 priv->rx_fifo_errors++; 1196 } 1197 } 1198 1199 static bool ravb_queue_interrupt(struct net_device *ndev, int q) 1200 { 1201 struct ravb_private *priv = netdev_priv(ndev); 1202 const struct ravb_hw_info *info = priv->info; 1203 u32 ris0 = ravb_read(ndev, RIS0); 1204 u32 ric0 = ravb_read(ndev, RIC0); 1205 u32 tis = ravb_read(ndev, TIS); 1206 u32 tic = ravb_read(ndev, TIC); 1207 1208 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) { 1209 if (napi_schedule_prep(&priv->napi[q])) { 1210 /* Mask RX and TX interrupts */ 1211 if (!info->irq_en_dis) { 1212 ravb_write(ndev, ric0 & ~BIT(q), RIC0); 1213 ravb_write(ndev, tic & ~BIT(q), TIC); 1214 } else { 1215 ravb_write(ndev, BIT(q), RID0); 1216 ravb_write(ndev, BIT(q), TID); 1217 } 1218 __napi_schedule(&priv->napi[q]); 1219 } else { 1220 netdev_warn(ndev, 1221 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n", 1222 ris0, ric0); 1223 netdev_warn(ndev, 1224 " tx status 0x%08x, tx mask 0x%08x.\n", 1225 tis, tic); 1226 } 1227 return true; 1228 } 1229 return false; 1230 } 1231 1232 static bool ravb_timestamp_interrupt(struct net_device *ndev) 1233 { 1234 u32 tis = ravb_read(ndev, TIS); 1235 1236 if (tis & TIS_TFUF) { 1237 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS); 1238 ravb_get_tx_tstamp(ndev); 1239 return true; 1240 } 1241 return false; 1242 } 1243 1244 static irqreturn_t ravb_interrupt(int irq, void *dev_id) 1245 { 1246 struct net_device *ndev = dev_id; 1247 struct ravb_private *priv = netdev_priv(ndev); 1248 const struct ravb_hw_info *info = priv->info; 1249 struct device *dev = &priv->pdev->dev; 1250 irqreturn_t result = IRQ_NONE; 1251 u32 iss; 1252 1253 pm_runtime_get_noresume(dev); 1254 1255 if (unlikely(!pm_runtime_active(dev))) 1256 goto out_rpm_put; 1257 1258 spin_lock(&priv->lock); 1259 /* Get interrupt status */ 1260 iss = ravb_read(ndev, ISS); 1261 1262 /* Received and transmitted interrupts */ 1263 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) { 1264 int q; 1265 1266 /* Timestamp updated */ 1267 if (ravb_timestamp_interrupt(ndev)) 1268 result = IRQ_HANDLED; 1269 1270 /* Network control and best effort queue RX/TX */ 1271 if (info->nc_queues) { 1272 for (q = RAVB_NC; q >= RAVB_BE; q--) { 1273 if (ravb_queue_interrupt(ndev, q)) 1274 result = IRQ_HANDLED; 1275 } 1276 } else { 1277 if (ravb_queue_interrupt(ndev, RAVB_BE)) 1278 result = IRQ_HANDLED; 1279 } 1280 } 1281 1282 /* E-MAC status summary */ 1283 if (iss & ISS_MS) { 1284 ravb_emac_interrupt_unlocked(ndev); 1285 result = IRQ_HANDLED; 1286 } 1287 1288 /* Error status summary */ 1289 if (iss & ISS_ES) { 1290 ravb_error_interrupt(ndev); 1291 result = IRQ_HANDLED; 1292 } 1293 1294 /* gPTP interrupt status summary */ 1295 if (iss & ISS_CGIS) { 1296 ravb_ptp_interrupt(ndev); 1297 result = IRQ_HANDLED; 1298 } 1299 1300 spin_unlock(&priv->lock); 1301 1302 out_rpm_put: 1303 pm_runtime_put_noidle(dev); 1304 return result; 1305 } 1306 1307 /* Timestamp/Error/gPTP interrupt handler */ 1308 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id) 1309 { 1310 struct net_device *ndev = dev_id; 1311 struct ravb_private *priv = netdev_priv(ndev); 1312 struct device *dev = &priv->pdev->dev; 1313 irqreturn_t result = IRQ_NONE; 1314 u32 iss; 1315 1316 pm_runtime_get_noresume(dev); 1317 1318 if (unlikely(!pm_runtime_active(dev))) 1319 goto out_rpm_put; 1320 1321 spin_lock(&priv->lock); 1322 /* Get interrupt status */ 1323 iss = ravb_read(ndev, ISS); 1324 1325 /* Timestamp updated */ 1326 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev)) 1327 result = IRQ_HANDLED; 1328 1329 /* Error status summary */ 1330 if (iss & ISS_ES) { 1331 ravb_error_interrupt(ndev); 1332 result = IRQ_HANDLED; 1333 } 1334 1335 /* gPTP interrupt status summary */ 1336 if (iss & ISS_CGIS) { 1337 ravb_ptp_interrupt(ndev); 1338 result = IRQ_HANDLED; 1339 } 1340 1341 spin_unlock(&priv->lock); 1342 1343 out_rpm_put: 1344 pm_runtime_put_noidle(dev); 1345 return result; 1346 } 1347 1348 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q) 1349 { 1350 struct net_device *ndev = dev_id; 1351 struct ravb_private *priv = netdev_priv(ndev); 1352 struct device *dev = &priv->pdev->dev; 1353 irqreturn_t result = IRQ_NONE; 1354 1355 pm_runtime_get_noresume(dev); 1356 1357 if (unlikely(!pm_runtime_active(dev))) 1358 goto out_rpm_put; 1359 1360 spin_lock(&priv->lock); 1361 1362 /* Network control/Best effort queue RX/TX */ 1363 if (ravb_queue_interrupt(ndev, q)) 1364 result = IRQ_HANDLED; 1365 1366 spin_unlock(&priv->lock); 1367 1368 out_rpm_put: 1369 pm_runtime_put_noidle(dev); 1370 return result; 1371 } 1372 1373 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id) 1374 { 1375 return ravb_dma_interrupt(irq, dev_id, RAVB_BE); 1376 } 1377 1378 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id) 1379 { 1380 return ravb_dma_interrupt(irq, dev_id, RAVB_NC); 1381 } 1382 1383 static int ravb_poll(struct napi_struct *napi, int budget) 1384 { 1385 struct net_device *ndev = napi->dev; 1386 struct ravb_private *priv = netdev_priv(ndev); 1387 const struct ravb_hw_info *info = priv->info; 1388 unsigned long flags; 1389 int q = napi - priv->napi; 1390 int mask = BIT(q); 1391 int work_done; 1392 1393 /* Processing RX Descriptor Ring */ 1394 /* Clear RX interrupt */ 1395 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0); 1396 work_done = ravb_rx(ndev, budget, q); 1397 1398 /* Processing TX Descriptor Ring */ 1399 spin_lock_irqsave(&priv->lock, flags); 1400 /* Clear TX interrupt */ 1401 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS); 1402 ravb_tx_free(ndev, q, true); 1403 netif_wake_subqueue(ndev, q); 1404 spin_unlock_irqrestore(&priv->lock, flags); 1405 1406 /* Receive error message handling */ 1407 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors; 1408 if (info->nc_queues) 1409 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors; 1410 if (priv->rx_over_errors != ndev->stats.rx_over_errors) 1411 ndev->stats.rx_over_errors = priv->rx_over_errors; 1412 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors) 1413 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors; 1414 1415 if (work_done < budget && napi_complete_done(napi, work_done)) { 1416 /* Re-enable RX/TX interrupts */ 1417 spin_lock_irqsave(&priv->lock, flags); 1418 if (!info->irq_en_dis) { 1419 ravb_modify(ndev, RIC0, mask, mask); 1420 ravb_modify(ndev, TIC, mask, mask); 1421 } else { 1422 ravb_write(ndev, mask, RIE0); 1423 ravb_write(ndev, mask, TIE); 1424 } 1425 spin_unlock_irqrestore(&priv->lock, flags); 1426 } 1427 1428 return work_done; 1429 } 1430 1431 static void ravb_set_duplex_gbeth(struct net_device *ndev) 1432 { 1433 struct ravb_private *priv = netdev_priv(ndev); 1434 1435 ravb_modify(ndev, ECMR, ECMR_DM, priv->duplex > 0 ? ECMR_DM : 0); 1436 } 1437 1438 /* PHY state control function */ 1439 static void ravb_adjust_link(struct net_device *ndev) 1440 { 1441 struct ravb_private *priv = netdev_priv(ndev); 1442 const struct ravb_hw_info *info = priv->info; 1443 struct phy_device *phydev = ndev->phydev; 1444 bool new_state = false; 1445 unsigned long flags; 1446 1447 spin_lock_irqsave(&priv->lock, flags); 1448 1449 /* Disable TX and RX right over here, if E-MAC change is ignored */ 1450 if (priv->no_avb_link) 1451 ravb_rcv_snd_disable(ndev); 1452 1453 if (phydev->link) { 1454 if (info->half_duplex && phydev->duplex != priv->duplex) { 1455 new_state = true; 1456 priv->duplex = phydev->duplex; 1457 ravb_set_duplex_gbeth(ndev); 1458 } 1459 1460 if (phydev->speed != priv->speed) { 1461 new_state = true; 1462 priv->speed = phydev->speed; 1463 info->set_rate(ndev); 1464 } 1465 if (!priv->link) { 1466 ravb_modify(ndev, ECMR, ECMR_TXF, 0); 1467 new_state = true; 1468 priv->link = phydev->link; 1469 } 1470 } else if (priv->link) { 1471 new_state = true; 1472 priv->link = 0; 1473 priv->speed = 0; 1474 if (info->half_duplex) 1475 priv->duplex = -1; 1476 } 1477 1478 /* Enable TX and RX right over here, if E-MAC change is ignored */ 1479 if (priv->no_avb_link && phydev->link) 1480 ravb_rcv_snd_enable(ndev); 1481 1482 spin_unlock_irqrestore(&priv->lock, flags); 1483 1484 if (new_state && netif_msg_link(priv)) 1485 phy_print_status(phydev); 1486 } 1487 1488 /* PHY init function */ 1489 static int ravb_phy_init(struct net_device *ndev) 1490 { 1491 struct device_node *np = ndev->dev.parent->of_node; 1492 struct ravb_private *priv = netdev_priv(ndev); 1493 const struct ravb_hw_info *info = priv->info; 1494 struct phy_device *phydev; 1495 struct device_node *pn; 1496 phy_interface_t iface; 1497 int err; 1498 1499 priv->link = 0; 1500 priv->speed = 0; 1501 priv->duplex = -1; 1502 1503 /* Try connecting to PHY */ 1504 pn = of_parse_phandle(np, "phy-handle", 0); 1505 if (!pn) { 1506 /* In the case of a fixed PHY, the DT node associated 1507 * to the PHY is the Ethernet MAC DT node. 1508 */ 1509 if (of_phy_is_fixed_link(np)) { 1510 err = of_phy_register_fixed_link(np); 1511 if (err) 1512 return err; 1513 } 1514 pn = of_node_get(np); 1515 } 1516 1517 iface = priv->rgmii_override ? PHY_INTERFACE_MODE_RGMII 1518 : priv->phy_interface; 1519 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0, iface); 1520 of_node_put(pn); 1521 if (!phydev) { 1522 netdev_err(ndev, "failed to connect PHY\n"); 1523 err = -ENOENT; 1524 goto err_deregister_fixed_link; 1525 } 1526 1527 if (!info->half_duplex) { 1528 /* 10BASE, Pause and Asym Pause is not supported */ 1529 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 1530 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_10baseT_Full_BIT); 1531 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Pause_BIT); 1532 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 1533 1534 /* Half Duplex is not supported */ 1535 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 1536 phy_remove_link_mode(phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 1537 } 1538 1539 phy_attached_info(phydev); 1540 1541 return 0; 1542 1543 err_deregister_fixed_link: 1544 if (of_phy_is_fixed_link(np)) 1545 of_phy_deregister_fixed_link(np); 1546 1547 return err; 1548 } 1549 1550 /* PHY control start function */ 1551 static int ravb_phy_start(struct net_device *ndev) 1552 { 1553 int error; 1554 1555 error = ravb_phy_init(ndev); 1556 if (error) 1557 return error; 1558 1559 phy_start(ndev->phydev); 1560 1561 return 0; 1562 } 1563 1564 static u32 ravb_get_msglevel(struct net_device *ndev) 1565 { 1566 struct ravb_private *priv = netdev_priv(ndev); 1567 1568 return priv->msg_enable; 1569 } 1570 1571 static void ravb_set_msglevel(struct net_device *ndev, u32 value) 1572 { 1573 struct ravb_private *priv = netdev_priv(ndev); 1574 1575 priv->msg_enable = value; 1576 } 1577 1578 static const char ravb_gstrings_stats_gbeth[][ETH_GSTRING_LEN] = { 1579 "rx_queue_0_current", 1580 "tx_queue_0_current", 1581 "rx_queue_0_dirty", 1582 "tx_queue_0_dirty", 1583 "rx_queue_0_packets", 1584 "tx_queue_0_packets", 1585 "rx_queue_0_bytes", 1586 "tx_queue_0_bytes", 1587 "rx_queue_0_mcast_packets", 1588 "rx_queue_0_errors", 1589 "rx_queue_0_crc_errors", 1590 "rx_queue_0_frame_errors", 1591 "rx_queue_0_length_errors", 1592 "rx_queue_0_csum_offload_errors", 1593 "rx_queue_0_over_errors", 1594 }; 1595 1596 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = { 1597 "rx_queue_0_current", 1598 "tx_queue_0_current", 1599 "rx_queue_0_dirty", 1600 "tx_queue_0_dirty", 1601 "rx_queue_0_packets", 1602 "tx_queue_0_packets", 1603 "rx_queue_0_bytes", 1604 "tx_queue_0_bytes", 1605 "rx_queue_0_mcast_packets", 1606 "rx_queue_0_errors", 1607 "rx_queue_0_crc_errors", 1608 "rx_queue_0_frame_errors", 1609 "rx_queue_0_length_errors", 1610 "rx_queue_0_missed_errors", 1611 "rx_queue_0_over_errors", 1612 1613 "rx_queue_1_current", 1614 "tx_queue_1_current", 1615 "rx_queue_1_dirty", 1616 "tx_queue_1_dirty", 1617 "rx_queue_1_packets", 1618 "tx_queue_1_packets", 1619 "rx_queue_1_bytes", 1620 "tx_queue_1_bytes", 1621 "rx_queue_1_mcast_packets", 1622 "rx_queue_1_errors", 1623 "rx_queue_1_crc_errors", 1624 "rx_queue_1_frame_errors", 1625 "rx_queue_1_length_errors", 1626 "rx_queue_1_missed_errors", 1627 "rx_queue_1_over_errors", 1628 }; 1629 1630 static int ravb_get_sset_count(struct net_device *netdev, int sset) 1631 { 1632 struct ravb_private *priv = netdev_priv(netdev); 1633 const struct ravb_hw_info *info = priv->info; 1634 1635 switch (sset) { 1636 case ETH_SS_STATS: 1637 return info->stats_len; 1638 default: 1639 return -EOPNOTSUPP; 1640 } 1641 } 1642 1643 static void ravb_get_ethtool_stats(struct net_device *ndev, 1644 struct ethtool_stats *estats, u64 *data) 1645 { 1646 struct ravb_private *priv = netdev_priv(ndev); 1647 const struct ravb_hw_info *info = priv->info; 1648 int num_rx_q; 1649 int i = 0; 1650 int q; 1651 1652 num_rx_q = info->nc_queues ? NUM_RX_QUEUE : 1; 1653 /* Device-specific stats */ 1654 for (q = RAVB_BE; q < num_rx_q; q++) { 1655 struct net_device_stats *stats = &priv->stats[q]; 1656 1657 data[i++] = priv->cur_rx[q]; 1658 data[i++] = priv->cur_tx[q]; 1659 data[i++] = priv->dirty_rx[q]; 1660 data[i++] = priv->dirty_tx[q]; 1661 data[i++] = stats->rx_packets; 1662 data[i++] = stats->tx_packets; 1663 data[i++] = stats->rx_bytes; 1664 data[i++] = stats->tx_bytes; 1665 data[i++] = stats->multicast; 1666 data[i++] = stats->rx_errors; 1667 data[i++] = stats->rx_crc_errors; 1668 data[i++] = stats->rx_frame_errors; 1669 data[i++] = stats->rx_length_errors; 1670 data[i++] = stats->rx_missed_errors; 1671 data[i++] = stats->rx_over_errors; 1672 } 1673 } 1674 1675 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1676 { 1677 struct ravb_private *priv = netdev_priv(ndev); 1678 const struct ravb_hw_info *info = priv->info; 1679 1680 switch (stringset) { 1681 case ETH_SS_STATS: 1682 memcpy(data, info->gstrings_stats, info->gstrings_size); 1683 break; 1684 } 1685 } 1686 1687 static void ravb_get_ringparam(struct net_device *ndev, 1688 struct ethtool_ringparam *ring, 1689 struct kernel_ethtool_ringparam *kernel_ring, 1690 struct netlink_ext_ack *extack) 1691 { 1692 struct ravb_private *priv = netdev_priv(ndev); 1693 1694 ring->rx_max_pending = BE_RX_RING_MAX; 1695 ring->tx_max_pending = BE_TX_RING_MAX; 1696 ring->rx_pending = priv->num_rx_ring[RAVB_BE]; 1697 ring->tx_pending = priv->num_tx_ring[RAVB_BE]; 1698 } 1699 1700 static int ravb_set_ringparam(struct net_device *ndev, 1701 struct ethtool_ringparam *ring, 1702 struct kernel_ethtool_ringparam *kernel_ring, 1703 struct netlink_ext_ack *extack) 1704 { 1705 struct ravb_private *priv = netdev_priv(ndev); 1706 const struct ravb_hw_info *info = priv->info; 1707 int error; 1708 1709 if (ring->tx_pending > BE_TX_RING_MAX || 1710 ring->rx_pending > BE_RX_RING_MAX || 1711 ring->tx_pending < BE_TX_RING_MIN || 1712 ring->rx_pending < BE_RX_RING_MIN) 1713 return -EINVAL; 1714 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1715 return -EINVAL; 1716 1717 if (netif_running(ndev)) { 1718 netif_device_detach(ndev); 1719 /* Stop PTP Clock driver */ 1720 if (info->gptp) 1721 ravb_ptp_stop(ndev); 1722 /* Wait for DMA stopping */ 1723 error = ravb_stop_dma(ndev); 1724 if (error) { 1725 netdev_err(ndev, 1726 "cannot set ringparam! Any AVB processes are still running?\n"); 1727 return error; 1728 } 1729 synchronize_irq(ndev->irq); 1730 1731 /* Free all the skb's in the RX queue and the DMA buffers. */ 1732 ravb_ring_free(ndev, RAVB_BE); 1733 if (info->nc_queues) 1734 ravb_ring_free(ndev, RAVB_NC); 1735 } 1736 1737 /* Set new parameters */ 1738 priv->num_rx_ring[RAVB_BE] = ring->rx_pending; 1739 priv->num_tx_ring[RAVB_BE] = ring->tx_pending; 1740 1741 if (netif_running(ndev)) { 1742 error = ravb_dmac_init(ndev); 1743 if (error) { 1744 netdev_err(ndev, 1745 "%s: ravb_dmac_init() failed, error %d\n", 1746 __func__, error); 1747 return error; 1748 } 1749 1750 ravb_emac_init(ndev); 1751 1752 /* Initialise PTP Clock driver */ 1753 if (info->gptp) 1754 ravb_ptp_init(ndev, priv->pdev); 1755 1756 netif_device_attach(ndev); 1757 } 1758 1759 return 0; 1760 } 1761 1762 static int ravb_get_ts_info(struct net_device *ndev, 1763 struct kernel_ethtool_ts_info *info) 1764 { 1765 struct ravb_private *priv = netdev_priv(ndev); 1766 const struct ravb_hw_info *hw_info = priv->info; 1767 1768 if (hw_info->gptp || hw_info->ccc_gac) { 1769 info->so_timestamping = 1770 SOF_TIMESTAMPING_TX_SOFTWARE | 1771 SOF_TIMESTAMPING_TX_HARDWARE | 1772 SOF_TIMESTAMPING_RX_HARDWARE | 1773 SOF_TIMESTAMPING_RAW_HARDWARE; 1774 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); 1775 info->rx_filters = 1776 (1 << HWTSTAMP_FILTER_NONE) | 1777 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 1778 (1 << HWTSTAMP_FILTER_ALL); 1779 info->phc_index = ptp_clock_index(priv->ptp.clock); 1780 } 1781 1782 return 0; 1783 } 1784 1785 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1786 { 1787 struct ravb_private *priv = netdev_priv(ndev); 1788 1789 wol->supported = WAKE_MAGIC; 1790 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0; 1791 } 1792 1793 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1794 { 1795 struct ravb_private *priv = netdev_priv(ndev); 1796 const struct ravb_hw_info *info = priv->info; 1797 1798 if (!info->magic_pkt || (wol->wolopts & ~WAKE_MAGIC)) 1799 return -EOPNOTSUPP; 1800 1801 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC); 1802 1803 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled); 1804 1805 return 0; 1806 } 1807 1808 static const struct ethtool_ops ravb_ethtool_ops = { 1809 .nway_reset = phy_ethtool_nway_reset, 1810 .get_msglevel = ravb_get_msglevel, 1811 .set_msglevel = ravb_set_msglevel, 1812 .get_link = ethtool_op_get_link, 1813 .get_strings = ravb_get_strings, 1814 .get_ethtool_stats = ravb_get_ethtool_stats, 1815 .get_sset_count = ravb_get_sset_count, 1816 .get_ringparam = ravb_get_ringparam, 1817 .set_ringparam = ravb_set_ringparam, 1818 .get_ts_info = ravb_get_ts_info, 1819 .get_link_ksettings = phy_ethtool_get_link_ksettings, 1820 .set_link_ksettings = phy_ethtool_set_link_ksettings, 1821 .get_wol = ravb_get_wol, 1822 .set_wol = ravb_set_wol, 1823 }; 1824 1825 static int ravb_set_config_mode(struct net_device *ndev) 1826 { 1827 struct ravb_private *priv = netdev_priv(ndev); 1828 const struct ravb_hw_info *info = priv->info; 1829 int error; 1830 1831 if (info->gptp) { 1832 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1833 if (error) 1834 return error; 1835 /* Set CSEL value */ 1836 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB); 1837 } else if (info->ccc_gac) { 1838 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG | CCC_GAC | CCC_CSEL_HPB); 1839 } else { 1840 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 1841 } 1842 1843 return error; 1844 } 1845 1846 static void ravb_set_gti(struct net_device *ndev) 1847 { 1848 struct ravb_private *priv = netdev_priv(ndev); 1849 const struct ravb_hw_info *info = priv->info; 1850 1851 if (!(info->gptp || info->ccc_gac)) 1852 return; 1853 1854 ravb_write(ndev, priv->gti_tiv, GTI); 1855 1856 /* Request GTI loading */ 1857 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI); 1858 } 1859 1860 static int ravb_compute_gti(struct net_device *ndev) 1861 { 1862 struct ravb_private *priv = netdev_priv(ndev); 1863 const struct ravb_hw_info *info = priv->info; 1864 struct device *dev = ndev->dev.parent; 1865 unsigned long rate; 1866 u64 inc; 1867 1868 if (!(info->gptp || info->ccc_gac)) 1869 return 0; 1870 1871 if (info->gptp_ref_clk) 1872 rate = clk_get_rate(priv->gptp_clk); 1873 else 1874 rate = clk_get_rate(priv->clk); 1875 if (!rate) 1876 return -EINVAL; 1877 1878 inc = div64_ul(1000000000ULL << 20, rate); 1879 1880 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) { 1881 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n", 1882 inc, GTI_TIV_MIN, GTI_TIV_MAX); 1883 return -EINVAL; 1884 } 1885 priv->gti_tiv = inc; 1886 1887 return 0; 1888 } 1889 1890 /* Set tx and rx clock internal delay modes */ 1891 static void ravb_parse_delay_mode(struct device_node *np, struct net_device *ndev) 1892 { 1893 struct ravb_private *priv = netdev_priv(ndev); 1894 bool explicit_delay = false; 1895 u32 delay; 1896 1897 if (!priv->info->internal_delay) 1898 return; 1899 1900 if (!of_property_read_u32(np, "rx-internal-delay-ps", &delay)) { 1901 /* Valid values are 0 and 1800, according to DT bindings */ 1902 priv->rxcidm = !!delay; 1903 explicit_delay = true; 1904 } 1905 if (!of_property_read_u32(np, "tx-internal-delay-ps", &delay)) { 1906 /* Valid values are 0 and 2000, according to DT bindings */ 1907 priv->txcidm = !!delay; 1908 explicit_delay = true; 1909 } 1910 1911 if (explicit_delay) 1912 return; 1913 1914 /* Fall back to legacy rgmii-*id behavior */ 1915 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1916 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) { 1917 priv->rxcidm = 1; 1918 priv->rgmii_override = 1; 1919 } 1920 1921 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || 1922 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) { 1923 priv->txcidm = 1; 1924 priv->rgmii_override = 1; 1925 } 1926 } 1927 1928 static void ravb_set_delay_mode(struct net_device *ndev) 1929 { 1930 struct ravb_private *priv = netdev_priv(ndev); 1931 u32 set = 0; 1932 1933 if (!priv->info->internal_delay) 1934 return; 1935 1936 if (priv->rxcidm) 1937 set |= APSR_RDM; 1938 if (priv->txcidm) 1939 set |= APSR_TDM; 1940 ravb_modify(ndev, APSR, APSR_RDM | APSR_TDM, set); 1941 } 1942 1943 /* Network device open function for Ethernet AVB */ 1944 static int ravb_open(struct net_device *ndev) 1945 { 1946 struct ravb_private *priv = netdev_priv(ndev); 1947 const struct ravb_hw_info *info = priv->info; 1948 struct device *dev = &priv->pdev->dev; 1949 int error; 1950 1951 napi_enable(&priv->napi[RAVB_BE]); 1952 if (info->nc_queues) 1953 napi_enable(&priv->napi[RAVB_NC]); 1954 1955 error = pm_runtime_resume_and_get(dev); 1956 if (error < 0) 1957 goto out_napi_off; 1958 1959 /* Set AVB config mode */ 1960 error = ravb_set_config_mode(ndev); 1961 if (error) 1962 goto out_rpm_put; 1963 1964 ravb_set_delay_mode(ndev); 1965 ravb_write(ndev, priv->desc_bat_dma, DBAT); 1966 1967 /* Device init */ 1968 error = ravb_dmac_init(ndev); 1969 if (error) 1970 goto out_set_reset; 1971 1972 ravb_emac_init(ndev); 1973 1974 ravb_set_gti(ndev); 1975 1976 /* Initialise PTP Clock driver */ 1977 if (info->gptp || info->ccc_gac) 1978 ravb_ptp_init(ndev, priv->pdev); 1979 1980 /* PHY control start */ 1981 error = ravb_phy_start(ndev); 1982 if (error) 1983 goto out_ptp_stop; 1984 1985 netif_tx_start_all_queues(ndev); 1986 1987 return 0; 1988 1989 out_ptp_stop: 1990 /* Stop PTP Clock driver */ 1991 if (info->gptp || info->ccc_gac) 1992 ravb_ptp_stop(ndev); 1993 ravb_stop_dma(ndev); 1994 out_set_reset: 1995 ravb_set_opmode(ndev, CCC_OPC_RESET); 1996 out_rpm_put: 1997 pm_runtime_put_autosuspend(dev); 1998 out_napi_off: 1999 if (info->nc_queues) 2000 napi_disable(&priv->napi[RAVB_NC]); 2001 napi_disable(&priv->napi[RAVB_BE]); 2002 return error; 2003 } 2004 2005 /* Timeout function for Ethernet AVB */ 2006 static void ravb_tx_timeout(struct net_device *ndev, unsigned int txqueue) 2007 { 2008 struct ravb_private *priv = netdev_priv(ndev); 2009 2010 netif_err(priv, tx_err, ndev, 2011 "transmit timed out, status %08x, resetting...\n", 2012 ravb_read(ndev, ISS)); 2013 2014 /* tx_errors count up */ 2015 ndev->stats.tx_errors++; 2016 2017 schedule_work(&priv->work); 2018 } 2019 2020 static void ravb_tx_timeout_work(struct work_struct *work) 2021 { 2022 struct ravb_private *priv = container_of(work, struct ravb_private, 2023 work); 2024 const struct ravb_hw_info *info = priv->info; 2025 struct net_device *ndev = priv->ndev; 2026 int error; 2027 2028 if (!rtnl_trylock()) { 2029 usleep_range(1000, 2000); 2030 schedule_work(&priv->work); 2031 return; 2032 } 2033 2034 netif_tx_stop_all_queues(ndev); 2035 2036 /* Stop PTP Clock driver */ 2037 if (info->gptp) 2038 ravb_ptp_stop(ndev); 2039 2040 /* Wait for DMA stopping */ 2041 if (ravb_stop_dma(ndev)) { 2042 /* If ravb_stop_dma() fails, the hardware is still operating 2043 * for TX and/or RX. So, this should not call the following 2044 * functions because ravb_dmac_init() is possible to fail too. 2045 * Also, this should not retry ravb_stop_dma() again and again 2046 * here because it's possible to wait forever. So, this just 2047 * re-enables the TX and RX and skip the following 2048 * re-initialization procedure. 2049 */ 2050 ravb_rcv_snd_enable(ndev); 2051 goto out; 2052 } 2053 2054 ravb_ring_free(ndev, RAVB_BE); 2055 if (info->nc_queues) 2056 ravb_ring_free(ndev, RAVB_NC); 2057 2058 /* Device init */ 2059 error = ravb_dmac_init(ndev); 2060 if (error) { 2061 /* If ravb_dmac_init() fails, descriptors are freed. So, this 2062 * should return here to avoid re-enabling the TX and RX in 2063 * ravb_emac_init(). 2064 */ 2065 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n", 2066 __func__, error); 2067 goto out_unlock; 2068 } 2069 ravb_emac_init(ndev); 2070 2071 out: 2072 /* Initialise PTP Clock driver */ 2073 if (info->gptp) 2074 ravb_ptp_init(ndev, priv->pdev); 2075 2076 netif_tx_start_all_queues(ndev); 2077 2078 out_unlock: 2079 rtnl_unlock(); 2080 } 2081 2082 static bool ravb_can_tx_csum_gbeth(struct sk_buff *skb) 2083 { 2084 u16 net_protocol = ntohs(skb->protocol); 2085 u8 inner_protocol; 2086 2087 /* GbEth IP can calculate the checksum if: 2088 * - there are zero or one VLAN headers with TPID=0x8100 2089 * - the network protocol is IPv4 or IPv6 2090 * - the transport protocol is TCP, UDP or ICMP 2091 * - the packet is not fragmented 2092 */ 2093 2094 if (net_protocol == ETH_P_8021Q) { 2095 struct vlan_hdr vhdr, *vh; 2096 2097 vh = skb_header_pointer(skb, ETH_HLEN, sizeof(vhdr), &vhdr); 2098 if (!vh) 2099 return false; 2100 2101 net_protocol = ntohs(vh->h_vlan_encapsulated_proto); 2102 } 2103 2104 switch (net_protocol) { 2105 case ETH_P_IP: 2106 inner_protocol = ip_hdr(skb)->protocol; 2107 break; 2108 case ETH_P_IPV6: 2109 inner_protocol = ipv6_hdr(skb)->nexthdr; 2110 break; 2111 default: 2112 return false; 2113 } 2114 2115 switch (inner_protocol) { 2116 case IPPROTO_TCP: 2117 case IPPROTO_UDP: 2118 return true; 2119 default: 2120 return false; 2121 } 2122 } 2123 2124 /* Packet transmit function for Ethernet AVB */ 2125 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev) 2126 { 2127 struct ravb_private *priv = netdev_priv(ndev); 2128 const struct ravb_hw_info *info = priv->info; 2129 unsigned int num_tx_desc = priv->num_tx_desc; 2130 u16 q = skb_get_queue_mapping(skb); 2131 struct ravb_tstamp_skb *ts_skb; 2132 struct ravb_tx_desc *desc; 2133 unsigned long flags; 2134 dma_addr_t dma_addr; 2135 void *buffer; 2136 u32 entry; 2137 u32 len; 2138 2139 if (skb->ip_summed == CHECKSUM_PARTIAL && !ravb_can_tx_csum_gbeth(skb)) 2140 skb_checksum_help(skb); 2141 2142 spin_lock_irqsave(&priv->lock, flags); 2143 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) * 2144 num_tx_desc) { 2145 netif_err(priv, tx_queued, ndev, 2146 "still transmitting with the full ring!\n"); 2147 netif_stop_subqueue(ndev, q); 2148 spin_unlock_irqrestore(&priv->lock, flags); 2149 return NETDEV_TX_BUSY; 2150 } 2151 2152 if (skb_put_padto(skb, ETH_ZLEN)) 2153 goto exit; 2154 2155 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * num_tx_desc); 2156 priv->tx_skb[q][entry / num_tx_desc] = skb; 2157 2158 if (num_tx_desc > 1) { 2159 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) + 2160 entry / num_tx_desc * DPTR_ALIGN; 2161 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data; 2162 2163 /* Zero length DMA descriptors are problematic as they seem 2164 * to terminate DMA transfers. Avoid them by simply using a 2165 * length of DPTR_ALIGN (4) when skb data is aligned to 2166 * DPTR_ALIGN. 2167 * 2168 * As skb is guaranteed to have at least ETH_ZLEN (60) 2169 * bytes of data by the call to skb_put_padto() above this 2170 * is safe with respect to both the length of the first DMA 2171 * descriptor (len) overflowing the available data and the 2172 * length of the second DMA descriptor (skb->len - len) 2173 * being negative. 2174 */ 2175 if (len == 0) 2176 len = DPTR_ALIGN; 2177 2178 memcpy(buffer, skb->data, len); 2179 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2180 DMA_TO_DEVICE); 2181 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2182 goto drop; 2183 2184 desc = &priv->tx_ring[q][entry]; 2185 desc->ds_tagl = cpu_to_le16(len); 2186 desc->dptr = cpu_to_le32(dma_addr); 2187 2188 buffer = skb->data + len; 2189 len = skb->len - len; 2190 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, 2191 DMA_TO_DEVICE); 2192 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2193 goto unmap; 2194 2195 desc++; 2196 } else { 2197 desc = &priv->tx_ring[q][entry]; 2198 len = skb->len; 2199 dma_addr = dma_map_single(ndev->dev.parent, skb->data, skb->len, 2200 DMA_TO_DEVICE); 2201 if (dma_mapping_error(ndev->dev.parent, dma_addr)) 2202 goto drop; 2203 } 2204 desc->ds_tagl = cpu_to_le16(len); 2205 desc->dptr = cpu_to_le32(dma_addr); 2206 2207 /* TX timestamp required */ 2208 if (info->gptp || info->ccc_gac) { 2209 if (q == RAVB_NC) { 2210 ts_skb = kmalloc_obj(*ts_skb, GFP_ATOMIC); 2211 if (!ts_skb) { 2212 if (num_tx_desc > 1) { 2213 desc--; 2214 dma_unmap_single(ndev->dev.parent, dma_addr, 2215 len, DMA_TO_DEVICE); 2216 } 2217 goto unmap; 2218 } 2219 ts_skb->skb = skb_get(skb); 2220 ts_skb->tag = priv->ts_skb_tag++; 2221 priv->ts_skb_tag &= 0x3ff; 2222 list_add_tail(&ts_skb->list, &priv->ts_skb_list); 2223 2224 /* TAG and timestamp required flag */ 2225 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2226 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR; 2227 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12); 2228 } 2229 2230 skb_tx_timestamp(skb); 2231 } 2232 2233 if (num_tx_desc > 1) { 2234 desc->die_dt = DT_FEND; 2235 desc--; 2236 /* When using multi-descriptors, DT_FEND needs to get written 2237 * before DT_FSTART, but the compiler may reorder the memory 2238 * writes in an attempt to optimize the code. 2239 * Use a dma_wmb() barrier to make sure DT_FEND and DT_FSTART 2240 * are written exactly in the order shown in the code. 2241 * This is particularly important for cases where the DMA engine 2242 * is already running when we are running this code. If the DMA 2243 * sees DT_FSTART without the corresponding DT_FEND it will enter 2244 * an error condition. 2245 */ 2246 dma_wmb(); 2247 desc->die_dt = DT_FSTART; 2248 } else { 2249 /* Descriptor type must be set after all the above writes */ 2250 dma_wmb(); 2251 desc->die_dt = DT_FSINGLE; 2252 } 2253 2254 /* Before ringing the doorbell we need to make sure that the latest 2255 * writes have been committed to memory, otherwise it could delay 2256 * things until the doorbell is rang again. 2257 * This is in replacement of the read operation mentioned in the HW 2258 * manuals. 2259 */ 2260 dma_wmb(); 2261 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q); 2262 2263 priv->cur_tx[q] += num_tx_desc; 2264 if (priv->cur_tx[q] - priv->dirty_tx[q] > 2265 (priv->num_tx_ring[q] - 1) * num_tx_desc && 2266 !ravb_tx_free(ndev, q, true)) 2267 netif_stop_subqueue(ndev, q); 2268 2269 exit: 2270 spin_unlock_irqrestore(&priv->lock, flags); 2271 return NETDEV_TX_OK; 2272 2273 unmap: 2274 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr), 2275 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE); 2276 drop: 2277 dev_kfree_skb_any(skb); 2278 priv->tx_skb[q][entry / num_tx_desc] = NULL; 2279 goto exit; 2280 } 2281 2282 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb, 2283 struct net_device *sb_dev) 2284 { 2285 /* If skb needs TX timestamp, it is handled in network control queue */ 2286 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC : 2287 RAVB_BE; 2288 2289 } 2290 2291 static struct net_device_stats *ravb_get_stats(struct net_device *ndev) 2292 { 2293 struct ravb_private *priv = netdev_priv(ndev); 2294 const struct ravb_hw_info *info = priv->info; 2295 struct net_device_stats *nstats, *stats0, *stats1; 2296 struct device *dev = &priv->pdev->dev; 2297 2298 nstats = &ndev->stats; 2299 2300 pm_runtime_get_noresume(dev); 2301 2302 if (!pm_runtime_active(dev)) 2303 goto out_rpm_put; 2304 2305 stats0 = &priv->stats[RAVB_BE]; 2306 2307 if (info->tx_counters) { 2308 nstats->tx_dropped += ravb_read(ndev, TROCR); 2309 ravb_write(ndev, 0, TROCR); /* (write clear) */ 2310 } 2311 2312 if (info->carrier_counters) { 2313 nstats->collisions += ravb_read(ndev, CXR41); 2314 ravb_write(ndev, 0, CXR41); /* (write clear) */ 2315 nstats->tx_carrier_errors += ravb_read(ndev, CXR42); 2316 ravb_write(ndev, 0, CXR42); /* (write clear) */ 2317 } 2318 2319 nstats->rx_packets = stats0->rx_packets; 2320 nstats->tx_packets = stats0->tx_packets; 2321 nstats->rx_bytes = stats0->rx_bytes; 2322 nstats->tx_bytes = stats0->tx_bytes; 2323 nstats->multicast = stats0->multicast; 2324 nstats->rx_errors = stats0->rx_errors; 2325 nstats->rx_crc_errors = stats0->rx_crc_errors; 2326 nstats->rx_frame_errors = stats0->rx_frame_errors; 2327 nstats->rx_length_errors = stats0->rx_length_errors; 2328 nstats->rx_missed_errors = stats0->rx_missed_errors; 2329 nstats->rx_over_errors = stats0->rx_over_errors; 2330 if (info->nc_queues) { 2331 stats1 = &priv->stats[RAVB_NC]; 2332 2333 nstats->rx_packets += stats1->rx_packets; 2334 nstats->tx_packets += stats1->tx_packets; 2335 nstats->rx_bytes += stats1->rx_bytes; 2336 nstats->tx_bytes += stats1->tx_bytes; 2337 nstats->multicast += stats1->multicast; 2338 nstats->rx_errors += stats1->rx_errors; 2339 nstats->rx_crc_errors += stats1->rx_crc_errors; 2340 nstats->rx_frame_errors += stats1->rx_frame_errors; 2341 nstats->rx_length_errors += stats1->rx_length_errors; 2342 nstats->rx_missed_errors += stats1->rx_missed_errors; 2343 nstats->rx_over_errors += stats1->rx_over_errors; 2344 } 2345 2346 out_rpm_put: 2347 pm_runtime_put_noidle(dev); 2348 return nstats; 2349 } 2350 2351 /* Update promiscuous bit */ 2352 static void ravb_set_rx_mode(struct net_device *ndev) 2353 { 2354 struct ravb_private *priv = netdev_priv(ndev); 2355 unsigned long flags; 2356 2357 spin_lock_irqsave(&priv->lock, flags); 2358 ravb_modify(ndev, ECMR, ECMR_PRM, 2359 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0); 2360 spin_unlock_irqrestore(&priv->lock, flags); 2361 } 2362 2363 /* Device close function for Ethernet AVB */ 2364 static int ravb_close(struct net_device *ndev) 2365 { 2366 struct device_node *np = ndev->dev.parent->of_node; 2367 struct ravb_private *priv = netdev_priv(ndev); 2368 const struct ravb_hw_info *info = priv->info; 2369 struct ravb_tstamp_skb *ts_skb, *ts_skb2; 2370 struct device *dev = &priv->pdev->dev; 2371 int error; 2372 2373 netif_tx_stop_all_queues(ndev); 2374 2375 /* Disable interrupts by clearing the interrupt masks. */ 2376 ravb_write(ndev, 0, RIC0); 2377 ravb_write(ndev, 0, RIC2); 2378 ravb_write(ndev, 0, TIC); 2379 ravb_write(ndev, 0, ECSIPR); 2380 2381 /* PHY disconnect */ 2382 if (ndev->phydev) { 2383 phy_stop(ndev->phydev); 2384 phy_disconnect(ndev->phydev); 2385 if (of_phy_is_fixed_link(np)) 2386 of_phy_deregister_fixed_link(np); 2387 } 2388 2389 /* Stop PTP Clock driver */ 2390 if (info->gptp || info->ccc_gac) 2391 ravb_ptp_stop(ndev); 2392 2393 /* Set the config mode to stop the AVB-DMAC's processes */ 2394 if (ravb_stop_dma(ndev) < 0) 2395 netdev_err(ndev, 2396 "device will be stopped after h/w processes are done.\n"); 2397 2398 /* Clear the timestamp list */ 2399 if (info->gptp || info->ccc_gac) { 2400 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) { 2401 list_del(&ts_skb->list); 2402 kfree_skb(ts_skb->skb); 2403 kfree(ts_skb); 2404 } 2405 } 2406 2407 cancel_work_sync(&priv->work); 2408 2409 if (info->nc_queues) 2410 napi_disable(&priv->napi[RAVB_NC]); 2411 napi_disable(&priv->napi[RAVB_BE]); 2412 2413 /* Free all the skb's in the RX queue and the DMA buffers. */ 2414 ravb_ring_free(ndev, RAVB_BE); 2415 if (info->nc_queues) 2416 ravb_ring_free(ndev, RAVB_NC); 2417 2418 /* Update statistics. */ 2419 ravb_get_stats(ndev); 2420 2421 /* Set reset mode. */ 2422 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 2423 if (error) 2424 return error; 2425 2426 pm_runtime_put_autosuspend(dev); 2427 2428 return 0; 2429 } 2430 2431 static int ravb_hwtstamp_get(struct net_device *ndev, 2432 struct kernel_hwtstamp_config *config) 2433 { 2434 struct ravb_private *priv = netdev_priv(ndev); 2435 2436 config->flags = 0; 2437 config->tx_type = priv->tstamp_tx_ctrl; 2438 config->rx_filter = priv->tstamp_rx_ctrl; 2439 2440 return 0; 2441 } 2442 2443 /* Control hardware time stamping */ 2444 static int ravb_hwtstamp_set(struct net_device *ndev, 2445 struct kernel_hwtstamp_config *config, 2446 struct netlink_ext_ack *extack) 2447 { 2448 struct ravb_private *priv = netdev_priv(ndev); 2449 enum hwtstamp_rx_filters tstamp_rx_ctrl; 2450 enum hwtstamp_tx_types tstamp_tx_ctrl; 2451 2452 switch (config->tx_type) { 2453 case HWTSTAMP_TX_OFF: 2454 case HWTSTAMP_TX_ON: 2455 tstamp_tx_ctrl = config->tx_type; 2456 break; 2457 default: 2458 return -ERANGE; 2459 } 2460 2461 switch (config->rx_filter) { 2462 case HWTSTAMP_FILTER_NONE: 2463 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2464 tstamp_rx_ctrl = config->rx_filter; 2465 break; 2466 default: 2467 config->rx_filter = HWTSTAMP_FILTER_ALL; 2468 tstamp_rx_ctrl = HWTSTAMP_FILTER_ALL; 2469 } 2470 2471 priv->tstamp_tx_ctrl = tstamp_tx_ctrl; 2472 priv->tstamp_rx_ctrl = tstamp_rx_ctrl; 2473 2474 return 0; 2475 } 2476 2477 static int ravb_change_mtu(struct net_device *ndev, int new_mtu) 2478 { 2479 struct ravb_private *priv = netdev_priv(ndev); 2480 2481 WRITE_ONCE(ndev->mtu, new_mtu); 2482 2483 if (netif_running(ndev)) { 2484 synchronize_irq(priv->emac_irq); 2485 ravb_emac_init(ndev); 2486 } 2487 2488 netdev_update_features(ndev); 2489 2490 return 0; 2491 } 2492 2493 static void ravb_set_rx_csum(struct net_device *ndev, bool enable) 2494 { 2495 struct ravb_private *priv = netdev_priv(ndev); 2496 unsigned long flags; 2497 2498 spin_lock_irqsave(&priv->lock, flags); 2499 2500 /* Disable TX and RX */ 2501 ravb_rcv_snd_disable(ndev); 2502 2503 /* Modify RX Checksum setting */ 2504 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0); 2505 2506 /* Enable TX and RX */ 2507 ravb_rcv_snd_enable(ndev); 2508 2509 spin_unlock_irqrestore(&priv->lock, flags); 2510 } 2511 2512 static int ravb_endisable_csum_gbeth(struct net_device *ndev, enum ravb_reg reg, 2513 u32 val, u32 mask) 2514 { 2515 u32 csr0 = CSR0_TPE | CSR0_RPE; 2516 int ret; 2517 2518 ravb_write(ndev, csr0 & ~mask, CSR0); 2519 ret = ravb_wait(ndev, CSR0, mask, 0); 2520 if (!ret) 2521 ravb_write(ndev, val, reg); 2522 2523 ravb_write(ndev, csr0, CSR0); 2524 2525 return ret; 2526 } 2527 2528 static int ravb_set_features_gbeth(struct net_device *ndev, 2529 netdev_features_t features) 2530 { 2531 netdev_features_t changed = ndev->features ^ features; 2532 struct ravb_private *priv = netdev_priv(ndev); 2533 unsigned long flags; 2534 int ret = 0; 2535 u32 val; 2536 2537 spin_lock_irqsave(&priv->lock, flags); 2538 if (changed & NETIF_F_RXCSUM) { 2539 if (features & NETIF_F_RXCSUM) 2540 val = CSR2_CSUM_ENABLE; 2541 else 2542 val = 0; 2543 2544 ret = ravb_endisable_csum_gbeth(ndev, CSR2, val, CSR0_RPE); 2545 if (ret) 2546 goto done; 2547 } 2548 2549 if (changed & NETIF_F_HW_CSUM) { 2550 if (features & NETIF_F_HW_CSUM) 2551 val = CSR1_CSUM_ENABLE; 2552 else 2553 val = 0; 2554 2555 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE); 2556 if (ret) 2557 goto done; 2558 } 2559 2560 done: 2561 spin_unlock_irqrestore(&priv->lock, flags); 2562 2563 return ret; 2564 } 2565 2566 static int ravb_set_features_rcar(struct net_device *ndev, 2567 netdev_features_t features) 2568 { 2569 netdev_features_t changed = ndev->features ^ features; 2570 2571 if (changed & NETIF_F_RXCSUM) 2572 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM); 2573 2574 return 0; 2575 } 2576 2577 static int ravb_set_features(struct net_device *ndev, 2578 netdev_features_t features) 2579 { 2580 struct ravb_private *priv = netdev_priv(ndev); 2581 const struct ravb_hw_info *info = priv->info; 2582 struct device *dev = &priv->pdev->dev; 2583 int ret; 2584 2585 pm_runtime_get_noresume(dev); 2586 2587 if (pm_runtime_active(dev)) 2588 ret = info->set_feature(ndev, features); 2589 else 2590 ret = 0; 2591 2592 pm_runtime_put_noidle(dev); 2593 2594 if (ret) 2595 return ret; 2596 2597 ndev->features = features; 2598 2599 return 0; 2600 } 2601 2602 static const struct net_device_ops ravb_netdev_ops = { 2603 .ndo_open = ravb_open, 2604 .ndo_stop = ravb_close, 2605 .ndo_start_xmit = ravb_start_xmit, 2606 .ndo_select_queue = ravb_select_queue, 2607 .ndo_get_stats = ravb_get_stats, 2608 .ndo_set_rx_mode = ravb_set_rx_mode, 2609 .ndo_tx_timeout = ravb_tx_timeout, 2610 .ndo_eth_ioctl = phy_do_ioctl_running, 2611 .ndo_change_mtu = ravb_change_mtu, 2612 .ndo_validate_addr = eth_validate_addr, 2613 .ndo_set_mac_address = eth_mac_addr, 2614 .ndo_set_features = ravb_set_features, 2615 .ndo_hwtstamp_get = ravb_hwtstamp_get, 2616 .ndo_hwtstamp_set = ravb_hwtstamp_set, 2617 }; 2618 2619 /* MDIO bus init function */ 2620 static int ravb_mdio_init(struct ravb_private *priv) 2621 { 2622 struct platform_device *pdev = priv->pdev; 2623 struct device *dev = &pdev->dev; 2624 struct device_node *mdio_node; 2625 struct phy_device *phydev; 2626 struct device_node *pn; 2627 int error; 2628 2629 /* Bitbang init */ 2630 priv->mdiobb.ops = &bb_ops; 2631 2632 /* MII controller setting */ 2633 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb); 2634 if (!priv->mii_bus) 2635 return -ENOMEM; 2636 2637 /* Hook up MII support for ethtool */ 2638 priv->mii_bus->name = "ravb_mii"; 2639 priv->mii_bus->parent = dev; 2640 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2641 pdev->name, pdev->id); 2642 2643 /* Register MDIO bus */ 2644 mdio_node = of_get_child_by_name(dev->of_node, "mdio"); 2645 if (!mdio_node) { 2646 /* backwards compatibility for DT lacking mdio subnode */ 2647 mdio_node = of_node_get(dev->of_node); 2648 } 2649 error = of_mdiobus_register(priv->mii_bus, mdio_node); 2650 of_node_put(mdio_node); 2651 if (error) 2652 goto out_free_bus; 2653 2654 pn = of_parse_phandle(dev->of_node, "phy-handle", 0); 2655 phydev = of_phy_find_device(pn); 2656 if (phydev) { 2657 phydev->mac_managed_pm = true; 2658 put_device(&phydev->mdio.dev); 2659 } 2660 of_node_put(pn); 2661 2662 return 0; 2663 2664 out_free_bus: 2665 free_mdio_bitbang(priv->mii_bus); 2666 return error; 2667 } 2668 2669 /* MDIO bus release function */ 2670 static int ravb_mdio_release(struct ravb_private *priv) 2671 { 2672 /* Unregister mdio bus */ 2673 mdiobus_unregister(priv->mii_bus); 2674 2675 /* Free bitbang info */ 2676 free_mdio_bitbang(priv->mii_bus); 2677 2678 return 0; 2679 } 2680 2681 static const struct ravb_hw_info ravb_gen2_hw_info = { 2682 .receive = ravb_rx_rcar, 2683 .set_rate = ravb_set_rate_rcar, 2684 .set_feature = ravb_set_features_rcar, 2685 .dmac_init = ravb_dmac_init_rcar, 2686 .emac_init = ravb_emac_init_rcar, 2687 .gstrings_stats = ravb_gstrings_stats, 2688 .gstrings_size = sizeof(ravb_gstrings_stats), 2689 .net_hw_features = NETIF_F_RXCSUM, 2690 .net_features = NETIF_F_RXCSUM, 2691 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2692 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2693 .tx_max_frame_size = SZ_2K, 2694 .rx_max_frame_size = SZ_2K, 2695 .rx_buffer_size = SZ_2K + 2696 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2697 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2698 .dbat_entry_num = 22, 2699 .aligned_tx = 1, 2700 .gptp = 1, 2701 .nc_queues = 1, 2702 .magic_pkt = 1, 2703 }; 2704 2705 static const struct ravb_hw_info ravb_gen3_hw_info = { 2706 .receive = ravb_rx_rcar, 2707 .set_rate = ravb_set_rate_rcar, 2708 .set_feature = ravb_set_features_rcar, 2709 .dmac_init = ravb_dmac_init_rcar, 2710 .emac_init = ravb_emac_init_rcar, 2711 .gstrings_stats = ravb_gstrings_stats, 2712 .gstrings_size = sizeof(ravb_gstrings_stats), 2713 .net_hw_features = NETIF_F_RXCSUM, 2714 .net_features = NETIF_F_RXCSUM, 2715 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2716 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2717 .tx_max_frame_size = SZ_2K, 2718 .rx_max_frame_size = SZ_2K, 2719 .rx_buffer_size = SZ_2K + 2720 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2721 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2722 .dbat_entry_num = 22, 2723 .internal_delay = 1, 2724 .tx_counters = 1, 2725 .multi_irqs = 1, 2726 .irq_en_dis = 1, 2727 .ccc_gac = 1, 2728 .nc_queues = 1, 2729 .magic_pkt = 1, 2730 }; 2731 2732 static const struct ravb_hw_info ravb_gen4_hw_info = { 2733 .receive = ravb_rx_rcar, 2734 .set_rate = ravb_set_rate_rcar, 2735 .set_feature = ravb_set_features_rcar, 2736 .dmac_init = ravb_dmac_init_rcar, 2737 .emac_init = ravb_emac_init_rcar_gen4, 2738 .gstrings_stats = ravb_gstrings_stats, 2739 .gstrings_size = sizeof(ravb_gstrings_stats), 2740 .net_hw_features = NETIF_F_RXCSUM, 2741 .net_features = NETIF_F_RXCSUM, 2742 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2743 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2744 .tx_max_frame_size = SZ_2K, 2745 .rx_max_frame_size = SZ_2K, 2746 .rx_buffer_size = SZ_2K + 2747 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2748 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2749 .dbat_entry_num = 22, 2750 .internal_delay = 1, 2751 .tx_counters = 1, 2752 .multi_irqs = 1, 2753 .irq_en_dis = 1, 2754 .ccc_gac = 1, 2755 .nc_queues = 1, 2756 .magic_pkt = 1, 2757 }; 2758 2759 static const struct ravb_hw_info ravb_rzv2m_hw_info = { 2760 .receive = ravb_rx_rcar, 2761 .set_rate = ravb_set_rate_rcar, 2762 .set_feature = ravb_set_features_rcar, 2763 .dmac_init = ravb_dmac_init_rcar, 2764 .emac_init = ravb_emac_init_rcar, 2765 .gstrings_stats = ravb_gstrings_stats, 2766 .gstrings_size = sizeof(ravb_gstrings_stats), 2767 .net_hw_features = NETIF_F_RXCSUM, 2768 .net_features = NETIF_F_RXCSUM, 2769 .stats_len = ARRAY_SIZE(ravb_gstrings_stats), 2770 .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 2771 .tx_max_frame_size = SZ_2K, 2772 .rx_max_frame_size = SZ_2K, 2773 .rx_buffer_size = SZ_2K + 2774 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), 2775 .rx_desc_size = sizeof(struct ravb_ex_rx_desc), 2776 .dbat_entry_num = 22, 2777 .multi_irqs = 1, 2778 .err_mgmt_irqs = 1, 2779 .gptp = 1, 2780 .gptp_ref_clk = 1, 2781 .nc_queues = 1, 2782 .magic_pkt = 1, 2783 }; 2784 2785 static const struct ravb_hw_info gbeth_hw_info = { 2786 .receive = ravb_rx_gbeth, 2787 .set_rate = ravb_set_rate_gbeth, 2788 .set_feature = ravb_set_features_gbeth, 2789 .dmac_init = ravb_dmac_init_gbeth, 2790 .emac_init = ravb_emac_init_gbeth, 2791 .gstrings_stats = ravb_gstrings_stats_gbeth, 2792 .gstrings_size = sizeof(ravb_gstrings_stats_gbeth), 2793 .net_hw_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2794 .net_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2795 .vlan_features = NETIF_F_RXCSUM | NETIF_F_HW_CSUM, 2796 .stats_len = ARRAY_SIZE(ravb_gstrings_stats_gbeth), 2797 .tccr_mask = TCCR_TSRQ0, 2798 .tx_max_frame_size = 1522, 2799 .rx_max_frame_size = SZ_8K, 2800 .rx_buffer_size = SZ_2K, 2801 .rx_desc_size = sizeof(struct ravb_rx_desc), 2802 .dbat_entry_num = 2, 2803 .aligned_tx = 1, 2804 .coalesce_irqs = 1, 2805 .tx_counters = 1, 2806 .carrier_counters = 1, 2807 .half_duplex = 1, 2808 }; 2809 2810 static const struct of_device_id ravb_match_table[] = { 2811 { .compatible = "renesas,etheravb-r8a7790", .data = &ravb_gen2_hw_info }, 2812 { .compatible = "renesas,etheravb-r8a7794", .data = &ravb_gen2_hw_info }, 2813 { .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info }, 2814 { .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info }, 2815 { .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info }, 2816 { .compatible = "renesas,etheravb-rcar-gen4", .data = &ravb_gen4_hw_info }, 2817 { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info }, 2818 { .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info }, 2819 { } 2820 }; 2821 MODULE_DEVICE_TABLE(of, ravb_match_table); 2822 2823 static int ravb_setup_irq(struct ravb_private *priv, const char *irq_name, 2824 const char *ch, int *irq, irq_handler_t handler) 2825 { 2826 struct platform_device *pdev = priv->pdev; 2827 struct net_device *ndev = priv->ndev; 2828 struct device *dev = &pdev->dev; 2829 const char *devname = dev_name(dev); 2830 unsigned long flags; 2831 int error, irq_num; 2832 2833 if (irq_name) { 2834 devname = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", devname, ch); 2835 if (!devname) 2836 return -ENOMEM; 2837 2838 irq_num = platform_get_irq_byname(pdev, irq_name); 2839 flags = 0; 2840 } else { 2841 irq_num = platform_get_irq(pdev, 0); 2842 flags = IRQF_SHARED; 2843 } 2844 if (irq_num < 0) 2845 return irq_num; 2846 2847 if (irq) 2848 *irq = irq_num; 2849 2850 error = devm_request_irq(dev, irq_num, handler, flags, devname, ndev); 2851 if (error) 2852 netdev_err(ndev, "cannot request IRQ %s\n", devname); 2853 2854 return error; 2855 } 2856 2857 static int ravb_setup_irqs(struct ravb_private *priv) 2858 { 2859 const struct ravb_hw_info *info = priv->info; 2860 struct net_device *ndev = priv->ndev; 2861 const char *irq_name, *emac_irq_name; 2862 int error; 2863 2864 if (!info->multi_irqs) 2865 return ravb_setup_irq(priv, NULL, NULL, &ndev->irq, ravb_interrupt); 2866 2867 if (info->err_mgmt_irqs) { 2868 irq_name = "dia"; 2869 emac_irq_name = "line3"; 2870 } else { 2871 irq_name = "ch22"; 2872 emac_irq_name = "ch24"; 2873 } 2874 2875 error = ravb_setup_irq(priv, irq_name, "ch22:multi", &ndev->irq, ravb_multi_interrupt); 2876 if (error) 2877 return error; 2878 2879 error = ravb_setup_irq(priv, emac_irq_name, "ch24:emac", &priv->emac_irq, 2880 ravb_emac_interrupt); 2881 if (error) 2882 return error; 2883 2884 if (info->err_mgmt_irqs) { 2885 error = ravb_setup_irq(priv, "err_a", "err_a", NULL, ravb_multi_interrupt); 2886 if (error) 2887 return error; 2888 2889 error = ravb_setup_irq(priv, "mgmt_a", "mgmt_a", NULL, ravb_multi_interrupt); 2890 if (error) 2891 return error; 2892 } 2893 2894 error = ravb_setup_irq(priv, "ch0", "ch0:rx_be", NULL, ravb_be_interrupt); 2895 if (error) 2896 return error; 2897 2898 error = ravb_setup_irq(priv, "ch1", "ch1:rx_nc", NULL, ravb_nc_interrupt); 2899 if (error) 2900 return error; 2901 2902 error = ravb_setup_irq(priv, "ch18", "ch18:tx_be", NULL, ravb_be_interrupt); 2903 if (error) 2904 return error; 2905 2906 return ravb_setup_irq(priv, "ch19", "ch19:tx_nc", NULL, ravb_nc_interrupt); 2907 } 2908 2909 static int ravb_probe(struct platform_device *pdev) 2910 { 2911 struct device_node *np = pdev->dev.of_node; 2912 const struct ravb_hw_info *info; 2913 struct reset_control *rstc; 2914 struct ravb_private *priv; 2915 struct net_device *ndev; 2916 struct resource *res; 2917 int error, q; 2918 2919 if (!np) { 2920 dev_err(&pdev->dev, 2921 "this driver is required to be instantiated from device tree\n"); 2922 return -EINVAL; 2923 } 2924 2925 rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 2926 if (IS_ERR(rstc)) 2927 return dev_err_probe(&pdev->dev, PTR_ERR(rstc), 2928 "failed to get cpg reset\n"); 2929 2930 info = of_device_get_match_data(&pdev->dev); 2931 2932 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private), 2933 info->nc_queues ? NUM_TX_QUEUE : 1, 2934 info->nc_queues ? NUM_RX_QUEUE : 1); 2935 if (!ndev) 2936 return -ENOMEM; 2937 2938 ndev->features = info->net_features; 2939 ndev->hw_features = info->net_hw_features; 2940 ndev->vlan_features = info->vlan_features; 2941 2942 error = reset_control_deassert(rstc); 2943 if (error) 2944 goto out_free_netdev; 2945 2946 SET_NETDEV_DEV(ndev, &pdev->dev); 2947 2948 priv = netdev_priv(ndev); 2949 priv->info = info; 2950 priv->rstc = rstc; 2951 priv->ndev = ndev; 2952 priv->pdev = pdev; 2953 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE; 2954 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE; 2955 if (info->nc_queues) { 2956 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE; 2957 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE; 2958 } 2959 2960 error = ravb_setup_irqs(priv); 2961 if (error) 2962 goto out_reset_assert; 2963 2964 priv->clk = devm_clk_get(&pdev->dev, NULL); 2965 if (IS_ERR(priv->clk)) { 2966 error = PTR_ERR(priv->clk); 2967 goto out_reset_assert; 2968 } 2969 2970 if (info->gptp_ref_clk) { 2971 priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp"); 2972 if (IS_ERR(priv->gptp_clk)) { 2973 error = PTR_ERR(priv->gptp_clk); 2974 goto out_reset_assert; 2975 } 2976 } 2977 2978 priv->refclk = devm_clk_get_optional(&pdev->dev, "refclk"); 2979 if (IS_ERR(priv->refclk)) { 2980 error = PTR_ERR(priv->refclk); 2981 goto out_reset_assert; 2982 } 2983 clk_prepare(priv->refclk); 2984 2985 platform_set_drvdata(pdev, ndev); 2986 pm_runtime_set_autosuspend_delay(&pdev->dev, 100); 2987 pm_runtime_use_autosuspend(&pdev->dev); 2988 pm_runtime_enable(&pdev->dev); 2989 error = pm_runtime_resume_and_get(&pdev->dev); 2990 if (error < 0) 2991 goto out_rpm_disable; 2992 2993 priv->addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2994 if (IS_ERR(priv->addr)) { 2995 error = PTR_ERR(priv->addr); 2996 goto out_rpm_put; 2997 } 2998 2999 /* The Ether-specific entries in the device structure. */ 3000 ndev->base_addr = res->start; 3001 3002 spin_lock_init(&priv->lock); 3003 INIT_WORK(&priv->work, ravb_tx_timeout_work); 3004 3005 error = of_get_phy_mode(np, &priv->phy_interface); 3006 if (error && error != -ENODEV) 3007 goto out_rpm_put; 3008 3009 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link"); 3010 priv->avb_link_active_low = 3011 of_property_read_bool(np, "renesas,ether-link-active-low"); 3012 3013 ndev->max_mtu = info->tx_max_frame_size - 3014 (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN); 3015 ndev->min_mtu = ETH_MIN_MTU; 3016 3017 /* FIXME: R-Car Gen2 has 4byte alignment restriction for tx buffer 3018 * Use two descriptor to handle such situation. First descriptor to 3019 * handle aligned data buffer and second descriptor to handle the 3020 * overflow data because of alignment. 3021 */ 3022 priv->num_tx_desc = info->aligned_tx ? 2 : 1; 3023 3024 /* Set function */ 3025 ndev->netdev_ops = &ravb_netdev_ops; 3026 ndev->ethtool_ops = &ravb_ethtool_ops; 3027 3028 error = ravb_compute_gti(ndev); 3029 if (error) 3030 goto out_rpm_put; 3031 3032 ravb_parse_delay_mode(np, ndev); 3033 3034 /* Allocate descriptor base address table */ 3035 priv->desc_bat_size = sizeof(struct ravb_desc) * info->dbat_entry_num; 3036 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size, 3037 &priv->desc_bat_dma, GFP_KERNEL); 3038 if (!priv->desc_bat) { 3039 dev_err(&pdev->dev, 3040 "Cannot allocate desc base address table (size %d bytes)\n", 3041 priv->desc_bat_size); 3042 error = -ENOMEM; 3043 goto out_rpm_put; 3044 } 3045 for (q = RAVB_BE; q < info->dbat_entry_num; q++) 3046 priv->desc_bat[q].die_dt = DT_EOS; 3047 3048 /* Initialise HW timestamp list */ 3049 INIT_LIST_HEAD(&priv->ts_skb_list); 3050 3051 /* Debug message level */ 3052 priv->msg_enable = RAVB_DEF_MSG_ENABLE; 3053 3054 /* Set config mode as this is needed for PHY initialization. */ 3055 error = ravb_set_opmode(ndev, CCC_OPC_CONFIG); 3056 if (error) 3057 goto out_rpm_put; 3058 3059 /* Read and set MAC address */ 3060 ravb_read_mac_address(np, ndev); 3061 if (!is_valid_ether_addr(ndev->dev_addr)) { 3062 dev_warn(&pdev->dev, 3063 "no valid MAC address supplied, using a random one\n"); 3064 eth_hw_addr_random(ndev); 3065 } 3066 3067 /* MDIO bus init */ 3068 error = ravb_mdio_init(priv); 3069 if (error) { 3070 dev_err(&pdev->dev, "failed to initialize MDIO\n"); 3071 goto out_reset_mode; 3072 } 3073 3074 /* Undo previous switch to config opmode. */ 3075 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3076 if (error) 3077 goto out_mdio_release; 3078 3079 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll); 3080 if (info->nc_queues) 3081 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll); 3082 3083 if (info->coalesce_irqs) { 3084 netdev_sw_irq_coalesce_default_on(ndev); 3085 if (num_present_cpus() == 1) 3086 netif_threaded_enable(ndev); 3087 } 3088 3089 /* Network device register */ 3090 error = register_netdev(ndev); 3091 if (error) 3092 goto out_napi_del; 3093 3094 device_set_wakeup_capable(&pdev->dev, 1); 3095 3096 /* Print device information */ 3097 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n", 3098 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 3099 3100 pm_runtime_put_autosuspend(&pdev->dev); 3101 3102 return 0; 3103 3104 out_napi_del: 3105 if (info->nc_queues) 3106 netif_napi_del(&priv->napi[RAVB_NC]); 3107 3108 netif_napi_del(&priv->napi[RAVB_BE]); 3109 out_mdio_release: 3110 ravb_mdio_release(priv); 3111 out_reset_mode: 3112 ravb_set_opmode(ndev, CCC_OPC_RESET); 3113 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3114 priv->desc_bat_dma); 3115 out_rpm_put: 3116 pm_runtime_put(&pdev->dev); 3117 out_rpm_disable: 3118 pm_runtime_disable(&pdev->dev); 3119 pm_runtime_dont_use_autosuspend(&pdev->dev); 3120 clk_unprepare(priv->refclk); 3121 out_reset_assert: 3122 reset_control_assert(rstc); 3123 out_free_netdev: 3124 free_netdev(ndev); 3125 return error; 3126 } 3127 3128 static void ravb_remove(struct platform_device *pdev) 3129 { 3130 struct net_device *ndev = platform_get_drvdata(pdev); 3131 struct ravb_private *priv = netdev_priv(ndev); 3132 const struct ravb_hw_info *info = priv->info; 3133 struct device *dev = &priv->pdev->dev; 3134 int error; 3135 3136 error = pm_runtime_resume_and_get(dev); 3137 if (error < 0) 3138 return; 3139 3140 unregister_netdev(ndev); 3141 if (info->nc_queues) 3142 netif_napi_del(&priv->napi[RAVB_NC]); 3143 netif_napi_del(&priv->napi[RAVB_BE]); 3144 3145 ravb_mdio_release(priv); 3146 3147 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat, 3148 priv->desc_bat_dma); 3149 3150 pm_runtime_put_sync_suspend(&pdev->dev); 3151 pm_runtime_disable(&pdev->dev); 3152 pm_runtime_dont_use_autosuspend(dev); 3153 clk_unprepare(priv->refclk); 3154 reset_control_assert(priv->rstc); 3155 free_netdev(ndev); 3156 platform_set_drvdata(pdev, NULL); 3157 } 3158 3159 static int ravb_wol_setup(struct net_device *ndev) 3160 { 3161 struct ravb_private *priv = netdev_priv(ndev); 3162 const struct ravb_hw_info *info = priv->info; 3163 3164 /* Disable interrupts by clearing the interrupt masks. */ 3165 ravb_write(ndev, 0, RIC0); 3166 ravb_write(ndev, 0, RIC2); 3167 ravb_write(ndev, 0, TIC); 3168 3169 /* Only allow ECI interrupts */ 3170 synchronize_irq(priv->emac_irq); 3171 if (info->nc_queues) 3172 napi_disable(&priv->napi[RAVB_NC]); 3173 napi_disable(&priv->napi[RAVB_BE]); 3174 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR); 3175 3176 /* Enable MagicPacket */ 3177 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE); 3178 3179 if (priv->info->ccc_gac) 3180 ravb_ptp_stop(ndev); 3181 3182 return enable_irq_wake(priv->emac_irq); 3183 } 3184 3185 static int ravb_wol_restore(struct net_device *ndev) 3186 { 3187 struct ravb_private *priv = netdev_priv(ndev); 3188 const struct ravb_hw_info *info = priv->info; 3189 int error; 3190 3191 /* Set reset mode to rearm the WoL logic. */ 3192 error = ravb_set_opmode(ndev, CCC_OPC_RESET); 3193 if (error) 3194 return error; 3195 3196 /* Set AVB config mode. */ 3197 error = ravb_set_config_mode(ndev); 3198 if (error) 3199 return error; 3200 3201 if (priv->info->ccc_gac) 3202 ravb_ptp_init(ndev, priv->pdev); 3203 3204 if (info->nc_queues) 3205 napi_enable(&priv->napi[RAVB_NC]); 3206 napi_enable(&priv->napi[RAVB_BE]); 3207 3208 /* Disable MagicPacket */ 3209 ravb_modify(ndev, ECMR, ECMR_MPDE, 0); 3210 3211 ravb_close(ndev); 3212 3213 return disable_irq_wake(priv->emac_irq); 3214 } 3215 3216 static int ravb_suspend(struct device *dev) 3217 { 3218 struct net_device *ndev = dev_get_drvdata(dev); 3219 struct ravb_private *priv = netdev_priv(ndev); 3220 int ret; 3221 3222 if (!netif_running(ndev)) 3223 goto reset_assert; 3224 3225 netif_device_detach(ndev); 3226 3227 rtnl_lock(); 3228 if (priv->wol_enabled) { 3229 ret = ravb_wol_setup(ndev); 3230 rtnl_unlock(); 3231 return ret; 3232 } 3233 3234 ret = ravb_close(ndev); 3235 rtnl_unlock(); 3236 if (ret) 3237 return ret; 3238 3239 ret = pm_runtime_force_suspend(&priv->pdev->dev); 3240 if (ret) 3241 return ret; 3242 3243 reset_assert: 3244 return reset_control_assert(priv->rstc); 3245 } 3246 3247 static int ravb_resume(struct device *dev) 3248 { 3249 struct net_device *ndev = dev_get_drvdata(dev); 3250 struct ravb_private *priv = netdev_priv(ndev); 3251 int ret; 3252 3253 ret = reset_control_deassert(priv->rstc); 3254 if (ret) 3255 return ret; 3256 3257 if (!netif_running(ndev)) 3258 return 0; 3259 3260 rtnl_lock(); 3261 /* If WoL is enabled restore the interface. */ 3262 if (priv->wol_enabled) 3263 ret = ravb_wol_restore(ndev); 3264 else 3265 ret = pm_runtime_force_resume(dev); 3266 if (ret) { 3267 rtnl_unlock(); 3268 return ret; 3269 } 3270 3271 /* Reopening the interface will restore the device to the working state. */ 3272 ret = ravb_open(ndev); 3273 rtnl_unlock(); 3274 if (ret < 0) 3275 goto out_rpm_put; 3276 3277 ravb_set_rx_mode(ndev); 3278 netif_device_attach(ndev); 3279 3280 return 0; 3281 3282 out_rpm_put: 3283 if (!priv->wol_enabled) 3284 pm_runtime_put_autosuspend(dev); 3285 3286 return ret; 3287 } 3288 3289 static int ravb_runtime_suspend(struct device *dev) 3290 { 3291 struct net_device *ndev = dev_get_drvdata(dev); 3292 struct ravb_private *priv = netdev_priv(ndev); 3293 3294 clk_disable(priv->refclk); 3295 3296 return 0; 3297 } 3298 3299 static int ravb_runtime_resume(struct device *dev) 3300 { 3301 struct net_device *ndev = dev_get_drvdata(dev); 3302 struct ravb_private *priv = netdev_priv(ndev); 3303 3304 return clk_enable(priv->refclk); 3305 } 3306 3307 static const struct dev_pm_ops ravb_dev_pm_ops = { 3308 SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume) 3309 RUNTIME_PM_OPS(ravb_runtime_suspend, ravb_runtime_resume, NULL) 3310 }; 3311 3312 static struct platform_driver ravb_driver = { 3313 .probe = ravb_probe, 3314 .remove = ravb_remove, 3315 .driver = { 3316 .name = "ravb", 3317 .pm = pm_ptr(&ravb_dev_pm_ops), 3318 .of_match_table = ravb_match_table, 3319 }, 3320 }; 3321 3322 module_platform_driver(ravb_driver); 3323 3324 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai"); 3325 MODULE_DESCRIPTION("Renesas Ethernet AVB driver"); 3326 MODULE_LICENSE("GPL v2"); 3327