1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2025 Realtek Corporation
3 */
4
5 #include <linux/usb.h>
6 #include "main.h"
7 #include "coex.h"
8 #include "tx.h"
9 #include "phy.h"
10 #include "rtw8814a.h"
11 #include "rtw8814a_table.h"
12 #include "rtw88xxa.h"
13 #include "reg.h"
14 #include "debug.h"
15 #include "efuse.h"
16 #include "regd.h"
17 #include "usb.h"
18
rtw8814a_efuse_grant(struct rtw_dev * rtwdev,bool on)19 static void rtw8814a_efuse_grant(struct rtw_dev *rtwdev, bool on)
20 {
21 if (on) {
22 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
23
24 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
25 rtw_write16_set(rtwdev, REG_SYS_CLKR,
26 BIT_LOADER_CLK_EN | BIT_ANA8M);
27 } else {
28 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
29 }
30 }
31
rtw8814a_read_rfe_type(struct rtw_dev * rtwdev)32 static void rtw8814a_read_rfe_type(struct rtw_dev *rtwdev)
33 {
34 struct rtw_efuse *efuse = &rtwdev->efuse;
35
36 if (!(efuse->rfe_option & BIT(7)))
37 return;
38
39 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
40 efuse->rfe_option = 0;
41 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
42 efuse->rfe_option = 1;
43 }
44
rtw8814a_read_amplifier_type(struct rtw_dev * rtwdev)45 static void rtw8814a_read_amplifier_type(struct rtw_dev *rtwdev)
46 {
47 struct rtw_efuse *efuse = &rtwdev->efuse;
48
49 switch (efuse->rfe_option) {
50 case 1:
51 /* Internal 2G */
52 efuse->pa_type_2g = 0;
53 efuse->lna_type_2g = 0;
54 /* External 5G */
55 efuse->pa_type_5g = BIT(0);
56 efuse->lna_type_5g = BIT(3);
57 break;
58 case 2 ... 5:
59 /* External everything */
60 efuse->pa_type_2g = BIT(4);
61 efuse->lna_type_2g = BIT(3);
62 efuse->pa_type_5g = BIT(0);
63 efuse->lna_type_5g = BIT(3);
64 break;
65 case 6:
66 efuse->lna_type_5g = BIT(3);
67 break;
68 default:
69 break;
70 }
71 }
72
rtw8814a_read_rf_type(struct rtw_dev * rtwdev,struct rtw8814a_efuse * map)73 static void rtw8814a_read_rf_type(struct rtw_dev *rtwdev,
74 struct rtw8814a_efuse *map)
75 {
76 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
77 struct rtw_hal *hal = &rtwdev->hal;
78
79 switch (map->trx_antenna_option) {
80 case 0xff: /* 4T4R */
81 case 0xee: /* 3T3R */
82 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
83 rtwusb->udev->speed != USB_SPEED_SUPER)
84 hal->rf_type = RF_2T2R;
85 else
86 hal->rf_type = RF_3T3R;
87
88 break;
89 case 0x66: /* 2T2R */
90 case 0x6f: /* 2T4R */
91 default:
92 hal->rf_type = RF_2T2R;
93 break;
94 }
95
96 hal->rf_path_num = 4;
97 hal->rf_phy_num = 4;
98
99 if (hal->rf_type == RF_3T3R) {
100 hal->antenna_rx = BB_PATH_ABC;
101 hal->antenna_tx = BB_PATH_ABC;
102 } else {
103 hal->antenna_rx = BB_PATH_AB;
104 hal->antenna_tx = BB_PATH_AB;
105 }
106 }
107
rtw8814a_init_hwcap(struct rtw_dev * rtwdev)108 static void rtw8814a_init_hwcap(struct rtw_dev *rtwdev)
109 {
110 struct rtw_efuse *efuse = &rtwdev->efuse;
111 struct rtw_hal *hal = &rtwdev->hal;
112
113 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
114 BIT(RTW_CHANNEL_WIDTH_40) |
115 BIT(RTW_CHANNEL_WIDTH_80);
116 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
117
118 if (hal->rf_type == RF_3T3R)
119 efuse->hw_cap.nss = 3;
120 else
121 efuse->hw_cap.nss = 2;
122
123 rtw_dbg(rtwdev, RTW_DBG_EFUSE,
124 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
125 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
126 efuse->hw_cap.ant_num, efuse->hw_cap.nss);
127 }
128
rtw8814a_read_efuse(struct rtw_dev * rtwdev,u8 * log_map)129 static int rtw8814a_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
130 {
131 struct rtw_efuse *efuse = &rtwdev->efuse;
132 struct rtw8814a_efuse *map;
133 int i;
134
135 if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
136 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
137 log_map, rtwdev->chip->log_efuse_size, true);
138
139 map = (struct rtw8814a_efuse *)log_map;
140
141 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(4));
142 efuse->rfe_option = map->rfe_option;
143 efuse->rf_board_option = map->rf_board_option;
144 efuse->crystal_cap = map->xtal_k;
145 efuse->channel_plan = map->channel_plan;
146 efuse->country_code[0] = map->country_code[0];
147 efuse->country_code[1] = map->country_code[1];
148 efuse->bt_setting = map->rf_bt_setting;
149 efuse->regd = map->rf_board_option & 0x7;
150 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
151 efuse->thermal_meter_k = map->thermal_meter;
152 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
153 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
154
155 rtw8814a_read_rfe_type(rtwdev);
156 rtw8814a_read_amplifier_type(rtwdev);
157
158 /* Override rtw_chip_parameter_setup() */
159 rtw8814a_read_rf_type(rtwdev, map);
160
161 rtw8814a_init_hwcap(rtwdev);
162
163 for (i = 0; i < 4; i++)
164 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
165
166 switch (rtw_hci_type(rtwdev)) {
167 case RTW_HCI_TYPE_USB:
168 ether_addr_copy(efuse->addr, map->u.mac_addr);
169 break;
170 case RTW_HCI_TYPE_PCIE:
171 ether_addr_copy(efuse->addr, map->e.mac_addr);
172 break;
173 case RTW_HCI_TYPE_SDIO:
174 default:
175 /* unsupported now */
176 return -EOPNOTSUPP;
177 }
178
179 return 0;
180 }
181
rtw8814a_init_rfe_reg(struct rtw_dev * rtwdev)182 static void rtw8814a_init_rfe_reg(struct rtw_dev *rtwdev)
183 {
184 u8 rfe_option = rtwdev->efuse.rfe_option;
185
186 if (rfe_option == 2 || rfe_option == 1) {
187 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
188 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xf0);
189 } else if (rfe_option == 0) {
190 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
191 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xc0);
192 }
193 }
194
195 #define RTW_TXSCALE_SIZE 37
196 static const u32 rtw8814a_txscale_tbl[RTW_TXSCALE_SIZE] = {
197 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
198 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
199 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
200 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
201 };
202
rtw8814a_get_bb_swing(struct rtw_dev * rtwdev,u8 band,u8 rf_path)203 static u32 rtw8814a_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 rf_path)
204 {
205 static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
206 struct rtw_efuse *efuse = &rtwdev->efuse;
207 u8 tx_bb_swing;
208
209 if (band == RTW_BAND_2G)
210 tx_bb_swing = efuse->tx_bb_swing_setting_2g;
211 else
212 tx_bb_swing = efuse->tx_bb_swing_setting_5g;
213
214 tx_bb_swing >>= 2 * rf_path;
215 tx_bb_swing &= 0x3;
216
217 return swing2setting[tx_bb_swing];
218 }
219
rtw8814a_get_swing_index(struct rtw_dev * rtwdev)220 static u8 rtw8814a_get_swing_index(struct rtw_dev *rtwdev)
221 {
222 u32 swing, table_value;
223 u8 i;
224
225 swing = rtw8814a_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
226 RF_PATH_A);
227
228 for (i = 0; i < ARRAY_SIZE(rtw8814a_txscale_tbl); i++) {
229 table_value = rtw8814a_txscale_tbl[i];
230 if (swing == table_value)
231 return i;
232 }
233
234 return 24;
235 }
236
rtw8814a_pwrtrack_init(struct rtw_dev * rtwdev)237 static void rtw8814a_pwrtrack_init(struct rtw_dev *rtwdev)
238 {
239 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
240 u8 path;
241
242 dm_info->default_ofdm_index = rtw8814a_get_swing_index(rtwdev);
243
244 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
245 ewma_thermal_init(&dm_info->avg_thermal[path]);
246 dm_info->delta_power_index[path] = 0;
247 dm_info->delta_power_index_last[path] = 0;
248 }
249 dm_info->pwr_trk_triggered = false;
250 dm_info->pwr_trk_init_trigger = true;
251 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
252 }
253
rtw8814a_config_trx_path(struct rtw_dev * rtwdev)254 static void rtw8814a_config_trx_path(struct rtw_dev *rtwdev)
255 {
256 /* RX CCK disable 2R CCA */
257 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT,
258 BIT_CCK0_2RX | BIT_CCK0_MRC);
259 /* pathB tx on, path A/C/D tx off */
260 rtw_write32_mask(rtwdev, REG_CCK_RX, 0xf0000000, 0x4);
261 /* pathB rx */
262 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
263 }
264
rtw8814a_config_cck_rx_antenna_init(struct rtw_dev * rtwdev)265 static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev)
266 {
267 /* CCK 2R CCA parameters */
268
269 /* Disable Ant diversity */
270 rtw_write32_mask(rtwdev, REG_RXSB, BIT_RXSB_ANA_DIV, 0x0);
271 /* Concurrent CCA at LSB & USB */
272 rtw_write32_mask(rtwdev, REG_CCA, BIT_CCA_CO, 0);
273 /* RX path diversity enable */
274 rtw_write32_mask(rtwdev, REG_ANTSEL, BIT_ANT_BYCO, 0);
275 /* r_en_mrc_antsel */
276 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_DIS_CO_PATHSEL, 0);
277 /* MBC weighting */
278 rtw_write32_mask(rtwdev, REG_CCA_MF, BIT_MBC_WIN, 1);
279 /* 2R CCA only */
280 rtw_write32_mask(rtwdev, REG_CCKTX, BIT_CMB_CCA_2R, 1);
281 }
282
rtw8814a_phy_set_param(struct rtw_dev * rtwdev)283 static void rtw8814a_phy_set_param(struct rtw_dev *rtwdev)
284 {
285 u32 crystal_cap, val32;
286 u8 val8, rf_path;
287
288 /* power on BB/RF domain */
289 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
290 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_USBA);
291 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
292 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_PCIEA);
293
294 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2,
295 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
296
297 /* Power on RF paths A..D */
298 val8 = BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB;
299 rtw_write8(rtwdev, REG_RF_CTRL, val8);
300 rtw_write8(rtwdev, REG_RF_CTRL1, val8);
301 rtw_write8(rtwdev, REG_RF_CTRL2, val8);
302 rtw_write8(rtwdev, REG_RF_CTRL3, val8);
303
304 rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
305 rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
306
307 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
308 crystal_cap |= crystal_cap << 6;
309 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x07ff8000, crystal_cap);
310
311 rtw8814a_config_trx_path(rtwdev);
312
313 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
314 rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
315
316 val32 = rtw_read_rf(rtwdev, RF_PATH_A, RF_RCK1_V1, RFREG_MASK);
317 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK1_V1, RFREG_MASK, val32);
318 rtw_write_rf(rtwdev, RF_PATH_C, RF_RCK1_V1, RFREG_MASK, val32);
319 rtw_write_rf(rtwdev, RF_PATH_D, RF_RCK1_V1, RFREG_MASK, val32);
320
321 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
322
323 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xFF);
324
325 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff);
326
327 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
328
329 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0);
330
331 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5));
332
333 rtw8814a_config_cck_rx_antenna_init(rtwdev);
334
335 rtw_phy_init(rtwdev);
336 rtw8814a_pwrtrack_init(rtwdev);
337
338 rtw8814a_init_rfe_reg(rtwdev);
339
340 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3));
341
342 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 235);
343
344 /* enable Tx report. */
345 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x1F);
346
347 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
348 /* Reset USB mode switch setting */
349 rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0);
350 rtw_write8(rtwdev, REG_ACLK_MON, 0x0);
351 }
352 }
353
rtw8814ae_enable_rf_1_2v(struct rtw_dev * rtwdev)354 static void rtw8814ae_enable_rf_1_2v(struct rtw_dev *rtwdev)
355 {
356 /* This is for fullsize card, because GPIO7 there is floating.
357 * We should pull GPIO7 high to enable RF 1.2V Switch Power Supply
358 */
359
360 /* 1. set 0x40[1:0] to 0, BIT_GPIOSEL=0, select pin as GPIO */
361 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(1) | BIT(0));
362
363 /* 2. set 0x44[31] to 0
364 * mode=0: data port;
365 * mode=1 and BIT_GPIO_IO_SEL=0: interrupt mode;
366 */
367 rtw_write8_clr(rtwdev, REG_GPIO_PIN_CTRL + 3, BIT(7));
368
369 /* 3. data mode
370 * 3.1 set 0x44[23] to 1
371 * sel=0: input;
372 * sel=1: output;
373 */
374 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 2, BIT(7));
375
376 /* 3.2 set 0x44[15] to 1
377 * output high value;
378 */
379 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 1, BIT(7));
380 }
381
rtw8814a_mac_init(struct rtw_dev * rtwdev)382 static int rtw8814a_mac_init(struct rtw_dev *rtwdev)
383 {
384 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
385
386 rtw_write16(rtwdev, REG_CR,
387 MAC_TRX_ENABLE | BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN);
388
389 rtw_load_table(rtwdev, rtwdev->chip->mac_tbl);
390
391 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
392 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3,
393 rtwdev->chip->usb_tx_agg_desc_num << 1);
394
395 rtw_write32(rtwdev, REG_HIMR0, 0);
396 rtw_write32(rtwdev, REG_HIMR1, 0);
397
398 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xfffff);
399
400 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
401
402 rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
403 rtwdev->hal.rxfltmap1 = 0x0400;
404 rtw_write16(rtwdev, REG_RXFLTMAP1, rtwdev->hal.rxfltmap1);
405 rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
406
407 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, 0x36);
408 rtw_write8(rtwdev, REG_MAX_AGGR_NUM + 1, 0x36);
409
410 /* Set Spec SIFS (used in NAV) */
411 rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
412 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
413
414 /* Set SIFS for CCK */
415 rtw_write16(rtwdev, REG_SIFS, 0x100a);
416
417 /* Set SIFS for OFDM */
418 rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
419
420 /* TXOP */
421 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
422 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
423 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
424 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
425
426 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
427
428 rtw_write8(rtwdev, REG_ACKTO, 0x80);
429
430 rtw_write16(rtwdev, REG_BCN_CTRL,
431 BIT_DIS_TSF_UDT | (BIT_DIS_TSF_UDT << 8));
432 rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
433 rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
434 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
435 rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
436 rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xFF);
437
438 rtw_write32(rtwdev, REG_FAST_EDCA_VOVI_SETTING, 0x08070807);
439 rtw_write32(rtwdev, REG_FAST_EDCA_BEBK_SETTING, 0x08070807);
440
441 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
442 rtwusb->udev->speed == USB_SPEED_SUPER) {
443 /* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */
444 rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3));
445 /* To avoid usb 3.0 H2C fail. */
446 rtw_write16(rtwdev, 0xf002, 0);
447
448 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL,
449 BIT_PRE_TX_CMD);
450 } else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) {
451 rtw8814ae_enable_rf_1_2v(rtwdev);
452
453 /* Force the antenna b to wifi. */
454 rtw_write8_set(rtwdev, REG_PAD_CTRL1, BIT(2));
455 rtw_write8_set(rtwdev, REG_PAD_CTRL1 + 1, BIT(0));
456 rtw_write8_set(rtwdev, REG_LED_CFG + 3,
457 (BIT(27) | BIT_DPDT_WL_SEL) >> 24);
458 }
459
460 return 0;
461 }
462
rtw8814a_set_rfe_reg_24g(struct rtw_dev * rtwdev)463 static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev)
464 {
465 switch (rtwdev->efuse.rfe_option) {
466 case 2:
467 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270);
468 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270);
469 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270);
470 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770);
471
472 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
473 BIT_RFE_SELSW0_D, 0x72);
474
475 break;
476 case 1:
477 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
478 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
479 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
480 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
481
482 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
483 BIT_RFE_SELSW0_D, 0x77);
484
485 break;
486 case 0:
487 default:
488 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
489 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
490 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
491 /* Is it not necessary to set REG_RFE_PINMUX_D ? */
492
493 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
494 BIT_RFE_SELSW0_D, 0x77);
495
496 break;
497 }
498 }
499
rtw8814a_set_rfe_reg_5g(struct rtw_dev * rtwdev)500 static void rtw8814a_set_rfe_reg_5g(struct rtw_dev *rtwdev)
501 {
502 switch (rtwdev->efuse.rfe_option) {
503 case 2:
504 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x37173717);
505 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x37173717);
506 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x37173717);
507 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
508
509 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
510 BIT_RFE_SELSW0_D, 0x37);
511
512 break;
513 case 1:
514 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x33173317);
515 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x33173317);
516 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x33173317);
517 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
518
519 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
520 BIT_RFE_SELSW0_D, 0x33);
521
522 break;
523 case 0:
524 default:
525 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54775477);
526 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54775477);
527 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x54775477);
528 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x54775477);
529
530 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D,
531 BIT_RFE_SELSW0_D, 0x54);
532
533 break;
534 }
535 }
536
rtw8814a_set_channel_bb_swing(struct rtw_dev * rtwdev,u8 band)537 static void rtw8814a_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
538 {
539 rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
540 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_A));
541 rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
542 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_B));
543 rtw_write32_mask(rtwdev, REG_TXSCALE_C, BB_SWING_MASK,
544 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_C));
545 rtw_write32_mask(rtwdev, REG_TXSCALE_D, BB_SWING_MASK,
546 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_D));
547 rtw8814a_pwrtrack_init(rtwdev);
548 }
549
rtw8814a_set_bw_reg_adc(struct rtw_dev * rtwdev,u8 bw)550 static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw)
551 {
552 u32 adc = 0;
553
554 if (bw == RTW_CHANNEL_WIDTH_20)
555 adc = 0;
556 else if (bw == RTW_CHANNEL_WIDTH_40)
557 adc = 1;
558 else if (bw == RTW_CHANNEL_WIDTH_80)
559 adc = 2;
560
561 rtw_write32_mask(rtwdev, REG_ADCCLK, BIT(1) | BIT(0), adc);
562 }
563
rtw8814a_set_bw_reg_agc(struct rtw_dev * rtwdev,u8 new_band,u8 bw)564 static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
565 {
566 u32 agc = 7;
567
568 if (bw == RTW_CHANNEL_WIDTH_20) {
569 agc = 6;
570 } else if (bw == RTW_CHANNEL_WIDTH_40) {
571 if (new_band == RTW_BAND_5G)
572 agc = 8;
573 else
574 agc = 7;
575 } else if (bw == RTW_CHANNEL_WIDTH_80) {
576 agc = 3;
577 }
578
579 rtw_write32_mask(rtwdev, REG_CCASEL, 0xf000, agc);
580 }
581
rtw8814a_switch_band(struct rtw_dev * rtwdev,u8 new_band,u8 bw)582 static void rtw8814a_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
583 {
584 /* Clear 0x1000[16], When this bit is set to 0, CCK and OFDM
585 * are disabled, and clock are gated. Otherwise, CCK and OFDM
586 * are enabled.
587 */
588 rtw_write8_clr(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
589
590 if (new_band == RTW_BAND_2G) {
591 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 0);
592
593 rtw8814a_set_rfe_reg_24g(rtwdev);
594
595 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x2);
596 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
597
598 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x3);
599
600 rtw_write8(rtwdev, REG_CCK_CHECK, 0);
601
602 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 0);
603 } else {
604 rtw_write8(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
605
606 /* Enable CCK Tx function, even when CCK is off */
607 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 1);
608
609 rtw8814a_set_rfe_reg_5g(rtwdev);
610
611 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x0);
612 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
613
614 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x2);
615 }
616
617 rtw8814a_set_channel_bb_swing(rtwdev, new_band);
618
619 rtw8814a_set_bw_reg_adc(rtwdev, bw);
620 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw);
621
622 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
623 }
624
rtw8814a_switch_channel(struct rtw_dev * rtwdev,u8 channel)625 static void rtw8814a_switch_channel(struct rtw_dev *rtwdev, u8 channel)
626 {
627 struct rtw_hal *hal = &rtwdev->hal;
628 u32 fc_area, rf_mod_ag, cfgch;
629 u8 path;
630
631 switch (channel) {
632 case 36 ... 48:
633 fc_area = 0x494;
634 break;
635 case 50 ... 64:
636 fc_area = 0x453;
637 break;
638 case 100 ... 116:
639 fc_area = 0x452;
640 break;
641 default:
642 if (channel >= 118)
643 fc_area = 0x412;
644 else
645 fc_area = 0x96a;
646 break;
647 }
648
649 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area);
650
651 for (path = 0; path < hal->rf_path_num; path++) {
652 switch (channel) {
653 case 36 ... 64:
654 rf_mod_ag = 0x101;
655 break;
656 case 100 ... 140:
657 rf_mod_ag = 0x301;
658 break;
659 default:
660 if (channel > 140)
661 rf_mod_ag = 0x501;
662 else
663 rf_mod_ag = 0x000;
664 break;
665 }
666
667 cfgch = (rf_mod_ag << 8) | channel;
668
669 rtw_write_rf(rtwdev, path, RF_CFGCH,
670 RF18_RFSI_MASK | RF18_BAND_MASK | RF18_CHANNEL_MASK, cfgch);
671 }
672
673 switch (channel) {
674 case 36 ... 64:
675 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 1);
676 break;
677 case 100 ... 144:
678 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 2);
679 break;
680 default:
681 if (channel >= 149)
682 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 3);
683
684 break;
685 }
686 }
687
rtw8814a_24g_cck_tx_dfir(struct rtw_dev * rtwdev,u8 channel)688 static void rtw8814a_24g_cck_tx_dfir(struct rtw_dev *rtwdev, u8 channel)
689 {
690 if (channel >= 1 && channel <= 11) {
691 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
692 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1317);
693 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000204);
694 } else if (channel >= 12 && channel <= 13) {
695 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
696 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1217);
697 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000305);
698 } else if (channel == 14) {
699 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
700 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x00000E17);
701 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000000);
702 }
703 }
704
rtw8814a_set_bw_reg_mac(struct rtw_dev * rtwdev,u8 bw)705 static void rtw8814a_set_bw_reg_mac(struct rtw_dev *rtwdev, u8 bw)
706 {
707 u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL);
708
709 val16 &= ~BIT_RFMOD;
710 if (bw == RTW_CHANNEL_WIDTH_80)
711 val16 |= BIT_RFMOD_80M;
712 else if (bw == RTW_CHANNEL_WIDTH_40)
713 val16 |= BIT_RFMOD_40M;
714
715 rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16);
716 }
717
rtw8814a_set_bw_rf(struct rtw_dev * rtwdev,u8 bw)718 static void rtw8814a_set_bw_rf(struct rtw_dev *rtwdev, u8 bw)
719 {
720 u8 path;
721
722 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
723 switch (bw) {
724 case RTW_CHANNEL_WIDTH_5:
725 case RTW_CHANNEL_WIDTH_10:
726 case RTW_CHANNEL_WIDTH_20:
727 default:
728 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3);
729 break;
730 case RTW_CHANNEL_WIDTH_40:
731 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1);
732 break;
733 case RTW_CHANNEL_WIDTH_80:
734 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0);
735 break;
736 }
737 }
738 }
739
rtw8814a_adc_clk(struct rtw_dev * rtwdev)740 static void rtw8814a_adc_clk(struct rtw_dev *rtwdev)
741 {
742 static const u32 rxiqc_reg[2][4] = {
743 { REG_RX_IQC_AB_A, REG_RX_IQC_AB_B,
744 REG_RX_IQC_AB_C, REG_RX_IQC_AB_D },
745 { REG_RX_IQC_CD_A, REG_RX_IQC_CD_B,
746 REG_RX_IQC_CD_C, REG_RX_IQC_CD_D }
747 };
748 u32 bb_reg_8fc, bb_reg_808, rxiqc[4];
749 u32 i = 0, mac_active = 1;
750 u8 mac_reg_522;
751
752 if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A)
753 return;
754
755 /* 1 Step1. MAC TX pause */
756 mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE);
757 bb_reg_8fc = rtw_read32(rtwdev, REG_DBGSEL);
758 bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL);
759 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
760
761 /* 1 Step 2. Backup rxiqc & rxiqc = 0 */
762 for (i = 0; i < 4; i++) {
763 rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]);
764 rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0);
765 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0);
766 }
767 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x3);
768 i = 0;
769
770 /* 1 Step 3. Monitor MAC IDLE */
771 rtw_write32(rtwdev, REG_DBGSEL, 0x0);
772 while (mac_active) {
773 mac_active = rtw_read32(rtwdev, REG_DBGRPT) & 0x803e0008;
774 i++;
775 if (i > 1000)
776 break;
777 }
778
779 /* 1 Step 4. ADC clk flow */
780 rtw_write8(rtwdev, REG_RXPSEL, 0x11);
781 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1);
782 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x3);
783 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
784
785 /* 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be
786 * written when bbrstb=0
787 * 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line
788 * 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut
789 */
790
791 /* power_off/clk_off @ anapar_state=idle mode */
792 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x15800002);
793 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x01808003);
794 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x15800002);
795 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x01808003);
796 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x15800002);
797 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x01808003);
798 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x15800002);
799 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x01808003);
800
801 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x0);
802 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
803 /* [19] = 1 to turn off ADC */
804 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D080058);
805 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D080058);
806 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D080058);
807 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D080058);
808
809 /* power_on/clk_off */
810 /* [19] = 0 to turn on ADC */
811 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D000058);
812 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D000058);
813 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D000058);
814 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D000058);
815
816 /* power_on/clk_on @ anapar_state=BT mode */
817 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
818 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
819 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
820 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
821 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x1);
822 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
823
824 /* recover original setting @ anapar_state=BT mode */
825 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
826 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
827 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
828 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
829
830 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05800002);
831 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003);
832 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05800002);
833 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003);
834 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05800002);
835 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003);
836 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05800002);
837 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003);
838
839 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x0);
840 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
841 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x0);
842
843 /* 1 Step 5. Recover MAC TX & IQC */
844 rtw_write8(rtwdev, REG_TXPAUSE, mac_reg_522);
845 rtw_write32(rtwdev, REG_DBGSEL, bb_reg_8fc);
846 rtw_write32(rtwdev, REG_RXPSEL, bb_reg_808);
847 for (i = 0; i < 4; i++) {
848 rtw_write32(rtwdev, rxiqc_reg[0][i], rxiqc[i]);
849 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x01000000);
850 }
851 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x0);
852 }
853
rtw8814a_spur_calibration_ch140(struct rtw_dev * rtwdev,u8 channel)854 static void rtw8814a_spur_calibration_ch140(struct rtw_dev *rtwdev, u8 channel)
855 {
856 struct rtw_hal *hal = &rtwdev->hal;
857
858 /* Add for 8814AE module ch140 MP Rx */
859 if (channel == 140) {
860 if (hal->ch_param[0] == 0)
861 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
862 if (hal->ch_param[1] == 0)
863 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
864
865 rtw_write32(rtwdev, REG_CCASEL, 0x75438170);
866 rtw_write32(rtwdev, REG_PDMFTH, 0x79a18a0a);
867 } else {
868 if (rtw_read32(rtwdev, REG_CCASEL) == 0x75438170 &&
869 hal->ch_param[0] != 0)
870 rtw_write32(rtwdev, REG_CCASEL, hal->ch_param[0]);
871
872 if (rtw_read32(rtwdev, REG_PDMFTH) == 0x79a18a0a &&
873 hal->ch_param[1] != 0)
874 rtw_write32(rtwdev, REG_PDMFTH, hal->ch_param[1]);
875
876 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
877 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
878 }
879 }
880
rtw8814a_set_nbi_reg(struct rtw_dev * rtwdev,u32 tone_idx)881 static void rtw8814a_set_nbi_reg(struct rtw_dev *rtwdev, u32 tone_idx)
882 {
883 /* tone_idx X 10 */
884 static const u32 nbi_128[] = {
885 25, 55, 85, 115, 135,
886 155, 185, 205, 225, 245,
887 265, 285, 305, 335, 355,
888 375, 395, 415, 435, 455,
889 485, 505, 525, 555, 585, 615, 635
890 };
891 u32 reg_idx = 0;
892 u32 i;
893
894 for (i = 0; i < ARRAY_SIZE(nbi_128); i++) {
895 if (tone_idx < nbi_128[i]) {
896 reg_idx = i + 1;
897 break;
898 }
899 }
900
901 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 0xfc000, reg_idx);
902 }
903
rtw8814a_nbi_setting(struct rtw_dev * rtwdev,u32 ch,u32 f_intf)904 static void rtw8814a_nbi_setting(struct rtw_dev *rtwdev, u32 ch, u32 f_intf)
905 {
906 u32 fc, int_distance, tone_idx;
907
908 fc = 2412 + (ch - 1) * 5;
909 int_distance = abs_diff(fc, f_intf);
910
911 /* 10 * (int_distance / 0.3125) */
912 tone_idx = int_distance << 5;
913
914 rtw8814a_set_nbi_reg(rtwdev, tone_idx);
915
916 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 1);
917 }
918
rtw8814a_spur_nbi_setting(struct rtw_dev * rtwdev)919 static void rtw8814a_spur_nbi_setting(struct rtw_dev *rtwdev)
920 {
921 u8 primary_channel = rtwdev->hal.primary_channel;
922 u8 rfe_type = rtwdev->efuse.rfe_option;
923
924 if (rfe_type != 0 && rfe_type != 1 && rfe_type != 6 && rfe_type != 7)
925 return;
926
927 if (primary_channel == 14)
928 rtw8814a_nbi_setting(rtwdev, primary_channel, 2480);
929 else if (primary_channel >= 4 && primary_channel <= 8)
930 rtw8814a_nbi_setting(rtwdev, primary_channel, 2440);
931 else
932 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 0);
933 }
934
935 /* A workaround to eliminate the 5280 MHz & 5600 MHz & 5760 MHz spur of 8814A */
rtw8814a_spur_calibration(struct rtw_dev * rtwdev,u8 channel,u8 bw)936 static void rtw8814a_spur_calibration(struct rtw_dev *rtwdev, u8 channel, u8 bw)
937 {
938 u8 rfe_type = rtwdev->efuse.rfe_option;
939 bool reset_nbi_csi = true;
940
941 if (rfe_type == 0) {
942 switch (bw) {
943 case RTW_CHANNEL_WIDTH_40:
944 if (channel == 54 || channel == 118) {
945 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
946 0x000fe000, 0x3e >> 1);
947 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
948 BIT(0), 1);
949 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
950 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK1,
951 BIT(0), 1);
952 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
953 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
954
955 reset_nbi_csi = false;
956 } else if (channel == 151) {
957 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
958 0x000fe000, 0x1e >> 1);
959 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
960 BIT(0), 1);
961 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
962 BIT(16), 1);
963 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
964 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
965 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
966
967 reset_nbi_csi = false;
968 }
969 break;
970 case RTW_CHANNEL_WIDTH_80:
971 if (channel == 58 || channel == 122) {
972 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
973 0x000fe000, 0x3a >> 1);
974 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
975 BIT(0), 1);
976 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
977 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
978 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
979 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
980 BIT(0), 1);
981
982 reset_nbi_csi = false;
983 } else if (channel == 155) {
984 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
985 0x000fe000, 0x5a >> 1);
986 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
987 BIT(0), 1);
988 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
989 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
990 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6,
991 BIT(16), 1);
992 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
993
994 reset_nbi_csi = false;
995 }
996 break;
997 case RTW_CHANNEL_WIDTH_20:
998 if (channel == 153) {
999 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1000 0x000fe000, 0x1e >> 1);
1001 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1002 BIT(0), 1);
1003 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1004 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1005 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1006 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
1007 BIT(16), 1);
1008
1009 reset_nbi_csi = false;
1010 }
1011
1012 rtw8814a_spur_calibration_ch140(rtwdev, channel);
1013 break;
1014 default:
1015 break;
1016 }
1017 } else if (rfe_type == 1 || rfe_type == 2) {
1018 switch (bw) {
1019 case RTW_CHANNEL_WIDTH_20:
1020 if (channel == 153) {
1021 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1022 0x000fe000, 0x1E >> 1);
1023 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1024 BIT(0), 1);
1025 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1026 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1027 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1028 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
1029 BIT(16), 1);
1030
1031 reset_nbi_csi = false;
1032 }
1033 break;
1034 case RTW_CHANNEL_WIDTH_40:
1035 if (channel == 151) {
1036 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1037 0x000fe000, 0x1e >> 1);
1038 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1039 BIT(0), 1);
1040 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
1041 BIT(16), 1);
1042 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1043 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1044 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1045
1046 reset_nbi_csi = false;
1047 }
1048 break;
1049 case RTW_CHANNEL_WIDTH_80:
1050 if (channel == 155) {
1051 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1052 0x000fe000, 0x5a >> 1);
1053 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
1054 BIT(0), 1);
1055 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1056 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1057 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6,
1058 BIT(16), 1);
1059 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1060
1061 reset_nbi_csi = false;
1062 }
1063 break;
1064 default:
1065 break;
1066 }
1067 }
1068
1069 if (reset_nbi_csi) {
1070 rtw_write32_mask(rtwdev, REG_NBI_SETTING,
1071 0x000fe000, 0xfc >> 1);
1072 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, BIT(0), 0);
1073 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
1074 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
1075 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
1076 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
1077 }
1078
1079 rtw8814a_spur_nbi_setting(rtwdev);
1080 }
1081
rtw8814a_set_bw_mode(struct rtw_dev * rtwdev,u8 new_band,u8 channel,u8 bw,u8 primary_chan_idx)1082 static void rtw8814a_set_bw_mode(struct rtw_dev *rtwdev, u8 new_band,
1083 u8 channel, u8 bw, u8 primary_chan_idx)
1084 {
1085 u8 txsc40 = 0, txsc20, txsc;
1086
1087 rtw8814a_set_bw_reg_mac(rtwdev, bw);
1088
1089 txsc20 = primary_chan_idx;
1090 if (bw == RTW_CHANNEL_WIDTH_80) {
1091 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST)
1092 txsc40 = RTW_SC_40_UPPER;
1093 else
1094 txsc40 = RTW_SC_40_LOWER;
1095 }
1096
1097 txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40);
1098 rtw_write8(rtwdev, REG_DATA_SC, txsc);
1099
1100 rtw8814a_set_bw_reg_adc(rtwdev, bw);
1101 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw);
1102
1103 if (bw == RTW_CHANNEL_WIDTH_80) {
1104 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc);
1105 } else if (bw == RTW_CHANNEL_WIDTH_40) {
1106 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc);
1107
1108 if (txsc == RTW_SC_20_UPPER)
1109 rtw_write32_set(rtwdev, REG_RXSB, BIT(4));
1110 else
1111 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4));
1112 }
1113
1114 rtw8814a_set_bw_rf(rtwdev, bw);
1115
1116 rtw8814a_adc_clk(rtwdev);
1117
1118 rtw8814a_spur_calibration(rtwdev, channel, bw);
1119 }
1120
rtw8814a_set_channel(struct rtw_dev * rtwdev,u8 channel,u8 bw,u8 primary_chan_idx)1121 static void rtw8814a_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
1122 u8 primary_chan_idx)
1123 {
1124 u8 old_band, new_band;
1125
1126 if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN)
1127 old_band = RTW_BAND_5G;
1128 else
1129 old_band = RTW_BAND_2G;
1130
1131 if (channel > 14)
1132 new_band = RTW_BAND_5G;
1133 else
1134 new_band = RTW_BAND_2G;
1135
1136 if (new_band != old_band)
1137 rtw8814a_switch_band(rtwdev, new_band, bw);
1138
1139 rtw8814a_switch_channel(rtwdev, channel);
1140
1141 rtw8814a_24g_cck_tx_dfir(rtwdev, channel);
1142
1143 rtw8814a_set_bw_mode(rtwdev, new_band, channel, bw, primary_chan_idx);
1144 }
1145
rtw8814a_cck_rx_pwr(u8 lna_idx,u8 vga_idx)1146 static s8 rtw8814a_cck_rx_pwr(u8 lna_idx, u8 vga_idx)
1147 {
1148 s8 rx_pwr_all = 0;
1149
1150 switch (lna_idx) {
1151 case 7:
1152 rx_pwr_all = -38 - 2 * vga_idx;
1153 break;
1154 case 5:
1155 rx_pwr_all = -28 - 2 * vga_idx;
1156 break;
1157 case 3:
1158 rx_pwr_all = -8 - 2 * vga_idx;
1159 break;
1160 case 2:
1161 rx_pwr_all = -1 - 2 * vga_idx;
1162 break;
1163 default:
1164 break;
1165 }
1166
1167 return rx_pwr_all;
1168 }
1169
rtw8814a_query_phy_status(struct rtw_dev * rtwdev,u8 * phy_status,struct rtw_rx_pkt_stat * pkt_stat)1170 static void rtw8814a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
1171 struct rtw_rx_pkt_stat *pkt_stat)
1172 {
1173 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1174 struct rtw_jaguar_phy_status_rpt *rpt;
1175 u8 gain[RTW_RF_PATH_MAX], rssi, i;
1176 s8 rx_pwr_db, middle1, middle2;
1177 s8 snr[RTW_RF_PATH_MAX];
1178 s8 evm[RTW_RF_PATH_MAX];
1179 u8 rfmode, subchannel;
1180 u8 lna, vga;
1181 s8 cfo[2];
1182
1183 rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status;
1184
1185 pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
1186
1187 if (pkt_stat->rate <= DESC_RATE11M) {
1188 lna = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX);
1189 vga = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX);
1190
1191 rx_pwr_db = rtw8814a_cck_rx_pwr(lna, vga);
1192
1193 pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db;
1194 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
1195 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi;
1196 pkt_stat->signal_power = rx_pwr_db;
1197 } else { /* OFDM rate */
1198 gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A);
1199 gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B);
1200 gain[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_GAIN_C);
1201 gain[RF_PATH_D] = le32_get_bits(rpt->w6, RTW_JGRPHY_W6_GAIN_D);
1202
1203 snr[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXSNR_A);
1204 snr[RF_PATH_B] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXSNR_B);
1205 snr[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_C);
1206 snr[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_D);
1207
1208 evm[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_1);
1209 evm[RF_PATH_B] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_2);
1210 evm[RF_PATH_C] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXEVM_3);
1211 evm[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXEVM_4);
1212
1213 if (pkt_stat->rate <= DESC_RATE54M)
1214 evm[RF_PATH_A] = le32_get_bits(rpt->w6,
1215 RTW_JGRPHY_W6_SIGEVM);
1216
1217 for (i = RF_PATH_A; i < RTW_RF_PATH_MAX; i++) {
1218 pkt_stat->rx_power[i] = gain[i] - 110;
1219
1220 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1);
1221 dm_info->rssi[i] = rssi;
1222
1223 pkt_stat->rx_snr[i] = snr[i];
1224 dm_info->rx_snr[i] = snr[i] >> 1;
1225
1226 pkt_stat->rx_evm[i] = evm[i];
1227 evm[i] = max_t(s8, -127, evm[i]);
1228 dm_info->rx_evm_dbm[i] = abs(evm[i]) >> 1;
1229 }
1230
1231 rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power,
1232 RTW_RF_PATH_MAX);
1233 pkt_stat->rssi = rssi;
1234
1235 /* When power saving is enabled the hardware sometimes
1236 * reports unbelievably high gain for paths A and C
1237 * (e.g. one frame 64 68 68 72, the next frame 106 66 88 72,
1238 * the next 66 66 68 72), so use the second lowest gain
1239 * instead of the highest.
1240 */
1241 middle1 = max(min(gain[RF_PATH_A], gain[RF_PATH_B]),
1242 min(gain[RF_PATH_C], gain[RF_PATH_D]));
1243 middle2 = min(max(gain[RF_PATH_A], gain[RF_PATH_B]),
1244 max(gain[RF_PATH_C], gain[RF_PATH_D]));
1245 rx_pwr_db = min(middle1, middle2);
1246 rx_pwr_db -= 110;
1247 pkt_stat->signal_power = rx_pwr_db;
1248
1249 rfmode = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_R_RFMOD);
1250 subchannel = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_SUB_CHNL);
1251
1252 if (rfmode == 1 && subchannel == 0) {
1253 pkt_stat->bw = RTW_CHANNEL_WIDTH_40;
1254 } else if (rfmode == 2) {
1255 if (subchannel == 0)
1256 pkt_stat->bw = RTW_CHANNEL_WIDTH_80;
1257 else if (subchannel == 9 || subchannel == 10)
1258 pkt_stat->bw = RTW_CHANNEL_WIDTH_40;
1259 }
1260
1261 cfo[RF_PATH_A] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_A);
1262 cfo[RF_PATH_B] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_B);
1263
1264 for (i = RF_PATH_A; i < 2; i++) {
1265 pkt_stat->cfo_tail[i] = cfo[i];
1266 dm_info->cfo_tail[i] = (cfo[i] * 5) >> 1;
1267 }
1268 }
1269 }
1270
1271 static void
rtw8814a_set_tx_power_index_by_rate(struct rtw_dev * rtwdev,u8 path,u8 rs)1272 rtw8814a_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs)
1273 {
1274 struct rtw_hal *hal = &rtwdev->hal;
1275 u32 txagc_table_wd;
1276 u8 rate, pwr_index;
1277 int j;
1278
1279 for (j = 0; j < rtw_rate_size[rs]; j++) {
1280 rate = rtw_rate_section[rs][j];
1281
1282 pwr_index = hal->tx_pwr_tbl[path][rate] + 2;
1283 if (pwr_index > rtwdev->chip->max_power_index)
1284 pwr_index = rtwdev->chip->max_power_index;
1285
1286 txagc_table_wd = 0x00801000;
1287 txagc_table_wd |= (pwr_index << 24) | (path << 8) | rate;
1288
1289 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd);
1290
1291 /* first time to turn on the txagc table
1292 * second to write the addr0
1293 */
1294 if (rate == DESC_RATE1M)
1295 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd);
1296 }
1297 }
1298
rtw8814a_set_tx_power_index(struct rtw_dev * rtwdev)1299 static void rtw8814a_set_tx_power_index(struct rtw_dev *rtwdev)
1300 {
1301 struct rtw_hal *hal = &rtwdev->hal;
1302 int path;
1303
1304 for (path = 0; path < hal->rf_path_num; path++) {
1305 if (hal->current_band_type == RTW_BAND_2G)
1306 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1307 RTW_RATE_SECTION_CCK);
1308
1309 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1310 RTW_RATE_SECTION_OFDM);
1311
1312 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags))
1313 continue;
1314
1315 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1316 RTW_RATE_SECTION_HT_1S);
1317 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1318 RTW_RATE_SECTION_VHT_1S);
1319
1320 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1321 RTW_RATE_SECTION_HT_2S);
1322 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1323 RTW_RATE_SECTION_VHT_2S);
1324
1325 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1326 RTW_RATE_SECTION_HT_3S);
1327 rtw8814a_set_tx_power_index_by_rate(rtwdev, path,
1328 RTW_RATE_SECTION_VHT_3S);
1329 }
1330 }
1331
rtw8814a_cfg_ldo25(struct rtw_dev * rtwdev,bool enable)1332 static void rtw8814a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
1333 {
1334 }
1335
1336 /* Without this RTL8814A sends too many frames and (some?) 11n AP
1337 * can't handle it, resulting in low TX speed. Other chips seem fine.
1338 */
rtw8814a_set_ampdu_factor(struct rtw_dev * rtwdev,u8 factor)1339 static void rtw8814a_set_ampdu_factor(struct rtw_dev *rtwdev, u8 factor)
1340 {
1341 factor = min_t(u8, factor, IEEE80211_VHT_MAX_AMPDU_256K);
1342
1343 rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, (8192 << factor) - 1);
1344 }
1345
rtw8814a_false_alarm_statistics(struct rtw_dev * rtwdev)1346 static void rtw8814a_false_alarm_statistics(struct rtw_dev *rtwdev)
1347 {
1348 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1349 u32 cck_fa_cnt, ofdm_fa_cnt;
1350 u32 crc32_cnt, cca32_cnt;
1351 u32 cck_enable;
1352
1353 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28);
1354 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK);
1355 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM);
1356
1357 dm_info->cck_fa_cnt = cck_fa_cnt;
1358 dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
1359 dm_info->total_fa_cnt = ofdm_fa_cnt;
1360 if (cck_enable)
1361 dm_info->total_fa_cnt += cck_fa_cnt;
1362
1363 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK);
1364 dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1365 dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1366
1367 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM);
1368 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1369 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1370
1371 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT);
1372 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1373 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1374
1375 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT);
1376 dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD);
1377 dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD);
1378
1379 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM);
1380 dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD);
1381 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
1382 if (cck_enable) {
1383 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK);
1384 dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD);
1385 dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
1386 }
1387
1388 rtw_write32_set(rtwdev, REG_FAS, BIT(17));
1389 rtw_write32_clr(rtwdev, REG_FAS, BIT(17));
1390 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1391 rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15));
1392 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0));
1393 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0));
1394 }
1395
1396 #define MAC_REG_NUM_8814 2
1397 #define BB_REG_NUM_8814 14
1398 #define RF_REG_NUM_8814 1
1399
rtw8814a_iqk_backup_mac_bb(struct rtw_dev * rtwdev,u32 * mac_backup,u32 * bb_backup,const u32 * mac_regs,const u32 * bb_regs)1400 static void rtw8814a_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
1401 u32 *mac_backup, u32 *bb_backup,
1402 const u32 *mac_regs,
1403 const u32 *bb_regs)
1404 {
1405 u32 i;
1406
1407 /* save MACBB default value */
1408 for (i = 0; i < MAC_REG_NUM_8814; i++)
1409 mac_backup[i] = rtw_read32(rtwdev, mac_regs[i]);
1410
1411 for (i = 0; i < BB_REG_NUM_8814; i++)
1412 bb_backup[i] = rtw_read32(rtwdev, bb_regs[i]);
1413 }
1414
rtw8814a_iqk_backup_rf(struct rtw_dev * rtwdev,u32 rf_backup[][4],const u32 * rf_regs)1415 static void rtw8814a_iqk_backup_rf(struct rtw_dev *rtwdev,
1416 u32 rf_backup[][4], const u32 *rf_regs)
1417 {
1418 u32 i;
1419
1420 /* Save RF Parameters */
1421 for (i = 0; i < RF_REG_NUM_8814; i++) {
1422 rf_backup[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
1423 rf_regs[i], RFREG_MASK);
1424 rf_backup[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
1425 rf_regs[i], RFREG_MASK);
1426 rf_backup[i][RF_PATH_C] = rtw_read_rf(rtwdev, RF_PATH_C,
1427 rf_regs[i], RFREG_MASK);
1428 rf_backup[i][RF_PATH_D] = rtw_read_rf(rtwdev, RF_PATH_D,
1429 rf_regs[i], RFREG_MASK);
1430 }
1431 }
1432
rtw8814a_iqk_afe_setting(struct rtw_dev * rtwdev,bool do_iqk)1433 static void rtw8814a_iqk_afe_setting(struct rtw_dev *rtwdev, bool do_iqk)
1434 {
1435 if (do_iqk) {
1436 /* IQK AFE setting RX_WAIT_CCA mode */
1437 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x0e808003);
1438 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x0e808003);
1439 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x0e808003);
1440 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x0e808003);
1441 } else {
1442 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003);
1443 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003);
1444 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003);
1445 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003);
1446 }
1447
1448 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1);
1449
1450 rtw_write8_set(rtwdev, REG_GNT_BT, BIT(2) | BIT(1));
1451 rtw_write8_clr(rtwdev, REG_GNT_BT, BIT(2) | BIT(1));
1452
1453 rtw_write32_set(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
1454 rtw_write32_clr(rtwdev, REG_CCK_RPT_FORMAT, BIT(2));
1455 }
1456
rtw8814a_iqk_restore_mac_bb(struct rtw_dev * rtwdev,u32 * mac_backup,u32 * bb_backup,const u32 * mac_regs,const u32 * bb_regs)1457 static void rtw8814a_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
1458 u32 *mac_backup, u32 *bb_backup,
1459 const u32 *mac_regs,
1460 const u32 *bb_regs)
1461 {
1462 u32 i;
1463
1464 /* Reload MacBB Parameters */
1465 for (i = 0; i < MAC_REG_NUM_8814; i++)
1466 rtw_write32(rtwdev, mac_regs[i], mac_backup[i]);
1467
1468 for (i = 0; i < BB_REG_NUM_8814; i++)
1469 rtw_write32(rtwdev, bb_regs[i], bb_backup[i]);
1470 }
1471
rtw8814a_iqk_restore_rf(struct rtw_dev * rtwdev,const u32 rf_backup[][4],const u32 * rf_regs)1472 static void rtw8814a_iqk_restore_rf(struct rtw_dev *rtwdev,
1473 const u32 rf_backup[][4],
1474 const u32 *rf_regs)
1475 {
1476 u32 i;
1477
1478 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x0);
1479 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x0);
1480 rtw_write_rf(rtwdev, RF_PATH_C, RF_LUTWE, RFREG_MASK, 0x0);
1481 rtw_write_rf(rtwdev, RF_PATH_D, RF_LUTWE, RFREG_MASK, 0x0);
1482
1483 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001);
1484 rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x88001);
1485 rtw_write_rf(rtwdev, RF_PATH_C, RF_RXBB2, RFREG_MASK, 0x88001);
1486 rtw_write_rf(rtwdev, RF_PATH_D, RF_RXBB2, RFREG_MASK, 0x88001);
1487
1488 for (i = 0; i < RF_REG_NUM_8814; i++) {
1489 rtw_write_rf(rtwdev, RF_PATH_A, rf_regs[i],
1490 RFREG_MASK, rf_backup[i][RF_PATH_A]);
1491 rtw_write_rf(rtwdev, RF_PATH_B, rf_regs[i],
1492 RFREG_MASK, rf_backup[i][RF_PATH_B]);
1493 rtw_write_rf(rtwdev, RF_PATH_C, rf_regs[i],
1494 RFREG_MASK, rf_backup[i][RF_PATH_C]);
1495 rtw_write_rf(rtwdev, RF_PATH_D, rf_regs[i],
1496 RFREG_MASK, rf_backup[i][RF_PATH_D]);
1497 }
1498 }
1499
rtw8814a_iqk_reset_nctl(struct rtw_dev * rtwdev)1500 static void rtw8814a_iqk_reset_nctl(struct rtw_dev *rtwdev)
1501 {
1502 rtw_write32(rtwdev, 0x1b00, 0xf8000000);
1503 rtw_write32(rtwdev, 0x1b80, 0x00000006);
1504
1505 rtw_write32(rtwdev, 0x1b00, 0xf8000000);
1506 rtw_write32(rtwdev, 0x1b80, 0x00000002);
1507 }
1508
rtw8814a_iqk_configure_mac(struct rtw_dev * rtwdev)1509 static void rtw8814a_iqk_configure_mac(struct rtw_dev *rtwdev)
1510 {
1511 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
1512 rtw_write32_clr(rtwdev, REG_BCN_CTRL,
1513 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION);
1514
1515 /* RX ante off */
1516 rtw_write8(rtwdev, REG_RXPSEL, 0x00);
1517 /* CCA off */
1518 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xe);
1519 /* CCK RX path off */
1520 rtw_write32_set(rtwdev, REG_PRECTRL, BIT_IQ_WGT);
1521 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
1522 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
1523 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
1524 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
1525 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, BIT_RFE_SELSW0_D, 0x77);
1526 rtw_write32_mask(rtwdev, REG_PSD, BIT_PSD_INI, 0x0);
1527
1528 rtw_write32_mask(rtwdev, REG_RFE_INV0, 0xf, 0x0);
1529 }
1530
rtw8814a_lok_one_shot(struct rtw_dev * rtwdev,u8 path)1531 static void rtw8814a_lok_one_shot(struct rtw_dev *rtwdev, u8 path)
1532 {
1533 u32 lok_temp1, lok_temp2;
1534 bool lok_ready;
1535 u8 ii;
1536
1537 /* ADC Clock source */
1538 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1539 /* LOK: CMD ID = 0
1540 * {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081}
1541 */
1542 rtw_write32(rtwdev, 0x1b00, 0xf8000001 | (BIT(path) << 4));
1543
1544 usleep_range(1000, 1100);
1545
1546 if (read_poll_timeout(!rtw_read32_mask, lok_ready, lok_ready,
1547 1000, 10000, false,
1548 rtwdev, 0x1b00, BIT(0))) {
1549 rtw_dbg(rtwdev, RTW_DBG_RFK, "==>S%d LOK timed out\n", path);
1550
1551 rtw8814a_iqk_reset_nctl(rtwdev);
1552
1553 rtw_write_rf(rtwdev, path, RF_DTXLOK, RFREG_MASK, 0x08400);
1554
1555 return;
1556 }
1557
1558 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1559 rtw_write32(rtwdev, 0x1bd4, 0x003f0001);
1560
1561 lok_temp2 = rtw_read32_mask(rtwdev, 0x1bfc, 0x003e0000);
1562 lok_temp2 = (lok_temp2 + 0x10) & 0x1f;
1563
1564 lok_temp1 = rtw_read32_mask(rtwdev, 0x1bfc, 0x0000003e);
1565 lok_temp1 = (lok_temp1 + 0x10) & 0x1f;
1566
1567 for (ii = 1; ii < 5; ii++) {
1568 lok_temp1 += (lok_temp1 & BIT(4 - ii)) << (ii * 2);
1569 lok_temp2 += (lok_temp2 & BIT(4 - ii)) << (ii * 2);
1570 }
1571
1572 rtw_dbg(rtwdev, RTW_DBG_RFK,
1573 "path %d lok_temp1 = %#x, lok_temp2 = %#x\n",
1574 path, lok_temp1 >> 4, lok_temp2 >> 4);
1575
1576 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0x07c00, lok_temp1 >> 4);
1577 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0xf8000, lok_temp2 >> 4);
1578 }
1579
rtw8814a_iqk_tx_one_shot(struct rtw_dev * rtwdev,u8 path,u32 * tx_matrix,bool * tx_ok)1580 static void rtw8814a_iqk_tx_one_shot(struct rtw_dev *rtwdev, u8 path,
1581 u32 *tx_matrix, bool *tx_ok)
1582 {
1583 u8 bw = rtwdev->hal.current_band_width;
1584 u8 cal_retry;
1585 u32 iqk_cmd;
1586
1587 for (cal_retry = 0; cal_retry < 4; cal_retry++) {
1588 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1589
1590 iqk_cmd = 0xf8000001 | ((bw + 3) << 8) | (BIT(path) << 4);
1591
1592 rtw_dbg(rtwdev, RTW_DBG_RFK, "TXK_Trigger = %#x\n", iqk_cmd);
1593
1594 rtw_write32(rtwdev, 0x1b00, iqk_cmd);
1595
1596 usleep_range(10000, 11000);
1597
1598 if (read_poll_timeout(!rtw_read32_mask, *tx_ok, *tx_ok,
1599 1000, 20000, false,
1600 rtwdev, 0x1b00, BIT(0))) {
1601 rtw_dbg(rtwdev, RTW_DBG_RFK,
1602 "tx iqk S%d timed out\n", path);
1603
1604 rtw8814a_iqk_reset_nctl(rtwdev);
1605 } else {
1606 *tx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
1607
1608 if (*tx_ok)
1609 break;
1610 }
1611 }
1612
1613 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b00 = 0x%x\n",
1614 path, rtw_read32(rtwdev, 0x1b00));
1615 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b08 = 0x%x\n",
1616 path, rtw_read32(rtwdev, 0x1b08));
1617 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> cal_retry = %x\n",
1618 path, cal_retry);
1619
1620 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1621
1622 if (*tx_ok) {
1623 *tx_matrix = rtw_read32(rtwdev, 0x1b38);
1624
1625 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n",
1626 path, *tx_matrix);
1627 }
1628 }
1629
rtw8814a_iqk_rx_one_shot(struct rtw_dev * rtwdev,u8 path,u32 * tx_matrix,bool * tx_ok)1630 static void rtw8814a_iqk_rx_one_shot(struct rtw_dev *rtwdev, u8 path,
1631 u32 *tx_matrix, bool *tx_ok)
1632 {
1633 static const u16 iqk_apply[RTW_RF_PATH_MAX] = {
1634 REG_TXAGCIDX, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D
1635 };
1636 u8 band = rtwdev->hal.current_band_type;
1637 u8 bw = rtwdev->hal.current_band_width;
1638 u32 rx_matrix;
1639 u8 cal_retry;
1640 u32 iqk_cmd;
1641 bool rx_ok;
1642
1643 for (cal_retry = 0; cal_retry < 4; cal_retry++) {
1644 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path);
1645
1646 if (band == RTW_BAND_2G) {
1647 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x1);
1648 rtw_write_rf(rtwdev, path, RF_GAINTX, 0xfffff, 0x51ce1);
1649
1650 switch (path) {
1651 case 0:
1652 case 1:
1653 rtw_write32(rtwdev, REG_RFE_PINMUX_B,
1654 0x54775477);
1655 break;
1656 case 2:
1657 rtw_write32(rtwdev, REG_RFE_PINMUX_C,
1658 0x54775477);
1659 break;
1660 case 3:
1661 rtw_write32(rtwdev, REG_RFE_INVSEL_D, 0x75400000);
1662 rtw_write32(rtwdev, REG_RFE_PINMUX_D,
1663 0x77777777);
1664 break;
1665 }
1666 }
1667
1668 iqk_cmd = 0xf8000001 | ((9 - bw) << 8) | (BIT(path) << 4);
1669
1670 rtw_dbg(rtwdev, RTW_DBG_RFK, "RXK_Trigger = 0x%x\n", iqk_cmd);
1671
1672 rtw_write32(rtwdev, 0x1b00, iqk_cmd);
1673
1674 usleep_range(10000, 11000);
1675
1676 if (read_poll_timeout(!rtw_read32_mask, rx_ok, rx_ok,
1677 1000, 20000, false,
1678 rtwdev, 0x1b00, BIT(0))) {
1679 rtw_dbg(rtwdev, RTW_DBG_RFK,
1680 "rx iqk S%d timed out\n", path);
1681
1682 rtw8814a_iqk_reset_nctl(rtwdev);
1683 } else {
1684 rx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26));
1685
1686 if (rx_ok)
1687 break;
1688 }
1689 }
1690
1691 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b00 = 0x%x\n",
1692 path, rtw_read32(rtwdev, 0x1b00));
1693 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b08 = 0x%x\n",
1694 path, rtw_read32(rtwdev, 0x1b08));
1695 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> cal_retry = %x\n",
1696 path, cal_retry);
1697
1698 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1));
1699
1700 if (rx_ok) {
1701 rtw_write32(rtwdev, 0x1b3c, 0x20000000);
1702 rx_matrix = rtw_read32(rtwdev, 0x1b3c);
1703
1704 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n",
1705 path, rx_matrix);
1706 }
1707
1708 if (*tx_ok)
1709 rtw_write32(rtwdev, 0x1b38, *tx_matrix);
1710 else
1711 rtw_write32_mask(rtwdev, iqk_apply[path], BIT(0), 0x0);
1712
1713 if (!rx_ok)
1714 rtw_write32_mask(rtwdev, iqk_apply[path],
1715 BIT(11) | BIT(10), 0x0);
1716
1717 if (band == RTW_BAND_2G)
1718 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x0);
1719 }
1720
rtw8814a_iqk(struct rtw_dev * rtwdev)1721 static void rtw8814a_iqk(struct rtw_dev *rtwdev)
1722 {
1723 u8 band = rtwdev->hal.current_band_type;
1724 u8 bw = rtwdev->hal.current_band_width;
1725 u32 tx_matrix[RTW_RF_PATH_MAX];
1726 bool tx_ok[RTW_RF_PATH_MAX];
1727 u8 path;
1728
1729 rtw_dbg(rtwdev, RTW_DBG_RFK, "IQK band = %d GHz bw = %d MHz\n",
1730 band == RTW_BAND_2G ? 2 : 5, (1 << (bw + 1)) * 10);
1731
1732 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, BIT(19), 0x1);
1733 rtw_write_rf(rtwdev, RF_PATH_B, RF_TXMOD, BIT(19), 0x1);
1734 rtw_write_rf(rtwdev, RF_PATH_C, RF_TXMOD, BIT(19), 0x1);
1735 rtw_write_rf(rtwdev, RF_PATH_D, RF_TXMOD, BIT(19), 0x1);
1736
1737 rtw_write32_mask(rtwdev, REG_TXAGCIDX,
1738 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1739 rtw_write32_mask(rtwdev, REG_TX_AGC_B,
1740 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1741 rtw_write32_mask(rtwdev, REG_TX_AGC_C,
1742 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1743 rtw_write32_mask(rtwdev, REG_TX_AGC_D,
1744 (BIT(11) | BIT(10) | BIT(0)), 0x401);
1745
1746 if (band == RTW_BAND_5G)
1747 rtw_write32(rtwdev, 0x1b00, 0xf8000ff1);
1748 else
1749 rtw_write32(rtwdev, 0x1b00, 0xf8000ef1);
1750
1751 usleep_range(1000, 1100);
1752
1753 rtw_write32(rtwdev, 0x810, 0x20101063);
1754 rtw_write32(rtwdev, REG_DAC_RSTB, 0x0B00C000);
1755
1756 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1757 rtw8814a_lok_one_shot(rtwdev, path);
1758
1759 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1760 rtw8814a_iqk_tx_one_shot(rtwdev, path,
1761 &tx_matrix[path], &tx_ok[path]);
1762
1763 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++)
1764 rtw8814a_iqk_rx_one_shot(rtwdev, path,
1765 &tx_matrix[path], &tx_ok[path]);
1766 }
1767
rtw8814a_do_iqk(struct rtw_dev * rtwdev)1768 static void rtw8814a_do_iqk(struct rtw_dev *rtwdev)
1769 {
1770 static const u32 backup_mac_reg[MAC_REG_NUM_8814] = {0x520, 0x550};
1771 static const u32 backup_bb_reg[BB_REG_NUM_8814] = {
1772 0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0,
1773 0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910
1774 };
1775 static const u32 backup_rf_reg[RF_REG_NUM_8814] = {0x0};
1776 u32 rf_backup[RF_REG_NUM_8814][RTW_RF_PATH_MAX];
1777 u32 mac_backup[MAC_REG_NUM_8814];
1778 u32 bb_backup[BB_REG_NUM_8814];
1779
1780 rtw8814a_iqk_backup_mac_bb(rtwdev, mac_backup, bb_backup,
1781 backup_mac_reg, backup_bb_reg);
1782 rtw8814a_iqk_afe_setting(rtwdev, true);
1783 rtw8814a_iqk_backup_rf(rtwdev, rf_backup, backup_rf_reg);
1784 rtw8814a_iqk_configure_mac(rtwdev);
1785 rtw8814a_iqk(rtwdev);
1786 rtw8814a_iqk_reset_nctl(rtwdev); /* for 3-wire to BB use */
1787 rtw8814a_iqk_afe_setting(rtwdev, false);
1788 rtw8814a_iqk_restore_mac_bb(rtwdev, mac_backup, bb_backup,
1789 backup_mac_reg, backup_bb_reg);
1790 rtw8814a_iqk_restore_rf(rtwdev, rf_backup, backup_rf_reg);
1791 }
1792
rtw8814a_phy_calibration(struct rtw_dev * rtwdev)1793 static void rtw8814a_phy_calibration(struct rtw_dev *rtwdev)
1794 {
1795 rtw8814a_do_iqk(rtwdev);
1796 }
1797
rtw8814a_coex_cfg_init(struct rtw_dev * rtwdev)1798 static void rtw8814a_coex_cfg_init(struct rtw_dev *rtwdev)
1799 {
1800 }
1801
rtw8814a_coex_cfg_ant_switch(struct rtw_dev * rtwdev,u8 ctrl_type,u8 pos_type)1802 static void rtw8814a_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type,
1803 u8 pos_type)
1804 {
1805 /* Override rtw_coex_coex_ctrl_owner(). RF path C does not
1806 * function when BIT_LTE_MUX_CTRL_PATH is set.
1807 */
1808 rtw_write8_clr(rtwdev, REG_SYS_SDIO_CTRL + 3,
1809 BIT_LTE_MUX_CTRL_PATH >> 24);
1810 }
1811
rtw8814a_coex_cfg_gnt_fix(struct rtw_dev * rtwdev)1812 static void rtw8814a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
1813 {
1814 }
1815
rtw8814a_coex_cfg_gnt_debug(struct rtw_dev * rtwdev)1816 static void rtw8814a_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
1817 {
1818 }
1819
rtw8814a_coex_cfg_rfe_type(struct rtw_dev * rtwdev)1820 static void rtw8814a_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
1821 {
1822 struct rtw_coex *coex = &rtwdev->coex;
1823 struct rtw_coex_rfe *coex_rfe = &coex->rfe;
1824
1825 /* Only needed to make rtw8814a_coex_cfg_ant_switch() run. */
1826 coex_rfe->ant_switch_exist = true;
1827 }
1828
rtw8814a_coex_cfg_wl_tx_power(struct rtw_dev * rtwdev,u8 wl_pwr)1829 static void rtw8814a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
1830 {
1831 }
1832
rtw8814a_coex_cfg_wl_rx_gain(struct rtw_dev * rtwdev,bool low_gain)1833 static void rtw8814a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
1834 {
1835 }
1836
rtw8814a_txagc_swing_offset(struct rtw_dev * rtwdev,u8 path,u8 tx_pwr_idx_offset,s8 * txagc_idx,u8 * swing_idx)1837 static void rtw8814a_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path,
1838 u8 tx_pwr_idx_offset,
1839 s8 *txagc_idx, u8 *swing_idx)
1840 {
1841 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1842 u8 swing_upper_bound = dm_info->default_ofdm_index + 10;
1843 s8 delta_pwr_idx = dm_info->delta_power_index[path];
1844 u8 swing_index = dm_info->default_ofdm_index;
1845 u8 max_tx_pwr_idx_offset = 0xf;
1846 u8 swing_lower_bound = 0;
1847 s8 agc_index = 0;
1848
1849 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset);
1850
1851 if (delta_pwr_idx >= 0) {
1852 if (delta_pwr_idx <= tx_pwr_idx_offset) {
1853 agc_index = delta_pwr_idx;
1854 swing_index = dm_info->default_ofdm_index;
1855 } else if (delta_pwr_idx > tx_pwr_idx_offset) {
1856 agc_index = tx_pwr_idx_offset;
1857 swing_index = dm_info->default_ofdm_index +
1858 delta_pwr_idx - tx_pwr_idx_offset;
1859 swing_index = min_t(u8, swing_index, swing_upper_bound);
1860 }
1861 } else {
1862 if (dm_info->default_ofdm_index > abs(delta_pwr_idx))
1863 swing_index =
1864 dm_info->default_ofdm_index + delta_pwr_idx;
1865 else
1866 swing_index = swing_lower_bound;
1867 swing_index = max_t(u8, swing_index, swing_lower_bound);
1868
1869 agc_index = 0;
1870 }
1871
1872 if (swing_index >= RTW_TXSCALE_SIZE) {
1873 rtw_warn(rtwdev, "swing index overflow\n");
1874 swing_index = RTW_TXSCALE_SIZE - 1;
1875 }
1876 *txagc_idx = agc_index;
1877 *swing_idx = swing_index;
1878 }
1879
rtw8814a_pwrtrack_set_pwr(struct rtw_dev * rtwdev,u8 path,u8 pwr_idx_offset)1880 static void rtw8814a_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path,
1881 u8 pwr_idx_offset)
1882 {
1883 static const u32 txagc_reg[RTW_RF_PATH_MAX] = {
1884 REG_TX_AGC_A, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D
1885 };
1886 static const u32 txscale_reg[RTW_RF_PATH_MAX] = {
1887 REG_TXSCALE_A, REG_TXSCALE_B, REG_TXSCALE_C, REG_TXSCALE_D
1888 };
1889 s8 txagc_idx;
1890 u8 swing_idx;
1891
1892 rtw8814a_txagc_swing_offset(rtwdev, path, pwr_idx_offset,
1893 &txagc_idx, &swing_idx);
1894 rtw_write32_mask(rtwdev, txagc_reg[path], GENMASK(29, 25),
1895 txagc_idx);
1896 rtw_write32_mask(rtwdev, txscale_reg[path], BB_SWING_MASK,
1897 rtw8814a_txscale_tbl[swing_idx]);
1898 }
1899
rtw8814a_pwrtrack_set(struct rtw_dev * rtwdev,u8 path)1900 static void rtw8814a_pwrtrack_set(struct rtw_dev *rtwdev, u8 path)
1901 {
1902 u8 max_pwr_idx = rtwdev->chip->max_power_index;
1903 u8 band_width = rtwdev->hal.current_band_width;
1904 u8 channel = rtwdev->hal.current_channel;
1905 u8 tx_rate = rtwdev->dm_info.tx_rate;
1906 u8 regd = rtw_regd_get(rtwdev);
1907 u8 pwr_idx_offset, tx_pwr_idx;
1908
1909 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate,
1910 band_width, channel, regd);
1911
1912 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx);
1913
1914 pwr_idx_offset = max_pwr_idx - tx_pwr_idx;
1915
1916 rtw8814a_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset);
1917 }
1918
rtw8814a_phy_pwrtrack_path(struct rtw_dev * rtwdev,struct rtw_swing_table * swing_table,u8 path)1919 static void rtw8814a_phy_pwrtrack_path(struct rtw_dev *rtwdev,
1920 struct rtw_swing_table *swing_table,
1921 u8 path)
1922 {
1923 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1924 u8 power_idx_cur, power_idx_last;
1925 u8 delta;
1926
1927 /* 8814A only has one thermal meter at PATH A */
1928 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A);
1929
1930 power_idx_last = dm_info->delta_power_index[path];
1931 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table,
1932 path, RF_PATH_A, delta);
1933
1934 /* if delta of power indexes are the same, just skip */
1935 if (power_idx_cur == power_idx_last)
1936 return;
1937
1938 dm_info->delta_power_index[path] = power_idx_cur;
1939 rtw8814a_pwrtrack_set(rtwdev, path);
1940 }
1941
rtw8814a_phy_pwrtrack(struct rtw_dev * rtwdev)1942 static void rtw8814a_phy_pwrtrack(struct rtw_dev *rtwdev)
1943 {
1944 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1945 struct rtw_swing_table swing_table;
1946 u8 thermal_value, path;
1947
1948 rtw_phy_config_swing_table(rtwdev, &swing_table);
1949
1950 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff)
1951 return;
1952
1953 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00);
1954
1955 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A);
1956
1957 if (dm_info->pwr_trk_init_trigger)
1958 dm_info->pwr_trk_init_trigger = false;
1959 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value,
1960 RF_PATH_A))
1961 goto iqk;
1962
1963 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++)
1964 rtw8814a_phy_pwrtrack_path(rtwdev, &swing_table, path);
1965
1966 iqk:
1967 if (rtw_phy_pwrtrack_need_iqk(rtwdev))
1968 rtw8814a_do_iqk(rtwdev);
1969 }
1970
rtw8814a_pwr_track(struct rtw_dev * rtwdev)1971 static void rtw8814a_pwr_track(struct rtw_dev *rtwdev)
1972 {
1973 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1974
1975 if (!dm_info->pwr_trk_triggered) {
1976 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER,
1977 GENMASK(17, 16), 0x03);
1978 dm_info->pwr_trk_triggered = true;
1979 return;
1980 }
1981
1982 rtw8814a_phy_pwrtrack(rtwdev);
1983 dm_info->pwr_trk_triggered = false;
1984 }
1985
rtw8814a_phy_cck_pd_set(struct rtw_dev * rtwdev,u8 new_lvl)1986 static void rtw8814a_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl)
1987 {
1988 static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed};
1989 struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1990
1991 /* Override rtw_phy_cck_pd_lv_link(). It implements something
1992 * like type 2/3/4. We need type 1 here.
1993 */
1994 if (rtw_is_assoc(rtwdev)) {
1995 if (dm_info->min_rssi > 60) {
1996 new_lvl = CCK_PD_LV3;
1997 } else if (dm_info->min_rssi > 35) {
1998 new_lvl = CCK_PD_LV2;
1999 } else if (dm_info->min_rssi > 20) {
2000 if (dm_info->cck_fa_avg > 500)
2001 new_lvl = CCK_PD_LV2;
2002 else if (dm_info->cck_fa_avg < 250)
2003 new_lvl = CCK_PD_LV1;
2004 else
2005 return;
2006 } else {
2007 new_lvl = CCK_PD_LV1;
2008 }
2009 }
2010
2011 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n",
2012 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl);
2013
2014 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl)
2015 return;
2016
2017 dm_info->cck_fa_avg = CCK_FA_AVG_RESET;
2018 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl;
2019
2020 rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]);
2021 }
2022
rtw8814a_led_set(struct led_classdev * led,enum led_brightness brightness)2023 static void rtw8814a_led_set(struct led_classdev *led,
2024 enum led_brightness brightness)
2025 {
2026 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev);
2027 u32 led_gpio_cfg;
2028
2029 led_gpio_cfg = rtw_read32(rtwdev, REG_GPIO_PIN_CTRL_2);
2030 led_gpio_cfg |= BIT(16) | BIT(17) | BIT(21) | BIT(22);
2031
2032 if (brightness == LED_OFF) {
2033 led_gpio_cfg |= BIT(8) | BIT(9) | BIT(13) | BIT(14);
2034 } else {
2035 led_gpio_cfg &= ~(BIT(8) | BIT(9) | BIT(13) | BIT(14));
2036 led_gpio_cfg &= ~(BIT(0) | BIT(1) | BIT(5) | BIT(6));
2037 }
2038
2039 rtw_write32(rtwdev, REG_GPIO_PIN_CTRL_2, led_gpio_cfg);
2040 }
2041
rtw8814a_fill_txdesc_checksum(struct rtw_dev * rtwdev,struct rtw_tx_pkt_info * pkt_info,u8 * txdesc)2042 static void rtw8814a_fill_txdesc_checksum(struct rtw_dev *rtwdev,
2043 struct rtw_tx_pkt_info *pkt_info,
2044 u8 *txdesc)
2045 {
2046 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */
2047
2048 fill_txdesc_checksum_common(txdesc, words);
2049 }
2050
2051 static const struct rtw_chip_ops rtw8814a_ops = {
2052 .power_on = rtw_power_on,
2053 .power_off = rtw_power_off,
2054 .phy_set_param = rtw8814a_phy_set_param,
2055 .read_efuse = rtw8814a_read_efuse,
2056 .query_phy_status = rtw8814a_query_phy_status,
2057 .set_channel = rtw8814a_set_channel,
2058 .mac_init = rtw8814a_mac_init,
2059 .mac_postinit = NULL,
2060 .read_rf = rtw_phy_read_rf,
2061 .write_rf = rtw_phy_write_rf_reg_sipi,
2062 .set_tx_power_index = rtw8814a_set_tx_power_index,
2063 .set_antenna = NULL,
2064 .cfg_ldo25 = rtw8814a_cfg_ldo25,
2065 .efuse_grant = rtw8814a_efuse_grant,
2066 .set_ampdu_factor = rtw8814a_set_ampdu_factor,
2067 .false_alarm_statistics = rtw8814a_false_alarm_statistics,
2068 .phy_calibration = rtw8814a_phy_calibration,
2069 .cck_pd_set = rtw8814a_phy_cck_pd_set,
2070 .pwr_track = rtw8814a_pwr_track,
2071 .config_bfee = NULL,
2072 .set_gid_table = NULL,
2073 .cfg_csi_rate = NULL,
2074 .led_set = rtw8814a_led_set,
2075 .fill_txdesc_checksum = rtw8814a_fill_txdesc_checksum,
2076
2077 .coex_set_init = rtw8814a_coex_cfg_init,
2078 .coex_set_ant_switch = rtw8814a_coex_cfg_ant_switch,
2079 .coex_set_gnt_fix = rtw8814a_coex_cfg_gnt_fix,
2080 .coex_set_gnt_debug = rtw8814a_coex_cfg_gnt_debug,
2081 .coex_set_rfe_type = rtw8814a_coex_cfg_rfe_type,
2082 .coex_set_wl_tx_power = rtw8814a_coex_cfg_wl_tx_power,
2083 .coex_set_wl_rx_gain = rtw8814a_coex_cfg_wl_rx_gain,
2084 };
2085
2086 static const struct rtw_rqpn rqpn_table_8814a[] = {
2087 /* SDIO */
2088 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, /* vo vi */
2089 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, /* be bk */
2090 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, /* mg hi */
2091 /* PCIE */
2092 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2093 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2094 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2095 /* USB, 2 bulk out */
2096 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH,
2097 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL,
2098 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2099 /* USB, 3 bulk out */
2100 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2101 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2102 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2103 /* USB, 4 bulk out */
2104 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL,
2105 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW,
2106 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH},
2107 };
2108
2109 static const struct rtw_prioq_addrs prioq_addrs_8814a = {
2110 .prio[RTW_DMA_MAPPING_EXTRA] = {
2111 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2,
2112 },
2113 .prio[RTW_DMA_MAPPING_LOW] = {
2114 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2,
2115 },
2116 .prio[RTW_DMA_MAPPING_NORMAL] = {
2117 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2,
2118 },
2119 .prio[RTW_DMA_MAPPING_HIGH] = {
2120 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2,
2121 },
2122 .wsize = true,
2123 };
2124
2125 static const struct rtw_page_table page_table_8814a[] = {
2126 /* SDIO */
2127 {0, 0, 0, 0, 0}, /* hq nq lq exq gapq */
2128 /* PCIE */
2129 {32, 32, 32, 32, 0},
2130 /* USB, 2 bulk out */
2131 {32, 32, 32, 32, 0},
2132 /* USB, 3 bulk out */
2133 {32, 32, 32, 32, 0},
2134 /* USB, 4 bulk out */
2135 {32, 32, 32, 32, 0},
2136 };
2137
2138 static const struct rtw_intf_phy_para_table phy_para_table_8814a = {};
2139
2140 static const struct rtw_hw_reg rtw8814a_dig[] = {
2141 [0] = { .addr = 0xc50, .mask = 0x7f },
2142 [1] = { .addr = 0xe50, .mask = 0x7f },
2143 [2] = { .addr = 0x1850, .mask = 0x7f },
2144 [3] = { .addr = 0x1a50, .mask = 0x7f },
2145 };
2146
2147 static const struct rtw_rfe_def rtw8814a_rfe_defs[] = {
2148 [0] = { .phy_pg_tbl = &rtw8814a_bb_pg_type0_tbl,
2149 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type0_tbl,
2150 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_type0_tbl },
2151 [1] = { .phy_pg_tbl = &rtw8814a_bb_pg_tbl,
2152 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type1_tbl,
2153 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_tbl },
2154 };
2155
2156 /* rssi in percentage % (dbm = % - 100) */
2157 static const u8 wl_rssi_step_8814a[] = {60, 50, 44, 30};
2158 static const u8 bt_rssi_step_8814a[] = {30, 30, 30, 30};
2159
2160 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */
2161 static const struct coex_rf_para rf_para_tx_8814a[] = {
2162 {0, 0, false, 7}, /* for normal */
2163 {0, 16, false, 7}, /* for WL-CPT */
2164 {4, 0, true, 1},
2165 {3, 6, true, 1},
2166 {2, 9, true, 1},
2167 {1, 13, true, 1}
2168 };
2169
2170 static const struct coex_rf_para rf_para_rx_8814a[] = {
2171 {0, 0, false, 7}, /* for normal */
2172 {0, 16, false, 7}, /* for WL-CPT */
2173 {4, 0, true, 1},
2174 {3, 6, true, 1},
2175 {2, 9, true, 1},
2176 {1, 13, true, 1}
2177 };
2178
2179 static_assert(ARRAY_SIZE(rf_para_tx_8814a) == ARRAY_SIZE(rf_para_rx_8814a));
2180
2181 const struct rtw_chip_info rtw8814a_hw_spec = {
2182 .ops = &rtw8814a_ops,
2183 .id = RTW_CHIP_TYPE_8814A,
2184 .fw_name = "rtw88/rtw8814a_fw.bin",
2185 .wlan_cpu = RTW_WCPU_3081,
2186 .tx_pkt_desc_sz = 40,
2187 .tx_buf_desc_sz = 16,
2188 .rx_pkt_desc_sz = 24,
2189 .rx_buf_desc_sz = 8,
2190 .phy_efuse_size = 1024,
2191 .log_efuse_size = 512,
2192 .ptct_efuse_size = 0,
2193 .txff_size = (2048 - 10) * TX_PAGE_SIZE,
2194 .rxff_size = 23552,
2195 .rsvd_drv_pg_num = 8,
2196 .band = RTW_BAND_2G | RTW_BAND_5G,
2197 .page_size = TX_PAGE_SIZE,
2198 .csi_buf_pg_num = 0,
2199 .dig_min = 0x1c,
2200 .txgi_factor = 1,
2201 .is_pwr_by_rate_dec = true,
2202 .rx_ldpc = true,
2203 .max_power_index = 0x3f,
2204 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2,
2205 .amsdu_in_ampdu = false, /* RX speed is better without AMSDU */
2206 .usb_tx_agg_desc_num = 3,
2207 .hw_feature_report = false,
2208 .c2h_ra_report_size = 6,
2209 .old_datarate_fb_limit = false,
2210 .ht_supported = true,
2211 .vht_supported = true,
2212 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),
2213 .sys_func_en = 0xDC,
2214 .pwr_on_seq = card_enable_flow_8814a,
2215 .pwr_off_seq = card_disable_flow_8814a,
2216 .rqpn_table = rqpn_table_8814a,
2217 .prioq_addrs = &prioq_addrs_8814a,
2218 .page_table = page_table_8814a,
2219 .intf_table = &phy_para_table_8814a,
2220 .dig = rtw8814a_dig,
2221 .dig_cck = NULL,
2222 .rf_base_addr = {0x2800, 0x2c00, 0x3800, 0x3c00},
2223 .rf_sipi_addr = {0xc90, 0xe90, 0x1890, 0x1a90},
2224 .ltecoex_addr = NULL,
2225 .mac_tbl = &rtw8814a_mac_tbl,
2226 .agc_tbl = &rtw8814a_agc_tbl,
2227 .bb_tbl = &rtw8814a_bb_tbl,
2228 .rf_tbl = {&rtw8814a_rf_a_tbl, &rtw8814a_rf_b_tbl,
2229 &rtw8814a_rf_c_tbl, &rtw8814a_rf_d_tbl},
2230 .rfe_defs = rtw8814a_rfe_defs,
2231 .rfe_defs_size = ARRAY_SIZE(rtw8814a_rfe_defs),
2232 .iqk_threshold = 8,
2233 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN,
2234
2235 .coex_para_ver = 0,
2236 .bt_desired_ver = 0,
2237 .scbd_support = false,
2238 .new_scbd10_def = false,
2239 .ble_hid_profile_support = false,
2240 .wl_mimo_ps_support = false,
2241 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF,
2242 .bt_rssi_type = COEX_BTRSSI_RATIO,
2243 .ant_isolation = 15,
2244 .rssi_tolerance = 2,
2245 .wl_rssi_step = wl_rssi_step_8814a,
2246 .bt_rssi_step = bt_rssi_step_8814a,
2247 .table_sant_num = 0,
2248 .table_sant = NULL,
2249 .table_nsant_num = 0,
2250 .table_nsant = NULL,
2251 .tdma_sant_num = 0,
2252 .tdma_sant = NULL,
2253 .tdma_nsant_num = 0,
2254 .tdma_nsant = NULL,
2255 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8814a),
2256 .wl_rf_para_tx = rf_para_tx_8814a,
2257 .wl_rf_para_rx = rf_para_rx_8814a,
2258 .bt_afh_span_bw20 = 0x24,
2259 .bt_afh_span_bw40 = 0x36,
2260 .afh_5g_num = 0,
2261 .afh_5g = NULL,
2262 .coex_info_hw_regs_num = 0,
2263 .coex_info_hw_regs = NULL,
2264 };
2265 EXPORT_SYMBOL(rtw8814a_hw_spec);
2266
2267 MODULE_FIRMWARE("rtw88/rtw8814a_fw.bin");
2268
2269 MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>");
2270 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8814a driver");
2271 MODULE_LICENSE("Dual BSD/GPL");
2272