1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,glymur-camcc.h> 7#include <dt-bindings/clock/qcom,glymur-dispcc.h> 8#include <dt-bindings/clock/qcom,glymur-evacc.h> 9#include <dt-bindings/clock/qcom,glymur-gcc.h> 10#include <dt-bindings/clock/qcom,glymur-gpucc.h> 11#include <dt-bindings/clock/qcom,glymur-tcsr.h> 12#include <dt-bindings/clock/qcom,glymur-videocc.h> 13#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/firmware/qcom,scm.h> 17#include <dt-bindings/gpio/gpio.h> 18#include <dt-bindings/interconnect/qcom,icc.h> 19#include <dt-bindings/interconnect/qcom,glymur-rpmh.h> 20#include <dt-bindings/interrupt-controller/arm-gic.h> 21#include <dt-bindings/mailbox/qcom-ipcc.h> 22#include <dt-bindings/phy/phy-qcom-qmp.h> 23#include <dt-bindings/power/qcom,rpmhpd.h> 24#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 25#include <dt-bindings/soc/qcom,gpr.h> 26#include <dt-bindings/soc/qcom,rpmh-rsc.h> 27#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 28#include <dt-bindings/spmi/spmi.h> 29#include <dt-bindings/thermal/thermal.h> 30 31#include "glymur-ipcc.h" 32 33/ { 34 interrupt-parent = <&intc>; 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "qcom,oryon-2-2"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 capacity-dmips-mhz = <1024>; 48 power-domains = <&cpu_pd0>, <&scmi_perf 0>; 49 power-domain-names = "psci", "perf"; 50 next-level-cache = <&l2_0>; 51 #cooling-cells = <2>; 52 53 l2_0: l2-cache { 54 compatible = "cache"; 55 cache-level = <2>; 56 cache-unified; 57 }; 58 }; 59 60 cpu1: cpu@100 { 61 device_type = "cpu"; 62 compatible = "qcom,oryon-2-2"; 63 reg = <0x0 0x100>; 64 enable-method = "psci"; 65 capacity-dmips-mhz = <1024>; 66 power-domains = <&cpu_pd1>, <&scmi_perf 0>; 67 power-domain-names = "psci", "perf"; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu2: cpu@200 { 73 device_type = "cpu"; 74 compatible = "qcom,oryon-2-2"; 75 reg = <0x0 0x200>; 76 enable-method = "psci"; 77 capacity-dmips-mhz = <1024>; 78 power-domains = <&cpu_pd2>, <&scmi_perf 0>; 79 power-domain-names = "psci", "perf"; 80 next-level-cache = <&l2_0>; 81 #cooling-cells = <2>; 82 }; 83 84 cpu3: cpu@300 { 85 device_type = "cpu"; 86 compatible = "qcom,oryon-2-2"; 87 reg = <0x0 0x300>; 88 enable-method = "psci"; 89 capacity-dmips-mhz = <1024>; 90 power-domains = <&cpu_pd3>, <&scmi_perf 0>; 91 power-domain-names = "psci", "perf"; 92 next-level-cache = <&l2_0>; 93 #cooling-cells = <2>; 94 }; 95 96 cpu4: cpu@400 { 97 device_type = "cpu"; 98 compatible = "qcom,oryon-2-2"; 99 reg = <0x0 0x400>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <1024>; 102 power-domains = <&cpu_pd4>, <&scmi_perf 0>; 103 power-domain-names = "psci", "perf"; 104 next-level-cache = <&l2_0>; 105 #cooling-cells = <2>; 106 }; 107 108 cpu5: cpu@500 { 109 device_type = "cpu"; 110 compatible = "qcom,oryon-2-2"; 111 reg = <0x0 0x500>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <1024>; 114 power-domains = <&cpu_pd5>, <&scmi_perf 0>; 115 power-domain-names = "psci", "perf"; 116 next-level-cache = <&l2_0>; 117 #cooling-cells = <2>; 118 }; 119 120 cpu6: cpu@10000 { 121 device_type = "cpu"; 122 compatible = "qcom,oryon-2-1"; 123 reg = <0x0 0x10000>; 124 enable-method = "psci"; 125 capacity-dmips-mhz = <1372>; 126 power-domains = <&cpu_pd6>, <&scmi_perf 1>; 127 power-domain-names = "psci", "perf"; 128 next-level-cache = <&l2_1>; 129 #cooling-cells = <2>; 130 131 l2_1: l2-cache { 132 compatible = "cache"; 133 cache-level = <2>; 134 cache-unified; 135 }; 136 }; 137 138 cpu7: cpu@10100 { 139 device_type = "cpu"; 140 compatible = "qcom,oryon-2-1"; 141 reg = <0x0 0x10100>; 142 enable-method = "psci"; 143 capacity-dmips-mhz = <1372>; 144 power-domains = <&cpu_pd7>, <&scmi_perf 1>; 145 power-domain-names = "psci", "perf"; 146 next-level-cache = <&l2_1>; 147 #cooling-cells = <2>; 148 }; 149 150 cpu8: cpu@10200 { 151 device_type = "cpu"; 152 compatible = "qcom,oryon-2-1"; 153 reg = <0x0 0x10200>; 154 enable-method = "psci"; 155 capacity-dmips-mhz = <1372>; 156 power-domains = <&cpu_pd8>, <&scmi_perf 1>; 157 power-domain-names = "psci", "perf"; 158 next-level-cache = <&l2_1>; 159 #cooling-cells = <2>; 160 }; 161 162 cpu9: cpu@10300 { 163 device_type = "cpu"; 164 compatible = "qcom,oryon-2-1"; 165 reg = <0x0 0x10300>; 166 enable-method = "psci"; 167 capacity-dmips-mhz = <1372>; 168 power-domains = <&cpu_pd9>, <&scmi_perf 1>; 169 power-domain-names = "psci", "perf"; 170 next-level-cache = <&l2_1>; 171 #cooling-cells = <2>; 172 }; 173 174 cpu10: cpu@10400 { 175 device_type = "cpu"; 176 compatible = "qcom,oryon-2-1"; 177 reg = <0x0 0x10400>; 178 enable-method = "psci"; 179 capacity-dmips-mhz = <1372>; 180 power-domains = <&cpu_pd10>, <&scmi_perf 1>; 181 power-domain-names = "psci", "perf"; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu11: cpu@10500 { 187 device_type = "cpu"; 188 compatible = "qcom,oryon-2-1"; 189 reg = <0x0 0x10500>; 190 enable-method = "psci"; 191 capacity-dmips-mhz = <1372>; 192 power-domains = <&cpu_pd11>, <&scmi_perf 1>; 193 power-domain-names = "psci", "perf"; 194 next-level-cache = <&l2_1>; 195 #cooling-cells = <2>; 196 }; 197 198 cpu12: cpu@20000 { 199 device_type = "cpu"; 200 compatible = "qcom,oryon-2-1"; 201 reg = <0x0 0x20000>; 202 enable-method = "psci"; 203 capacity-dmips-mhz = <1372>; 204 power-domains = <&cpu_pd12>, <&scmi_perf 2>; 205 power-domain-names = "psci", "perf"; 206 next-level-cache = <&l2_2>; 207 #cooling-cells = <2>; 208 209 l2_2: l2-cache { 210 compatible = "cache"; 211 cache-level = <2>; 212 cache-unified; 213 }; 214 }; 215 216 cpu13: cpu@20100 { 217 device_type = "cpu"; 218 compatible = "qcom,oryon-2-1"; 219 reg = <0x0 0x20100>; 220 enable-method = "psci"; 221 capacity-dmips-mhz = <1372>; 222 power-domains = <&cpu_pd13>, <&scmi_perf 2>; 223 power-domain-names = "psci", "perf"; 224 next-level-cache = <&l2_2>; 225 #cooling-cells = <2>; 226 }; 227 228 cpu14: cpu@20200 { 229 device_type = "cpu"; 230 compatible = "qcom,oryon-2-1"; 231 reg = <0x0 0x20200>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1372>; 234 power-domains = <&cpu_pd14>, <&scmi_perf 2>; 235 power-domain-names = "psci", "perf"; 236 next-level-cache = <&l2_2>; 237 #cooling-cells = <2>; 238 }; 239 240 cpu15: cpu@20300 { 241 device_type = "cpu"; 242 compatible = "qcom,oryon-2-1"; 243 reg = <0x0 0x20300>; 244 enable-method = "psci"; 245 capacity-dmips-mhz = <1372>; 246 power-domains = <&cpu_pd15>, <&scmi_perf 2>; 247 power-domain-names = "psci", "perf"; 248 next-level-cache = <&l2_2>; 249 #cooling-cells = <2>; 250 }; 251 252 cpu16: cpu@20400 { 253 device_type = "cpu"; 254 compatible = "qcom,oryon-2-1"; 255 reg = <0x0 0x20400>; 256 enable-method = "psci"; 257 capacity-dmips-mhz = <1372>; 258 power-domains = <&cpu_pd16>, <&scmi_perf 2>; 259 power-domain-names = "psci", "perf"; 260 next-level-cache = <&l2_2>; 261 #cooling-cells = <2>; 262 }; 263 264 cpu17: cpu@20500 { 265 device_type = "cpu"; 266 compatible = "qcom,oryon-2-1"; 267 reg = <0x0 0x20500>; 268 enable-method = "psci"; 269 capacity-dmips-mhz = <1372>; 270 power-domains = <&cpu_pd17>, <&scmi_perf 2>; 271 power-domain-names = "psci", "perf"; 272 next-level-cache = <&l2_2>; 273 #cooling-cells = <2>; 274 }; 275 276 cpu-map { 277 cluster0 { 278 core0 { 279 cpu = <&cpu0>; 280 }; 281 282 core1 { 283 cpu = <&cpu1>; 284 }; 285 286 core2 { 287 cpu = <&cpu2>; 288 }; 289 290 core3 { 291 cpu = <&cpu3>; 292 }; 293 294 core4 { 295 cpu = <&cpu4>; 296 }; 297 298 core5 { 299 cpu = <&cpu5>; 300 }; 301 }; 302 303 cluster1 { 304 core0 { 305 cpu = <&cpu6>; 306 }; 307 308 core1 { 309 cpu = <&cpu7>; 310 }; 311 312 core2 { 313 cpu = <&cpu8>; 314 }; 315 316 core3 { 317 cpu = <&cpu9>; 318 }; 319 320 core4 { 321 cpu = <&cpu10>; 322 }; 323 324 core5 { 325 cpu = <&cpu11>; 326 }; 327 }; 328 329 cpu_map_cluster2: cluster2 { 330 core0 { 331 cpu = <&cpu12>; 332 }; 333 334 core1 { 335 cpu = <&cpu13>; 336 }; 337 338 core2 { 339 cpu = <&cpu14>; 340 }; 341 342 core3 { 343 cpu = <&cpu15>; 344 }; 345 346 core4 { 347 cpu = <&cpu16>; 348 }; 349 350 core5 { 351 cpu = <&cpu17>; 352 }; 353 }; 354 }; 355 356 idle-states { 357 entry-method = "psci"; 358 359 cpu_c4: cpu-sleep-0 { 360 compatible = "arm,idle-state"; 361 idle-state-name = "ret"; 362 arm,psci-suspend-param = <0x00000004>; 363 entry-latency-us = <180>; 364 exit-latency-us = <320>; 365 min-residency-us = <1000>; 366 }; 367 }; 368 369 domain-idle-states { 370 cluster_cl5: cluster-sleep-0 { 371 compatible = "domain-idle-state"; 372 arm,psci-suspend-param = <0x01000054>; 373 entry-latency-us = <2000>; 374 exit-latency-us = <2000>; 375 min-residency-us = <9000>; 376 }; 377 378 domain_ss3: domain-sleep-0 { 379 compatible = "domain-idle-state"; 380 arm,psci-suspend-param = <0x0200c354>; 381 entry-latency-us = <2800>; 382 exit-latency-us = <4400>; 383 min-residency-us = <10150>; 384 }; 385 }; 386 }; 387 388 dummy-sink { 389 compatible = "arm,coresight-dummy-sink"; 390 391 in-ports { 392 port { 393 eud_in: endpoint { 394 remote-endpoint = <&swao_rep_out1>; 395 }; 396 }; 397 }; 398 }; 399 400 firmware { 401 scm: scm { 402 compatible = "qcom,scm-glymur", "qcom,scm"; 403 qcom,dload-mode = <&tcsr 0x4000>; 404 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 405 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 406 }; 407 408 scmi { 409 compatible = "arm,scmi"; 410 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 411 mbox-names = "tx", "rx"; 412 shmem = <&cpu_scp_lpri1>, <&cpu_scp_lpri0>; 413 414 #address-cells = <1>; 415 #size-cells = <0>; 416 417 scmi_perf: protocol@13 { 418 reg = <0x13>; 419 #power-domain-cells = <1>; 420 }; 421 }; 422 }; 423 424 clk_virt: interconnect-0 { 425 compatible = "qcom,glymur-clk-virt"; 426 #interconnect-cells = <2>; 427 qcom,bcm-voters = <&apps_bcm_voter>; 428 }; 429 430 mc_virt: interconnect-1 { 431 compatible = "qcom,glymur-mc-virt"; 432 #interconnect-cells = <2>; 433 qcom,bcm-voters = <&apps_bcm_voter>; 434 }; 435 436 pmu { 437 compatible = "arm,armv8-pmuv3"; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 445 cpu_pd0: power-domain-cpu0 { 446 #power-domain-cells = <0>; 447 power-domains = <&cluster0_pd>; 448 domain-idle-states = <&cpu_c4>; 449 }; 450 451 cpu_pd1: power-domain-cpu1 { 452 #power-domain-cells = <0>; 453 power-domains = <&cluster0_pd>; 454 domain-idle-states = <&cpu_c4>; 455 }; 456 457 cpu_pd2: power-domain-cpu2 { 458 #power-domain-cells = <0>; 459 power-domains = <&cluster0_pd>; 460 domain-idle-states = <&cpu_c4>; 461 }; 462 463 cpu_pd3: power-domain-cpu3 { 464 #power-domain-cells = <0>; 465 power-domains = <&cluster0_pd>; 466 domain-idle-states = <&cpu_c4>; 467 }; 468 469 cpu_pd4: power-domain-cpu4 { 470 #power-domain-cells = <0>; 471 power-domains = <&cluster0_pd>; 472 domain-idle-states = <&cpu_c4>; 473 }; 474 475 cpu_pd5: power-domain-cpu5 { 476 #power-domain-cells = <0>; 477 power-domains = <&cluster0_pd>; 478 domain-idle-states = <&cpu_c4>; 479 }; 480 481 cpu_pd6: power-domain-cpu6 { 482 #power-domain-cells = <0>; 483 power-domains = <&cluster1_pd>; 484 domain-idle-states = <&cpu_c4>; 485 }; 486 487 cpu_pd7: power-domain-cpu7 { 488 #power-domain-cells = <0>; 489 power-domains = <&cluster1_pd>; 490 domain-idle-states = <&cpu_c4>; 491 }; 492 493 cpu_pd8: power-domain-cpu8 { 494 #power-domain-cells = <0>; 495 power-domains = <&cluster1_pd>; 496 domain-idle-states = <&cpu_c4>; 497 }; 498 499 cpu_pd9: power-domain-cpu9 { 500 #power-domain-cells = <0>; 501 power-domains = <&cluster1_pd>; 502 domain-idle-states = <&cpu_c4>; 503 }; 504 505 cpu_pd10: power-domain-cpu10 { 506 #power-domain-cells = <0>; 507 power-domains = <&cluster1_pd>; 508 domain-idle-states = <&cpu_c4>; 509 }; 510 511 cpu_pd11: power-domain-cpu11 { 512 #power-domain-cells = <0>; 513 power-domains = <&cluster1_pd>; 514 domain-idle-states = <&cpu_c4>; 515 }; 516 517 cpu_pd12: power-domain-cpu12 { 518 #power-domain-cells = <0>; 519 power-domains = <&cluster2_pd>; 520 domain-idle-states = <&cpu_c4>; 521 }; 522 523 cpu_pd13: power-domain-cpu13 { 524 #power-domain-cells = <0>; 525 power-domains = <&cluster2_pd>; 526 domain-idle-states = <&cpu_c4>; 527 }; 528 529 cpu_pd14: power-domain-cpu14 { 530 #power-domain-cells = <0>; 531 power-domains = <&cluster2_pd>; 532 domain-idle-states = <&cpu_c4>; 533 }; 534 535 cpu_pd15: power-domain-cpu15 { 536 #power-domain-cells = <0>; 537 power-domains = <&cluster2_pd>; 538 domain-idle-states = <&cpu_c4>; 539 }; 540 541 cpu_pd16: power-domain-cpu16 { 542 #power-domain-cells = <0>; 543 power-domains = <&cluster2_pd>; 544 domain-idle-states = <&cpu_c4>; 545 }; 546 547 cpu_pd17: power-domain-cpu17 { 548 #power-domain-cells = <0>; 549 power-domains = <&cluster2_pd>; 550 domain-idle-states = <&cpu_c4>; 551 }; 552 553 cluster0_pd: power-domain-cpu-cluster0 { 554 #power-domain-cells = <0>; 555 power-domains = <&system_pd>; 556 domain-idle-states = <&cluster_cl5>; 557 }; 558 559 cluster1_pd: power-domain-cpu-cluster1 { 560 #power-domain-cells = <0>; 561 power-domains = <&system_pd>; 562 domain-idle-states = <&cluster_cl5>; 563 }; 564 565 cluster2_pd: power-domain-cpu-cluster2 { 566 #power-domain-cells = <0>; 567 power-domains = <&system_pd>; 568 domain-idle-states = <&cluster_cl5>; 569 }; 570 571 system_pd: power-domain-system { 572 #power-domain-cells = <0>; 573 domain-idle-states = <&domain_ss3>; 574 }; 575 }; 576 577 reserved-memory { 578 #address-cells = <2>; 579 #size-cells = <2>; 580 ranges; 581 582 pdp_mem: pdp@81400000 { 583 reg = <0x0 0x81400000 0x0 0x100000>; 584 no-map; 585 }; 586 587 aop_cmd_db_mem: aop-cmd-db@81c60000 { 588 compatible = "qcom,cmd-db"; 589 reg = <0x0 0x81c60000 0x0 0x20000>; 590 no-map; 591 }; 592 593 pdp_ns_shared_mem: pdp-ns-shared@81e00000 { 594 reg = <0x0 0x81e00000 0x0 0x200000>; 595 no-map; 596 }; 597 598 oobdaretag_mem: oobdaretag@86e10000 { 599 reg = <0x0 0x86e10000 0x0 0x360000>; 600 no-map; 601 }; 602 603 oob_secure_mem: oob-secure@87170000 { 604 reg = <0x0 0x87170000 0x0 0xbc0000>; 605 no-map; 606 }; 607 608 oobdtbqc_mem: oobdtbqc@87d30000 { 609 reg = <0x0 0x87d30000 0x0 0x20000>; 610 no-map; 611 }; 612 613 oobdtboem_mem: oobdtboem@87d50000 { 614 reg = <0x0 0x87d50000 0x0 0x20000>; 615 no-map; 616 }; 617 618 oob_nonsecure_mem: oob-nonsecure@87e00000 { 619 reg = <0x0 0x87e00000 0x0 0xc00000>; 620 no-map; 621 }; 622 623 spss_region_mem: spss@88a00000 { 624 reg = <0x0 0x88a00000 0x0 0x400000>; 625 no-map; 626 }; 627 628 soccp_mem: soccp@88e00000 { 629 reg = <0x0 0x88e00000 0x0 0x400000>; 630 no-map; 631 }; 632 633 soccpdtb_mem: soccpdtb@89200000 { 634 reg = <0x0 0x89200000 0x0 0x20000>; 635 no-map; 636 }; 637 638 cvp_mem: cvp@89700000 { 639 reg = <0x0 0x89700000 0x0 0x700000>; 640 no-map; 641 }; 642 643 adspslpi_mem: adspslpi@89e00000 { 644 reg = <0x0 0x89e00000 0x0 0x3a00000>; 645 no-map; 646 }; 647 648 q6_adsp_dtb_mem: q6-adsp-dtb@8d800000 { 649 reg = <0x0 0x8d800000 0x0 0x80000>; 650 no-map; 651 }; 652 653 cdsp_mem: cdsp@8d900000 { 654 reg = <0x0 0x8d900000 0x0 0x4000000>; 655 no-map; 656 }; 657 658 q6_cdsp_dtb_mem: q6-cdsp-dtb@91900000 { 659 reg = <0x0 0x91900000 0x0 0x80000>; 660 no-map; 661 }; 662 663 gpu_microcode_mem: gpu-microcode@919fe000 { 664 reg = <0x0 0x919fe000 0x0 0x2000>; 665 no-map; 666 }; 667 668 camera_mem: camera@91a00000 { 669 reg = <0x0 0x91a00000 0x0 0x800000>; 670 no-map; 671 }; 672 673 av1_encoder_mem: av1-encoder@92200000 { 674 reg = <0x0 0x92200000 0x0 0x700000>; 675 no-map; 676 }; 677 678 video_mem: video@92900000 { 679 reg = <0x0 0x92900000 0x0 0xc00000>; 680 no-map; 681 }; 682 683 smem_mem: smem@ffe00000 { 684 compatible = "qcom,smem"; 685 reg = <0x0 0xffe00000 0x0 0x200000>; 686 hwlocks = <&tcsr_mutex 3>; 687 no-map; 688 }; 689 690 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap { 691 compatible = "shared-dma-pool"; 692 alloc-ranges = <0x0 0x80000000 0x0 0x80000000>; 693 reusable; 694 alignment = <0x0 0x400000>; 695 size = <0x0 0x800000>; 696 }; 697 }; 698 699 smp2p-adsp { 700 compatible = "qcom,smp2p"; 701 702 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 703 IPCC_MPROC_SIGNAL_SMP2P 704 IRQ_TYPE_EDGE_RISING>; 705 706 mboxes = <&ipcc IPCC_MPROC_LPASS IPCC_MPROC_SIGNAL_SMP2P>; 707 708 qcom,smem = <443>, <429>; 709 qcom,local-pid = <0>; 710 qcom,remote-pid = <2>; 711 712 smp2p_adsp_out: master-kernel { 713 qcom,entry-name = "master-kernel"; 714 #qcom,smem-state-cells = <1>; 715 }; 716 717 smp2p_adsp_in: slave-kernel { 718 qcom,entry-name = "slave-kernel"; 719 interrupt-controller; 720 #interrupt-cells = <2>; 721 }; 722 }; 723 724 smp2p-cdsp { 725 compatible = "qcom,smp2p"; 726 727 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 728 IPCC_MPROC_SIGNAL_SMP2P 729 IRQ_TYPE_EDGE_RISING>; 730 731 mboxes = <&ipcc IPCC_MPROC_CDSP IPCC_MPROC_SIGNAL_SMP2P>; 732 733 qcom,smem = <94>, <432>; 734 qcom,local-pid = <0>; 735 qcom,remote-pid = <5>; 736 737 smp2p_cdsp_out: master-kernel { 738 qcom,entry-name = "master-kernel"; 739 #qcom,smem-state-cells = <1>; 740 }; 741 742 smp2p_cdsp_in: slave-kernel { 743 qcom,entry-name = "slave-kernel"; 744 interrupt-controller; 745 #interrupt-cells = <2>; 746 }; 747 }; 748 749 smp2p-soccp { 750 compatible = "qcom,smp2p"; 751 752 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 753 IPCC_MPROC_SIGNAL_SMP2P 754 IRQ_TYPE_EDGE_RISING>; 755 756 mboxes = <&ipcc IPCC_MPROC_SOCCP 757 IPCC_MPROC_SIGNAL_SMP2P>; 758 759 qcom,smem = <617>, <616>; 760 qcom,local-pid = <0>; 761 qcom,remote-pid = <19>; 762 763 soccp_smp2p_out: master-kernel { 764 qcom,entry-name = "master-kernel"; 765 #qcom,smem-state-cells = <1>; 766 }; 767 768 soccp_smp2p_in: slave-kernel { 769 qcom,entry-name = "slave-kernel"; 770 interrupt-controller; 771 #interrupt-cells = <2>; 772 }; 773 }; 774 775 soc: soc@0 { 776 compatible = "simple-bus"; 777 #address-cells = <2>; 778 #size-cells = <2>; 779 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 780 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; 781 782 gcc: clock-controller@100000 { 783 compatible = "qcom,glymur-gcc"; 784 reg = <0x0 0x00100000 0x0 0x1f9000>; 785 clocks = <&rpmhcc RPMH_CXO_CLK>, /* Board XO source */ 786 <&rpmhcc RPMH_CXO_CLK_A>, /* Board XO_A source */ 787 <&sleep_clk>, /* Sleep */ 788 <0>, /* USB 0 Phy DP0 GMUX */ 789 <0>, /* USB 0 Phy DP1 GMUX */ 790 <0>, /* USB 0 Phy PCIE PIPEGMUX */ 791 <0>, /* USB 0 Phy PIPEGMUX */ 792 <0>, /* USB 0 Phy SYS PCIE PIPEGMUX */ 793 <0>, /* USB 1 Phy DP0 GMUX 2 */ 794 <0>, /* USB 1 Phy DP1 GMUX 2 */ 795 <0>, /* USB 1 Phy PCIE PIPEGMUX */ 796 <0>, /* USB 1 Phy PIPEGMUX */ 797 <0>, /* USB 1 Phy SYS PCIE PIPEGMUX */ 798 <0>, /* USB 2 Phy DP0 GMUX 2 */ 799 <0>, /* USB 2 Phy DP1 GMUX 2 */ 800 <0>, /* USB 2 Phy PCIE PIPEGMUX */ 801 <0>, /* USB 2 Phy PIPEGMUX */ 802 <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ 803 <&pcie3_phy 0>, /* PCIe 3a pipe */ 804 <&pcie3_phy 1>, /* PCIe 3b pipe */ 805 <&pcie4_phy>, /* PCIe 4 */ 806 <&pcie5_phy>, /* PCIe 5 */ 807 <&pcie6_phy>, /* PCIe 6 */ 808 <0>, /* QUSB4 0 PHY RX 0 */ 809 <0>, /* QUSB4 0 PHY RX 1 */ 810 <0>, /* QUSB4 1 PHY RX 0 */ 811 <0>, /* QUSB4 1 PHY RX 1 */ 812 <0>, /* QUSB4 2 PHY RX 0 */ 813 <0>, /* QUSB4 2 PHY RX 1 */ 814 <0>, /* UFS PHY RX Symbol 0 */ 815 <0>, /* UFS PHY RX Symbol 1 */ 816 <0>, /* UFS PHY TX Symbol 0 */ 817 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 818 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 819 <&usb_2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 820 <&usb_mp_qmpphy0>, /* USB3 UNI PHY pipe 0 */ 821 <&usb_mp_qmpphy1>, /* USB3 UNI PHY pipe 1 */ 822 <0>, /* USB4 PHY 0 pcie pipe */ 823 <0>, /* USB4 PHY 0 Max pipe */ 824 <0>, /* USB4 PHY 1 pcie pipe */ 825 <0>, /* USB4 PHY 1 Max pipe */ 826 <0>, /* USB4 PHY 2 pcie */ 827 <0>; /* USB4 PHY 2 Max */ 828 #clock-cells = <1>; 829 #reset-cells = <1>; 830 #power-domain-cells = <1>; 831 power-domains = <&rpmhpd RPMHPD_CX>; 832 }; 833 834 gpi_dma2: dma-controller@800000 { 835 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 836 reg = <0x0 0x00800000 0x0 0x60000>; 837 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_ESPI 129 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_ESPI 130 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_ESPI 131 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_ESPI 132 IRQ_TYPE_LEVEL_HIGH>; 853 dma-channels = <16>; 854 dma-channel-mask = <0x3f>; 855 #dma-cells = <3>; 856 iommus = <&apps_smmu 0xd76 0x0>; 857 }; 858 859 qupv3_2: geniqup@8c0000 { 860 compatible = "qcom,geni-se-qup"; 861 reg = <0x0 0x008c0000 0x0 0x3000>; 862 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 863 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 864 clock-names = "m-ahb", 865 "s-ahb"; 866 iommus = <&apps_smmu 0xd63 0x0>; 867 #address-cells = <2>; 868 #size-cells = <2>; 869 ranges; 870 871 i2c16: i2c@880000 { 872 compatible = "qcom,geni-i2c"; 873 reg = <0x0 0x00880000 0x0 0x4000>; 874 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 876 clock-names = "se"; 877 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 878 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 879 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 880 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 881 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 882 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 883 interconnect-names = "qup-core", 884 "qup-config", 885 "qup-memory"; 886 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 887 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 888 dma-names = "tx", 889 "rx"; 890 pinctrl-0 = <&qup_i2c16_data_clk>; 891 pinctrl-names = "default"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 status = "disabled"; 896 }; 897 898 spi16: spi@880000 { 899 compatible = "qcom,geni-spi"; 900 reg = <0x0 0x00880000 0x0 0x4000>; 901 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 902 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 903 clock-names = "se"; 904 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 905 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 906 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 907 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 908 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 909 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 910 interconnect-names = "qup-core", 911 "qup-config", 912 "qup-memory"; 913 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 914 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 915 dma-names = "tx", 916 "rx"; 917 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 918 pinctrl-names = "default"; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 922 status = "disabled"; 923 }; 924 925 i2c17: i2c@884000 { 926 compatible = "qcom,geni-i2c"; 927 reg = <0x0 0x00884000 0x0 0x4000>; 928 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 929 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 930 clock-names = "se"; 931 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 932 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 933 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 934 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 935 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 936 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 937 interconnect-names = "qup-core", 938 "qup-config", 939 "qup-memory"; 940 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 941 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 942 dma-names = "tx", 943 "rx"; 944 pinctrl-0 = <&qup_i2c17_data_clk>; 945 pinctrl-names = "default"; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 949 status = "disabled"; 950 }; 951 952 spi17: spi@884000 { 953 compatible = "qcom,geni-spi"; 954 reg = <0x0 0x00884000 0x0 0x4000>; 955 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 957 clock-names = "se"; 958 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 959 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 960 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 961 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 962 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 963 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 964 interconnect-names = "qup-core", 965 "qup-config", 966 "qup-memory"; 967 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 968 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 969 dma-names = "tx", 970 "rx"; 971 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 972 pinctrl-names = "default"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 976 status = "disabled"; 977 }; 978 979 i2c18: i2c@888000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0x0 0x00888000 0x0 0x4000>; 982 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 984 clock-names = "se"; 985 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 986 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 987 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 988 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 989 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 990 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 991 interconnect-names = "qup-core", 992 "qup-config", 993 "qup-memory"; 994 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 995 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 996 dma-names = "tx", 997 "rx"; 998 pinctrl-0 = <&qup_i2c18_data_clk>; 999 pinctrl-names = "default"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 1003 status = "disabled"; 1004 }; 1005 1006 spi18: spi@888000 { 1007 compatible = "qcom,geni-spi"; 1008 reg = <0x0 0x00888000 0x0 0x4000>; 1009 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1011 clock-names = "se"; 1012 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1013 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1014 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1015 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1016 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1017 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1018 interconnect-names = "qup-core", 1019 "qup-config", 1020 "qup-memory"; 1021 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1022 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1023 dma-names = "tx", 1024 "rx"; 1025 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1026 pinctrl-names = "default"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 1030 status = "disabled"; 1031 }; 1032 1033 i2c19: i2c@88c000 { 1034 compatible = "qcom,geni-i2c"; 1035 reg = <0x0 0x0088c000 0x0 0x4000>; 1036 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1037 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1038 clock-names = "se"; 1039 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1040 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1041 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1042 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1043 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1045 interconnect-names = "qup-core", 1046 "qup-config", 1047 "qup-memory"; 1048 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1049 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1050 dma-names = "tx", 1051 "rx"; 1052 pinctrl-0 = <&qup_i2c19_data_clk>; 1053 pinctrl-names = "default"; 1054 #address-cells = <1>; 1055 #size-cells = <0>; 1056 1057 status = "disabled"; 1058 }; 1059 1060 spi19: spi@88c000 { 1061 compatible = "qcom,geni-spi"; 1062 reg = <0x0 0x0088c000 0x0 0x4000>; 1063 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1065 clock-names = "se"; 1066 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1067 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1068 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1069 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1070 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1071 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1072 interconnect-names = "qup-core", 1073 "qup-config", 1074 "qup-memory"; 1075 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1076 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1077 dma-names = "tx", 1078 "rx"; 1079 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1080 pinctrl-names = "default"; 1081 #address-cells = <1>; 1082 #size-cells = <0>; 1083 1084 status = "disabled"; 1085 }; 1086 1087 uart19: serial@88c000 { 1088 compatible = "qcom,geni-uart"; 1089 reg = <0x0 0x0088c000 0x0 0x4000>; 1090 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1091 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1092 clock-names = "se"; 1093 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1094 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1095 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1096 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1097 interconnect-names = "qup-core", 1098 "qup-config"; 1099 pinctrl-0 = <&qup_uart19_default>; 1100 pinctrl-names = "default"; 1101 1102 status = "disabled"; 1103 }; 1104 1105 i2c20: i2c@890000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0x0 0x00890000 0x0 0x4000>; 1108 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1110 clock-names = "se"; 1111 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1112 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1113 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1114 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1115 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1116 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1117 interconnect-names = "qup-core", 1118 "qup-config", 1119 "qup-memory"; 1120 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1121 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1122 dma-names = "tx", 1123 "rx"; 1124 pinctrl-0 = <&qup_i2c20_data_clk>; 1125 pinctrl-names = "default"; 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 1129 status = "disabled"; 1130 }; 1131 1132 spi20: spi@890000 { 1133 compatible = "qcom,geni-spi"; 1134 reg = <0x0 0x00890000 0x0 0x4000>; 1135 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1136 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1137 clock-names = "se"; 1138 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1139 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1140 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1141 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1142 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1143 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1144 interconnect-names = "qup-core", 1145 "qup-config", 1146 "qup-memory"; 1147 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1148 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1149 dma-names = "tx", 1150 "rx"; 1151 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1152 pinctrl-names = "default"; 1153 #address-cells = <1>; 1154 #size-cells = <0>; 1155 1156 status = "disabled"; 1157 }; 1158 1159 i2c21: i2c@894000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0x0 0x00894000 0x0 0x4000>; 1162 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1163 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1164 clock-names = "se"; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1166 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1167 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1168 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1169 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1170 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1175 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1176 dma-names = "tx", 1177 "rx"; 1178 pinctrl-0 = <&qup_i2c21_data_clk>; 1179 pinctrl-names = "default"; 1180 #address-cells = <1>; 1181 #size-cells = <0>; 1182 1183 status = "disabled"; 1184 }; 1185 1186 spi21: spi@894000 { 1187 compatible = "qcom,geni-spi"; 1188 reg = <0x0 0x00894000 0x0 0x4000>; 1189 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1191 clock-names = "se"; 1192 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1193 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1194 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1195 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1196 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1198 interconnect-names = "qup-core", 1199 "qup-config", 1200 "qup-memory"; 1201 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1202 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1203 dma-names = "tx", 1204 "rx"; 1205 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1206 pinctrl-names = "default"; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 1210 status = "disabled"; 1211 }; 1212 1213 uart21: serial@894000 { 1214 compatible = "qcom,geni-debug-uart"; 1215 reg = <0x0 0x00894000 0x0 0x4000>; 1216 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1217 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1218 clock-names = "se"; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1220 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1221 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1222 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1223 interconnect-names = "qup-core", 1224 "qup-config"; 1225 pinctrl-0 = <&qup_uart21_default>; 1226 pinctrl-names = "default"; 1227 }; 1228 1229 i2c22: i2c@898000 { 1230 compatible = "qcom,geni-i2c"; 1231 reg = <0x0 0x00898000 0x0 0x4000>; 1232 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1233 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1234 clock-names = "se"; 1235 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1236 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1237 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1238 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1239 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1240 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "qup-core", 1242 "qup-config", 1243 "qup-memory"; 1244 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1245 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1246 dma-names = "tx", 1247 "rx"; 1248 pinctrl-0 = <&qup_i2c22_data_clk>; 1249 pinctrl-names = "default"; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 1253 status = "disabled"; 1254 }; 1255 1256 spi22: spi@898000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0x0 0x00898000 0x0 0x4000>; 1259 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1261 clock-names = "se"; 1262 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1263 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1264 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1265 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1266 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1267 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1268 interconnect-names = "qup-core", 1269 "qup-config", 1270 "qup-memory"; 1271 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1272 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1273 dma-names = "tx", 1274 "rx"; 1275 pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>; 1276 pinctrl-names = "default"; 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 status = "disabled"; 1281 }; 1282 1283 uart22: serial@898000 { 1284 compatible = "qcom,geni-uart"; 1285 reg = <0x0 0x00898000 0x0 0x4000>; 1286 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1288 clock-names = "se"; 1289 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1290 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1291 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1292 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1293 interconnect-names = "qup-core", 1294 "qup-config"; 1295 pinctrl-0 = <&qup_uart22_default>; 1296 pinctrl-names = "default"; 1297 1298 status = "disabled"; 1299 }; 1300 1301 i2c23: i2c@89c000 { 1302 compatible = "qcom,geni-i2c"; 1303 reg = <0x0 0x0089c000 0x0 0x4000>; 1304 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1305 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1306 clock-names = "se"; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1308 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1309 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1310 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1311 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1312 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1313 interconnect-names = "qup-core", 1314 "qup-config", 1315 "qup-memory"; 1316 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1317 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1318 dma-names = "tx", 1319 "rx"; 1320 pinctrl-0 = <&qup_i2c23_data_clk>; 1321 pinctrl-names = "default"; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 1325 status = "disabled"; 1326 }; 1327 1328 spi23: spi@89c000 { 1329 compatible = "qcom,geni-spi"; 1330 reg = <0x0 0x0089c000 0x0 0x4000>; 1331 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1333 clock-names = "se"; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1336 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1338 <&aggre3_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1339 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1340 interconnect-names = "qup-core", 1341 "qup-config", 1342 "qup-memory"; 1343 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1344 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1345 dma-names = "tx", 1346 "rx"; 1347 pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>; 1348 pinctrl-names = "default"; 1349 #address-cells = <1>; 1350 #size-cells = <0>; 1351 1352 status = "disabled"; 1353 }; 1354 }; 1355 1356 gpi_dma1: dma-controller@a00000 { 1357 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1358 reg = <0x0 0x00a00000 0x0 0x60000>; 1359 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_ESPI 124 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_ESPI 125 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_ESPI 126 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_ESPI 127 IRQ_TYPE_LEVEL_HIGH>; 1375 dma-channels = <16>; 1376 dma-channel-mask = <0x3f>; 1377 #dma-cells = <3>; 1378 iommus = <&apps_smmu 0xcb6 0x0>; 1379 }; 1380 1381 qupv3_1: geniqup@ac0000 { 1382 compatible = "qcom,geni-se-qup"; 1383 reg = <0x0 0x00ac0000 0x0 0x3000>; 1384 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1385 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1386 clock-names = "m-ahb", 1387 "s-ahb"; 1388 iommus = <&apps_smmu 0xca3 0x0>; 1389 #address-cells = <2>; 1390 #size-cells = <2>; 1391 ranges; 1392 1393 i2c8: i2c@a80000 { 1394 compatible = "qcom,geni-i2c"; 1395 reg = <0x0 0x00a80000 0x0 0x4000>; 1396 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1397 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1398 clock-names = "se"; 1399 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1400 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1401 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1402 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1403 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1404 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1405 interconnect-names = "qup-core", 1406 "qup-config", 1407 "qup-memory"; 1408 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1409 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1410 dma-names = "tx", 1411 "rx"; 1412 pinctrl-0 = <&qup_i2c8_data_clk>; 1413 pinctrl-names = "default"; 1414 #address-cells = <1>; 1415 #size-cells = <0>; 1416 1417 status = "disabled"; 1418 }; 1419 1420 spi8: spi@a80000 { 1421 compatible = "qcom,geni-spi"; 1422 reg = <0x0 0x00a80000 0x0 0x4000>; 1423 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1424 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1425 clock-names = "se"; 1426 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1427 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1428 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1429 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1430 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1431 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1432 interconnect-names = "qup-core", 1433 "qup-config", 1434 "qup-memory"; 1435 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1436 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1437 dma-names = "tx", 1438 "rx"; 1439 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1440 pinctrl-names = "default"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 1444 status = "disabled"; 1445 }; 1446 1447 i2c9: i2c@a84000 { 1448 compatible = "qcom,geni-i2c"; 1449 reg = <0x0 0x00a84000 0x0 0x4000>; 1450 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1452 clock-names = "se"; 1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1454 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1455 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1456 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1457 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1458 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1459 interconnect-names = "qup-core", 1460 "qup-config", 1461 "qup-memory"; 1462 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1463 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1464 dma-names = "tx", 1465 "rx"; 1466 pinctrl-0 = <&qup_i2c9_data_clk>; 1467 pinctrl-names = "default"; 1468 #address-cells = <1>; 1469 #size-cells = <0>; 1470 1471 status = "disabled"; 1472 }; 1473 1474 spi9: spi@a84000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0x0 0x00a84000 0x0 0x4000>; 1477 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1479 clock-names = "se"; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1482 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1484 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1485 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1486 interconnect-names = "qup-core", 1487 "qup-config", 1488 "qup-memory"; 1489 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1490 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1491 dma-names = "tx", 1492 "rx"; 1493 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1494 pinctrl-names = "default"; 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 status = "disabled"; 1499 }; 1500 1501 i2c10: i2c@a88000 { 1502 compatible = "qcom,geni-i2c"; 1503 reg = <0x0 0x00a88000 0x0 0x4000>; 1504 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1505 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1506 clock-names = "se"; 1507 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1508 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1509 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1510 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1511 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1512 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1513 interconnect-names = "qup-core", 1514 "qup-config", 1515 "qup-memory"; 1516 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1517 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1518 dma-names = "tx", 1519 "rx"; 1520 pinctrl-0 = <&qup_i2c10_data_clk>; 1521 pinctrl-names = "default"; 1522 #address-cells = <1>; 1523 #size-cells = <0>; 1524 1525 status = "disabled"; 1526 }; 1527 1528 spi10: spi@a88000 { 1529 compatible = "qcom,geni-spi"; 1530 reg = <0x0 0x00a88000 0x0 0x4000>; 1531 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1533 clock-names = "se"; 1534 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1535 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1536 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1537 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1538 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1539 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1540 interconnect-names = "qup-core", 1541 "qup-config", 1542 "qup-memory"; 1543 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1544 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1545 dma-names = "tx", 1546 "rx"; 1547 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1548 pinctrl-names = "default"; 1549 #address-cells = <1>; 1550 #size-cells = <0>; 1551 1552 status = "disabled"; 1553 }; 1554 1555 i2c11: i2c@a8c000 { 1556 compatible = "qcom,geni-i2c"; 1557 reg = <0x0 0x00a8c000 0x0 0x4000>; 1558 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1559 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1560 clock-names = "se"; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1562 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1563 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1564 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1565 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1566 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1567 interconnect-names = "qup-core", 1568 "qup-config", 1569 "qup-memory"; 1570 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1571 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1572 dma-names = "tx", 1573 "rx"; 1574 pinctrl-0 = <&qup_i2c11_data_clk>; 1575 pinctrl-names = "default"; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 1579 status = "disabled"; 1580 }; 1581 1582 spi11: spi@a8c000 { 1583 compatible = "qcom,geni-spi"; 1584 reg = <0x0 0x00a8c000 0x0 0x4000>; 1585 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1586 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1587 clock-names = "se"; 1588 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1589 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1590 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1591 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1592 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1593 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1594 interconnect-names = "qup-core", 1595 "qup-config", 1596 "qup-memory"; 1597 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1598 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1599 dma-names = "tx", 1600 "rx"; 1601 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1602 pinctrl-names = "default"; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 1606 status = "disabled"; 1607 }; 1608 1609 i2c12: i2c@a90000 { 1610 compatible = "qcom,geni-i2c"; 1611 reg = <0x0 0x00a90000 0x0 0x4000>; 1612 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1613 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1614 clock-names = "se"; 1615 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1617 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1619 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1620 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1621 interconnect-names = "qup-core", 1622 "qup-config", 1623 "qup-memory"; 1624 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1625 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1626 dma-names = "tx", 1627 "rx"; 1628 pinctrl-0 = <&qup_i2c12_data_clk>; 1629 pinctrl-names = "default"; 1630 #address-cells = <1>; 1631 #size-cells = <0>; 1632 1633 status = "disabled"; 1634 }; 1635 1636 spi12: spi@a90000 { 1637 compatible = "qcom,geni-spi"; 1638 reg = <0x0 0x00a90000 0x0 0x4000>; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1641 clock-names = "se"; 1642 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1643 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1644 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1645 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1646 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1647 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1648 interconnect-names = "qup-core", 1649 "qup-config", 1650 "qup-memory"; 1651 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1652 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1653 dma-names = "tx", 1654 "rx"; 1655 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1656 pinctrl-names = "default"; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 status = "disabled"; 1661 }; 1662 1663 i2c13: i2c@a94000 { 1664 compatible = "qcom,geni-i2c"; 1665 reg = <0x0 0x00a94000 0x0 0x4000>; 1666 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1667 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1668 clock-names = "se"; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1670 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1671 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1672 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1673 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1674 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1675 interconnect-names = "qup-core", 1676 "qup-config", 1677 "qup-memory"; 1678 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1679 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1680 dma-names = "tx", 1681 "rx"; 1682 pinctrl-0 = <&qup_i2c13_data_clk>; 1683 pinctrl-names = "default"; 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 1687 status = "disabled"; 1688 }; 1689 1690 spi13: spi@a94000 { 1691 compatible = "qcom,geni-spi"; 1692 reg = <0x0 0x00a94000 0x0 0x4000>; 1693 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1694 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1695 clock-names = "se"; 1696 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1697 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1698 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1699 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1700 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1701 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1702 interconnect-names = "qup-core", 1703 "qup-config", 1704 "qup-memory"; 1705 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1706 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1707 dma-names = "tx", 1708 "rx"; 1709 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1710 pinctrl-names = "default"; 1711 #address-cells = <1>; 1712 #size-cells = <0>; 1713 1714 status = "disabled"; 1715 }; 1716 1717 i2c14: i2c@a98000 { 1718 compatible = "qcom,geni-i2c"; 1719 reg = <0x0 0x00a98000 0x0 0x4000>; 1720 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1721 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1722 clock-names = "se"; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1724 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1725 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1726 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1727 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1729 interconnect-names = "qup-core", 1730 "qup-config", 1731 "qup-memory"; 1732 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1733 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1734 dma-names = "tx", 1735 "rx"; 1736 pinctrl-0 = <&qup_i2c14_data_clk>; 1737 pinctrl-names = "default"; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 status = "disabled"; 1742 }; 1743 1744 spi14: spi@a98000 { 1745 compatible = "qcom,geni-spi"; 1746 reg = <0x0 0x00a98000 0x0 0x4000>; 1747 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1749 clock-names = "se"; 1750 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1751 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1752 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1753 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1754 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1755 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1756 interconnect-names = "qup-core", 1757 "qup-config", 1758 "qup-memory"; 1759 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1760 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1761 dma-names = "tx", 1762 "rx"; 1763 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1764 pinctrl-names = "default"; 1765 #address-cells = <1>; 1766 #size-cells = <0>; 1767 1768 status = "disabled"; 1769 }; 1770 1771 uart14: serial@a98000 { 1772 compatible = "qcom,geni-uart"; 1773 reg = <0x0 0x00a98000 0x0 0x4000>; 1774 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1775 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1776 clock-names = "se"; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1778 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1779 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1780 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1781 interconnect-names = "qup-core", 1782 "qup-config"; 1783 pinctrl-0 = <&qup_uart14_default>; 1784 pinctrl-names = "default"; 1785 1786 status = "disabled"; 1787 }; 1788 1789 i2c15: i2c@a9c000 { 1790 compatible = "qcom,geni-i2c"; 1791 reg = <0x0 0x00a9c000 0x0 0x4000>; 1792 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1794 clock-names = "se"; 1795 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1796 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1797 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1798 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1799 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1800 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1801 interconnect-names = "qup-core", 1802 "qup-config", 1803 "qup-memory"; 1804 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1805 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1806 dma-names = "tx", 1807 "rx"; 1808 pinctrl-0 = <&qup_i2c15_data_clk>; 1809 pinctrl-names = "default"; 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 1813 status = "disabled"; 1814 }; 1815 1816 spi15: spi@a9c000 { 1817 compatible = "qcom,geni-spi"; 1818 reg = <0x0 0x00a9c000 0x0 0x4000>; 1819 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1820 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1821 clock-names = "se"; 1822 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1823 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1824 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1825 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&aggre3_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1827 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1828 interconnect-names = "qup-core", 1829 "qup-config", 1830 "qup-memory"; 1831 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 1832 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 1833 dma-names = "tx", 1834 "rx"; 1835 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1836 pinctrl-names = "default"; 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 status = "disabled"; 1841 }; 1842 }; 1843 1844 gpi_dma0: dma-controller@b00000 { 1845 compatible = "qcom,glymur-gpi-dma", "qcom,sm6350-gpi-dma"; 1846 reg = <0x0 0x00b00000 0x0 0x60000>; 1847 interrupts = <GIC_ESPI 76 IRQ_TYPE_LEVEL_HIGH>, 1848 <GIC_ESPI 77 IRQ_TYPE_LEVEL_HIGH>, 1849 <GIC_ESPI 78 IRQ_TYPE_LEVEL_HIGH>, 1850 <GIC_ESPI 79 IRQ_TYPE_LEVEL_HIGH>, 1851 <GIC_ESPI 80 IRQ_TYPE_LEVEL_HIGH>, 1852 <GIC_ESPI 81 IRQ_TYPE_LEVEL_HIGH>, 1853 <GIC_ESPI 82 IRQ_TYPE_LEVEL_HIGH>, 1854 <GIC_ESPI 83 IRQ_TYPE_LEVEL_HIGH>, 1855 <GIC_ESPI 84 IRQ_TYPE_LEVEL_HIGH>, 1856 <GIC_ESPI 85 IRQ_TYPE_LEVEL_HIGH>, 1857 <GIC_ESPI 86 IRQ_TYPE_LEVEL_HIGH>, 1858 <GIC_ESPI 87 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_ESPI 88 IRQ_TYPE_LEVEL_HIGH>, 1860 <GIC_ESPI 89 IRQ_TYPE_LEVEL_HIGH>, 1861 <GIC_ESPI 90 IRQ_TYPE_LEVEL_HIGH>, 1862 <GIC_ESPI 91 IRQ_TYPE_LEVEL_HIGH>; 1863 dma-channels = <16>; 1864 dma-channel-mask = <0x3f>; 1865 #dma-cells = <3>; 1866 iommus = <&apps_smmu 0xd36 0x0>; 1867 }; 1868 1869 qupv3_0: geniqup@bc0000 { 1870 compatible = "qcom,geni-se-qup"; 1871 reg = <0x0 0x00bc0000 0x0 0x3000>; 1872 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1873 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1874 clock-names = "m-ahb", 1875 "s-ahb"; 1876 iommus = <&apps_smmu 0xd23 0x0>; 1877 #address-cells = <2>; 1878 #size-cells = <2>; 1879 ranges; 1880 1881 i2c0: i2c@b80000 { 1882 compatible = "qcom,geni-i2c"; 1883 reg = <0x0 0x00b80000 0x0 0x4000>; 1884 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1885 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1886 clock-names = "se"; 1887 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1888 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1889 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1890 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1891 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1892 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1893 interconnect-names = "qup-core", 1894 "qup-config", 1895 "qup-memory"; 1896 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1897 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1898 dma-names = "tx", 1899 "rx"; 1900 pinctrl-0 = <&qup_i2c0_data_clk>; 1901 pinctrl-names = "default"; 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 1905 status = "disabled"; 1906 }; 1907 1908 spi0: spi@b80000 { 1909 compatible = "qcom,geni-spi"; 1910 reg = <0x0 0x00b80000 0x0 0x4000>; 1911 interrupts = <GIC_ESPI 92 IRQ_TYPE_LEVEL_HIGH>; 1912 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1913 clock-names = "se"; 1914 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1915 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1916 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1917 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1918 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1919 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1920 interconnect-names = "qup-core", 1921 "qup-config", 1922 "qup-memory"; 1923 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1924 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1925 dma-names = "tx", 1926 "rx"; 1927 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1928 pinctrl-names = "default"; 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 1932 status = "disabled"; 1933 }; 1934 1935 i2c1: i2c@b84000 { 1936 compatible = "qcom,geni-i2c"; 1937 reg = <0x0 0x00b84000 0x0 0x4000>; 1938 interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>; 1939 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1940 clock-names = "se"; 1941 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1942 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1943 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1944 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1945 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1946 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1947 interconnect-names = "qup-core", 1948 "qup-config", 1949 "qup-memory"; 1950 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1951 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1952 dma-names = "tx", 1953 "rx"; 1954 pinctrl-0 = <&qup_i2c1_data_clk>; 1955 pinctrl-names = "default"; 1956 #address-cells = <1>; 1957 #size-cells = <0>; 1958 1959 status = "disabled"; 1960 }; 1961 1962 spi1: spi@b84000 { 1963 compatible = "qcom,geni-spi"; 1964 reg = <0x0 0x00b84000 0x0 0x4000>; 1965 interrupts = <GIC_ESPI 93 IRQ_TYPE_LEVEL_HIGH>; 1966 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1967 clock-names = "se"; 1968 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1969 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1970 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1971 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1972 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1973 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1974 interconnect-names = "qup-core", 1975 "qup-config", 1976 "qup-memory"; 1977 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1978 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1979 dma-names = "tx", 1980 "rx"; 1981 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1982 pinctrl-names = "default"; 1983 #address-cells = <1>; 1984 #size-cells = <0>; 1985 1986 status = "disabled"; 1987 }; 1988 1989 i2c2: i2c@b88000 { 1990 compatible = "qcom,geni-i2c"; 1991 reg = <0x0 0x00b88000 0x0 0x4000>; 1992 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 1993 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1994 clock-names = "se"; 1995 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1996 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1997 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1998 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1999 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2000 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2001 interconnect-names = "qup-core", 2002 "qup-config", 2003 "qup-memory"; 2004 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 2005 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 2006 dma-names = "tx", 2007 "rx"; 2008 pinctrl-0 = <&qup_i2c2_data_clk>; 2009 pinctrl-names = "default"; 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 2013 status = "disabled"; 2014 }; 2015 2016 spi2: spi@b88000 { 2017 compatible = "qcom,geni-spi"; 2018 reg = <0x0 0x00b88000 0x0 0x4000>; 2019 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 2020 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2021 clock-names = "se"; 2022 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2023 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2024 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2025 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2026 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2027 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2028 interconnect-names = "qup-core", 2029 "qup-config", 2030 "qup-memory"; 2031 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 2032 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 2033 dma-names = "tx", 2034 "rx"; 2035 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 2036 pinctrl-names = "default"; 2037 #address-cells = <1>; 2038 #size-cells = <0>; 2039 2040 status = "disabled"; 2041 }; 2042 2043 uart2: serial@b88000 { 2044 compatible = "qcom,geni-uart"; 2045 reg = <0x0 0x00b88000 0x0 0x4000>; 2046 interrupts = <GIC_ESPI 94 IRQ_TYPE_LEVEL_HIGH>; 2047 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 2048 clock-names = "se"; 2049 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2050 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2051 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2052 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 2053 interconnect-names = "qup-core", 2054 "qup-config"; 2055 pinctrl-0 = <&qup_uart2_default>; 2056 pinctrl-names = "default"; 2057 2058 status = "disabled"; 2059 }; 2060 2061 i2c3: i2c@b8c000 { 2062 compatible = "qcom,geni-i2c"; 2063 reg = <0x0 0x00b8c000 0x0 0x4000>; 2064 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2065 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2066 clock-names = "se"; 2067 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2068 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2069 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2070 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2071 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2072 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2073 interconnect-names = "qup-core", 2074 "qup-config", 2075 "qup-memory"; 2076 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 2077 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 2078 dma-names = "tx", 2079 "rx"; 2080 pinctrl-0 = <&qup_i2c3_data_clk>; 2081 pinctrl-names = "default"; 2082 #address-cells = <1>; 2083 #size-cells = <0>; 2084 2085 status = "disabled"; 2086 }; 2087 2088 spi3: spi@b8c000 { 2089 compatible = "qcom,geni-spi"; 2090 reg = <0x0 0x00b8c000 0x0 0x4000>; 2091 interrupts = <GIC_ESPI 95 IRQ_TYPE_LEVEL_HIGH>; 2092 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 2093 clock-names = "se"; 2094 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2095 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2096 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2097 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2098 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2099 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2100 interconnect-names = "qup-core", 2101 "qup-config", 2102 "qup-memory"; 2103 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 2104 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 2105 dma-names = "tx", 2106 "rx"; 2107 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 2108 pinctrl-names = "default"; 2109 #address-cells = <1>; 2110 #size-cells = <0>; 2111 2112 status = "disabled"; 2113 }; 2114 2115 i2c4: i2c@b90000 { 2116 compatible = "qcom,geni-i2c"; 2117 reg = <0x0 0x00b90000 0x0 0x4000>; 2118 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2119 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2120 clock-names = "se"; 2121 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2122 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2123 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2124 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2125 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2126 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2127 interconnect-names = "qup-core", 2128 "qup-config", 2129 "qup-memory"; 2130 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 2131 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 2132 dma-names = "tx", 2133 "rx"; 2134 pinctrl-0 = <&qup_i2c4_data_clk>; 2135 pinctrl-names = "default"; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 2139 status = "disabled"; 2140 }; 2141 2142 spi4: spi@b90000 { 2143 compatible = "qcom,geni-spi"; 2144 reg = <0x0 0x00b90000 0x0 0x4000>; 2145 interrupts = <GIC_ESPI 96 IRQ_TYPE_LEVEL_HIGH>; 2146 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 2147 clock-names = "se"; 2148 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2149 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2150 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2151 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2152 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2153 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2154 interconnect-names = "qup-core", 2155 "qup-config", 2156 "qup-memory"; 2157 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 2158 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 2159 dma-names = "tx", 2160 "rx"; 2161 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 2162 pinctrl-names = "default"; 2163 #address-cells = <1>; 2164 #size-cells = <0>; 2165 2166 status = "disabled"; 2167 }; 2168 2169 i2c5: i2c@b94000 { 2170 compatible = "qcom,geni-i2c"; 2171 reg = <0x0 0x00b94000 0x0 0x4000>; 2172 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2173 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2174 clock-names = "se"; 2175 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2176 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2177 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2178 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2179 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2180 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2181 interconnect-names = "qup-core", 2182 "qup-config", 2183 "qup-memory"; 2184 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 2185 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 2186 dma-names = "tx", 2187 "rx"; 2188 pinctrl-0 = <&qup_i2c5_data_clk>; 2189 pinctrl-names = "default"; 2190 #address-cells = <1>; 2191 #size-cells = <0>; 2192 2193 status = "disabled"; 2194 }; 2195 2196 spi5: spi@b94000 { 2197 compatible = "qcom,geni-spi"; 2198 reg = <0x0 0x00b94000 0x0 0x4000>; 2199 interrupts = <GIC_ESPI 97 IRQ_TYPE_LEVEL_HIGH>; 2200 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 2201 clock-names = "se"; 2202 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2203 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2204 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2205 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2206 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2208 interconnect-names = "qup-core", 2209 "qup-config", 2210 "qup-memory"; 2211 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 2212 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 2213 dma-names = "tx", 2214 "rx"; 2215 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 2216 pinctrl-names = "default"; 2217 #address-cells = <1>; 2218 #size-cells = <0>; 2219 2220 status = "disabled"; 2221 }; 2222 2223 i2c6: i2c@b98000 { 2224 compatible = "qcom,geni-i2c"; 2225 reg = <0x0 0x00b98000 0x0 0x4000>; 2226 interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>; 2227 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2228 clock-names = "se"; 2229 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2230 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2231 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2232 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2233 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2234 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2235 interconnect-names = "qup-core", 2236 "qup-config", 2237 "qup-memory"; 2238 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 2239 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 2240 dma-names = "tx", 2241 "rx"; 2242 pinctrl-0 = <&qup_i2c6_data_clk>; 2243 pinctrl-names = "default"; 2244 #address-cells = <1>; 2245 #size-cells = <0>; 2246 2247 status = "disabled"; 2248 }; 2249 2250 spi6: spi@b98000 { 2251 compatible = "qcom,geni-spi"; 2252 reg = <0x0 0x00b98000 0x0 0x4000>; 2253 interrupts = <GIC_ESPI 98 IRQ_TYPE_LEVEL_HIGH>; 2254 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 2255 clock-names = "se"; 2256 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2257 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2258 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2259 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2260 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2261 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2262 interconnect-names = "qup-core", 2263 "qup-config", 2264 "qup-memory"; 2265 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 2266 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 2267 dma-names = "tx", 2268 "rx"; 2269 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 2270 pinctrl-names = "default"; 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 2274 status = "disabled"; 2275 }; 2276 2277 i2c7: i2c@b9c000 { 2278 compatible = "qcom,geni-i2c"; 2279 reg = <0x0 0x00b9c000 0x0 0x4000>; 2280 interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>; 2281 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2282 clock-names = "se"; 2283 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2284 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2285 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2286 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2287 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2288 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2289 interconnect-names = "qup-core", 2290 "qup-config", 2291 "qup-memory"; 2292 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 2293 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 2294 dma-names = "tx", 2295 "rx"; 2296 pinctrl-0 = <&qup_i2c7_data_clk>; 2297 pinctrl-names = "default"; 2298 #address-cells = <1>; 2299 #size-cells = <0>; 2300 2301 status = "disabled"; 2302 }; 2303 2304 spi7: spi@b9c000 { 2305 compatible = "qcom,geni-spi"; 2306 reg = <0x0 0x00b9c000 0x0 0x4000>; 2307 interrupts = <GIC_ESPI 99 IRQ_TYPE_LEVEL_HIGH>; 2308 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 2309 clock-names = "se"; 2310 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 2311 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 2312 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2313 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 2314 <&aggre3_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 2315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2316 interconnect-names = "qup-core", 2317 "qup-config", 2318 "qup-memory"; 2319 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 2320 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 2321 dma-names = "tx", 2322 "rx"; 2323 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 2324 pinctrl-names = "default"; 2325 #address-cells = <1>; 2326 #size-cells = <0>; 2327 2328 status = "disabled"; 2329 }; 2330 }; 2331 2332 remoteproc_soccp: remoteproc@d00000 { 2333 compatible = "qcom,glymur-soccp-pas"; 2334 reg = <0x0 0x00d00000 0x0 0x200000>; 2335 2336 interrupts-extended = <&intc GIC_SPI 167 IRQ_TYPE_EDGE_RISING>, 2337 <&soccp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2338 <&soccp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2339 <&soccp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2340 <&soccp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2341 <&soccp_smp2p_in 9 IRQ_TYPE_EDGE_RISING>; 2342 interrupt-names = "wdog", 2343 "fatal", 2344 "ready", 2345 "handover", 2346 "stop-ack", 2347 "pong"; 2348 2349 clocks = <&rpmhcc RPMH_CXO_CLK>; 2350 clock-names = "xo"; 2351 2352 power-domains = <&rpmhpd RPMHPD_CX>, 2353 <&rpmhpd RPMHPD_MX>; 2354 power-domain-names = "cx", 2355 "mx"; 2356 2357 memory-region = <&soccp_mem>, 2358 <&soccpdtb_mem>; 2359 2360 qcom,smem-states = <&soccp_smp2p_out 0>, 2361 <&soccp_smp2p_out 8>; 2362 qcom,smem-state-names = "stop", 2363 "ping"; 2364 2365 glink-edge { 2366 interrupts-extended = <&ipcc IPCC_MPROC_SOCCP 2367 IPCC_MPROC_SIGNAL_GLINK_QMP 2368 IRQ_TYPE_EDGE_RISING>; 2369 mboxes = <&ipcc IPCC_MPROC_SOCCP 2370 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2371 qcom,remote-pid = <19>; 2372 label = "soccp"; 2373 }; 2374 }; 2375 2376 pcie3_phy: phy@f00000 { 2377 compatible = "qcom,glymur-qmp-gen5x8-pcie-phy"; 2378 reg = <0x0 0x00f00000 0x0 0x10000>, 2379 <0x0 0x00f10000 0x0 0x10000>; 2380 reg-names = "port_a", 2381 "port_b"; 2382 2383 clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>, 2384 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2385 <&tcsr TCSR_PCIE_3_CLKREF_EN>, 2386 <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, 2387 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2388 <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, 2389 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 2390 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, 2391 <&gcc GCC_PCIE_3B_PIPE_CLK>, 2392 <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; 2393 clock-names = "aux", 2394 "cfg_ahb", 2395 "ref", 2396 "rchng", 2397 "pipe", 2398 "phy_b_aux", 2399 "cfg_ahb_b", 2400 "rchng_b", 2401 "pipe_b", 2402 "pipediv2_b"; 2403 2404 resets = <&gcc GCC_PCIE_3A_PHY_BCR>, 2405 <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>, 2406 <&gcc GCC_PCIE_3B_PHY_BCR>, 2407 <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; 2408 reset-names = "port_a", 2409 "port_a_nocsr", 2410 "port_b", 2411 "port_b_nocsr"; 2412 2413 assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>, 2414 <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; 2415 assigned-clock-rates = <100000000>, <100000000>; 2416 2417 power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>, 2418 <&gcc GCC_PCIE_3B_PHY_GDSC>; 2419 power-domain-names = "port_a", "port_b"; 2420 2421 qcom,link-mode = <&tcsr 0x5000>; 2422 2423 #clock-cells = <1>; 2424 clock-output-names = "pcie3a_pipe_clk", 2425 "pcie3b_pipe_clk"; 2426 2427 #phy-cells = <1>; 2428 2429 status = "disabled"; 2430 }; 2431 2432 usb_hs_phy: phy@fa0000 { 2433 compatible = "qcom,glymur-m31-eusb2-phy", 2434 "qcom,sm8750-m31-eusb2-phy"; 2435 reg = <0x0 0x00fa0000 0x0 0x154>; 2436 #phy-cells = <0>; 2437 2438 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2439 clock-names = "ref"; 2440 2441 resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>; 2442 2443 status = "disabled"; 2444 }; 2445 2446 usb_mp_hsphy0: phy@fa1000 { 2447 compatible = "qcom,glymur-m31-eusb2-phy", 2448 "qcom,sm8750-m31-eusb2-phy"; 2449 2450 reg = <0x0 0x00fa1000 0x0 0x29c>; 2451 #phy-cells = <0>; 2452 2453 clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>; 2454 clock-names = "ref"; 2455 2456 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2457 2458 status = "disabled"; 2459 }; 2460 2461 usb_mp_hsphy1: phy@fa2000 { 2462 compatible = "qcom,glymur-m31-eusb2-phy", 2463 "qcom,sm8750-m31-eusb2-phy"; 2464 2465 reg = <0x0 0x00fa2000 0x0 0x29c>; 2466 #phy-cells = <0>; 2467 2468 clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>; 2469 clock-names = "ref"; 2470 2471 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2472 2473 status = "disabled"; 2474 }; 2475 2476 usb_mp_qmpphy0: phy@fa3000 { 2477 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2478 reg = <0x0 0x00fa3000 0x0 0x2000>; 2479 2480 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2481 <&tcsr TCSR_USB3_0_CLKREF_EN>, 2482 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2483 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2484 clock-names = "aux", 2485 "ref", 2486 "com_aux", 2487 "pipe"; 2488 2489 power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>; 2490 2491 resets = <&gcc GCC_USB3_MP_SS0_PHY_BCR>, 2492 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2493 reset-names = "phy", 2494 "phy_phy"; 2495 2496 clock-output-names = "usb3_uni_phy_0_pipe_clk_src"; 2497 #clock-cells = <0>; 2498 #phy-cells = <0>; 2499 2500 status = "disabled"; 2501 }; 2502 2503 usb_mp_qmpphy1: phy@fa5000 { 2504 compatible = "qcom,glymur-qmp-usb3-uni-phy"; 2505 reg = <0x0 0x00fa5000 0x0 0x2000>; 2506 2507 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2508 <&tcsr TCSR_USB3_1_CLKREF_EN>, 2509 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2510 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2511 clock-names = "aux", 2512 "ref", 2513 "com_aux", 2514 "pipe"; 2515 2516 power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>; 2517 2518 resets = <&gcc GCC_USB3_MP_SS1_PHY_BCR>, 2519 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2520 reset-names = "phy", 2521 "phy_phy"; 2522 2523 clock-output-names = "usb3_uni_phy_1_pipe_clk_src"; 2524 2525 #clock-cells = <0>; 2526 #phy-cells = <0>; 2527 2528 status = "disabled"; 2529 }; 2530 2531 mdss_dp3_phy: phy@faac00 { 2532 compatible = "qcom,glymur-dp-phy"; 2533 reg = <0x0 0x00faac00 0x0 0x1d0>, 2534 <0x0 0x00faa400 0x0 0x128>, 2535 <0x0 0x00faa800 0x0 0x128>, 2536 <0x0 0x00faa000 0x0 0x358>; 2537 2538 clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 2539 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2540 <&tcsr TCSR_EDP_CLKREF_EN>; 2541 clock-names = "aux", 2542 "cfg_ahb", 2543 "ref"; 2544 2545 power-domains = <&rpmhpd RPMHPD_MX>; 2546 2547 #clock-cells = <1>; 2548 #phy-cells = <0>; 2549 2550 status = "disabled"; 2551 }; 2552 2553 usb_0_hsphy: phy@fd3000 { 2554 compatible = "qcom,glymur-m31-eusb2-phy", 2555 "qcom,sm8750-m31-eusb2-phy"; 2556 2557 reg = <0x0 0x00fd3000 0x0 0x29c>; 2558 #phy-cells = <0>; 2559 2560 clocks = <&rpmhcc RPMH_CXO_CLK>; 2561 clock-names = "ref"; 2562 2563 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2564 2565 status = "disabled"; 2566 }; 2567 2568 usb_0_qmpphy: phy@fd5000 { 2569 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2570 reg = <0x0 0x00fd5000 0x0 0x8000>; 2571 2572 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2573 <&rpmhcc RPMH_CXO_CLK>, 2574 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2575 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2576 clock-names = "aux", 2577 "ref", 2578 "com_aux", 2579 "usb3_pipe"; 2580 2581 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2582 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 2583 2584 reset-names = "phy", 2585 "common"; 2586 2587 power-domains = <&gcc GCC_USB_0_PHY_GDSC>; 2588 2589 #clock-cells = <1>; 2590 #phy-cells = <1>; 2591 2592 mode-switch; 2593 orientation-switch; 2594 2595 status = "disabled"; 2596 2597 ports { 2598 #address-cells = <1>; 2599 #size-cells = <0>; 2600 2601 port@0 { 2602 reg = <0>; 2603 2604 usb_0_qmpphy_out: endpoint { 2605 }; 2606 }; 2607 2608 port@1 { 2609 reg = <1>; 2610 2611 usb_0_qmpphy_usb_ss_in: endpoint { 2612 remote-endpoint = <&usb_0_dwc3_ss>; 2613 }; 2614 }; 2615 2616 port@2 { 2617 reg = <2>; 2618 2619 usb_dp_qmpphy_dp_in: endpoint { 2620 remote-endpoint = <&mdss_dp0_out>; 2621 }; 2622 }; 2623 }; 2624 }; 2625 2626 usb_1_hsphy: phy@fdd000 { 2627 compatible = "qcom,glymur-m31-eusb2-phy", 2628 "qcom,sm8750-m31-eusb2-phy"; 2629 2630 reg = <0x0 0x00fdd000 0x0 0x29c>; 2631 #phy-cells = <0>; 2632 2633 clocks = <&rpmhcc RPMH_CXO_CLK>; 2634 clock-names = "ref"; 2635 2636 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2637 2638 status = "disabled"; 2639 }; 2640 2641 usb_1_qmpphy: phy@fde000 { 2642 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 2643 reg = <0x0 0x00fde000 0x0 0x8000>; 2644 2645 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2646 <&tcsr TCSR_USB4_1_CLKREF_EN>, 2647 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2648 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2649 clock-names = "aux", 2650 "ref", 2651 "com_aux", 2652 "usb3_pipe"; 2653 2654 power-domains = <&gcc GCC_USB_1_PHY_GDSC>; 2655 2656 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2657 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2658 reset-names = "phy", 2659 "common"; 2660 2661 #clock-cells = <1>; 2662 #phy-cells = <1>; 2663 2664 mode-switch; 2665 orientation-switch; 2666 2667 status = "disabled"; 2668 2669 ports { 2670 #address-cells = <1>; 2671 #size-cells = <0>; 2672 2673 port@0 { 2674 reg = <0>; 2675 2676 usb_1_qmpphy_out: endpoint { 2677 }; 2678 }; 2679 2680 port@1 { 2681 reg = <1>; 2682 2683 usb_1_qmpphy_usb_ss_in: endpoint { 2684 remote-endpoint = <&usb_1_dwc3_ss>; 2685 }; 2686 }; 2687 2688 port@2 { 2689 reg = <2>; 2690 2691 usb_1_qmpphy_dp_in: endpoint { 2692 remote-endpoint = <&mdss_dp1_out>; 2693 }; 2694 }; 2695 }; 2696 }; 2697 2698 2699 /* cluster0 */ 2700 bwmon_cluster0: pmu@100c400 { 2701 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2702 reg = <0x0 0x0100c400 0x0 0x600>; 2703 2704 interrupts = <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>; 2705 2706 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2707 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2708 2709 operating-points-v2 = <&cpu_bwmon_opp_table>; 2710 2711 cpu_bwmon_opp_table: opp-table { 2712 compatible = "operating-points-v2"; 2713 2714 opp-0 { 2715 opp-peak-kBps = <800000>; 2716 }; 2717 2718 opp-1 { 2719 opp-peak-kBps = <2188800>; 2720 }; 2721 2722 opp-2 { 2723 opp-peak-kBps = <5414400>; 2724 }; 2725 2726 opp-3 { 2727 opp-peak-kBps = <6220800>; 2728 }; 2729 2730 opp-4 { 2731 opp-peak-kBps = <6835200>; 2732 }; 2733 2734 opp-5 { 2735 opp-peak-kBps = <8371200>; 2736 }; 2737 2738 opp-6 { 2739 opp-peak-kBps = <10944000>; 2740 }; 2741 2742 opp-7 { 2743 opp-peak-kBps = <12748800>; 2744 }; 2745 2746 opp-8 { 2747 opp-peak-kBps = <14745600>; 2748 }; 2749 2750 opp-9 { 2751 opp-peak-kBps = <16896000>; 2752 }; 2753 2754 opp-10 { 2755 opp-peak-kBps = <19046400>; 2756 }; 2757 2758 opp-11 { 2759 opp-peak-kBps = <21332000>; 2760 }; 2761 }; 2762 }; 2763 2764 /* cluster1 */ 2765 bwmon_cluster1: pmu@100d400 { 2766 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2767 reg = <0x0 0x0100d400 0x0 0x600>; 2768 2769 interrupts = <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>; 2770 2771 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2772 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2773 2774 operating-points-v2 = <&cpu_bwmon_opp_table>; 2775 }; 2776 2777 /* cluster2 */ 2778 bwmon_cluster2: pmu@100e400 { 2779 compatible = "qcom,glymur-cpu-bwmon", "qcom,sdm845-bwmon"; 2780 reg = <0x0 0x0100e400 0x0 0x600>; 2781 2782 interrupts = <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>; 2783 2784 interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2785 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2786 2787 operating-points-v2 = <&cpu_bwmon_opp_table>; 2788 }; 2789 cnoc_main: interconnect@1500000 { 2790 compatible = "qcom,glymur-cnoc-main"; 2791 reg = <0x0 0x01500000 0x0 0x17080>; 2792 qcom,bcm-voters = <&apps_bcm_voter>; 2793 #interconnect-cells = <2>; 2794 }; 2795 2796 config_noc: interconnect@1600000 { 2797 compatible = "qcom,glymur-cnoc-cfg"; 2798 reg = <0x0 0x01600000 0x0 0x6600>; 2799 qcom,bcm-voters = <&apps_bcm_voter>; 2800 #interconnect-cells = <2>; 2801 }; 2802 2803 system_noc: interconnect@1680000 { 2804 compatible = "qcom,glymur-system-noc"; 2805 reg = <0x0 0x01680000 0x0 0x1c080>; 2806 qcom,bcm-voters = <&apps_bcm_voter>; 2807 #interconnect-cells = <2>; 2808 }; 2809 2810 pcie_west_anoc: interconnect@16c0000 { 2811 compatible = "qcom,glymur-pcie-west-anoc"; 2812 reg = <0x0 0x016c0000 0x0 0xf580>; 2813 qcom,bcm-voters = <&apps_bcm_voter>; 2814 #interconnect-cells = <2>; 2815 clocks = <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>, 2816 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>, 2817 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>, 2818 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 2819 }; 2820 2821 pcie_east_anoc: interconnect@16d0000 { 2822 compatible = "qcom,glymur-pcie-east-anoc"; 2823 reg = <0x0 0x016d0000 0x0 0xf300>; 2824 qcom,bcm-voters = <&apps_bcm_voter>; 2825 #interconnect-cells = <2>; 2826 clocks = <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 2827 }; 2828 2829 aggre1_noc: interconnect@16e0000 { 2830 compatible = "qcom,glymur-aggre1-noc"; 2831 reg = <0x0 0x016e0000 0x0 0x14400>; 2832 qcom,bcm-voters = <&apps_bcm_voter>; 2833 #interconnect-cells = <2>; 2834 }; 2835 2836 aggre2_noc: interconnect@1720000 { 2837 compatible = "qcom,glymur-aggre2-noc"; 2838 reg = <0x0 0x01720000 0x0 0x14400>; 2839 qcom,bcm-voters = <&apps_bcm_voter>; 2840 #interconnect-cells = <2>; 2841 clocks = <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 2842 <&gcc GCC_AGGRE_USB4_2_AXI_CLK>, 2843 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 2844 }; 2845 2846 aggre3_noc: interconnect@1700000 { 2847 compatible = "qcom,glymur-aggre3-noc"; 2848 reg = <0x0 0x01700000 0x0 0x1d400>; 2849 qcom,bcm-voters = <&apps_bcm_voter>; 2850 #interconnect-cells = <2>; 2851 }; 2852 2853 aggre4_noc: interconnect@1740000 { 2854 compatible = "qcom,glymur-aggre4-noc"; 2855 reg = <0x0 0x01740000 0x0 0x14400>; 2856 qcom,bcm-voters = <&apps_bcm_voter>; 2857 #interconnect-cells = <2>; 2858 clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2859 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2860 <&gcc GCC_AGGRE_USB4_0_AXI_CLK>, 2861 <&gcc GCC_AGGRE_USB4_1_AXI_CLK>; 2862 }; 2863 2864 mmss_noc: interconnect@1780000 { 2865 compatible = "qcom,glymur-mmss-noc"; 2866 reg = <0x0 0x01780000 0x0 0x5b800>; 2867 qcom,bcm-voters = <&apps_bcm_voter>; 2868 #interconnect-cells = <2>; 2869 }; 2870 2871 pcie_east_slv_noc: interconnect@1900000 { 2872 compatible = "qcom,glymur-pcie-east-slv-noc"; 2873 reg = <0x0 0x01900000 0x0 0xe080>; 2874 qcom,bcm-voters = <&apps_bcm_voter>; 2875 #interconnect-cells = <2>; 2876 }; 2877 2878 pcie_west_slv_noc: interconnect@1920000 { 2879 compatible = "qcom,glymur-pcie-west-slv-noc"; 2880 reg = <0x0 0x01920000 0x0 0xf180>; 2881 qcom,bcm-voters = <&apps_bcm_voter>; 2882 #interconnect-cells = <2>; 2883 }; 2884 2885 pcie4: pcie@1bf0000 { 2886 device_type = "pci"; 2887 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 2888 reg = <0x0 0x01bf0000 0x0 0x3000>, 2889 <0x0 0x78000000 0x0 0xf20>, 2890 <0x0 0x78000f40 0x0 0xa8>, 2891 <0x0 0x78001000 0x0 0x4000>, 2892 <0x0 0x78005000 0x0 0x100000>, 2893 <0x0 0x01bf3000 0x0 0x1000>; 2894 reg-names = "parf", 2895 "dbi", 2896 "elbi", 2897 "atu", 2898 "config", 2899 "mhi"; 2900 #address-cells = <3>; 2901 #size-cells = <2>; 2902 ranges = <0x01000000 0x0 0x00000000 0x0 0x78105000 0x0 0x100000>, 2903 <0x02000000 0x0 0x78205000 0x0 0x78205000 0x0 0x1dfb000>, 2904 <0x03000000 0x7 0x80000000 0x7 0x80000000 0x0 0x20000000>; 2905 bus-range = <0x00 0xff>; 2906 2907 dma-coherent; 2908 2909 linux,pci-domain = <4>; 2910 num-lanes = <2>; 2911 2912 operating-points-v2 = <&pcie4_opp_table>; 2913 2914 msi-map = <0x0 &gic_its 0xc0000 0x10000>; 2915 iommu-map = <0x0 &pcie_smmu 0x40000 0x10000>; 2916 2917 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 2918 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2919 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2920 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 2921 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 2922 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 2923 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 2924 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 2925 <GIC_SPI 944 IRQ_TYPE_LEVEL_HIGH>; 2926 interrupt-names = "msi0", 2927 "msi1", 2928 "msi2", 2929 "msi3", 2930 "msi4", 2931 "msi5", 2932 "msi6", 2933 "msi7", 2934 "global"; 2935 2936 #interrupt-cells = <1>; 2937 interrupt-map-mask = <0 0 0 0x7>; 2938 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 2939 <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 2940 <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 2941 <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 2942 2943 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 2944 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 2945 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 2946 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 2947 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 2948 <&gcc GCC_AGGRE_NOC_PCIE_4_WEST_SF_AXI_CLK>; 2949 clock-names = "aux", 2950 "cfg", 2951 "bus_master", 2952 "bus_slave", 2953 "slave_q2a", 2954 "noc_aggr"; 2955 2956 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 2957 assigned-clock-rates = <19200000>; 2958 2959 interconnects = <&pcie_west_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS 2960 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2961 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2962 &pcie_west_slv_noc SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>; 2963 interconnect-names = "pcie-mem", 2964 "cpu-pcie"; 2965 2966 resets = <&gcc GCC_PCIE_4_BCR>, 2967 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>; 2968 reset-names = "pci", 2969 "link_down"; 2970 2971 power-domains = <&gcc GCC_PCIE_4_GDSC>; 2972 2973 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2974 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2975 2976 status = "disabled"; 2977 2978 pcie4_opp_table: opp-table { 2979 compatible = "operating-points-v2"; 2980 2981 /* GEN 1 x1 */ 2982 opp-2500000-1 { 2983 opp-hz = /bits/ 64 <2500000>; 2984 required-opps = <&rpmhpd_opp_low_svs>; 2985 opp-peak-kBps = <250000 1>; 2986 opp-level = <1>; 2987 }; 2988 2989 /* GEN 1 x2 */ 2990 opp-5000000-1 { 2991 opp-hz = /bits/ 64 <5000000>; 2992 required-opps = <&rpmhpd_opp_low_svs>; 2993 opp-peak-kBps = <500000 1>; 2994 opp-level = <1>; 2995 }; 2996 2997 /* GEN 2 x1 */ 2998 opp-5000000-2 { 2999 opp-hz = /bits/ 64 <5000000>; 3000 required-opps = <&rpmhpd_opp_low_svs>; 3001 opp-peak-kBps = <500000 1>; 3002 opp-level = <2>; 3003 }; 3004 3005 /* GEN 2 x2 */ 3006 opp-10000000-2 { 3007 opp-hz = /bits/ 64 <10000000>; 3008 required-opps = <&rpmhpd_opp_low_svs>; 3009 opp-peak-kBps = <1000000 1>; 3010 opp-level = <2>; 3011 }; 3012 3013 /* GEN 3 x1 */ 3014 opp-8000000-3 { 3015 opp-hz = /bits/ 64 <8000000>; 3016 required-opps = <&rpmhpd_opp_low_svs>; 3017 opp-peak-kBps = <984500 1>; 3018 opp-level = <3>; 3019 }; 3020 3021 /* GEN 3 x2 */ 3022 opp-16000000-3 { 3023 opp-hz = /bits/ 64 <16000000>; 3024 required-opps = <&rpmhpd_opp_low_svs>; 3025 opp-peak-kBps = <1969000 1>; 3026 opp-level = <3>; 3027 }; 3028 3029 /* GEN 4 x1 */ 3030 opp-16000000-4 { 3031 opp-hz = /bits/ 64 <16000000>; 3032 required-opps = <&rpmhpd_opp_low_svs>; 3033 opp-peak-kBps = <1969000 1>; 3034 opp-level = <4>; 3035 }; 3036 3037 /* GEN 4 x2 */ 3038 opp-32000000-4 { 3039 opp-hz = /bits/ 64 <32000000>; 3040 required-opps = <&rpmhpd_opp_low_svs>; 3041 opp-peak-kBps = <3938000 1>; 3042 opp-level = <4>; 3043 }; 3044 3045 }; 3046 3047 pcie4_port0: pcie@0 { 3048 device_type = "pci"; 3049 compatible = "pciclass,0604"; 3050 reg = <0x0 0x0 0x0 0x0 0x0>; 3051 bus-range = <0x01 0xff>; 3052 3053 phys = <&pcie4_phy>; 3054 3055 #address-cells = <3>; 3056 #size-cells = <2>; 3057 ranges; 3058 3059 port { 3060 pcie4_port0_ep: endpoint { 3061 }; 3062 }; 3063 }; 3064 }; 3065 3066 pcie4_phy: phy@1bf6000 { 3067 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3068 reg = <0x0 0x01bf6000 0x0 0x2000>; 3069 3070 clocks = <&gcc GCC_PCIE_PHY_4_AUX_CLK>, 3071 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 3072 <&tcsr TCSR_PCIE_2_CLKREF_EN>, 3073 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>, 3074 <&gcc GCC_PCIE_4_PIPE_CLK>, 3075 <&gcc GCC_PCIE_4_PIPE_DIV2_CLK>; 3076 clock-names = "aux", 3077 "cfg_ahb", 3078 "ref", 3079 "rchng", 3080 "pipe", 3081 "pipediv2"; 3082 3083 resets = <&gcc GCC_PCIE_4_PHY_BCR>, 3084 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>; 3085 reset-names = "phy", 3086 "phy_nocsr"; 3087 3088 assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>; 3089 assigned-clock-rates = <100000000>; 3090 3091 power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>; 3092 3093 #clock-cells = <0>; 3094 clock-output-names = "pcie4_pipe_clk"; 3095 3096 #phy-cells = <0>; 3097 3098 status = "disabled"; 3099 }; 3100 3101 pcie5: pcie@1b40000 { 3102 device_type = "pci"; 3103 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3104 reg = <0x0 0x01b40000 0x0 0x3000>, 3105 <0x0 0x7a000000 0x0 0xf20>, 3106 <0x0 0x7a000f40 0x0 0xa8>, 3107 <0x0 0x7a001000 0x0 0x4000>, 3108 <0x0 0x7a100000 0x0 0x100000>, 3109 <0x0 0x01b43000 0x0 0x1000>; 3110 reg-names = "parf", 3111 "dbi", 3112 "elbi", 3113 "atu", 3114 "config", 3115 "mhi"; 3116 #address-cells = <3>; 3117 #size-cells = <2>; 3118 ranges = <0x01000000 0x0 0x00000000 0x0 0x7a200000 0x0 0x100000>, 3119 <0x02000000 0x0 0x7a300000 0x0 0x7a300000 0x0 0x3d00000>, 3120 <0x03000000 0x7 0xa0000000 0x7 0xa0000000 0x0 0x40000000>; 3121 bus-range = <0x00 0xff>; 3122 3123 dma-coherent; 3124 3125 linux,pci-domain = <5>; 3126 num-lanes = <4>; 3127 3128 operating-points-v2 = <&pcie5_opp_table>; 3129 3130 msi-map = <0x0 &gic_its 0xd0000 0x10000>; 3131 iommu-map = <0x0 &pcie_smmu 0x50000 0x10000>; 3132 3133 interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 3134 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 3135 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 3136 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 3137 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 3138 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 3139 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 3140 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 3141 <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 3142 interrupt-names = "msi0", 3143 "msi1", 3144 "msi2", 3145 "msi3", 3146 "msi4", 3147 "msi5", 3148 "msi6", 3149 "msi7", 3150 "global"; 3151 3152 #interrupt-cells = <1>; 3153 interrupt-map-mask = <0 0 0 0x7>; 3154 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 3155 <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 3156 <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 3157 <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>; 3158 3159 clocks = <&gcc GCC_PCIE_5_AUX_CLK>, 3160 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3161 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>, 3162 <&gcc GCC_PCIE_5_SLV_AXI_CLK>, 3163 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>, 3164 <&gcc GCC_AGGRE_NOC_PCIE_5_EAST_SF_AXI_CLK>; 3165 clock-names = "aux", 3166 "cfg", 3167 "bus_master", 3168 "bus_slave", 3169 "slave_q2a", 3170 "noc_aggr"; 3171 3172 assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>; 3173 assigned-clock-rates = <19200000>; 3174 3175 interconnects = <&pcie_east_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS 3176 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3177 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3178 &pcie_east_slv_noc SLAVE_PCIE_5 QCOM_ICC_TAG_ALWAYS>; 3179 interconnect-names = "pcie-mem", 3180 "cpu-pcie"; 3181 3182 resets = <&gcc GCC_PCIE_5_BCR>, 3183 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>; 3184 reset-names = "pci", 3185 "link_down"; 3186 3187 power-domains = <&gcc GCC_PCIE_5_GDSC>; 3188 3189 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3190 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3191 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3192 3193 status = "disabled"; 3194 3195 pcie5_opp_table: opp-table { 3196 compatible = "operating-points-v2"; 3197 3198 /* GEN 1 x1 */ 3199 opp-2500000-1 { 3200 opp-hz = /bits/ 64 <2500000>; 3201 required-opps = <&rpmhpd_opp_low_svs>; 3202 opp-peak-kBps = <250000 1>; 3203 opp-level = <1>; 3204 }; 3205 3206 /* GEN 1 x2 */ 3207 opp-5000000-1 { 3208 opp-hz = /bits/ 64 <5000000>; 3209 required-opps = <&rpmhpd_opp_low_svs>; 3210 opp-peak-kBps = <500000 1>; 3211 opp-level = <1>; 3212 }; 3213 3214 /* GEN 1 x4 */ 3215 opp-10000000-1 { 3216 opp-hz = /bits/ 64 <10000000>; 3217 required-opps = <&rpmhpd_opp_low_svs>; 3218 opp-peak-kBps = <1000000 1>; 3219 opp-level = <1>; 3220 }; 3221 3222 /* GEN 2 x1 */ 3223 opp-5000000-2 { 3224 opp-hz = /bits/ 64 <5000000>; 3225 required-opps = <&rpmhpd_opp_low_svs>; 3226 opp-peak-kBps = <500000 1>; 3227 opp-level = <2>; 3228 }; 3229 3230 /* GEN 2 x2 */ 3231 opp-10000000-2 { 3232 opp-hz = /bits/ 64 <10000000>; 3233 required-opps = <&rpmhpd_opp_low_svs>; 3234 opp-peak-kBps = <1000000 1>; 3235 opp-level = <2>; 3236 }; 3237 3238 /* GEN 2 x4 */ 3239 opp-20000000-2 { 3240 opp-hz = /bits/ 64 <20000000>; 3241 required-opps = <&rpmhpd_opp_low_svs>; 3242 opp-peak-kBps = <2000000 1>; 3243 opp-level = <2>; 3244 }; 3245 3246 /* GEN 3 x1 */ 3247 opp-8000000-3 { 3248 opp-hz = /bits/ 64 <8000000>; 3249 required-opps = <&rpmhpd_opp_low_svs>; 3250 opp-peak-kBps = <984500 1>; 3251 opp-level = <3>; 3252 }; 3253 3254 /* GEN 3 x2 */ 3255 opp-16000000-3 { 3256 opp-hz = /bits/ 64 <16000000>; 3257 required-opps = <&rpmhpd_opp_low_svs>; 3258 opp-peak-kBps = <1969000 1>; 3259 opp-level = <3>; 3260 }; 3261 3262 /* GEN 3 x4 */ 3263 opp-32000000-3 { 3264 opp-hz = /bits/ 64 <32000000>; 3265 required-opps = <&rpmhpd_opp_low_svs>; 3266 opp-peak-kBps = <3938000 1>; 3267 opp-level = <3>; 3268 }; 3269 3270 /* GEN 4 x1 */ 3271 opp-16000000-4 { 3272 opp-hz = /bits/ 64 <16000000>; 3273 required-opps = <&rpmhpd_opp_svs>; 3274 opp-peak-kBps = <1969000 1>; 3275 opp-level = <4>; 3276 }; 3277 3278 /* GEN 4 x2 */ 3279 opp-32000000-4 { 3280 opp-hz = /bits/ 64 <32000000>; 3281 required-opps = <&rpmhpd_opp_svs>; 3282 opp-peak-kBps = <3938000 1>; 3283 opp-level = <4>; 3284 }; 3285 3286 /* GEN 4 x4 */ 3287 opp-64000000-4 { 3288 opp-hz = /bits/ 64 <64000000>; 3289 required-opps = <&rpmhpd_opp_svs>; 3290 opp-peak-kBps = <7876000 1>; 3291 opp-level = <4>; 3292 }; 3293 3294 /* GEN 5 x1 */ 3295 opp-32000000-5 { 3296 opp-hz = /bits/ 64 <32000000>; 3297 required-opps = <&rpmhpd_opp_nom>; 3298 opp-peak-kBps = <3938000 1>; 3299 opp-level = <5>; 3300 }; 3301 3302 /* GEN 5 x2 */ 3303 opp-64000000-5 { 3304 opp-hz = /bits/ 64 <64000000>; 3305 required-opps = <&rpmhpd_opp_nom>; 3306 opp-peak-kBps = <7876000 1>; 3307 opp-level = <5>; 3308 }; 3309 3310 /* GEN 5 x4 */ 3311 opp-128000000-5 { 3312 opp-hz = /bits/ 64 <128000000>; 3313 required-opps = <&rpmhpd_opp_nom>; 3314 opp-peak-kBps = <15753000 1>; 3315 opp-level = <5>; 3316 }; 3317 }; 3318 3319 pcie5_port0: pcie@0 { 3320 device_type = "pci"; 3321 compatible = "pciclass,0604"; 3322 reg = <0x0 0x0 0x0 0x0 0x0>; 3323 bus-range = <0x01 0xff>; 3324 3325 phys = <&pcie5_phy>; 3326 3327 #address-cells = <3>; 3328 #size-cells = <2>; 3329 ranges; 3330 3331 port { 3332 pcie5_port0_ep: endpoint { 3333 }; 3334 }; 3335 }; 3336 }; 3337 3338 pcie5_phy: phy@1b50000 { 3339 compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; 3340 reg = <0x0 0x01b50000 0x0 0x10000>; 3341 3342 clocks = <&gcc GCC_PCIE_PHY_5_AUX_CLK>, 3343 <&gcc GCC_PCIE_5_CFG_AHB_CLK>, 3344 <&tcsr TCSR_PCIE_1_CLKREF_EN>, 3345 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, 3346 <&gcc GCC_PCIE_5_PIPE_CLK>, 3347 <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; 3348 clock-names = "aux", 3349 "cfg_ahb", 3350 "ref", 3351 "rchng", 3352 "pipe", 3353 "pipediv2"; 3354 3355 resets = <&gcc GCC_PCIE_5_PHY_BCR>, 3356 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>; 3357 reset-names = "phy", 3358 "phy_nocsr"; 3359 3360 assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>; 3361 assigned-clock-rates = <100000000>; 3362 3363 power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>; 3364 3365 #clock-cells = <0>; 3366 clock-output-names = "pcie5_pipe_clk"; 3367 3368 #phy-cells = <0>; 3369 3370 status = "disabled"; 3371 }; 3372 3373 pcie6: pcie@1c00000 { 3374 device_type = "pci"; 3375 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3376 reg = <0x0 0x01c00000 0x0 0x3000>, 3377 <0x0 0x7e000000 0x0 0xf20>, 3378 <0x0 0x7e000f40 0x0 0xa8>, 3379 <0x0 0x7e001000 0x0 0x4000>, 3380 <0x0 0x7e100000 0x0 0x100000>, 3381 <0x0 0x01c03000 0x0 0x1000>; 3382 reg-names = "parf", 3383 "dbi", 3384 "elbi", 3385 "atu", 3386 "config", 3387 "mhi"; 3388 #address-cells = <3>; 3389 #size-cells = <2>; 3390 ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>, 3391 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>, 3392 <0x03000000 0x7 0xe0000000 0x7 0xe0000000 0x0 0x20000000>; 3393 bus-range = <0x00 0xff>; 3394 3395 dma-coherent; 3396 3397 linux,pci-domain = <6>; 3398 num-lanes = <2>; 3399 3400 operating-points-v2 = <&pcie6_opp_table>; 3401 3402 msi-map = <0x0 &gic_its 0xe0000 0x10000>; 3403 iommu-map = <0x0 &pcie_smmu 0x60000 0x10000>; 3404 3405 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>; 3414 interrupt-names = "msi0", 3415 "msi1", 3416 "msi2", 3417 "msi3", 3418 "msi4", 3419 "msi5", 3420 "msi6", 3421 "msi7", 3422 "global"; 3423 3424 #interrupt-cells = <1>; 3425 interrupt-map-mask = <0 0 0 0x7>; 3426 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 3427 <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 3428 <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 3429 <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 3430 3431 clocks = <&gcc GCC_PCIE_6_AUX_CLK>, 3432 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3433 <&gcc GCC_PCIE_6_MSTR_AXI_CLK>, 3434 <&gcc GCC_PCIE_6_SLV_AXI_CLK>, 3435 <&gcc GCC_PCIE_6_SLV_Q2A_AXI_CLK>, 3436 <&gcc GCC_AGGRE_NOC_PCIE_6_WEST_SF_AXI_CLK>; 3437 clock-names = "aux", 3438 "cfg", 3439 "bus_master", 3440 "bus_slave", 3441 "slave_q2a", 3442 "noc_aggr"; 3443 3444 assigned-clocks = <&gcc GCC_PCIE_6_AUX_CLK>; 3445 assigned-clock-rates = <19200000>; 3446 3447 interconnects = <&pcie_west_anoc MASTER_PCIE_6 QCOM_ICC_TAG_ALWAYS 3448 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3449 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3450 &pcie_west_slv_noc SLAVE_PCIE_6 QCOM_ICC_TAG_ALWAYS>; 3451 interconnect-names = "pcie-mem", 3452 "cpu-pcie"; 3453 3454 resets = <&gcc GCC_PCIE_6_BCR>, 3455 <&gcc GCC_PCIE_6_LINK_DOWN_BCR>; 3456 reset-names = "pci", 3457 "link_down"; 3458 3459 power-domains = <&gcc GCC_PCIE_6_GDSC>; 3460 3461 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 3462 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 3463 3464 status = "disabled"; 3465 3466 pcie6_opp_table: opp-table { 3467 compatible = "operating-points-v2"; 3468 3469 /* GEN 1 x1 */ 3470 opp-2500000-1 { 3471 opp-hz = /bits/ 64 <2500000>; 3472 required-opps = <&rpmhpd_opp_low_svs>; 3473 opp-peak-kBps = <250000 1>; 3474 opp-level = <1>; 3475 }; 3476 3477 /* GEN 1 x2 */ 3478 opp-5000000-1 { 3479 opp-hz = /bits/ 64 <5000000>; 3480 required-opps = <&rpmhpd_opp_low_svs>; 3481 opp-peak-kBps = <500000 1>; 3482 opp-level = <1>; 3483 }; 3484 3485 /* GEN 2 x1 */ 3486 opp-5000000-2 { 3487 opp-hz = /bits/ 64 <5000000>; 3488 required-opps = <&rpmhpd_opp_low_svs>; 3489 opp-peak-kBps = <500000 1>; 3490 opp-level = <2>; 3491 }; 3492 3493 /* GEN 2 x2 */ 3494 opp-10000000-2 { 3495 opp-hz = /bits/ 64 <10000000>; 3496 required-opps = <&rpmhpd_opp_low_svs>; 3497 opp-peak-kBps = <1000000 1>; 3498 opp-level = <2>; 3499 }; 3500 3501 /* GEN 3 x1 */ 3502 opp-8000000-3 { 3503 opp-hz = /bits/ 64 <8000000>; 3504 required-opps = <&rpmhpd_opp_low_svs>; 3505 opp-peak-kBps = <984500 1>; 3506 opp-level = <3>; 3507 }; 3508 3509 /* GEN 3 x2 */ 3510 opp-16000000-3 { 3511 opp-hz = /bits/ 64 <16000000>; 3512 required-opps = <&rpmhpd_opp_low_svs>; 3513 opp-peak-kBps = <1969000 1>; 3514 opp-level = <3>; 3515 }; 3516 3517 /* GEN 4 x1 */ 3518 opp-16000000-4 { 3519 opp-hz = /bits/ 64 <16000000>; 3520 required-opps = <&rpmhpd_opp_low_svs>; 3521 opp-peak-kBps = <1969000 1>; 3522 opp-level = <4>; 3523 }; 3524 3525 /* GEN 4 x2 */ 3526 opp-32000000-4 { 3527 opp-hz = /bits/ 64 <32000000>; 3528 required-opps = <&rpmhpd_opp_low_svs>; 3529 opp-peak-kBps = <3938000 1>; 3530 opp-level = <4>; 3531 }; 3532 3533 }; 3534 3535 pcie6_port0: pcie@0 { 3536 device_type = "pci"; 3537 compatible = "pciclass,0604"; 3538 reg = <0x0 0x0 0x0 0x0 0x0>; 3539 bus-range = <0x01 0xff>; 3540 3541 phys = <&pcie6_phy>; 3542 3543 #address-cells = <3>; 3544 #size-cells = <2>; 3545 ranges; 3546 3547 port { 3548 pcie6_port0_ep: endpoint { 3549 }; 3550 }; 3551 }; 3552 }; 3553 3554 pcie6_phy: phy@1c06000 { 3555 compatible = "qcom,glymur-qmp-gen4x2-pcie-phy"; 3556 reg = <0x0 0x01c06000 0x0 0x2000>; 3557 3558 clocks = <&gcc GCC_PCIE_PHY_6_AUX_CLK>, 3559 <&gcc GCC_PCIE_6_CFG_AHB_CLK>, 3560 <&tcsr TCSR_PCIE_4_CLKREF_EN>, 3561 <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>, 3562 <&gcc GCC_PCIE_6_PIPE_CLK>, 3563 <&gcc GCC_PCIE_6_PIPE_DIV2_CLK>; 3564 clock-names = "aux", 3565 "cfg_ahb", 3566 "ref", 3567 "rchng", 3568 "pipe", 3569 "pipediv2"; 3570 3571 resets = <&gcc GCC_PCIE_6_PHY_BCR>, 3572 <&gcc GCC_PCIE_6_NOCSR_COM_PHY_BCR>; 3573 reset-names = "phy", 3574 "phy_nocsr"; 3575 3576 assigned-clocks = <&gcc GCC_PCIE_6_PHY_RCHNG_CLK>; 3577 assigned-clock-rates = <100000000>; 3578 3579 power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>; 3580 3581 #clock-cells = <0>; 3582 clock-output-names = "pcie6_pipe_clk"; 3583 3584 #phy-cells = <0>; 3585 3586 status = "disabled"; 3587 }; 3588 3589 pcie3b: pcie@1b80000 { 3590 device_type = "pci"; 3591 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3592 reg = <0x0 0x01b80000 0x0 0x3000>, 3593 <0x0 0x74000000 0x0 0xf20>, 3594 <0x0 0x74000f40 0x0 0xa8>, 3595 <0x0 0x74001000 0x0 0x4000>, 3596 <0x0 0x74100000 0x0 0x100000>, 3597 <0x0 0x01b83000 0x0 0x1000>; 3598 reg-names = "parf", 3599 "dbi", 3600 "elbi", 3601 "atu", 3602 "config", 3603 "mhi"; 3604 #address-cells = <3>; 3605 #size-cells = <2>; 3606 ranges = <0x01000000 0x0 0x00000000 0x0 0x74200000 0x0 0x100000>, 3607 <0x02000000 0x0 0x74300000 0x0 0x74300000 0x0 0x3d00000>, 3608 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>; 3609 bus-range = <0x00 0xff>; 3610 3611 dma-coherent; 3612 3613 linux,pci-domain = <7>; 3614 num-lanes = <4>; 3615 3616 operating-points-v2 = <&pcie3b_opp_table>; 3617 3618 msi-map = <0x0 &gic_its 0xf0000 0x10000>; 3619 iommu-map = <0x0 &pcie_smmu 0x70000 0x10000>; 3620 3621 interrupts = <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 3622 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 3623 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3624 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3625 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3626 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3627 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3628 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 3629 <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH>; 3630 interrupt-names = "msi0", 3631 "msi1", 3632 "msi2", 3633 "msi3", 3634 "msi4", 3635 "msi5", 3636 "msi6", 3637 "msi7", 3638 "global"; 3639 3640 #interrupt-cells = <1>; 3641 interrupt-map-mask = <0 0 0 0x7>; 3642 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>, 3643 <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 3644 <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>, 3645 <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 3646 3647 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 3648 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 3649 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 3650 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 3651 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 3652 <&gcc GCC_AGGRE_NOC_PCIE_3B_WEST_SF_AXI_CLK>; 3653 clock-names = "aux", 3654 "cfg", 3655 "bus_master", 3656 "bus_slave", 3657 "slave_q2a", 3658 "noc_aggr"; 3659 3660 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 3661 assigned-clock-rates = <19200000>; 3662 3663 interconnects = <&pcie_west_anoc MASTER_PCIE_3B QCOM_ICC_TAG_ALWAYS 3664 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3665 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3666 &pcie_west_slv_noc SLAVE_PCIE_3B QCOM_ICC_TAG_ALWAYS>; 3667 interconnect-names = "pcie-mem", 3668 "cpu-pcie"; 3669 3670 resets = <&gcc GCC_PCIE_3B_BCR>, 3671 <&gcc GCC_PCIE_3B_LINK_DOWN_BCR>; 3672 reset-names = "pci", 3673 "link_down"; 3674 3675 power-domains = <&gcc GCC_PCIE_3B_GDSC>; 3676 3677 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 3678 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3679 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 3680 3681 status = "disabled"; 3682 3683 pcie3b_opp_table: opp-table { 3684 compatible = "operating-points-v2"; 3685 3686 /* GEN 1 x1 */ 3687 opp-2500000-1 { 3688 opp-hz = /bits/ 64 <2500000>; 3689 required-opps = <&rpmhpd_opp_low_svs>; 3690 opp-peak-kBps = <250000 1>; 3691 opp-level = <1>; 3692 }; 3693 3694 /* GEN 1 x2 */ 3695 opp-5000000-1 { 3696 opp-hz = /bits/ 64 <5000000>; 3697 required-opps = <&rpmhpd_opp_low_svs>; 3698 opp-peak-kBps = <500000 1>; 3699 opp-level = <1>; 3700 }; 3701 3702 /* GEN 1 x4 */ 3703 opp-10000000-1 { 3704 opp-hz = /bits/ 64 <10000000>; 3705 required-opps = <&rpmhpd_opp_low_svs>; 3706 opp-peak-kBps = <1000000 1>; 3707 opp-level = <1>; 3708 }; 3709 3710 /* GEN 2 x1 */ 3711 opp-5000000-2 { 3712 opp-hz = /bits/ 64 <5000000>; 3713 required-opps = <&rpmhpd_opp_low_svs>; 3714 opp-peak-kBps = <500000 1>; 3715 opp-level = <2>; 3716 }; 3717 3718 /* GEN 2 x2 */ 3719 opp-10000000-2 { 3720 opp-hz = /bits/ 64 <10000000>; 3721 required-opps = <&rpmhpd_opp_low_svs>; 3722 opp-peak-kBps = <1000000 1>; 3723 opp-level = <2>; 3724 }; 3725 3726 /* GEN 2 x4 */ 3727 opp-20000000-2 { 3728 opp-hz = /bits/ 64 <20000000>; 3729 required-opps = <&rpmhpd_opp_low_svs>; 3730 opp-peak-kBps = <2000000 1>; 3731 opp-level = <2>; 3732 }; 3733 3734 /* GEN 3 x1 */ 3735 opp-8000000-3 { 3736 opp-hz = /bits/ 64 <8000000>; 3737 required-opps = <&rpmhpd_opp_low_svs>; 3738 opp-peak-kBps = <984500 1>; 3739 opp-level = <3>; 3740 }; 3741 3742 /* GEN 3 x2 */ 3743 opp-16000000-3 { 3744 opp-hz = /bits/ 64 <16000000>; 3745 required-opps = <&rpmhpd_opp_low_svs>; 3746 opp-peak-kBps = <1969000 1>; 3747 opp-level = <3>; 3748 }; 3749 3750 /* GEN 3 x4 */ 3751 opp-32000000-3 { 3752 opp-hz = /bits/ 64 <32000000>; 3753 required-opps = <&rpmhpd_opp_low_svs>; 3754 opp-peak-kBps = <3938000 1>; 3755 opp-level = <3>; 3756 }; 3757 3758 /* GEN 4 x1 */ 3759 opp-16000000-4 { 3760 opp-hz = /bits/ 64 <16000000>; 3761 required-opps = <&rpmhpd_opp_svs>; 3762 opp-peak-kBps = <1969000 1>; 3763 opp-level = <4>; 3764 }; 3765 3766 /* GEN 4 x2 */ 3767 opp-32000000-4 { 3768 opp-hz = /bits/ 64 <32000000>; 3769 required-opps = <&rpmhpd_opp_svs>; 3770 opp-peak-kBps = <3938000 1>; 3771 opp-level = <4>; 3772 }; 3773 3774 /* GEN 4 x4 */ 3775 opp-64000000-4 { 3776 opp-hz = /bits/ 64 <64000000>; 3777 required-opps = <&rpmhpd_opp_svs>; 3778 opp-peak-kBps = <7876000 1>; 3779 opp-level = <4>; 3780 }; 3781 3782 /* GEN 5 x1 */ 3783 opp-32000000-5 { 3784 opp-hz = /bits/ 64 <32000000>; 3785 required-opps = <&rpmhpd_opp_nom>; 3786 opp-peak-kBps = <3938000 1>; 3787 opp-level = <5>; 3788 }; 3789 3790 /* GEN 5 x2 */ 3791 opp-64000000-5 { 3792 opp-hz = /bits/ 64 <64000000>; 3793 required-opps = <&rpmhpd_opp_nom>; 3794 opp-peak-kBps = <7876000 1>; 3795 opp-level = <5>; 3796 }; 3797 3798 /* GEN 5 x4 */ 3799 opp-128000000-5 { 3800 opp-hz = /bits/ 64 <128000000>; 3801 required-opps = <&rpmhpd_opp_nom>; 3802 opp-peak-kBps = <15753000 1>; 3803 opp-level = <5>; 3804 }; 3805 }; 3806 3807 pcie3b_port0: pcie@0 { 3808 device_type = "pci"; 3809 compatible = "pciclass,0604"; 3810 reg = <0x0 0x0 0x0 0x0 0x0>; 3811 bus-range = <0x01 0xff>; 3812 3813 phys = <&pcie3_phy 1>; 3814 3815 #address-cells = <3>; 3816 #size-cells = <2>; 3817 ranges; 3818 3819 port { 3820 pcie3b_port0_ep: endpoint { 3821 }; 3822 }; 3823 }; 3824 }; 3825 3826 pcie3a: pcie@1c10000 { 3827 device_type = "pci"; 3828 compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; 3829 reg = <0x0 0x01c10000 0x0 0x3000>, 3830 <0x0 0x70000000 0x0 0xf20>, 3831 <0x0 0x70000f40 0x0 0xa8>, 3832 <0x0 0x70001000 0x0 0x4000>, 3833 <0x0 0x70100000 0x0 0x100000>, 3834 <0x0 0x01c13000 0x0 0x1000>; 3835 reg-names = "parf", 3836 "dbi", 3837 "elbi", 3838 "atu", 3839 "config", 3840 "mhi"; 3841 #address-cells = <3>; 3842 #size-cells = <2>; 3843 ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, 3844 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>, 3845 <0x03000000 0x7 0x00000000 0x7 0x00000000 0x0 0x40000000>, 3846 <0x43000000 0x70 0x00000000 0x70 0x00000000 0x10 0x00000000>; 3847 3848 bus-range = <0x00 0xff>; 3849 3850 dma-coherent; 3851 3852 linux,pci-domain = <3>; 3853 3854 operating-points-v2 = <&pcie3a_opp_table>; 3855 3856 msi-map = <0x0 &gic_its 0xb0000 0x10000>; 3857 iommu-map = <0x0 &pcie_smmu 0x30000 0x10000>; 3858 3859 interrupts = <GIC_SPI 948 IRQ_TYPE_LEVEL_HIGH>, 3860 <GIC_SPI 949 IRQ_TYPE_LEVEL_HIGH>, 3861 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 3862 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 3863 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 3864 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 3865 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 3866 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 3867 <GIC_SPI 942 IRQ_TYPE_LEVEL_HIGH>; 3868 interrupt-names = "msi0", 3869 "msi1", 3870 "msi2", 3871 "msi3", 3872 "msi4", 3873 "msi5", 3874 "msi6", 3875 "msi7", 3876 "global"; 3877 3878 #interrupt-cells = <1>; 3879 interrupt-map-mask = <0 0 0 0x7>; 3880 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 3881 <0 0 0 2 &intc 0 0 GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 3882 <0 0 0 3 &intc 0 0 GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, 3883 <0 0 0 4 &intc 0 0 GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>; 3884 3885 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 3886 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 3887 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 3888 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 3889 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 3890 <&gcc GCC_AGGRE_NOC_PCIE_3A_WEST_SF_AXI_CLK>; 3891 clock-names = "aux", 3892 "cfg", 3893 "bus_master", 3894 "bus_slave", 3895 "slave_q2a", 3896 "noc_aggr"; 3897 3898 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 3899 assigned-clock-rates = <19200000>; 3900 3901 interconnects = <&pcie_west_anoc MASTER_PCIE_3A QCOM_ICC_TAG_ALWAYS 3902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3903 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3904 &pcie_west_slv_noc SLAVE_PCIE_3A QCOM_ICC_TAG_ALWAYS>; 3905 interconnect-names = "pcie-mem", 3906 "cpu-pcie"; 3907 3908 resets = <&gcc GCC_PCIE_3A_BCR>, 3909 <&gcc GCC_PCIE_3A_LINK_DOWN_BCR>; 3910 reset-names = "pci", 3911 "link_down"; 3912 3913 power-domains = <&gcc GCC_PCIE_3A_GDSC>; 3914 3915 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555 3916 0x5555 0x5555 0x5555 0x5555>; 3917 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3918 eq-presets-32gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; 3919 3920 status = "disabled"; 3921 3922 pcie3a_opp_table: opp-table { 3923 compatible = "operating-points-v2"; 3924 3925 /* GEN 1 x1 */ 3926 opp-2500000-1 { 3927 opp-hz = /bits/ 64 <2500000>; 3928 required-opps = <&rpmhpd_opp_low_svs>; 3929 opp-peak-kBps = <250000 1>; 3930 opp-level = <1>; 3931 }; 3932 3933 /* GEN 1 x2 */ 3934 opp-5000000-1 { 3935 opp-hz = /bits/ 64 <5000000>; 3936 required-opps = <&rpmhpd_opp_low_svs>; 3937 opp-peak-kBps = <500000 1>; 3938 opp-level = <1>; 3939 }; 3940 3941 /* GEN 1 x4 */ 3942 opp-10000000-1 { 3943 opp-hz = /bits/ 64 <10000000>; 3944 required-opps = <&rpmhpd_opp_low_svs>; 3945 opp-peak-kBps = <1000000 1>; 3946 opp-level = <1>; 3947 }; 3948 3949 /* GEN 1 x8 */ 3950 opp-20000000-1 { 3951 opp-hz = /bits/ 64 <20000000>; 3952 required-opps = <&rpmhpd_opp_low_svs>; 3953 opp-peak-kBps = <2000000 1>; 3954 opp-level = <1>; 3955 }; 3956 3957 /* GEN 2 x1 */ 3958 opp-5000000-2 { 3959 opp-hz = /bits/ 64 <5000000>; 3960 required-opps = <&rpmhpd_opp_low_svs>; 3961 opp-peak-kBps = <500000 1>; 3962 opp-level = <2>; 3963 }; 3964 3965 /* GEN 2 x2 */ 3966 opp-10000000-2 { 3967 opp-hz = /bits/ 64 <10000000>; 3968 required-opps = <&rpmhpd_opp_low_svs>; 3969 opp-peak-kBps = <1000000 1>; 3970 opp-level = <2>; 3971 }; 3972 3973 /* GEN 2 x4 */ 3974 opp-20000000-2 { 3975 opp-hz = /bits/ 64 <20000000>; 3976 required-opps = <&rpmhpd_opp_low_svs>; 3977 opp-peak-kBps = <2000000 1>; 3978 opp-level = <2>; 3979 }; 3980 3981 /* GEN 2 x8 */ 3982 opp-40000000-2 { 3983 opp-hz = /bits/ 64 <40000000>; 3984 required-opps = <&rpmhpd_opp_low_svs>; 3985 opp-peak-kBps = <4000000 1>; 3986 opp-level = <2>; 3987 }; 3988 3989 /* GEN 3 x1 */ 3990 opp-8000000-3 { 3991 opp-hz = /bits/ 64 <8000000>; 3992 required-opps = <&rpmhpd_opp_low_svs>; 3993 opp-peak-kBps = <984500 1>; 3994 opp-level = <3>; 3995 }; 3996 3997 /* GEN 3 x2 */ 3998 opp-16000000-3 { 3999 opp-hz = /bits/ 64 <16000000>; 4000 required-opps = <&rpmhpd_opp_low_svs>; 4001 opp-peak-kBps = <1969000 1>; 4002 opp-level = <3>; 4003 }; 4004 4005 /* GEN 3 x4 */ 4006 opp-32000000-3 { 4007 opp-hz = /bits/ 64 <32000000>; 4008 required-opps = <&rpmhpd_opp_low_svs>; 4009 opp-peak-kBps = <3938000 1>; 4010 opp-level = <3>; 4011 }; 4012 4013 /* GEN 3 x8 */ 4014 opp-64000000-3 { 4015 opp-hz = /bits/ 64 <64000000>; 4016 required-opps = <&rpmhpd_opp_low_svs>; 4017 opp-peak-kBps = <7876000 1>; 4018 opp-level = <3>; 4019 }; 4020 4021 /* GEN 4 x1 */ 4022 opp-16000000-4 { 4023 opp-hz = /bits/ 64 <16000000>; 4024 required-opps = <&rpmhpd_opp_svs>; 4025 opp-peak-kBps = <1969000 1>; 4026 opp-level = <4>; 4027 }; 4028 4029 /* GEN 4 x2 */ 4030 opp-32000000-4 { 4031 opp-hz = /bits/ 64 <32000000>; 4032 required-opps = <&rpmhpd_opp_svs>; 4033 opp-peak-kBps = <3938000 1>; 4034 opp-level = <4>; 4035 }; 4036 4037 /* GEN 4 x4 */ 4038 opp-64000000-4 { 4039 opp-hz = /bits/ 64 <64000000>; 4040 required-opps = <&rpmhpd_opp_svs>; 4041 opp-peak-kBps = <7876000 1>; 4042 opp-level = <4>; 4043 }; 4044 4045 /* GEN 4 x8 */ 4046 opp-128000000-4 { 4047 opp-hz = /bits/ 64 <128000000>; 4048 required-opps = <&rpmhpd_opp_svs>; 4049 opp-peak-kBps = <15753000 1>; 4050 opp-level = <4>; 4051 }; 4052 4053 /* GEN 5 x1 */ 4054 opp-32000000-5 { 4055 opp-hz = /bits/ 64 <32000000>; 4056 required-opps = <&rpmhpd_opp_nom>; 4057 opp-peak-kBps = <3938000 1>; 4058 opp-level = <5>; 4059 }; 4060 4061 /* GEN 5 x2 */ 4062 opp-64000000-5 { 4063 opp-hz = /bits/ 64 <64000000>; 4064 required-opps = <&rpmhpd_opp_nom>; 4065 opp-peak-kBps = <7876000 1>; 4066 opp-level = <5>; 4067 }; 4068 4069 /* GEN 5 x4 */ 4070 opp-128000000-5 { 4071 opp-hz = /bits/ 64 <128000000>; 4072 required-opps = <&rpmhpd_opp_nom>; 4073 opp-peak-kBps = <15753000 1>; 4074 opp-level = <5>; 4075 }; 4076 4077 /* GEN 5 x8 */ 4078 opp-256000000-5 { 4079 opp-hz = /bits/ 64 <256000000>; 4080 required-opps = <&rpmhpd_opp_nom>; 4081 opp-peak-kBps = <31506000 1>; 4082 opp-level = <5>; 4083 }; 4084 }; 4085 4086 pcie3a_port0: pcie@0 { 4087 device_type = "pci"; 4088 compatible = "pciclass,0604"; 4089 reg = <0x0 0x0 0x0 0x0 0x0>; 4090 bus-range = <0x01 0xff>; 4091 4092 phys = <&pcie3_phy 0>; 4093 4094 #address-cells = <3>; 4095 #size-cells = <2>; 4096 ranges; 4097 }; 4098 }; 4099 4100 rng: rng@10c3000 { 4101 compatible = "qcom,glymur-trng", "qcom,trng"; 4102 reg = <0x0 0x010c3000 0x0 0x1000>; 4103 }; 4104 4105 cryptobam: dma-controller@1dc4000 { 4106 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 4107 reg = <0x0 0x01dc4000 0x0 0x28000>; 4108 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 4109 #dma-cells = <1>; 4110 iommus = <&apps_smmu 0x80 0x0>, 4111 <&apps_smmu 0x81 0x0>; 4112 qcom,ee = <0>; 4113 qcom,controlled-remotely; 4114 num-channels = <20>; 4115 qcom,num-ees = <4>; 4116 }; 4117 4118 crypto: crypto@1dfa000 { 4119 compatible = "qcom,glymur-qce", "qcom,sm8150-qce", "qcom,qce"; 4120 reg = <0x0 0x01dfa000 0x0 0x6000>; 4121 dmas = <&cryptobam 4>, <&cryptobam 5>; 4122 dma-names = "rx", 4123 "tx"; 4124 iommus = <&apps_smmu 0x80 0x0>, 4125 <&apps_smmu 0x81 0x0>; 4126 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 4127 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4128 interconnect-names = "memory"; 4129 }; 4130 4131 tcsr_mutex: hwlock@1f40000 { 4132 compatible = "qcom,tcsr-mutex"; 4133 reg = <0x0 0x01f40000 0x0 0x20000>; 4134 4135 #hwlock-cells = <1>; 4136 }; 4137 4138 tcsr: clock-controller@1fd5000 { 4139 compatible = "qcom,glymur-tcsr", 4140 "syscon"; 4141 reg = <0x0 0x1fd5000 0x0 0x21000>; 4142 clocks = <&rpmhcc RPMH_CXO_CLK>; 4143 #clock-cells = <1>; 4144 #reset-cells = <1>; 4145 }; 4146 4147 hsc_noc: interconnect@2000000 { 4148 compatible = "qcom,glymur-hscnoc"; 4149 reg = <0x0 0x02000000 0x0 0x93a080>; 4150 qcom,bcm-voters = <&apps_bcm_voter>; 4151 #interconnect-cells = <2>; 4152 }; 4153 4154 gpu: gpu@3d00000 { 4155 compatible = "qcom,adreno-44070001", "qcom,adreno"; 4156 reg = <0x0 0x03d00000 0x0 0x6c000>, 4157 <0x0 0x03d9e000 0x0 0x2000>; 4158 reg-names = "kgsl_3d0_reg_memory", 4159 "cx_mem"; 4160 4161 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4162 4163 iommus = <&adreno_smmu 0 0x0>, 4164 <&adreno_smmu 1 0x0>; 4165 4166 operating-points-v2 = <&gpu_opp_table>; 4167 4168 qcom,gmu = <&gmu>; 4169 #cooling-cells = <2>; 4170 4171 interconnects = <&hsc_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4172 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4173 interconnect-names = "gfx-mem"; 4174 4175 gpu_opp_table: opp-table { 4176 compatible = "operating-points-v2-adreno", 4177 "operating-points-v2"; 4178 4179 opp-310000000 { 4180 opp-hz = /bits/ 64 <310000000>; 4181 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 4182 opp-peak-kBps = <2136719>; 4183 opp-supported-hw = <0xf>; 4184 /* ACD is disabled */ 4185 }; 4186 4187 opp-410000000 { 4188 opp-hz = /bits/ 64 <410000000>; 4189 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4190 opp-peak-kBps = <6074219>; 4191 opp-supported-hw = <0xf>; 4192 /* ACD is disabled */ 4193 }; 4194 4195 opp-572000000 { 4196 opp-hz = /bits/ 64 <572000000>; 4197 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4198 opp-peak-kBps = <12449219>; 4199 opp-supported-hw = <0xf>; 4200 qcom,opp-acd-level = <0xe02d5ffd>; 4201 }; 4202 4203 opp-760000000 { 4204 opp-hz = /bits/ 64 <760000000>; 4205 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4206 opp-peak-kBps = <12449219>; 4207 opp-supported-hw = <0xf>; 4208 qcom,opp-acd-level = <0xc0285ffd>; 4209 }; 4210 4211 opp-820000000 { 4212 opp-hz = /bits/ 64 <820000000>; 4213 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 4214 opp-peak-kBps = <16500000>; 4215 opp-supported-hw = <0xf>; 4216 qcom,opp-acd-level = <0xa82e5ffd>; 4217 }; 4218 4219 opp-915000000 { 4220 opp-hz = /bits/ 64 <915000000>; 4221 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4222 opp-peak-kBps = <16500000>; 4223 opp-supported-hw = <0xf>; 4224 qcom,opp-acd-level = <0x882d5ffd>; 4225 }; 4226 4227 opp-1070000000 { 4228 opp-hz = /bits/ 64 <1070000000>; 4229 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4230 opp-peak-kBps = <16500000>; 4231 opp-supported-hw = <0xf>; 4232 qcom,opp-acd-level = <0x882b5ffd>; 4233 }; 4234 4235 opp-1185000000 { 4236 opp-hz = /bits/ 64 <1185000000>; 4237 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4238 opp-peak-kBps = <16500000>; 4239 opp-supported-hw = <0xf>; 4240 qcom,opp-acd-level = <0x882a5ffd>; 4241 }; 4242 4243 opp-1350000000 { 4244 opp-hz = /bits/ 64 <1350000000>; 4245 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4246 opp-peak-kBps = <18597657>; 4247 opp-supported-hw = <0xf>; 4248 qcom,opp-acd-level = <0x882a5ffd>; 4249 }; 4250 4251 opp-1550000000 { 4252 opp-hz = /bits/ 64 <1550000000>; 4253 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 4254 opp-peak-kBps = <18597657>; 4255 opp-supported-hw = <0x7>; 4256 qcom,opp-acd-level = <0xa8295ffd>; 4257 }; 4258 4259 opp-1700000000 { 4260 opp-hz = /bits/ 64 <1700000000>; 4261 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 4262 opp-peak-kBps = <18597657>; 4263 opp-supported-hw = <0x7>; 4264 qcom,opp-acd-level = <0x88295ffd>; 4265 }; 4266 4267 opp-1850000000 { 4268 opp-hz = /bits/ 64 <1850000000>; 4269 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 4270 opp-peak-kBps = <18597657>; 4271 opp-supported-hw = <0x3>; 4272 qcom,opp-acd-level = <0x88285ffd>; 4273 }; 4274 }; 4275 }; 4276 4277 gxclkctl: clock-controller@3d64000 { 4278 compatible = "qcom,glymur-gxclkctl"; 4279 reg = <0x0 0x03d64000 0x0 0x6000>; 4280 4281 power-domains = <&rpmhpd RPMHPD_GFX>, 4282 <&rpmhpd RPMHPD_GMXC>, 4283 <&gpucc GPU_CC_CX_GDSC>; 4284 4285 #power-domain-cells = <1>; 4286 }; 4287 4288 gmu: gmu@3d6c000 { 4289 compatible = "qcom,adreno-gmu-x285.1", "qcom,adreno-gmu"; 4290 4291 reg = <0x0 0x03d6c000 0x0 0x32000>; 4292 reg-names = "gmu"; 4293 4294 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4295 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4296 interrupt-names = "hfi", 4297 "gmu"; 4298 4299 clocks = <&gpucc GPU_CC_AHB_CLK>, 4300 <&gpucc GPU_CC_CX_GMU_CLK>, 4301 <&gpucc GPU_CC_CXO_CLK>, 4302 <&gcc GCC_GPU_GEMNOC_GFX_CLK>, 4303 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4304 <&gpucc GPU_CC_RSCC_HUB_AON_CLK>; 4305 clock-names = "ahb", 4306 "gmu", 4307 "cxo", 4308 "memnoc", 4309 "hub", 4310 "rscc"; 4311 4312 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4313 <&gxclkctl GX_CLKCTL_GX_GDSC>; 4314 power-domain-names = "cx", 4315 "gx"; 4316 4317 iommus = <&adreno_smmu 5 0x0>; 4318 4319 qcom,qmp = <&aoss_qmp>; 4320 4321 operating-points-v2 = <&gmu_opp_table>; 4322 4323 gmu_opp_table: opp-table { 4324 compatible = "operating-points-v2"; 4325 4326 opp-575000000 { 4327 opp-hz = /bits/ 64 <575000000>; 4328 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4329 }; 4330 4331 opp-700000000 { 4332 opp-hz = /bits/ 64 <700000000>; 4333 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4334 }; 4335 4336 opp-725000000 { 4337 opp-hz = /bits/ 64 <725000000>; 4338 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4339 }; 4340 4341 opp-750000000 { 4342 opp-hz = /bits/ 64 <750000000>; 4343 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4344 }; 4345 }; 4346 }; 4347 4348 gpucc: clock-controller@3d90000 { 4349 compatible = "qcom,glymur-gpucc"; 4350 reg = <0x0 0x03d90000 0x0 0x9800>; 4351 clocks = <&rpmhcc RPMH_CXO_CLK>, 4352 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4353 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4354 4355 power-domains = <&rpmhpd RPMHPD_MX>, 4356 <&rpmhpd RPMHPD_CX>; 4357 required-opps = <&rpmhpd_opp_low_svs>, 4358 <&rpmhpd_opp_low_svs>; 4359 4360 #clock-cells = <1>; 4361 #reset-cells = <1>; 4362 #power-domain-cells = <1>; 4363 }; 4364 4365 adreno_smmu: iommu@3da0000 { 4366 compatible = "qcom,glymur-smmu-500", "qcom,adreno-smmu", 4367 "qcom,smmu-500", "arm,mmu-500"; 4368 reg = <0x0 0x03da0000 0x0 0x40000>; 4369 #iommu-cells = <2>; 4370 #global-interrupts = <1>; 4371 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 4372 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4373 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4374 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4375 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4377 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4378 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4379 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4380 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4381 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 4382 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 4383 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 4384 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 4385 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 4386 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 4387 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 4388 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 4389 <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>, 4390 <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4391 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 4392 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 4393 <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>, 4394 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 4395 <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>, 4396 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 4397 clocks = <&gpucc GPU_CC_GPU_SMMU_VOTE_CLK>; 4398 clock-names = "hlos"; 4399 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4400 dma-coherent; 4401 }; 4402 4403 ipcc: mailbox@3e04000 { 4404 compatible = "qcom,glymur-ipcc", "qcom,ipcc"; 4405 reg = <0x0 0x03e04000 0x0 0x1000>; 4406 4407 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 4408 interrupt-controller; 4409 #interrupt-cells = <3>; 4410 4411 #mbox-cells = <2>; 4412 }; 4413 4414 remoteproc_adsp: remoteproc@6800000 { 4415 compatible = "qcom,glymur-adsp-pas", "qcom,sm8550-adsp-pas"; 4416 reg = <0x0 0x06800000 0x0 0x10000>; 4417 4418 iommus = <&apps_smmu 0x1000 0x0>; 4419 4420 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4421 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 4422 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 4423 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 4424 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 4425 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 4426 interrupt-names = "wdog", 4427 "fatal", 4428 "ready", 4429 "handover", 4430 "stop-ack", 4431 "shutdown-ack"; 4432 4433 clocks = <&rpmhcc RPMH_CXO_CLK>; 4434 clock-names = "xo"; 4435 4436 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 4437 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4438 4439 power-domains = <&rpmhpd RPMHPD_LCX>, 4440 <&rpmhpd RPMHPD_LMX>; 4441 power-domain-names = "lcx", 4442 "lmx"; 4443 4444 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 4445 4446 qcom,qmp = <&aoss_qmp>; 4447 4448 qcom,smem-states = <&smp2p_adsp_out 0>; 4449 qcom,smem-state-names = "stop"; 4450 4451 status = "disabled"; 4452 4453 remoteproc_adsp_glink: glink-edge { 4454 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 4455 IPCC_MPROC_SIGNAL_GLINK_QMP 4456 IRQ_TYPE_EDGE_RISING>; 4457 4458 mboxes = <&ipcc IPCC_MPROC_LPASS 4459 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4460 4461 qcom,remote-pid = <2>; 4462 4463 label = "lpass"; 4464 4465 fastrpc { 4466 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 4467 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4468 label = "adsp"; 4469 memory-region = <&adsp_rpc_remote_heap_mem>; 4470 qcom,vmids = <QCOM_SCM_VMID_LPASS 4471 QCOM_SCM_VMID_ADSP_HEAP>; 4472 #address-cells = <1>; 4473 #size-cells = <0>; 4474 4475 compute-cb@3 { 4476 compatible = "qcom,fastrpc-compute-cb"; 4477 reg = <3>; 4478 4479 iommus = <&apps_smmu 0x1003 0x80>, 4480 <&apps_smmu 0x1063 0x20>; 4481 dma-coherent; 4482 }; 4483 4484 compute-cb@4 { 4485 compatible = "qcom,fastrpc-compute-cb"; 4486 reg = <4>; 4487 4488 iommus = <&apps_smmu 0x1004 0x80>, 4489 <&apps_smmu 0x1064 0x20>; 4490 dma-coherent; 4491 }; 4492 4493 compute-cb@5 { 4494 compatible = "qcom,fastrpc-compute-cb"; 4495 reg = <5>; 4496 4497 iommus = <&apps_smmu 0x1005 0x80>, 4498 <&apps_smmu 0x1065 0x20>; 4499 dma-coherent; 4500 }; 4501 4502 compute-cb@6 { 4503 compatible = "qcom,fastrpc-compute-cb"; 4504 reg = <6>; 4505 4506 iommus = <&apps_smmu 0x1006 0x80>, 4507 <&apps_smmu 0x1066 0x20>; 4508 dma-coherent; 4509 }; 4510 4511 compute-cb@7 { 4512 compatible = "qcom,fastrpc-compute-cb"; 4513 reg = <7>; 4514 4515 iommus = <&apps_smmu 0x1007 0x40>, 4516 <&apps_smmu 0x1067 0x0>, 4517 <&apps_smmu 0x1087 0x0>; 4518 dma-coherent; 4519 }; 4520 4521 compute-cb@8 { 4522 compatible = "qcom,fastrpc-compute-cb"; 4523 reg = <8>; 4524 4525 iommus = <&apps_smmu 0x1008 0x80>, 4526 <&apps_smmu 0x1068 0x20>; 4527 dma-coherent; 4528 }; 4529 }; 4530 4531 gpr { 4532 compatible = "qcom,gpr"; 4533 qcom,glink-channels = "adsp_apps"; 4534 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 4535 qcom,intents = <512 20>; 4536 #address-cells = <1>; 4537 #size-cells = <0>; 4538 4539 q6apm: service@1 { 4540 compatible = "qcom,q6apm"; 4541 reg = <GPR_APM_MODULE_IID>; 4542 #sound-dai-cells = <0>; 4543 qcom,protection-domain = "avs/audio", 4544 "msm/adsp/audio_pd"; 4545 4546 q6apmbedai: bedais { 4547 compatible = "qcom,q6apm-lpass-dais"; 4548 #sound-dai-cells = <1>; 4549 }; 4550 4551 q6apmdai: dais { 4552 compatible = "qcom,q6apm-dais"; 4553 iommus = <&apps_smmu 0x1001 0x80>, 4554 <&apps_smmu 0x1061 0x20>; 4555 }; 4556 }; 4557 4558 q6prm: service@2 { 4559 compatible = "qcom,q6prm"; 4560 reg = <GPR_PRM_MODULE_IID>; 4561 qcom,protection-domain = "avs/audio", 4562 "msm/adsp/audio_pd"; 4563 4564 q6prmcc: clock-controller { 4565 compatible = "qcom,q6prm-lpass-clocks"; 4566 #clock-cells = <2>; 4567 }; 4568 }; 4569 }; 4570 }; 4571 }; 4572 4573 swr0: soundwire@6c80000 { 4574 compatible = "qcom,soundwire-v3.1.0"; 4575 reg = <0x0 0x06c80000 0x0 0x10000>; 4576 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 4577 clocks = <&lpass_wsamacro>; 4578 clock-names = "iface"; 4579 label = "WSA"; 4580 4581 pinctrl-0 = <&wsa_swr_active>; 4582 pinctrl-names = "default"; 4583 4584 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; 4585 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; 4586 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; 4587 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4588 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; 4589 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; 4590 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; 4591 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4592 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4593 #address-cells = <2>; 4594 #size-cells = <0>; 4595 #sound-dai-cells = <1>; 4596 status = "disabled"; 4597 }; 4598 4599 lpass_wsamacro: codec@6c90000 { 4600 compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4601 reg = <0x0 0x06c90000 0x0 0x1000>; 4602 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4603 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4604 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4605 <&lpass_vamacro>; 4606 clock-names = "mclk", 4607 "macro", 4608 "dcodec", 4609 "fsgen"; 4610 4611 #clock-cells = <0>; 4612 clock-output-names = "mclk"; 4613 #sound-dai-cells = <1>; 4614 sound-name-prefix = "WSA"; 4615 }; 4616 4617 swr3: soundwire@6ca0000 { 4618 compatible = "qcom,soundwire-v3.1.0"; 4619 reg = <0x0 0x06ca0000 0x0 0x10000>; 4620 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 4621 clocks = <&lpass_wsa2macro>; 4622 clock-names = "iface"; 4623 label = "WSA2"; 4624 4625 pinctrl-0 = <&wsa2_swr_active>; 4626 pinctrl-names = "default"; 4627 4628 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x01 0x00 0x00 0x01 0x01>; 4629 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x18 0x18 0xff 0xff>; 4630 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0xff 0xff 0x06 0x0d 0x0 0x19 0x06 0x06>; 4631 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4632 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0xff 0xff 0x0f 0x0f 0x31f 0x31f 0x0f 0x0f >; 4633 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0xf 0xf 0xff 0xff>; 4634 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff 0x0f 0x0f 0xff 0xff>; 4635 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4636 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 4637 4638 #address-cells = <2>; 4639 #size-cells = <0>; 4640 #sound-dai-cells = <1>; 4641 status = "disabled"; 4642 }; 4643 4644 lpass_wsa2macro: codec@6cb0000 { 4645 compatible = "qcom,glymur-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 4646 reg = <0x0 0x06cb0000 0x0 0x1000>; 4647 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4648 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4649 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4650 <&lpass_vamacro>; 4651 clock-names = "mclk", 4652 "macro", 4653 "dcodec", 4654 "fsgen"; 4655 4656 #clock-cells = <0>; 4657 clock-output-names = "wsa2-mclk"; 4658 #sound-dai-cells = <1>; 4659 sound-name-prefix = "WSA2"; 4660 }; 4661 4662 lpass_lpiaon_noc: interconnect@7400000 { 4663 compatible = "qcom,glymur-lpass-lpiaon-noc"; 4664 reg = <0x0 0x07400000 0x0 0x19080>; 4665 qcom,bcm-voters = <&apps_bcm_voter>; 4666 #interconnect-cells = <2>; 4667 }; 4668 4669 lpass_lpicx_noc: interconnect@7420000 { 4670 compatible = "qcom,glymur-lpass-lpicx-noc"; 4671 reg = <0x0 0x07420000 0x0 0x44080>; 4672 qcom,bcm-voters = <&apps_bcm_voter>; 4673 #interconnect-cells = <2>; 4674 }; 4675 4676 lpass_vamacro: codec@7660000 { 4677 compatible = "qcom,glymur-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 4678 reg = <0x0 0x07660000 0x0 0x2000>; 4679 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4680 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4681 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4682 clock-names = "mclk", 4683 "macro", 4684 "dcodec"; 4685 4686 #clock-cells = <0>; 4687 clock-output-names = "fsgen"; 4688 #sound-dai-cells = <1>; 4689 }; 4690 4691 lpass_tlmm: pinctrl@7760000 { 4692 compatible = "qcom,glymur-lpass-lpi-pinctrl", "qcom,sm8650-lpass-lpi-pinctrl"; 4693 reg = <0x0 0x07760000 0x0 0x20000>; 4694 4695 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4696 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4697 clock-names = "core", "audio"; 4698 4699 gpio-controller; 4700 #gpio-cells = <2>; 4701 gpio-ranges = <&lpass_tlmm 0 0 23>; 4702 4703 tx_swr_active: tx-swr-active-state { 4704 clk-pins { 4705 pins = "gpio0"; 4706 function = "swr_tx_clk"; 4707 drive-strength = <2>; 4708 slew-rate = <1>; 4709 bias-disable; 4710 }; 4711 4712 data-pins { 4713 pins = "gpio1", "gpio2"; 4714 function = "swr_tx_data"; 4715 drive-strength = <2>; 4716 slew-rate = <1>; 4717 bias-bus-hold; 4718 }; 4719 }; 4720 4721 rx_swr_active: rx-swr-active-state { 4722 clk-pins { 4723 pins = "gpio3"; 4724 function = "swr_rx_clk"; 4725 drive-strength = <2>; 4726 slew-rate = <1>; 4727 bias-disable; 4728 }; 4729 4730 data-pins { 4731 pins = "gpio4", "gpio5"; 4732 function = "swr_rx_data"; 4733 drive-strength = <2>; 4734 slew-rate = <1>; 4735 bias-bus-hold; 4736 }; 4737 }; 4738 4739 dmic01_default: dmic01-default-state { 4740 clk-pins { 4741 pins = "gpio6"; 4742 function = "dmic1_clk"; 4743 drive-strength = <8>; 4744 output-high; 4745 }; 4746 4747 data-pins { 4748 pins = "gpio7"; 4749 function = "dmic1_data"; 4750 drive-strength = <8>; 4751 input-enable; 4752 }; 4753 }; 4754 4755 dmic23_default: dmic23-default-state { 4756 clk-pins { 4757 pins = "gpio8"; 4758 function = "dmic2_clk"; 4759 drive-strength = <8>; 4760 output-high; 4761 }; 4762 4763 data-pins { 4764 pins = "gpio9"; 4765 function = "dmic2_data"; 4766 drive-strength = <8>; 4767 input-enable; 4768 }; 4769 }; 4770 4771 wsa_swr_active: wsa-swr-active-state { 4772 clk-pins { 4773 pins = "gpio10"; 4774 function = "wsa_swr_clk"; 4775 drive-strength = <2>; 4776 slew-rate = <1>; 4777 bias-disable; 4778 }; 4779 4780 data-pins { 4781 pins = "gpio11"; 4782 function = "wsa_swr_data"; 4783 drive-strength = <2>; 4784 slew-rate = <1>; 4785 bias-bus-hold; 4786 }; 4787 }; 4788 4789 wsa2_swr_active: wsa2-swr-active-state { 4790 clk-pins { 4791 pins = "gpio15"; 4792 function = "wsa2_swr_clk"; 4793 drive-strength = <2>; 4794 slew-rate = <1>; 4795 bias-disable; 4796 }; 4797 4798 data-pins { 4799 pins = "gpio16"; 4800 function = "wsa2_swr_data"; 4801 drive-strength = <2>; 4802 slew-rate = <1>; 4803 bias-bus-hold; 4804 }; 4805 }; 4806 }; 4807 4808 lpass_ag_noc: interconnect@7e40000 { 4809 compatible = "qcom,glymur-lpass-ag-noc"; 4810 reg = <0x0 0x07e40000 0x0 0xe080>; 4811 qcom,bcm-voters = <&apps_bcm_voter>; 4812 #interconnect-cells = <2>; 4813 }; 4814 4815 sdhc_2: mmc@8804000 { 4816 compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5"; 4817 4818 reg = <0x0 0x08804000 0x0 0x1000>; 4819 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4820 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4821 interrupt-names = "hc_irq", 4822 "pwr_irq"; 4823 4824 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4825 <&gcc GCC_SDCC2_APPS_CLK>, 4826 <&rpmhcc RPMH_CXO_CLK>; 4827 clock-names = "iface", 4828 "core", 4829 "xo"; 4830 4831 iommus = <&apps_smmu 0xd00 0x0>; 4832 qcom,dll-config = <0x0007442c>; 4833 qcom,ddr-config = <0x80040868>; 4834 4835 power-domains = <&rpmhpd RPMHPD_CX>; 4836 operating-points-v2 = <&sdhc2_opp_table>; 4837 4838 interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 4839 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4840 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4841 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 4842 interconnect-names = "sdhc-ddr", 4843 "cpu-sdhc"; 4844 4845 bus-width = <4>; 4846 dma-coherent; 4847 4848 resets = <&gcc GCC_SDCC2_BCR>; 4849 4850 status = "disabled"; 4851 4852 sdhc2_opp_table: opp-table { 4853 compatible = "operating-points-v2"; 4854 4855 opp-100000000 { 4856 opp-hz = /bits/ 64 <100000000>; 4857 required-opps = <&rpmhpd_opp_low_svs>; 4858 }; 4859 4860 opp-202000000 { 4861 opp-hz = /bits/ 64 <202000000>; 4862 required-opps = <&rpmhpd_opp_nom>; 4863 }; 4864 }; 4865 }; 4866 4867 usb_2_hsphy: phy@88e0000 { 4868 compatible = "qcom,glymur-m31-eusb2-phy", 4869 "qcom,sm8750-m31-eusb2-phy"; 4870 4871 reg = <0x0 0x088e0000 0x0 0x29c>; 4872 #phy-cells = <0>; 4873 4874 clocks = <&tcsr TCSR_USB2_4_CLKREF_EN>; 4875 clock-names = "ref"; 4876 4877 resets = <&gcc GCC_QUSB2PHY_TERT_BCR>; 4878 4879 status = "disabled"; 4880 }; 4881 4882 usb_2_qmpphy: phy@88e1000 { 4883 compatible = "qcom,glymur-qmp-usb3-dp-phy"; 4884 reg = <0x0 0x088e1000 0x0 0x8000>; 4885 4886 clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>, 4887 <&tcsr TCSR_USB4_2_CLKREF_EN>, 4888 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>, 4889 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>; 4890 clock-names = "aux", 4891 "ref", 4892 "com_aux", 4893 "usb3_pipe"; 4894 4895 power-domains = <&gcc GCC_USB_2_PHY_GDSC>; 4896 4897 resets = <&gcc GCC_USB3_PHY_TERT_BCR>, 4898 <&gcc GCC_USB3PHY_PHY_TERT_BCR>; 4899 reset-names = "phy", 4900 "common"; 4901 4902 #clock-cells = <1>; 4903 #phy-cells = <1>; 4904 4905 mode-switch; 4906 orientation-switch; 4907 4908 status = "disabled"; 4909 4910 ports { 4911 #address-cells = <1>; 4912 #size-cells = <0>; 4913 4914 port@0 { 4915 reg = <0>; 4916 4917 usb_2_qmpphy_out: endpoint { 4918 }; 4919 }; 4920 4921 port@1 { 4922 reg = <1>; 4923 4924 usb_2_qmpphy_usb_ss_in: endpoint { 4925 remote-endpoint = <&usb_2_dwc3_ss>; 4926 }; 4927 }; 4928 4929 port@2 { 4930 reg = <2>; 4931 4932 usb_2_qmpphy_dp_in: endpoint { 4933 remote-endpoint = <&mdss_dp2_out>; 4934 }; 4935 }; 4936 }; 4937 }; 4938 4939 usb_0: usb@a600000 { 4940 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 4941 reg = <0x0 0x0a600000 0x0 0xfc100>; 4942 4943 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4944 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4945 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4946 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4947 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4948 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 4949 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 4950 clock-names = "cfg_noc", 4951 "core", 4952 "iface", 4953 "sleep", 4954 "mock_utmi", 4955 "noc_aggr_north", 4956 "noc_aggr_south"; 4957 4958 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4959 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4960 assigned-clock-rates = <19200000>, <200000000>; 4961 4962 interrupts-extended = <&intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 4963 <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 4964 <&pdc 90 IRQ_TYPE_EDGE_BOTH>, 4965 <&pdc 60 IRQ_TYPE_EDGE_BOTH>, 4966 <&pdc 17 IRQ_TYPE_EDGE_BOTH>; 4967 interrupt-names = "dwc_usb3", 4968 "pwr_event", 4969 "dp_hs_phy_irq", 4970 "dm_hs_phy_irq", 4971 "ss_phy_irq"; 4972 4973 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4974 required-opps = <&rpmhpd_opp_nom>; 4975 resets = <&gcc GCC_USB30_PRIM_BCR>; 4976 4977 iommus = <&apps_smmu 0x1420 0x0>; 4978 4979 interconnects = <&aggre4_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4980 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4981 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4982 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 4983 interconnect-names = "usb-ddr", 4984 "apps-usb"; 4985 4986 phys = <&usb_0_hsphy>, 4987 <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 4988 phy-names = "usb2-phy", 4989 "usb3-phy"; 4990 4991 snps,hird-threshold = /bits/ 8 <0x0>; 4992 snps,dis-u1-entry-quirk; 4993 snps,dis-u2-entry-quirk; 4994 snps,is-utmi-l1-suspend; 4995 snps,usb3_lpm_capable; 4996 snps,has-lpm-erratum; 4997 tx-fifo-resize; 4998 snps,dis_u2_susphy_quirk; 4999 snps,dis_enblslpm_quirk; 5000 5001 usb-role-switch; 5002 wakeup-source; 5003 5004 dma-coherent; 5005 5006 status = "disabled"; 5007 5008 ports { 5009 #address-cells = <1>; 5010 #size-cells = <0>; 5011 5012 port@0 { 5013 reg = <0>; 5014 5015 usb_0_dwc3_hs: endpoint { 5016 }; 5017 }; 5018 5019 port@1 { 5020 reg = <1>; 5021 5022 usb_0_dwc3_ss: endpoint { 5023 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 5024 }; 5025 }; 5026 }; 5027 }; 5028 5029 usb_1: usb@a800000 { 5030 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 5031 reg = <0x0 0x0a800000 0x0 0xfc100>; 5032 5033 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 5034 <&gcc GCC_USB30_SEC_MASTER_CLK>, 5035 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 5036 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 5037 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5038 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 5039 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 5040 clock-names = "cfg_noc", 5041 "core", 5042 "iface", 5043 "sleep", 5044 "mock_utmi", 5045 "noc_aggr_north", 5046 "noc_aggr_south"; 5047 5048 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 5049 <&gcc GCC_USB30_SEC_MASTER_CLK>; 5050 assigned-clock-rates = <19200000>, <200000000>; 5051 5052 interrupts-extended = <&intc GIC_SPI 875 IRQ_TYPE_LEVEL_HIGH>, 5053 <&intc GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 5054 <&pdc 88 IRQ_TYPE_EDGE_BOTH>, 5055 <&pdc 87 IRQ_TYPE_EDGE_BOTH>, 5056 <&pdc 76 IRQ_TYPE_EDGE_BOTH>; 5057 interrupt-names = "dwc_usb3", 5058 "pwr_event", 5059 "dp_hs_phy_irq", 5060 "dm_hs_phy_irq", 5061 "ss_phy_irq"; 5062 5063 resets = <&gcc GCC_USB30_SEC_BCR>; 5064 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 5065 required-opps = <&rpmhpd_opp_nom>; 5066 5067 iommus = <&apps_smmu 0x1460 0x0>; 5068 5069 interconnects = <&aggre4_noc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS 5070 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5071 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5072 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5073 interconnect-names = "usb-ddr", 5074 "apps-usb"; 5075 5076 phys = <&usb_1_hsphy>, 5077 <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 5078 phy-names = "usb2-phy", 5079 "usb3-phy"; 5080 5081 snps,hird-threshold = /bits/ 8 <0x0>; 5082 snps,dis-u1-entry-quirk; 5083 snps,dis-u2-entry-quirk; 5084 snps,is-utmi-l1-suspend; 5085 snps,usb3_lpm_capable; 5086 snps,has-lpm-erratum; 5087 tx-fifo-resize; 5088 snps,dis_u2_susphy_quirk; 5089 snps,dis_enblslpm_quirk; 5090 5091 usb-role-switch; 5092 wakeup-source; 5093 5094 dma-coherent; 5095 5096 status = "disabled"; 5097 5098 ports { 5099 #address-cells = <1>; 5100 #size-cells = <0>; 5101 5102 port@0 { 5103 reg = <0>; 5104 5105 usb_1_dwc3_hs: endpoint { 5106 }; 5107 }; 5108 5109 port@1 { 5110 reg = <1>; 5111 5112 usb_1_dwc3_ss: endpoint { 5113 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 5114 }; 5115 }; 5116 }; 5117 }; 5118 5119 usb_2: usb@a000000 { 5120 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 5121 reg = <0x0 0x0a000000 0x0 0xfc100>; 5122 5123 clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>, 5124 <&gcc GCC_USB30_TERT_MASTER_CLK>, 5125 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>, 5126 <&gcc GCC_USB30_TERT_SLEEP_CLK>, 5127 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5128 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 5129 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 5130 clock-names = "cfg_noc", 5131 "core", 5132 "iface", 5133 "sleep", 5134 "mock_utmi", 5135 "noc_aggr_north", 5136 "noc_aggr_south"; 5137 5138 assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>, 5139 <&gcc GCC_USB30_TERT_MASTER_CLK>; 5140 assigned-clock-rates = <19200000>, <200000000>; 5141 5142 interrupts-extended = <&intc GIC_SPI 871 IRQ_TYPE_LEVEL_HIGH>, 5143 <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 5144 <&pdc 89 IRQ_TYPE_EDGE_BOTH>, 5145 <&pdc 81 IRQ_TYPE_EDGE_BOTH>, 5146 <&pdc 75 IRQ_TYPE_EDGE_BOTH>; 5147 interrupt-names = "dwc_usb3", 5148 "pwr_event", 5149 "dp_hs_phy_irq", 5150 "dm_hs_phy_irq", 5151 "ss_phy_irq"; 5152 5153 resets = <&gcc GCC_USB30_TERT_BCR>; 5154 power-domains = <&gcc GCC_USB30_TERT_GDSC>; 5155 required-opps = <&rpmhpd_opp_nom>; 5156 5157 iommus = <&apps_smmu 0x420 0x0>; 5158 5159 interconnects = <&aggre2_noc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS 5160 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5161 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5162 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5163 interconnect-names = "usb-ddr", 5164 "apps-usb"; 5165 5166 phys = <&usb_2_hsphy>, 5167 <&usb_2_qmpphy QMP_USB43DP_USB3_PHY>; 5168 phy-names = "usb2-phy", 5169 "usb3-phy"; 5170 5171 snps,hird-threshold = /bits/ 8 <0x0>; 5172 snps,dis-u1-entry-quirk; 5173 snps,dis-u2-entry-quirk; 5174 snps,is-utmi-l1-suspend; 5175 snps,usb3_lpm_capable; 5176 snps,has-lpm-erratum; 5177 tx-fifo-resize; 5178 snps,dis_u2_susphy_quirk; 5179 snps,dis_enblslpm_quirk; 5180 5181 usb-role-switch; 5182 wakeup-source; 5183 5184 dma-coherent; 5185 5186 status = "disabled"; 5187 5188 ports { 5189 #address-cells = <1>; 5190 #size-cells = <0>; 5191 5192 port@0 { 5193 reg = <0>; 5194 5195 usb_2_dwc3_hs: endpoint { 5196 }; 5197 }; 5198 5199 port@1 { 5200 reg = <1>; 5201 5202 usb_2_dwc3_ss: endpoint { 5203 remote-endpoint = <&usb_2_qmpphy_usb_ss_in>; 5204 }; 5205 }; 5206 }; 5207 }; 5208 5209 usb_hs: usb@a200000 { 5210 compatible = "qcom,glymur-dwc3", "qcom,snps-dwc3"; 5211 reg = <0x0 0x0a200000 0x0 0xfc100>; 5212 5213 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5214 <&gcc GCC_USB20_MASTER_CLK>, 5215 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5216 <&gcc GCC_USB20_SLEEP_CLK>, 5217 <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5218 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 5219 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 5220 clock-names = "cfg_noc", 5221 "core", 5222 "iface", 5223 "sleep", 5224 "mock_utmi", 5225 "noc_aggr_north", 5226 "noc_aggr_south"; 5227 5228 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5229 <&gcc GCC_USB20_MASTER_CLK>; 5230 assigned-clock-rates = <19200000>, <200000000>; 5231 5232 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 5233 <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 5234 <&pdc 92 IRQ_TYPE_EDGE_BOTH>, 5235 <&pdc 57 IRQ_TYPE_EDGE_BOTH>, 5236 <&intc GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 5237 interrupt-names = "dwc_usb3", 5238 "pwr_event", 5239 "dp_hs_phy_irq", 5240 "dm_hs_phy_irq", 5241 "hs_phy_irq"; 5242 5243 resets = <&gcc GCC_USB20_PRIM_BCR>; 5244 5245 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5246 required-opps = <&rpmhpd_opp_nom>; 5247 5248 iommus = <&apps_smmu 0x0ce0 0x0>; 5249 5250 interconnects = <&aggre3_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5251 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5252 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5253 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>; 5254 interconnect-names = "usb-ddr", 5255 "apps-usb"; 5256 5257 phys = <&usb_hs_phy>; 5258 phy-names = "usb2-phy"; 5259 5260 snps,hird-threshold = /bits/ 8 <0x0>; 5261 snps,dis-u1-entry-quirk; 5262 snps,dis-u2-entry-quirk; 5263 snps,is-utmi-l1-suspend; 5264 snps,usb3_lpm_capable; 5265 snps,has-lpm-erratum; 5266 tx-fifo-resize; 5267 snps,dis_u2_susphy_quirk; 5268 snps,dis_enblslpm_quirk; 5269 5270 maximum-speed = "high-speed"; 5271 5272 qcom,select-utmi-as-pipe-clk; 5273 usb-role-switch; 5274 wakeup-source; 5275 5276 dma-coherent; 5277 5278 status = "disabled"; 5279 }; 5280 5281 usb_mp: usb@a400000 { 5282 compatible = "qcom,glymur-dwc3-mp", "qcom,snps-dwc3"; 5283 reg = <0x0 0x0a400000 0x0 0xfc100>; 5284 5285 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 5286 <&gcc GCC_USB30_MP_MASTER_CLK>, 5287 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 5288 <&gcc GCC_USB30_MP_SLEEP_CLK>, 5289 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5290 <&gcc GCC_CFG_NOC_USB_ANOC_AHB_CLK>, 5291 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>; 5292 clock-names = "cfg_noc", 5293 "core", 5294 "iface", 5295 "sleep", 5296 "mock_utmi", 5297 "noc_aggr_north", 5298 "noc_aggr_south"; 5299 5300 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 5301 <&gcc GCC_USB30_MP_MASTER_CLK>; 5302 assigned-clock-rates = <19200000>, <200000000>; 5303 5304 interrupts-extended = <&intc GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 5305 <&intc GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5306 <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 5307 <&intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 5308 <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 5309 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>, 5310 <&pdc 11 IRQ_TYPE_LEVEL_HIGH>, 5311 <&pdc 14 IRQ_TYPE_LEVEL_HIGH>, 5312 <&pdc 13 IRQ_TYPE_LEVEL_HIGH>, 5313 <&pdc 78 IRQ_TYPE_LEVEL_HIGH>, 5314 <&pdc 77 IRQ_TYPE_LEVEL_HIGH>; 5315 interrupt-names = "dwc_usb3", 5316 "pwr_event_1", 5317 "pwr_event_2", 5318 "hs_phy_1", 5319 "hs_phy_2", 5320 "dp_hs_phy_1", 5321 "dm_hs_phy_1", 5322 "dp_hs_phy_2", 5323 "dm_hs_phy_2", 5324 "ss_phy_1", 5325 "ss_phy_2"; 5326 5327 resets = <&gcc GCC_USB30_MP_BCR>; 5328 power-domains = <&gcc GCC_USB30_MP_GDSC>; 5329 required-opps = <&rpmhpd_opp_nom>; 5330 5331 iommus = <&apps_smmu 0xda0 0x0>; 5332 5333 interconnects = <&aggre3_noc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS 5334 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5335 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5336 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>; 5337 interconnect-names = "usb-ddr", 5338 "apps-usb"; 5339 5340 phys = <&usb_mp_hsphy0>, 5341 <&usb_mp_qmpphy0>, 5342 <&usb_mp_hsphy1>, 5343 <&usb_mp_qmpphy1>; 5344 phy-names = "usb2-0", 5345 "usb3-0", 5346 "usb2-1", 5347 "usb3-1"; 5348 5349 snps,hird-threshold = /bits/ 8 <0x0>; 5350 snps,dis-u1-entry-quirk; 5351 snps,dis-u2-entry-quirk; 5352 snps,is-utmi-l1-suspend; 5353 snps,usb3_lpm_capable; 5354 snps,has-lpm-erratum; 5355 tx-fifo-resize; 5356 snps,dis_u2_susphy_quirk; 5357 snps,dis_enblslpm_quirk; 5358 5359 dr_mode = "host"; 5360 wakeup-source; 5361 5362 dma-coherent; 5363 5364 status = "disabled"; 5365 }; 5366 5367 camcc: clock-controller@ade0000 { 5368 compatible = "qcom,glymur-camcc"; 5369 reg = <0x0 0x0ade0000 0x0 0x20000>; 5370 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5371 <&rpmhcc RPMH_CXO_CLK>, 5372 <&rpmhcc RPMH_CXO_CLK_A>, 5373 <&sleep_clk>; 5374 power-domains = <&rpmhpd RPMHPD_MXC>, 5375 <&rpmhpd RPMHPD_MMCX>; 5376 required-opps = <&rpmhpd_opp_low_svs>, 5377 <&rpmhpd_opp_low_svs>; 5378 #clock-cells = <1>; 5379 #reset-cells = <1>; 5380 #power-domain-cells = <1>; 5381 }; 5382 5383 mdss: display-subsystem@ae00000 { 5384 compatible = "qcom,glymur-mdss"; 5385 reg = <0x0 0x0ae00000 0x0 0x1000>; 5386 reg-names = "mdss"; 5387 5388 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5389 5390 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5391 <&gcc GCC_DISP_HF_AXI_CLK>, 5392 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5393 5394 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5395 5396 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 5397 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5398 <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5399 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5400 interconnect-names = "mdp0-mem", 5401 "cpu-cfg"; 5402 5403 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 5404 5405 iommus = <&apps_smmu 0x1de0 0x2>; 5406 5407 interrupt-controller; 5408 #interrupt-cells = <1>; 5409 5410 #address-cells = <2>; 5411 #size-cells = <2>; 5412 ranges; 5413 5414 status = "disabled"; 5415 5416 mdss_mdp: display-controller@ae01000 { 5417 compatible = "qcom,glymur-dpu"; 5418 reg = <0x0 0x0ae01000 0x0 0x93000>, 5419 <0x0 0x0aeb0000 0x0 0x3000>; 5420 reg-names = "mdp", 5421 "vbif"; 5422 5423 interrupts-extended = <&mdss 0>; 5424 5425 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5426 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5427 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5428 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5429 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5430 clock-names = "nrt_bus", 5431 "iface", 5432 "lut", 5433 "core", 5434 "vsync"; 5435 5436 operating-points-v2 = <&mdp_opp_table>; 5437 5438 power-domains = <&rpmhpd RPMHPD_MMCX>; 5439 5440 ports { 5441 #address-cells = <1>; 5442 #size-cells = <0>; 5443 5444 port@0 { 5445 reg = <0>; 5446 5447 dpu_intf0_out: endpoint { 5448 remote-endpoint = <&mdss_dp0_in>; 5449 }; 5450 }; 5451 5452 port@4 { 5453 reg = <4>; 5454 5455 mdss_intf4_out: endpoint { 5456 remote-endpoint = <&mdss_dp1_in>; 5457 }; 5458 }; 5459 5460 port@5 { 5461 reg = <5>; 5462 5463 mdss_intf5_out: endpoint { 5464 remote-endpoint = <&mdss_dp3_in>; 5465 }; 5466 }; 5467 5468 port@6 { 5469 reg = <6>; 5470 5471 mdss_intf6_out: endpoint { 5472 remote-endpoint = <&mdss_dp2_in>; 5473 }; 5474 }; 5475 }; 5476 5477 mdp_opp_table: opp-table { 5478 compatible = "operating-points-v2"; 5479 5480 opp-156000000 { 5481 opp-hz = /bits/ 64 <156000000>; 5482 required-opps = <&rpmhpd_opp_low_svs_d1>; 5483 }; 5484 5485 opp-205000000 { 5486 opp-hz = /bits/ 64 <205000000>; 5487 required-opps = <&rpmhpd_opp_low_svs>; 5488 }; 5489 5490 opp-337000000 { 5491 opp-hz = /bits/ 64 <337000000>; 5492 required-opps = <&rpmhpd_opp_svs>; 5493 }; 5494 5495 opp-417000000 { 5496 opp-hz = /bits/ 64 <417000000>; 5497 required-opps = <&rpmhpd_opp_svs_l1>; 5498 }; 5499 5500 opp-532000000 { 5501 opp-hz = /bits/ 64 <532000000>; 5502 required-opps = <&rpmhpd_opp_nom>; 5503 }; 5504 5505 opp-600000000 { 5506 opp-hz = /bits/ 64 <600000000>; 5507 required-opps = <&rpmhpd_opp_nom_l1>; 5508 }; 5509 5510 opp-660000000 { 5511 opp-hz = /bits/ 64 <660000000>; 5512 required-opps = <&rpmhpd_opp_turbo>; 5513 }; 5514 5515 opp-717000000 { 5516 opp-hz = /bits/ 64 <717000000>; 5517 required-opps = <&rpmhpd_opp_turbo_l1>; 5518 }; 5519 }; 5520 }; 5521 5522 mdss_dp0: displayport-controller@af54000 { 5523 compatible = "qcom,glymur-dp"; 5524 reg = <0x0 0xaf54000 0x0 0x200>, 5525 <0x0 0xaf54200 0x0 0x200>, 5526 <0x0 0xaf55000 0x0 0xc00>, 5527 <0x0 0xaf56000 0x0 0x400>, 5528 <0x0 0xaf57000 0x0 0x400>, 5529 <0x0 0xaf58000 0x0 0x400>, 5530 <0x0 0xaf59000 0x0 0x400>, 5531 <0x0 0xaf5a000 0x0 0x600>, 5532 <0x0 0xaf5b000 0x0 0x600>; 5533 5534 interrupts-extended = <&mdss 12>; 5535 5536 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5537 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 5538 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 5539 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5540 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5541 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>; 5542 clock-names = "core_iface", 5543 "core_aux", 5544 "ctrl_link", 5545 "ctrl_link_iface", 5546 "stream_pixel", 5547 "stream_1_pixel"; 5548 5549 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5550 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5551 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; 5552 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5553 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5554 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5555 5556 operating-points-v2 = <&mdss_dp0_opp_table>; 5557 5558 power-domains = <&rpmhpd RPMHPD_MMCX>; 5559 5560 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 5561 phy-names = "dp"; 5562 5563 #sound-dai-cells = <0>; 5564 5565 status = "disabled"; 5566 5567 ports { 5568 #address-cells = <1>; 5569 #size-cells = <0>; 5570 5571 port@0 { 5572 reg = <0>; 5573 5574 mdss_dp0_in: endpoint { 5575 remote-endpoint = <&dpu_intf0_out>; 5576 }; 5577 }; 5578 5579 port@1 { 5580 reg = <1>; 5581 5582 mdss_dp0_out: endpoint { 5583 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5584 }; 5585 }; 5586 }; 5587 5588 mdss_dp0_opp_table: opp-table { 5589 compatible = "operating-points-v2"; 5590 5591 opp-270000000 { 5592 opp-hz = /bits/ 64 <270000000>; 5593 required-opps = <&rpmhpd_opp_low_svs>; 5594 }; 5595 5596 opp-540000000 { 5597 opp-hz = /bits/ 64 <540000000>; 5598 required-opps = <&rpmhpd_opp_svs>; 5599 }; 5600 5601 opp-675000000 { 5602 opp-hz = /bits/ 64 <675000000>; 5603 required-opps = <&rpmhpd_opp_svs_l1>; 5604 }; 5605 5606 opp-810000000 { 5607 opp-hz = /bits/ 64 <810000000>; 5608 required-opps = <&rpmhpd_opp_nom>; 5609 }; 5610 }; 5611 }; 5612 5613 mdss_dp1: displayport-controller@af5c000 { 5614 compatible = "qcom,glymur-dp"; 5615 reg = <0x0 0xaf5c000 0x0 0x200>, 5616 <0x0 0xaf5c200 0x0 0x200>, 5617 <0x0 0xaf5d000 0x0 0xc00>, 5618 <0x0 0xaf5e000 0x0 0x400>, 5619 <0x0 0xaf5f000 0x0 0x400>, 5620 <0x0 0xaf60000 0x0 0x400>, 5621 <0x0 0xaf61000 0x0 0x400>, 5622 <0x0 0xaf62000 0x0 0x600>, 5623 <0x0 0xaf63000 0x0 0x600>; 5624 5625 interrupts-extended = <&mdss 13>; 5626 5627 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5628 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>, 5629 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>, 5630 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5631 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>, 5632 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>; 5633 clock-names = "core_iface", 5634 "core_aux", 5635 "ctrl_link", 5636 "ctrl_link_iface", 5637 "stream_pixel", 5638 "stream_1_pixel"; 5639 5640 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5641 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>, 5642 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>; 5643 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5644 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5645 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5646 5647 operating-points-v2 = <&mdss_dp0_opp_table>; 5648 5649 power-domains = <&rpmhpd RPMHPD_MMCX>; 5650 5651 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5652 phy-names = "dp"; 5653 5654 #sound-dai-cells = <0>; 5655 5656 status = "disabled"; 5657 5658 ports { 5659 #address-cells = <1>; 5660 #size-cells = <0>; 5661 5662 port@0 { 5663 reg = <0>; 5664 5665 mdss_dp1_in: endpoint { 5666 remote-endpoint = <&mdss_intf4_out>; 5667 }; 5668 }; 5669 5670 port@1 { 5671 reg = <1>; 5672 5673 mdss_dp1_out: endpoint { 5674 remote-endpoint = <&usb_1_qmpphy_dp_in>; 5675 }; 5676 }; 5677 }; 5678 }; 5679 5680 mdss_dp2: displayport-controller@af64000 { 5681 compatible = "qcom,glymur-dp"; 5682 reg = <0x0 0x0af64000 0x0 0x200>, 5683 <0x0 0x0af64200 0x0 0x200>, 5684 <0x0 0x0af65000 0x0 0xc00>, 5685 <0x0 0x0af66000 0x0 0x400>, 5686 <0x0 0x0af67000 0x0 0x400>, 5687 <0x0 0x0af68000 0x0 0x400>, 5688 <0x0 0x0af69000 0x0 0x400>, 5689 <0x0 0x0af6a000 0x0 0x600>, 5690 <0x0 0x0af6b000 0x0 0x600>; 5691 5692 interrupts-extended = <&mdss 14>; 5693 5694 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5695 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>, 5696 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>, 5697 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5698 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>, 5699 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>; 5700 clock-names = "core_iface", 5701 "core_aux", 5702 "ctrl_link", 5703 "ctrl_link_iface", 5704 "stream_pixel", 5705 "stream_1_pixel"; 5706 5707 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5708 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>, 5709 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>; 5710 assigned-clock-parents = <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5711 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5712 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5713 5714 operating-points-v2 = <&mdss_dp0_opp_table>; 5715 5716 power-domains = <&rpmhpd RPMHPD_MMCX>; 5717 5718 phys = <&usb_2_qmpphy QMP_USB43DP_DP_PHY>; 5719 phy-names = "dp"; 5720 5721 #sound-dai-cells = <0>; 5722 5723 status = "disabled"; 5724 5725 ports { 5726 #address-cells = <1>; 5727 #size-cells = <0>; 5728 5729 port@0 { 5730 reg = <0>; 5731 mdss_dp2_in: endpoint { 5732 remote-endpoint = <&mdss_intf6_out>; 5733 }; 5734 }; 5735 5736 port@1 { 5737 reg = <1>; 5738 5739 mdss_dp2_out: endpoint { 5740 remote-endpoint = <&usb_2_qmpphy_dp_in>; 5741 }; 5742 }; 5743 }; 5744 }; 5745 5746 mdss_dp3: displayport-controller@af6c000 { 5747 compatible = "qcom,glymur-dp"; 5748 reg = <0x0 0x0af6c000 0x0 0x200>, 5749 <0x0 0x0af6c200 0x0 0x200>, 5750 <0x0 0x0af6d000 0x0 0xc00>, 5751 <0x0 0x0af6e000 0x0 0x400>, 5752 <0x0 0x0af6f000 0x0 0x400>, 5753 <0x0 0x0af70000 0x0 0x400>, 5754 <0x0 0x0af71000 0x0 0x400>, 5755 <0x0 0x0af72000 0x0 0x600>, 5756 <0x0 0x0af73000 0x0 0x600>; 5757 5758 interrupts-extended = <&mdss 15>; 5759 5760 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5761 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>, 5762 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>, 5763 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5764 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5765 clock-names = "core_iface", 5766 "core_aux", 5767 "ctrl_link", 5768 "ctrl_link_iface", 5769 "stream_pixel"; 5770 5771 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5772 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5773 assigned-clock-parents = <&mdss_dp3_phy 0>, 5774 <&mdss_dp3_phy 1>; 5775 5776 operating-points-v2 = <&mdss_dp0_opp_table>; 5777 5778 power-domains = <&rpmhpd RPMHPD_MMCX>; 5779 5780 phys = <&mdss_dp3_phy>; 5781 phy-names = "dp"; 5782 5783 #sound-dai-cells = <0>; 5784 5785 status = "disabled"; 5786 5787 ports { 5788 #address-cells = <1>; 5789 #size-cells = <0>; 5790 5791 port@0 { 5792 reg = <0>; 5793 5794 mdss_dp3_in: endpoint { 5795 remote-endpoint = <&mdss_intf5_out>; 5796 }; 5797 }; 5798 5799 port@1 { 5800 reg = <1>; 5801 5802 mdss_dp3_out: endpoint { 5803 }; 5804 }; 5805 }; 5806 }; 5807 }; 5808 5809 videocc: clock-controller@aaf0000 { 5810 compatible = "qcom,glymur-videocc"; 5811 reg = <0x0 0x0aaf0000 0x0 0x10000>; 5812 clocks = <&rpmhcc RPMH_CXO_CLK>, 5813 <&rpmhcc RPMH_CXO_CLK_A>; 5814 5815 power-domains = <&rpmhpd RPMHPD_MMCX>, 5816 <&rpmhpd RPMHPD_MXC>; 5817 required-opps = <&rpmhpd_opp_low_svs>, 5818 <&rpmhpd_opp_low_svs>; 5819 5820 #clock-cells = <1>; 5821 #reset-cells = <1>; 5822 #power-domain-cells = <1>; 5823 }; 5824 5825 evacc: clock-controller@abf0000 { 5826 compatible = "qcom,glymur-evacc"; 5827 reg = <0x0 0x0abf0000 0x0 0x10000>; 5828 clocks = <&gcc GCC_EVA_AHB_CLK>, 5829 <&rpmhcc RPMH_CXO_CLK>, 5830 <&sleep_clk>; 5831 5832 power-domains = <&rpmhpd RPMHPD_MMCX>, 5833 <&rpmhpd RPMHPD_MXC>; 5834 required-opps = <&rpmhpd_opp_low_svs>, 5835 <&rpmhpd_opp_low_svs>; 5836 5837 #clock-cells = <1>; 5838 #reset-cells = <1>; 5839 #power-domain-cells = <1>; 5840 }; 5841 5842 dispcc: clock-controller@af00000 { 5843 compatible = "qcom,glymur-dispcc"; 5844 reg = <0x0 0x0af00000 0x0 0x20000>; 5845 clocks = <&rpmhcc RPMH_CXO_CLK>, 5846 <&sleep_clk>, 5847 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */ 5848 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5849 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */ 5850 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5851 <&usb_2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */ 5852 <&usb_2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5853 <&mdss_dp3_phy 0>, /* dp3 */ 5854 <&mdss_dp3_phy 1>, 5855 <0>, /* dsi0 */ 5856 <0>, 5857 <0>, /* dsi1 */ 5858 <0>, 5859 <0>, 5860 <0>, 5861 <0>, 5862 <0>; 5863 power-domains = <&rpmhpd RPMHPD_MMCX>; 5864 required-opps = <&rpmhpd_opp_low_svs>; 5865 #clock-cells = <1>; 5866 #reset-cells = <1>; 5867 #power-domain-cells = <1>; 5868 }; 5869 5870 pdc: interrupt-controller@b220000 { 5871 compatible = "qcom,glymur-pdc", "qcom,pdc"; 5872 reg = <0x0 0x0b220000 0x0 0x10000>; 5873 qcom,pdc-ranges = <0 745 38>, 5874 <40 785 11>, 5875 <51 527 4>, 5876 <57 533 10>, 5877 <70 546 4>, 5878 <75 551 18>, 5879 <108 619 22>, 5880 <130 717 12>, 5881 <142 251 5>, 5882 <147 796 16>, 5883 <171 4104 36>; 5884 #interrupt-cells = <2>; 5885 interrupt-parent = <&intc>; 5886 interrupt-controller; 5887 }; 5888 5889 tsens0: thermal-sensor@c22c000 { 5890 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5891 reg = <0x0 0x0c22c000 0x0 0x1000>, 5892 <0x0 0x0c222000 0x0 0x1000>; 5893 5894 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 5896 interrupt-names = "uplow", 5897 "critical"; 5898 5899 #qcom,sensors = <13>; 5900 5901 #thermal-sensor-cells = <1>; 5902 }; 5903 5904 tsens1: thermal-sensor@c22d000 { 5905 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5906 reg = <0x0 0x0c22d000 0x0 0x1000>, 5907 <0x0 0x0c223000 0x0 0x1000>; 5908 5909 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 862 IRQ_TYPE_LEVEL_HIGH>; 5911 interrupt-names = "uplow", 5912 "critical"; 5913 5914 #qcom,sensors = <9>; 5915 5916 #thermal-sensor-cells = <1>; 5917 }; 5918 5919 tsens2: thermal-sensor@c22e000 { 5920 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5921 reg = <0x0 0x0c22e000 0x0 0x1000>, 5922 <0x0 0x0c224000 0x0 0x1000>; 5923 5924 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 863 IRQ_TYPE_LEVEL_HIGH>; 5926 interrupt-names = "uplow", 5927 "critical"; 5928 5929 #qcom,sensors = <13>; 5930 5931 #thermal-sensor-cells = <1>; 5932 }; 5933 5934 tsens3: thermal-sensor@c22f000 { 5935 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5936 reg = <0x0 0x0c22f000 0x0 0x1000>, 5937 <0x0 0x0c225000 0x0 0x1000>; 5938 5939 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 5941 interrupt-names = "uplow", 5942 "critical"; 5943 5944 #qcom,sensors = <8>; 5945 5946 #thermal-sensor-cells = <1>; 5947 }; 5948 5949 tsens4: thermal-sensor@c230000 { 5950 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5951 reg = <0x0 0x0c230000 0x0 0x1000>, 5952 <0x0 0x0c226000 0x0 0x1000>; 5953 5954 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5956 interrupt-names = "uplow", 5957 "critical"; 5958 5959 #qcom,sensors = <13>; 5960 5961 #thermal-sensor-cells = <1>; 5962 }; 5963 5964 tsens5: thermal-sensor@c231000 { 5965 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5966 reg = <0x0 0x0c231000 0x0 0x1000>, 5967 <0x0 0x0c227000 0x0 0x1000>; 5968 5969 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>, 5970 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>; 5971 interrupt-names = "uplow", 5972 "critical"; 5973 5974 #qcom,sensors = <8>; 5975 5976 #thermal-sensor-cells = <1>; 5977 }; 5978 5979 tsens6: thermal-sensor@c232000 { 5980 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5981 reg = <0x0 0x0c232000 0x0 0x1000>, 5982 <0x0 0x0c228000 0x0 0x1000>; 5983 5984 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>, 5985 <GIC_SPI 815 IRQ_TYPE_LEVEL_HIGH>; 5986 interrupt-names = "uplow", 5987 "critical"; 5988 5989 #qcom,sensors = <13>; 5990 5991 #thermal-sensor-cells = <1>; 5992 }; 5993 5994 tsens7: thermal-sensor@c233000 { 5995 compatible = "qcom,glymur-tsens", "qcom,tsens-v2"; 5996 reg = <0x0 0x0c233000 0x0 0x1000>, 5997 <0x0 0x0c229000 0x0 0x1000>; 5998 5999 interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>, 6000 <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 6001 interrupt-names = "uplow", 6002 "critical"; 6003 6004 #qcom,sensors = <15>; 6005 6006 #thermal-sensor-cells = <1>; 6007 }; 6008 6009 aoss_qmp: power-management@c300000 { 6010 compatible = "qcom,glymur-aoss-qmp", "qcom,aoss-qmp"; 6011 reg = <0x0 0x0c300000 0x0 0x400>; 6012 interrupt-parent = <&ipcc>; 6013 interrupts-extended = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 6014 IRQ_TYPE_EDGE_RISING>; 6015 mboxes = <&ipcc IPCC_MPROC_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6016 6017 #clock-cells = <0>; 6018 }; 6019 6020 sram@c30f000 { 6021 compatible = "qcom,rpmh-stats"; 6022 reg = <0x0 0x0c30f000 0x0 0x400>; 6023 }; 6024 6025 arbiter@c400000 { 6026 compatible = "qcom,glymur-spmi-pmic-arb"; 6027 reg = <0x0 0x0c400000 0x0 0x3000>, 6028 <0x0 0x0c900000 0x0 0x400000>, 6029 <0x0 0x0c4c0000 0x0 0x400000>, 6030 <0x0 0x0c403000 0x0 0x8000>; 6031 reg-names = "core", 6032 "chnls", 6033 "obsrvr", 6034 "chnl_map"; 6035 #address-cells = <2>; 6036 #size-cells = <2>; 6037 ranges; 6038 qcom,channel = <0>; 6039 qcom,ee = <0>; 6040 6041 spmi_bus0: spmi@c426000 { 6042 reg = <0x0 0x0c426000 0x0 0x4000>, 6043 <0x0 0x0c8c0000 0x0 0x10000>, 6044 <0x0 0x0c42a000 0x0 0x8000>; 6045 reg-names = "cnfg", 6046 "intr", 6047 "chnl_owner"; 6048 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6049 interrupt-names = "periph_irq"; 6050 interrupt-controller; 6051 #interrupt-cells = <4>; 6052 #address-cells = <2>; 6053 #size-cells = <0>; 6054 }; 6055 6056 spmi_bus1: spmi@c437000 { 6057 reg = <0x0 0x0c437000 0x0 0x4000>, 6058 <0x0 0x0c8d0000 0x0 0x10000>, 6059 <0x0 0x0c43b000 0x0 0x8000>; 6060 reg-names = "cnfg", 6061 "intr", 6062 "chnl_owner"; 6063 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 6064 interrupt-names = "periph_irq"; 6065 interrupt-controller; 6066 #interrupt-cells = <4>; 6067 #address-cells = <2>; 6068 #size-cells = <0>; 6069 }; 6070 6071 spmi_bus2: spmi@c448000 { 6072 reg = <0x0 0x0c448000 0x0 0x4000>, 6073 <0x0 0x0c8e0000 0x0 0x10000>, 6074 <0x0 0x0c44c000 0x0 0x8000>; 6075 reg-names = "cnfg", 6076 "intr", 6077 "chnl_owner"; 6078 interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; 6079 interrupt-names = "periph_irq"; 6080 interrupt-controller; 6081 #interrupt-cells = <4>; 6082 #address-cells = <2>; 6083 #size-cells = <0>; 6084 }; 6085 }; 6086 6087 tlmm: pinctrl@f100000 { 6088 compatible = "qcom,glymur-tlmm"; 6089 reg = <0x0 0x0f100000 0x0 0xf00000>; 6090 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6091 gpio-controller; 6092 #gpio-cells = <2>; 6093 interrupt-controller; 6094 #interrupt-cells = <2>; 6095 gpio-ranges = <&tlmm 0 0 249>; 6096 wakeup-parent = <&pdc>; 6097 6098 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6099 /* SDA, SCL */ 6100 pins = "gpio0", "gpio1"; 6101 function = "qup0_se0"; 6102 drive-strength = <2>; 6103 bias-pull-up = <2200>; 6104 }; 6105 6106 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6107 /* SDA, SCL */ 6108 pins = "gpio4", "gpio5"; 6109 function = "qup0_se1"; 6110 drive-strength = <2>; 6111 bias-pull-up = <2200>; 6112 }; 6113 6114 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6115 /* SDA, SCL */ 6116 pins = "gpio8", "gpio9"; 6117 function = "qup0_se2"; 6118 drive-strength = <2>; 6119 bias-pull-up = <2200>; 6120 }; 6121 6122 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6123 /* SDA, SCL */ 6124 pins = "gpio12", "gpio13"; 6125 function = "qup0_se3"; 6126 drive-strength = <2>; 6127 bias-pull-up = <2200>; 6128 }; 6129 6130 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6131 /* SDA, SCL */ 6132 pins = "gpio16", "gpio17"; 6133 function = "qup0_se4"; 6134 drive-strength = <2>; 6135 bias-pull-up = <2200>; 6136 }; 6137 6138 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6139 /* SDA, SCL */ 6140 pins = "gpio20", "gpio21"; 6141 function = "qup0_se5"; 6142 drive-strength = <2>; 6143 bias-pull-up = <2200>; 6144 }; 6145 6146 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6147 /* SDA, SCL */ 6148 pins = "gpio6", "gpio7"; 6149 function = "qup0_se6"; 6150 drive-strength = <2>; 6151 bias-pull-up = <2200>; 6152 }; 6153 6154 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6155 /* SDA, SCL */ 6156 pins = "gpio14", "gpio15"; 6157 function = "qup0_se7"; 6158 drive-strength = <2>; 6159 bias-pull-up = <2200>; 6160 }; 6161 6162 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6163 /* SDA, SCL */ 6164 pins = "gpio32", "gpio33"; 6165 function = "qup1_se0"; 6166 drive-strength = <2>; 6167 bias-pull-up = <2200>; 6168 }; 6169 6170 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6171 /* SDA, SCL */ 6172 pins = "gpio36", "gpio37"; 6173 function = "qup1_se1"; 6174 drive-strength = <2>; 6175 bias-pull-up = <2200>; 6176 }; 6177 6178 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6179 /* SDA, SCL */ 6180 pins = "gpio40", "gpio41"; 6181 function = "qup1_se2"; 6182 drive-strength = <2>; 6183 bias-pull-up = <2200>; 6184 }; 6185 6186 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6187 /* SDA, SCL */ 6188 pins = "gpio44", "gpio45"; 6189 function = "qup1_se3"; 6190 drive-strength = <2>; 6191 bias-pull-up = <2200>; 6192 }; 6193 6194 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6195 /* SDA, SCL */ 6196 pins = "gpio48", "gpio49"; 6197 function = "qup1_se4"; 6198 drive-strength = <2>; 6199 bias-pull-up = <2200>; 6200 }; 6201 6202 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6203 /* SDA, SCL */ 6204 pins = "gpio52", "gpio53"; 6205 function = "qup1_se5"; 6206 drive-strength = <2>; 6207 bias-pull-up = <2200>; 6208 }; 6209 6210 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6211 /* SDA, SCL */ 6212 pins = "gpio56", "gpio57"; 6213 function = "qup1_se6"; 6214 drive-strength = <2>; 6215 bias-pull-up = <2200>; 6216 }; 6217 6218 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6219 /* SDA, SCL */ 6220 pins = "gpio54", "gpio55"; 6221 function = "qup1_se7"; 6222 drive-strength = <2>; 6223 bias-pull-up = <2200>; 6224 }; 6225 6226 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6227 /* SDA, SCL */ 6228 pins = "gpio64", "gpio65"; 6229 function = "qup2_se0"; 6230 drive-strength = <2>; 6231 bias-pull-up = <2200>; 6232 }; 6233 6234 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 6235 /* SDA, SCL */ 6236 pins = "gpio68", "gpio69"; 6237 function = "qup2_se1"; 6238 drive-strength = <2>; 6239 bias-pull-up = <2200>; 6240 }; 6241 6242 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 6243 /* SDA, SCL */ 6244 pins = "gpio72", "gpio73"; 6245 function = "qup2_se2"; 6246 drive-strength = <2>; 6247 bias-pull-up = <2200>; 6248 }; 6249 6250 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 6251 /* SDA, SCL */ 6252 pins = "gpio76", "gpio77"; 6253 function = "qup2_se3"; 6254 drive-strength = <2>; 6255 bias-pull-up = <2200>; 6256 }; 6257 6258 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 6259 /* SDA, SCL */ 6260 pins = "gpio80", "gpio81"; 6261 function = "qup2_se4"; 6262 drive-strength = <2>; 6263 bias-pull-up = <2200>; 6264 }; 6265 6266 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 6267 /* SDA, SCL */ 6268 pins = "gpio84", "gpio85"; 6269 function = "qup2_se5"; 6270 drive-strength = <2>; 6271 bias-pull-up = <2200>; 6272 }; 6273 6274 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 6275 /* SDA, SCL */ 6276 pins = "gpio88", "gpio89"; 6277 function = "qup2_se6"; 6278 drive-strength = <2>; 6279 bias-pull-up = <2200>; 6280 }; 6281 6282 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 6283 /* SDA, SCL */ 6284 pins = "gpio80", "gpio81"; 6285 function = "qup2_se7"; 6286 drive-strength = <2>; 6287 bias-pull-up = <2200>; 6288 }; 6289 6290 qup_spi0_cs: qup-spi0-cs-state { 6291 pins = "gpio3"; 6292 function = "qup0_se0"; 6293 drive-strength = <6>; 6294 bias-disable; 6295 }; 6296 6297 qup_spi0_data_clk: qup-spi0-data-clk-state { 6298 /* MISO, MOSI, CLK */ 6299 pins = "gpio0", "gpio1", "gpio2"; 6300 function = "qup0_se0"; 6301 drive-strength = <6>; 6302 bias-disable; 6303 }; 6304 6305 qup_spi1_cs: qup-spi1-cs-state { 6306 pins = "gpio7"; 6307 function = "qup0_se1"; 6308 drive-strength = <6>; 6309 bias-disable; 6310 }; 6311 6312 qup_spi1_data_clk: qup-spi1-data-clk-state { 6313 /* MISO, MOSI, CLK */ 6314 pins = "gpio4", "gpio5", "gpio6"; 6315 function = "qup0_se1"; 6316 drive-strength = <6>; 6317 bias-disable; 6318 }; 6319 6320 qup_spi2_cs: qup-spi2-cs-state { 6321 pins = "gpio11"; 6322 function = "qup0_se2"; 6323 drive-strength = <6>; 6324 bias-disable; 6325 }; 6326 6327 qup_spi2_data_clk: qup-spi2-data-clk-state { 6328 /* MISO, MOSI, CLK */ 6329 pins = "gpio8", "gpio9", "gpio10"; 6330 function = "qup0_se2"; 6331 drive-strength = <6>; 6332 bias-disable; 6333 }; 6334 6335 qup_spi3_cs: qup-spi3-cs-state { 6336 pins = "gpio15"; 6337 function = "qup0_se3"; 6338 drive-strength = <6>; 6339 bias-disable; 6340 }; 6341 6342 qup_spi3_data_clk: qup-spi3-data-clk-state { 6343 /* MISO, MOSI, CLK */ 6344 pins = "gpio12", "gpio13", "gpio14"; 6345 function = "qup0_se3"; 6346 drive-strength = <6>; 6347 bias-disable; 6348 }; 6349 6350 qup_spi4_cs: qup-spi4-cs-state { 6351 pins = "gpio19"; 6352 function = "qup0_se4"; 6353 drive-strength = <6>; 6354 bias-disable; 6355 }; 6356 6357 qup_spi4_data_clk: qup-spi4-data-clk-state { 6358 /* MISO, MOSI, CLK */ 6359 pins = "gpio16", "gpio17", "gpio18"; 6360 function = "qup0_se4"; 6361 drive-strength = <6>; 6362 bias-disable; 6363 }; 6364 6365 qup_spi5_cs: qup-spi5-cs-state { 6366 pins = "gpio23"; 6367 function = "qup0_se5"; 6368 drive-strength = <6>; 6369 bias-disable; 6370 }; 6371 6372 qup_spi5_data_clk: qup-spi5-data-clk-state { 6373 /* MISO, MOSI, CLK */ 6374 pins = "gpio20", "gpio21", "gpio22"; 6375 function = "qup0_se5"; 6376 drive-strength = <6>; 6377 bias-disable; 6378 }; 6379 6380 qup_spi6_cs: qup-spi6-cs-state { 6381 pins = "gpio5"; 6382 function = "qup0_se6"; 6383 drive-strength = <6>; 6384 bias-disable; 6385 }; 6386 6387 qup_spi6_data_clk: qup-spi6-data-clk-state { 6388 /* MISO, MOSI, CLK */ 6389 pins = "gpio6", "gpio7", "gpio4"; 6390 function = "qup0_se6"; 6391 drive-strength = <6>; 6392 bias-disable; 6393 }; 6394 6395 qup_spi7_cs: qup-spi7-cs-state { 6396 pins = "gpio13"; 6397 function = "qup0_se7"; 6398 drive-strength = <6>; 6399 bias-disable; 6400 }; 6401 6402 qup_spi7_data_clk: qup-spi7-data-clk-state { 6403 /* MISO, MOSI, CLK */ 6404 pins = "gpio14", "gpio15", "gpio12"; 6405 function = "qup0_se7"; 6406 drive-strength = <6>; 6407 bias-disable; 6408 }; 6409 6410 qup_spi8_cs: qup-spi8-cs-state { 6411 pins = "gpio35"; 6412 function = "qup1_se0"; 6413 drive-strength = <6>; 6414 bias-disable; 6415 }; 6416 6417 qup_spi8_data_clk: qup-spi8-data-clk-state { 6418 /* MISO, MOSI, CLK */ 6419 pins = "gpio32", "gpio33", "gpio34"; 6420 function = "qup1_se0"; 6421 drive-strength = <6>; 6422 bias-disable; 6423 }; 6424 6425 qup_spi9_cs: qup-spi9-cs-state { 6426 pins = "gpio39"; 6427 function = "qup1_se1"; 6428 drive-strength = <6>; 6429 bias-disable; 6430 }; 6431 6432 qup_spi9_data_clk: qup-spi9-data-clk-state { 6433 /* MISO, MOSI, CLK */ 6434 pins = "gpio36", "gpio37", "gpio38"; 6435 function = "qup1_se1"; 6436 drive-strength = <6>; 6437 bias-disable; 6438 }; 6439 6440 qup_spi10_cs: qup-spi10-cs-state { 6441 pins = "gpio43"; 6442 function = "qup1_se2"; 6443 drive-strength = <6>; 6444 bias-disable; 6445 }; 6446 6447 qup_spi10_data_clk: qup-spi10-data-clk-state { 6448 /* MISO, MOSI, CLK */ 6449 pins = "gpio40", "gpio41", "gpio42"; 6450 function = "qup1_se2"; 6451 drive-strength = <6>; 6452 bias-disable; 6453 }; 6454 6455 qup_spi11_cs: qup-spi11-cs-state { 6456 pins = "gpio47"; 6457 function = "qup1_se3"; 6458 drive-strength = <6>; 6459 bias-disable; 6460 }; 6461 6462 qup_spi11_data_clk: qup-spi11-data-clk-state { 6463 pins = "gpio44", "gpio45", "gpio46"; 6464 function = "qup1_se3"; 6465 drive-strength = <6>; 6466 bias-disable; 6467 }; 6468 6469 qup_spi12_cs: qup-spi12-cs-state { 6470 pins = "gpio51"; 6471 function = "qup1_se4"; 6472 drive-strength = <6>; 6473 bias-disable; 6474 }; 6475 6476 qup_spi12_data_clk: qup-spi12-data-clk-state { 6477 /* MISO, MOSI, CLK */ 6478 pins = "gpio48", "gpio49", "gpio50"; 6479 function = "qup1_se4"; 6480 drive-strength = <6>; 6481 bias-disable; 6482 }; 6483 6484 qup_spi13_cs: qup-spi13-cs-state { 6485 pins = "gpio55"; 6486 function = "qup1_se5"; 6487 drive-strength = <6>; 6488 bias-disable; 6489 }; 6490 6491 qup_spi13_data_clk: qup-spi13-data-clk-state { 6492 /* MISO, MOSI, CLK */ 6493 pins = "gpio52", "gpio53", "gpio54"; 6494 function = "qup1_se5"; 6495 drive-strength = <6>; 6496 bias-disable; 6497 }; 6498 6499 qup_spi14_cs: qup-spi14-cs-state { 6500 pins = "gpio59"; 6501 function = "qup1_se6"; 6502 drive-strength = <6>; 6503 bias-disable; 6504 }; 6505 6506 qup_spi14_data_clk: qup-spi14-data-clk-state { 6507 /* MISO, MOSI, CLK */ 6508 pins = "gpio56", "gpio57", "gpio58"; 6509 function = "qup1_se6"; 6510 drive-strength = <6>; 6511 bias-disable; 6512 }; 6513 6514 qup_spi15_cs: qup-spi15-cs-state { 6515 pins = "gpio53"; 6516 function = "qup1_se7"; 6517 drive-strength = <6>; 6518 bias-disable; 6519 }; 6520 6521 qup_spi15_data_clk: qup-spi15-data-clk-state { 6522 /* MISO, MOSI, CLK */ 6523 pins = "gpio54", "gpio55", "gpio52"; 6524 function = "qup1_se7"; 6525 drive-strength = <6>; 6526 bias-disable; 6527 }; 6528 6529 qup_spi16_cs: qup-spi16-cs-state { 6530 pins = "gpio67"; 6531 function = "qup2_se0"; 6532 drive-strength = <6>; 6533 bias-disable; 6534 }; 6535 6536 qup_spi16_data_clk: qup-spi16-data-clk-state { 6537 /* MISO, MOSI, CLK */ 6538 pins = "gpio64", "gpio65", "gpio66"; 6539 function = "qup2_se0"; 6540 drive-strength = <6>; 6541 bias-disable; 6542 }; 6543 6544 qup_spi17_cs: qup-spi17-cs-state { 6545 pins = "gpio71"; 6546 function = "qup2_se1"; 6547 drive-strength = <6>; 6548 bias-disable; 6549 }; 6550 6551 qup_spi17_data_clk: qup-spi17-data-clk-state { 6552 /* MISO, MOSI, CLK */ 6553 pins = "gpio68", "gpio69", "gpio70"; 6554 function = "qup2_se1"; 6555 drive-strength = <6>; 6556 bias-disable; 6557 }; 6558 6559 qup_spi18_cs: qup-spi18-cs-state { 6560 pins = "gpio75"; 6561 function = "qup2_se2"; 6562 drive-strength = <6>; 6563 bias-disable; 6564 }; 6565 6566 qup_spi18_data_clk: qup-spi18-data-clk-state { 6567 /* MISO, MOSI, CLK */ 6568 pins = "gpio72", "gpio73", "gpio74"; 6569 function = "qup2_se2"; 6570 drive-strength = <6>; 6571 bias-disable; 6572 }; 6573 6574 qup_spi19_cs: qup-spi19-cs-state { 6575 pins = "gpio79"; 6576 function = "qup2_se3"; 6577 drive-strength = <6>; 6578 bias-disable; 6579 }; 6580 6581 qup_spi19_data_clk: qup-spi19-data-clk-state { 6582 /* MISO, MOSI, CLK */ 6583 pins = "gpio76", "gpio77", "gpio78"; 6584 function = "qup2_se3"; 6585 drive-strength = <6>; 6586 bias-disable; 6587 }; 6588 6589 qup_spi20_cs: qup-spi20-cs-state { 6590 pins = "gpio83"; 6591 function = "qup2_se4"; 6592 drive-strength = <6>; 6593 bias-disable; 6594 }; 6595 6596 qup_spi20_data_clk: qup-spi20-data-clk-state { 6597 /* MISO, MOSI, CLK */ 6598 pins = "gpio80", "gpio81", "gpio82"; 6599 function = "qup2_se4"; 6600 drive-strength = <6>; 6601 bias-disable; 6602 }; 6603 6604 qup_spi21_cs: qup-spi21-cs-state { 6605 pins = "gpio87"; 6606 function = "qup2_se5"; 6607 drive-strength = <6>; 6608 bias-disable; 6609 }; 6610 6611 qup_spi21_data_clk: qup-spi21-data-clk-state { 6612 /* MISO, MOSI, CLK */ 6613 pins = "gpio84", "gpio85", "gpio86"; 6614 function = "qup2_se5"; 6615 drive-strength = <6>; 6616 bias-disable; 6617 }; 6618 6619 qup_spi22_cs: qup-spi22-cs-state { 6620 pins = "gpio91"; 6621 function = "qup2_se6"; 6622 drive-strength = <6>; 6623 bias-disable; 6624 }; 6625 6626 qup_spi22_data_clk: qup-spi22-data-clk-state { 6627 /* MISO, MOSI, CLK */ 6628 pins = "gpio88", "gpio89", "gpio90"; 6629 function = "qup2_se6"; 6630 drive-strength = <6>; 6631 bias-disable; 6632 }; 6633 6634 qup_spi23_cs: qup-spi23-cs-state { 6635 pins = "gpio83"; 6636 function = "qup2_se7"; 6637 drive-strength = <6>; 6638 bias-disable; 6639 }; 6640 6641 qup_spi23_data_clk: qup-spi23-data-clk-state { 6642 /* MISO, MOSI, CLK */ 6643 pins = "gpio80", "gpio81", "gpio82"; 6644 function = "qup2_se7"; 6645 drive-strength = <6>; 6646 bias-disable; 6647 }; 6648 6649 qup_uart2_default: qup-uart2-default-state { 6650 tx-pins { 6651 pins = "gpio10"; 6652 function = "qup0_se2"; 6653 drive-strength = <2>; 6654 bias-disable; 6655 }; 6656 6657 rx-pins { 6658 pins = "gpio11"; 6659 function = "qup0_se2"; 6660 drive-strength = <2>; 6661 bias-disable; 6662 }; 6663 }; 6664 6665 qup_uart14_default: qup-uart14-default-state { 6666 cts-pins { 6667 pins = "gpio56"; 6668 function = "qup1_se6"; 6669 drive-strength = <2>; 6670 bias-disable; 6671 }; 6672 6673 rts-pins { 6674 pins = "gpio57"; 6675 function = "qup1_se6"; 6676 drive-strength = <2>; 6677 bias-disable; 6678 }; 6679 6680 tx-pins { 6681 pins = "gpio58"; 6682 function = "qup1_se6"; 6683 drive-strength = <2>; 6684 bias-disable; 6685 }; 6686 6687 rx-pins { 6688 pins = "gpio59"; 6689 function = "qup1_se6"; 6690 drive-strength = <2>; 6691 bias-disable; 6692 }; 6693 }; 6694 6695 qup_uart19_default: qup-uart19-default-state { 6696 cts-pins { 6697 pins = "gpio76"; 6698 function = "qup2_se3"; 6699 drive-strength = <2>; 6700 bias-disable; 6701 }; 6702 6703 rts-pins { 6704 pins = "gpio77"; 6705 function = "qup2_se3"; 6706 drive-strength = <2>; 6707 bias-disable; 6708 }; 6709 6710 tx-pins { 6711 pins = "gpio78"; 6712 function = "qup2_se3"; 6713 drive-strength = <2>; 6714 bias-disable; 6715 }; 6716 6717 rx-pins { 6718 pins = "gpio79"; 6719 function = "qup2_se3"; 6720 drive-strength = <2>; 6721 bias-disable; 6722 }; 6723 }; 6724 6725 qup_uart21_default: qup-uart21-default-state { 6726 tx-pins { 6727 pins = "gpio86"; 6728 function = "qup2_se5"; 6729 drive-strength = <2>; 6730 bias-disable; 6731 }; 6732 6733 rx-pins { 6734 pins = "gpio87"; 6735 function = "qup2_se5"; 6736 drive-strength = <2>; 6737 bias-disable; 6738 }; 6739 }; 6740 6741 qup_uart22_default: qup-uart22-default-state { 6742 tx-pins { 6743 pins = "gpio90"; 6744 function = "qup2_se6"; 6745 drive-strength = <2>; 6746 bias-disable; 6747 }; 6748 6749 rx-pins { 6750 pins = "gpio91"; 6751 function = "qup2_se6"; 6752 drive-strength = <2>; 6753 bias-disable; 6754 }; 6755 }; 6756 6757 sdc2_default_state: sdc2-default-state { 6758 clk-pins { 6759 pins = "sdc2_clk"; 6760 drive-strength = <16>; 6761 bias-disable; 6762 }; 6763 6764 cmd-pins { 6765 pins = "sdc2_cmd"; 6766 drive-strength = <10>; 6767 bias-pull-up; 6768 }; 6769 6770 data-pins { 6771 pins = "sdc2_data"; 6772 drive-strength = <10>; 6773 bias-pull-up; 6774 }; 6775 }; 6776 6777 sdc2_sleep_state: sdc2-sleep-state { 6778 clk-pins { 6779 pins = "sdc2_clk"; 6780 drive-strength = <2>; 6781 bias-disable; 6782 }; 6783 6784 cmd-pins { 6785 pins = "sdc2_cmd"; 6786 drive-strength = <2>; 6787 bias-pull-up; 6788 }; 6789 6790 data-pins { 6791 pins = "sdc2_data"; 6792 drive-strength = <2>; 6793 bias-pull-up; 6794 }; 6795 }; 6796 }; 6797 6798 ctcu@10001000 { 6799 compatible = "qcom,glymur-ctcu", "qcom,sa8775p-ctcu"; 6800 reg = <0x0 0x10001000 0x0 0x1000>; 6801 6802 clocks = <&aoss_qmp>; 6803 clock-names = "apb"; 6804 6805 in-ports { 6806 #address-cells = <1>; 6807 #size-cells = <0>; 6808 6809 port@0 { 6810 reg = <0>; 6811 6812 ctcu_in0: endpoint { 6813 remote-endpoint = <&etr0_out>; 6814 }; 6815 }; 6816 6817 port@1 { 6818 reg = <1>; 6819 6820 ctcu_in1: endpoint { 6821 remote-endpoint = <&etr1_out>; 6822 }; 6823 }; 6824 }; 6825 }; 6826 6827 stm: stm@10002000 { 6828 compatible = "arm,coresight-stm", "arm,primecell"; 6829 reg = <0x0 0x10002000 0x0 0x1000>, 6830 <0x0 0x16280000 0x0 0x180000>; 6831 reg-names = "stm-base", 6832 "stm-stimulus-base"; 6833 6834 clocks = <&aoss_qmp>; 6835 clock-names = "apb_pclk"; 6836 6837 out-ports { 6838 port { 6839 stm_out: endpoint { 6840 remote-endpoint = <&funnel0_in7>; 6841 }; 6842 }; 6843 }; 6844 }; 6845 6846 tpda@10004000 { 6847 compatible = "qcom,coresight-tpda", "arm,primecell"; 6848 reg = <0x0 0x10004000 0x0 0x1000>; 6849 6850 clocks = <&aoss_qmp>; 6851 clock-names = "apb_pclk"; 6852 6853 in-ports { 6854 #address-cells = <1>; 6855 #size-cells = <0>; 6856 6857 port@1 { 6858 reg = <1>; 6859 6860 qdss_tpda_in1: endpoint { 6861 remote-endpoint = <&spdm_tpdm_out>; 6862 }; 6863 }; 6864 }; 6865 6866 out-ports { 6867 port { 6868 qdss_tpda_out: endpoint { 6869 remote-endpoint = <&funnel0_in6>; 6870 }; 6871 }; 6872 }; 6873 }; 6874 6875 tpdm@1000f000 { 6876 compatible = "qcom,coresight-tpdm", "arm,primecell"; 6877 reg = <0x0 0x1000f000 0x0 0x1000>; 6878 6879 clocks = <&aoss_qmp>; 6880 clock-names = "apb_pclk"; 6881 label = "tpdm_spdm"; 6882 6883 qcom,cmb-element-bits = <32>; 6884 qcom,cmb-msrs-num = <32>; 6885 6886 out-ports { 6887 port { 6888 spdm_tpdm_out: endpoint { 6889 remote-endpoint = <&qdss_tpda_in1>; 6890 }; 6891 }; 6892 }; 6893 }; 6894 6895 funnel@10041000 { 6896 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 6897 reg = <0x0 0x10041000 0x0 0x1000>; 6898 6899 clocks = <&aoss_qmp>; 6900 clock-names = "apb_pclk"; 6901 6902 in-ports { 6903 #address-cells = <1>; 6904 #size-cells = <0>; 6905 6906 port@0 { 6907 reg = <0>; 6908 6909 funnel0_in0: endpoint { 6910 remote-endpoint = <&tn_ag_out>; 6911 }; 6912 }; 6913 6914 port@6 { 6915 reg = <6>; 6916 6917 funnel0_in6: endpoint { 6918 remote-endpoint = <&qdss_tpda_out>; 6919 }; 6920 }; 6921 6922 port@7 { 6923 reg = <7>; 6924 6925 funnel0_in7: endpoint { 6926 remote-endpoint = <&stm_out>; 6927 }; 6928 }; 6929 }; 6930 6931 out-ports { 6932 port { 6933 funnel0_out: endpoint { 6934 remote-endpoint = <&aoss_funnel_in6>; 6935 }; 6936 }; 6937 }; 6938 }; 6939 6940 replicator@10046000 { 6941 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6942 reg = <0x0 0x10046000 0x0 0x1000>; 6943 6944 clocks = <&aoss_qmp>; 6945 clock-names = "apb_pclk"; 6946 6947 in-ports { 6948 port { 6949 qdss_rep_in: endpoint { 6950 remote-endpoint = <&swao_rep_out0>; 6951 }; 6952 }; 6953 }; 6954 6955 out-ports { 6956 port { 6957 qdss_rep_out0: endpoint { 6958 remote-endpoint = <&etr_rep_in>; 6959 }; 6960 }; 6961 }; 6962 }; 6963 6964 tmc@10048000 { 6965 compatible = "arm,coresight-tmc", "arm,primecell"; 6966 reg = <0x0 0x10048000 0x0 0x1000>; 6967 6968 clocks = <&aoss_qmp>; 6969 clock-names = "apb_pclk"; 6970 6971 iommus = <&apps_smmu 0x00e0 0x0000>; 6972 arm,scatter-gather; 6973 6974 in-ports { 6975 port { 6976 etr0_in: endpoint { 6977 remote-endpoint = <&etr_rep_out0>; 6978 }; 6979 }; 6980 }; 6981 6982 out-ports { 6983 port { 6984 etr0_out: endpoint { 6985 remote-endpoint = <&ctcu_in0>; 6986 }; 6987 }; 6988 }; 6989 }; 6990 6991 replicator@1004e000 { 6992 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 6993 reg = <0x0 0x1004e000 0x0 0x1000>; 6994 6995 clocks = <&aoss_qmp>; 6996 clock-names = "apb_pclk"; 6997 6998 in-ports { 6999 port { 7000 etr_rep_in: endpoint { 7001 remote-endpoint = <&qdss_rep_out0>; 7002 }; 7003 }; 7004 }; 7005 7006 out-ports { 7007 #address-cells = <1>; 7008 #size-cells = <0>; 7009 7010 port@0 { 7011 reg = <0>; 7012 7013 etr_rep_out0: endpoint { 7014 remote-endpoint = <&etr0_in>; 7015 }; 7016 }; 7017 7018 port@1 { 7019 reg = <1>; 7020 7021 etr_rep_out1: endpoint { 7022 remote-endpoint = <&etr1_in>; 7023 }; 7024 }; 7025 }; 7026 }; 7027 7028 tmc@1004f000 { 7029 compatible = "arm,coresight-tmc", "arm,primecell"; 7030 reg = <0x0 0x1004f000 0x0 0x1000>; 7031 7032 clocks = <&aoss_qmp>; 7033 clock-names = "apb_pclk"; 7034 7035 iommus = <&apps_smmu 0x0100 0x0000>; 7036 arm,scatter-gather; 7037 7038 in-ports { 7039 port { 7040 etr1_in: endpoint { 7041 remote-endpoint = <&etr_rep_out1>; 7042 }; 7043 }; 7044 }; 7045 7046 out-ports { 7047 port { 7048 etr1_out: endpoint { 7049 remote-endpoint = <&ctcu_in1>; 7050 }; 7051 }; 7052 }; 7053 }; 7054 7055 tpdm@1102c000 { 7056 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7057 reg = <0x0 0x1102c000 0x0 0x1000>; 7058 7059 clocks = <&aoss_qmp>; 7060 clock-names = "apb_pclk"; 7061 label = "tpdm_gcc"; 7062 7063 qcom,dsb-msrs-num = <32>; 7064 7065 out-ports { 7066 port { 7067 gcc_tpdm_out: endpoint { 7068 remote-endpoint = <&tn_ag_in36>; 7069 }; 7070 }; 7071 }; 7072 }; 7073 7074 tpdm@11180000 { 7075 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7076 reg = <0x0 0x11180000 0x0 0x1000>; 7077 7078 clocks = <&aoss_qmp>; 7079 clock-names = "apb_pclk"; 7080 label = "tpdm_cdsp"; 7081 7082 qcom,dsb-element-bits = <32>; 7083 qcom,dsb-msrs-num = <32>; 7084 7085 out-ports { 7086 port { 7087 cdsp_tpdm_out: endpoint { 7088 remote-endpoint = <&cdsp_tpda_in0>; 7089 }; 7090 }; 7091 }; 7092 }; 7093 7094 tpdm@11185000 { 7095 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7096 reg = <0x0 0x11185000 0x0 0x1000>; 7097 7098 clocks = <&aoss_qmp>; 7099 clock-names = "apb_pclk"; 7100 label = "tpdm_cdsp_dpm_1"; 7101 7102 qcom,cmb-element-bits = <64>; 7103 qcom,cmb-msrs-num = <32>; 7104 7105 out-ports { 7106 port { 7107 cdsp_dpm1_tpdm_out: endpoint { 7108 remote-endpoint = <&cdsp_tpda_in5>; 7109 }; 7110 }; 7111 }; 7112 }; 7113 7114 tpdm@11186000 { 7115 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7116 reg = <0x0 0x11186000 0x0 0x1000>; 7117 7118 clocks = <&aoss_qmp>; 7119 clock-names = "apb_pclk"; 7120 label = "tpdm_cdsp_dpm_2"; 7121 7122 qcom,cmb-element-bits = <64>; 7123 qcom,cmb-msrs-num = <32>; 7124 7125 out-ports { 7126 port { 7127 cdsp_dpm2_tpdm_out: endpoint { 7128 remote-endpoint = <&cdsp_tpda_in6>; 7129 }; 7130 }; 7131 }; 7132 }; 7133 7134 tpda@11188000 { 7135 compatible = "qcom,coresight-tpda", "arm,primecell"; 7136 reg = <0x0 0x11188000 0x0 0x1000>; 7137 7138 clocks = <&aoss_qmp>; 7139 clock-names = "apb_pclk"; 7140 7141 in-ports { 7142 #address-cells = <1>; 7143 #size-cells = <0>; 7144 7145 port@0 { 7146 reg = <0>; 7147 7148 cdsp_tpda_in0: endpoint { 7149 remote-endpoint = <&cdsp_tpdm_out>; 7150 }; 7151 }; 7152 7153 port@1 { 7154 reg = <1>; 7155 7156 cdsp_tpda_in1: endpoint { 7157 remote-endpoint = <&cdsp_llm_tpdm_out>; 7158 }; 7159 }; 7160 7161 port@2 { 7162 reg = <2>; 7163 7164 cdsp_tpda_in2: endpoint { 7165 remote-endpoint = <&cdsp_llm2_tpdm_out>; 7166 }; 7167 }; 7168 7169 port@3 { 7170 reg = <3>; 7171 7172 cdsp_tpda_in3: endpoint { 7173 remote-endpoint = <&cdsp_cmsr_tpdm_out>; 7174 }; 7175 }; 7176 7177 port@4 { 7178 reg = <4>; 7179 7180 cdsp_tpda_in4: endpoint { 7181 remote-endpoint = <&cdsp_cmsr2_tpdm_out>; 7182 }; 7183 }; 7184 7185 port@5 { 7186 reg = <5>; 7187 7188 cdsp_tpda_in5: endpoint { 7189 remote-endpoint = <&cdsp_dpm1_tpdm_out>; 7190 }; 7191 }; 7192 7193 port@6 { 7194 reg = <6>; 7195 7196 cdsp_tpda_in6: endpoint { 7197 remote-endpoint = <&cdsp_dpm2_tpdm_out>; 7198 }; 7199 }; 7200 }; 7201 7202 out-ports { 7203 port { 7204 cdsp_tpda_out: endpoint { 7205 remote-endpoint = <&cdsp_funnel_in0>; 7206 }; 7207 }; 7208 }; 7209 }; 7210 7211 funnel@11189000 { 7212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7213 reg = <0x0 0x11189000 0x0 0x1000>; 7214 7215 clocks = <&aoss_qmp>; 7216 clock-names = "apb_pclk"; 7217 7218 in-ports { 7219 port { 7220 cdsp_funnel_in0: endpoint { 7221 remote-endpoint = <&cdsp_tpda_out>; 7222 }; 7223 }; 7224 }; 7225 7226 out-ports { 7227 port { 7228 cdsp_funnel_out: endpoint { 7229 remote-endpoint = <&tn_ag_in53>; 7230 }; 7231 }; 7232 }; 7233 }; 7234 7235 cti@11193000 { 7236 compatible = "arm,coresight-cti", "arm,primecell"; 7237 reg = <0x0 0x11193000 0x0 0x1000>; 7238 7239 clocks = <&aoss_qmp>; 7240 clock-names = "apb_pclk"; 7241 label = "cti_cdsp"; 7242 }; 7243 7244 cti_wpss: cti@111ab000 { 7245 compatible = "arm,coresight-cti", "arm,primecell"; 7246 reg = <0x0 0x111ab000 0x0 0x1000>; 7247 7248 clocks = <&aoss_qmp>; 7249 clock-names = "apb_pclk"; 7250 label = "cti_wpss"; 7251 }; 7252 7253 tpdm@111d0000 { 7254 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7255 reg = <0x0 0x111d0000 0x0 0x1000>; 7256 7257 clocks = <&aoss_qmp>; 7258 clock-names = "apb_pclk"; 7259 label = "tpdm_qm"; 7260 7261 qcom,dsb-msrs-num = <32>; 7262 7263 out-ports { 7264 port { 7265 qm_tpdm_out: endpoint { 7266 remote-endpoint = <&tn_ag_in35>; 7267 }; 7268 }; 7269 }; 7270 }; 7271 7272 itnoc@11200000 { 7273 compatible = "qcom,coresight-itnoc"; 7274 reg = <0x0 0x11200000 0x0 0x3c00>; 7275 7276 clocks = <&aoss_qmp>; 7277 clock-names = "apb"; 7278 7279 in-ports { 7280 #address-cells = <1>; 7281 #size-cells = <0>; 7282 7283 port@6 { 7284 reg = <6>; 7285 7286 tn_ag_in6: endpoint { 7287 remote-endpoint = <&mm_dsb_tpdm_out>; 7288 }; 7289 }; 7290 7291 port@10 { 7292 reg = <0x10>; 7293 7294 tn_ag_in16: endpoint { 7295 remote-endpoint = <&east_dsb_tpdm_out>; 7296 }; 7297 }; 7298 7299 port@21 { 7300 reg = <0x21>; 7301 7302 tn_ag_in33: endpoint { 7303 remote-endpoint = <&west_dsb_tpdm_out>; 7304 }; 7305 }; 7306 7307 port@23 { 7308 reg = <0x23>; 7309 7310 tn_ag_in35: endpoint { 7311 remote-endpoint = <&qm_tpdm_out>; 7312 }; 7313 }; 7314 7315 port@24 { 7316 reg = <0x24>; 7317 7318 tn_ag_in36: endpoint { 7319 remote-endpoint = <&gcc_tpdm_out>; 7320 }; 7321 }; 7322 7323 port@32 { 7324 reg = <0x32>; 7325 7326 tn_ag_in50: endpoint { 7327 remote-endpoint = <&pcie_rscc_tpda_out>; 7328 }; 7329 }; 7330 7331 port@35 { 7332 reg = <0x35>; 7333 7334 tn_ag_in53: endpoint { 7335 remote-endpoint = <&cdsp_funnel_out>; 7336 }; 7337 }; 7338 7339 port@3f { 7340 reg = <0x3f>; 7341 7342 tn_ag_in63: endpoint { 7343 remote-endpoint = <¢er_dsb_tpdm_out>; 7344 }; 7345 }; 7346 7347 port@40 { 7348 reg = <0x40>; 7349 7350 tn_ag_in64: endpoint { 7351 remote-endpoint = <&ipcc_cmb_tpdm_out>; 7352 }; 7353 }; 7354 7355 port@41 { 7356 reg = <0x41>; 7357 7358 tn_ag_in65: endpoint { 7359 remote-endpoint = <&qrng_tpdm_out>; 7360 }; 7361 }; 7362 7363 port@42 { 7364 reg = <0x42>; 7365 7366 tn_ag_in66: endpoint { 7367 remote-endpoint = <&pmu_tpdm_out>; 7368 }; 7369 }; 7370 7371 port@43 { 7372 reg = <0x43>; 7373 7374 tn_ag_in67: endpoint { 7375 remote-endpoint = <&rdpm_west_cmb0_tpdm_out>; 7376 }; 7377 }; 7378 7379 port@44 { 7380 reg = <0x44>; 7381 7382 tn_ag_in68: endpoint { 7383 remote-endpoint = <&rdpm_west_cmb1_tpdm_out>; 7384 }; 7385 }; 7386 7387 port@45 { 7388 reg = <0x45>; 7389 7390 tn_ag_in69: endpoint { 7391 remote-endpoint = <&rdpm_west_cmb2_tpdm_out>; 7392 }; 7393 }; 7394 7395 port@4b { 7396 reg = <0x4b>; 7397 7398 tn_ag_in75: endpoint { 7399 remote-endpoint = <&south_dsb2_tpdm_out>; 7400 }; 7401 }; 7402 7403 port@52 { 7404 reg = <0x52>; 7405 7406 tn_ag_in82: endpoint { 7407 remote-endpoint = <&south_dsb_tpdm_out>; 7408 }; 7409 }; 7410 7411 port@53 { 7412 reg = <0x53>; 7413 7414 tn_ag_in83: endpoint { 7415 remote-endpoint = <¢er_dsb1_tpdm_out>; 7416 }; 7417 }; 7418 }; 7419 7420 out-ports { 7421 port { 7422 tn_ag_out: endpoint { 7423 remote-endpoint = <&funnel0_in0>; 7424 }; 7425 }; 7426 }; 7427 }; 7428 7429 tpdm@11207000 { 7430 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7431 reg = <0x0 0x11207000 0x0 0x1000>; 7432 7433 clocks = <&aoss_qmp>; 7434 clock-names = "apb_pclk"; 7435 label = "tpdm_mm_dsb"; 7436 7437 qcom,dsb-msrs-num = <32>; 7438 7439 out-ports { 7440 port { 7441 mm_dsb_tpdm_out: endpoint { 7442 remote-endpoint = <&tn_ag_in6>; 7443 }; 7444 }; 7445 }; 7446 }; 7447 7448 tpdm@1120b000 { 7449 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7450 reg = <0x0 0x1120b000 0x0 0x1000>; 7451 7452 clocks = <&aoss_qmp>; 7453 clock-names = "apb_pclk"; 7454 label = "tpdm_east_dsb"; 7455 7456 qcom,dsb-msrs-num = <32>; 7457 7458 out-ports { 7459 port { 7460 east_dsb_tpdm_out: endpoint { 7461 remote-endpoint = <&tn_ag_in16>; 7462 }; 7463 }; 7464 }; 7465 }; 7466 7467 tpdm@11213000 { 7468 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7469 reg = <0x0 0x11213000 0x0 0x1000>; 7470 7471 clocks = <&aoss_qmp>; 7472 clock-names = "apb_pclk"; 7473 label = "tpdm_west_dsb"; 7474 7475 qcom,dsb-msrs-num = <32>; 7476 7477 out-ports { 7478 port { 7479 west_dsb_tpdm_out: endpoint { 7480 remote-endpoint = <&tn_ag_in33>; 7481 }; 7482 }; 7483 }; 7484 }; 7485 7486 tpdm@11219000 { 7487 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7488 reg = <0x0 0x11219000 0x0 0x1000>; 7489 7490 clocks = <&aoss_qmp>; 7491 clock-names = "apb_pclk"; 7492 label = "tpdm_center_dsb"; 7493 7494 qcom,dsb-msrs-num = <32>; 7495 7496 out-ports { 7497 port { 7498 center_dsb_tpdm_out: endpoint { 7499 remote-endpoint = <&tn_ag_in63>; 7500 }; 7501 }; 7502 }; 7503 }; 7504 7505 tpdm@1121a000 { 7506 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7507 reg = <0x0 0x1121a000 0x0 0x1000>; 7508 7509 clocks = <&aoss_qmp>; 7510 clock-names = "apb_pclk"; 7511 label = "tpdm_ipcc"; 7512 7513 qcom,cmb-msrs-num = <32>; 7514 7515 out-ports { 7516 port { 7517 ipcc_cmb_tpdm_out: endpoint { 7518 remote-endpoint = <&tn_ag_in64>; 7519 }; 7520 }; 7521 }; 7522 }; 7523 7524 tpdm@1121b000 { 7525 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7526 reg = <0x0 0x1121b000 0x0 0x1000>; 7527 7528 clocks = <&aoss_qmp>; 7529 clock-names = "apb_pclk"; 7530 label = "tpdm_qrng"; 7531 7532 qcom,cmb-msrs-num = <32>; 7533 7534 out-ports { 7535 port { 7536 qrng_tpdm_out: endpoint { 7537 remote-endpoint = <&tn_ag_in65>; 7538 }; 7539 }; 7540 }; 7541 }; 7542 7543 tpdm@1121c000 { 7544 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7545 reg = <0x0 0x1121c000 0x0 0x1000>; 7546 7547 clocks = <&aoss_qmp>; 7548 clock-names = "apb_pclk"; 7549 label = "tpdm_pmu"; 7550 7551 qcom,dsb-msrs-num = <32>; 7552 7553 out-ports { 7554 port { 7555 pmu_tpdm_out: endpoint { 7556 remote-endpoint = <&tn_ag_in66>; 7557 }; 7558 }; 7559 }; 7560 }; 7561 7562 tpdm@1121d000 { 7563 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7564 reg = <0x0 0x1121d000 0x0 0x1000>; 7565 7566 clocks = <&aoss_qmp>; 7567 clock-names = "apb_pclk"; 7568 label = "tpdm_rdpm_cx"; 7569 7570 qcom,cmb-msrs-num = <32>; 7571 7572 out-ports { 7573 port { 7574 rdpm_west_cmb0_tpdm_out: endpoint { 7575 remote-endpoint = <&tn_ag_in67>; 7576 }; 7577 }; 7578 }; 7579 }; 7580 7581 tpdm@1121e000 { 7582 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7583 reg = <0x0 0x1121e000 0x0 0x1000>; 7584 7585 clocks = <&aoss_qmp>; 7586 clock-names = "apb_pclk"; 7587 label = "tpdm_rdpm_mxc"; 7588 7589 qcom,cmb-msrs-num = <32>; 7590 7591 out-ports { 7592 port { 7593 rdpm_west_cmb1_tpdm_out: endpoint { 7594 remote-endpoint = <&tn_ag_in68>; 7595 }; 7596 }; 7597 }; 7598 }; 7599 7600 tpdm@1121f000 { 7601 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7602 reg = <0x0 0x1121f000 0x0 0x1000>; 7603 7604 clocks = <&aoss_qmp>; 7605 clock-names = "apb_pclk"; 7606 label = "tpdm_rdpm_mxa"; 7607 7608 qcom,cmb-msrs-num = <32>; 7609 7610 out-ports { 7611 port { 7612 rdpm_west_cmb2_tpdm_out: endpoint { 7613 remote-endpoint = <&tn_ag_in69>; 7614 }; 7615 }; 7616 }; 7617 }; 7618 7619 tpdm@11220000 { 7620 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7621 reg = <0x0 0x11220000 0x0 0x1000>; 7622 7623 clocks = <&aoss_qmp>; 7624 clock-names = "apb_pclk"; 7625 label = "tpdm_center_dsb_1"; 7626 7627 qcom,dsb-msrs-num = <32>; 7628 7629 out-ports { 7630 port { 7631 center_dsb1_tpdm_out: endpoint { 7632 remote-endpoint = <&tn_ag_in83>; 7633 }; 7634 }; 7635 }; 7636 }; 7637 7638 tpdm@11224000 { 7639 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7640 reg = <0x0 0x11224000 0x0 0x1000>; 7641 7642 clocks = <&aoss_qmp>; 7643 clock-names = "apb_pclk"; 7644 label = "tpdm_south2_dsb"; 7645 7646 qcom,dsb-msrs-num = <32>; 7647 7648 out-ports { 7649 port { 7650 south_dsb2_tpdm_out: endpoint { 7651 remote-endpoint = <&tn_ag_in75>; 7652 }; 7653 }; 7654 }; 7655 }; 7656 7657 tpdm@11228000 { 7658 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7659 reg = <0x0 0x11228000 0x0 0x1000>; 7660 7661 clocks = <&aoss_qmp>; 7662 clock-names = "apb_pclk"; 7663 label = "tpdm_south_dsb"; 7664 7665 qcom,dsb-msrs-num = <32>; 7666 7667 out-ports { 7668 port { 7669 south_dsb_tpdm_out: endpoint { 7670 remote-endpoint = <&tn_ag_in82>; 7671 }; 7672 }; 7673 }; 7674 }; 7675 7676 tpdm@11470000 { 7677 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7678 reg = <0x0 0x11470000 0x0 0x1000>; 7679 7680 clocks = <&aoss_qmp>; 7681 clock-names = "apb_pclk"; 7682 label = "tpdm_pcie_rscc"; 7683 7684 qcom,cmb-element-bits = <32>; 7685 qcom,cmb-msrs-num = <32>; 7686 7687 out-ports { 7688 port { 7689 pcie_rscc_tpdm_out: endpoint { 7690 remote-endpoint = <&pcie_rscc_tpda_in0>; 7691 }; 7692 }; 7693 }; 7694 }; 7695 7696 tpda@11471000 { 7697 compatible = "qcom,coresight-tpda", "arm,primecell"; 7698 reg = <0x0 0x11471000 0x0 0x1000>; 7699 7700 clocks = <&aoss_qmp>; 7701 clock-names = "apb_pclk"; 7702 7703 in-ports { 7704 port { 7705 pcie_rscc_tpda_in0: endpoint { 7706 remote-endpoint = <&pcie_rscc_tpdm_out>; 7707 }; 7708 }; 7709 }; 7710 7711 out-ports { 7712 port { 7713 pcie_rscc_tpda_out: endpoint { 7714 remote-endpoint = <&tn_ag_in50>; 7715 }; 7716 }; 7717 }; 7718 }; 7719 7720 tpdm@11c03000 { 7721 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7722 reg = <0x0 0x11c03000 0x0 0x1000>; 7723 7724 clocks = <&aoss_qmp>; 7725 clock-names = "apb_pclk"; 7726 label = "tpdm_swao_prio_4"; 7727 7728 qcom,cmb-element-bits = <64>; 7729 qcom,cmb-msrs-num = <32>; 7730 7731 out-ports { 7732 port { 7733 swao_prio4_tpdm_out: endpoint { 7734 remote-endpoint = <&aoss_tpda_in4>; 7735 }; 7736 }; 7737 }; 7738 }; 7739 7740 funnel@11c04000 { 7741 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 7742 reg = <0x0 0x11c04000 0x0 0x1000>; 7743 7744 clocks = <&aoss_qmp>; 7745 clock-names = "apb_pclk"; 7746 7747 in-ports { 7748 #address-cells = <1>; 7749 #size-cells = <0>; 7750 7751 port@5 { 7752 reg = <5>; 7753 7754 aoss_funnel_in5: endpoint { 7755 remote-endpoint = <&aoss_tpda_out>; 7756 }; 7757 }; 7758 7759 port@6 { 7760 reg = <6>; 7761 7762 aoss_funnel_in6: endpoint { 7763 remote-endpoint = <&funnel0_out>; 7764 }; 7765 }; 7766 }; 7767 7768 out-ports { 7769 port { 7770 aoss_funnel_out: endpoint { 7771 remote-endpoint = <&etf0_in>; 7772 }; 7773 }; 7774 }; 7775 }; 7776 7777 tmc_etf: tmc@11c05000 { 7778 compatible = "arm,coresight-tmc", "arm,primecell"; 7779 reg = <0x0 0x11c05000 0x0 0x1000>; 7780 7781 clocks = <&aoss_qmp>; 7782 clock-names = "apb_pclk"; 7783 7784 in-ports { 7785 port { 7786 etf0_in: endpoint { 7787 remote-endpoint = <&aoss_funnel_out>; 7788 }; 7789 }; 7790 }; 7791 7792 out-ports { 7793 port { 7794 etf0_out: endpoint { 7795 remote-endpoint = <&swao_rep_in>; 7796 }; 7797 }; 7798 }; 7799 }; 7800 7801 replicator@11c06000 { 7802 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 7803 reg = <0x0 0x11c06000 0x0 0x1000>; 7804 7805 clocks = <&aoss_qmp>; 7806 clock-names = "apb_pclk"; 7807 7808 in-ports { 7809 port { 7810 swao_rep_in: endpoint { 7811 remote-endpoint = <&etf0_out>; 7812 }; 7813 }; 7814 }; 7815 7816 out-ports { 7817 #address-cells = <1>; 7818 #size-cells = <0>; 7819 7820 port@0 { 7821 reg = <0>; 7822 7823 swao_rep_out0: endpoint { 7824 remote-endpoint = <&qdss_rep_in>; 7825 }; 7826 }; 7827 7828 port@1 { 7829 reg = <1>; 7830 7831 swao_rep_out1: endpoint { 7832 remote-endpoint = <&eud_in>; 7833 }; 7834 }; 7835 }; 7836 }; 7837 7838 tpda@11c08000 { 7839 compatible = "qcom,coresight-tpda", "arm,primecell"; 7840 reg = <0x0 0x11c08000 0x0 0x1000>; 7841 7842 clocks = <&aoss_qmp>; 7843 clock-names = "apb_pclk"; 7844 7845 in-ports { 7846 #address-cells = <1>; 7847 #size-cells = <0>; 7848 7849 port@0 { 7850 reg = <0>; 7851 7852 aoss_tpda_in0: endpoint { 7853 remote-endpoint = <&swao_prio0_tpdm_out>; 7854 }; 7855 }; 7856 7857 port@1 { 7858 reg = <1>; 7859 7860 aoss_tpda_in1: endpoint { 7861 remote-endpoint = <&swao_prio1_tpdm_out>; 7862 }; 7863 }; 7864 7865 port@2 { 7866 reg = <2>; 7867 7868 aoss_tpda_in2: endpoint { 7869 remote-endpoint = <&swao_prio2_tpdm_out>; 7870 }; 7871 }; 7872 7873 port@3 { 7874 reg = <3>; 7875 7876 aoss_tpda_in3: endpoint { 7877 remote-endpoint = <&swao_prio3_tpdm_out>; 7878 }; 7879 }; 7880 7881 port@4 { 7882 reg = <4>; 7883 7884 aoss_tpda_in4: endpoint { 7885 remote-endpoint = <&swao_prio4_tpdm_out>; 7886 }; 7887 }; 7888 7889 port@5 { 7890 reg = <5>; 7891 7892 aoss_tpda_in5: endpoint { 7893 remote-endpoint = <&swao_tpdm_out>; 7894 }; 7895 }; 7896 }; 7897 7898 out-ports { 7899 port { 7900 aoss_tpda_out: endpoint { 7901 remote-endpoint = <&aoss_funnel_in5>; 7902 }; 7903 }; 7904 }; 7905 }; 7906 7907 tpdm@11c09000 { 7908 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7909 reg = <0x0 0x11c09000 0x0 0x1000>; 7910 7911 clocks = <&aoss_qmp>; 7912 clock-names = "apb_pclk"; 7913 label = "tpdm_swao_prio_0"; 7914 7915 qcom,cmb-element-bits = <64>; 7916 qcom,cmb-msrs-num = <32>; 7917 7918 out-ports { 7919 port { 7920 swao_prio0_tpdm_out: endpoint { 7921 remote-endpoint = <&aoss_tpda_in0>; 7922 }; 7923 }; 7924 }; 7925 }; 7926 7927 tpdm@11c0a000 { 7928 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7929 reg = <0x0 0x11c0a000 0x0 0x1000>; 7930 7931 clocks = <&aoss_qmp>; 7932 clock-names = "apb_pclk"; 7933 label = "tpdm_swao_prio_1"; 7934 7935 qcom,cmb-element-bits = <64>; 7936 qcom,cmb-msrs-num = <32>; 7937 7938 out-ports { 7939 port { 7940 swao_prio1_tpdm_out: endpoint { 7941 remote-endpoint = <&aoss_tpda_in1>; 7942 }; 7943 }; 7944 }; 7945 }; 7946 7947 tpdm@11c0b000 { 7948 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7949 reg = <0x0 0x11c0b000 0x0 0x1000>; 7950 7951 clocks = <&aoss_qmp>; 7952 clock-names = "apb_pclk"; 7953 label = "tpdm_swao_prio_2"; 7954 7955 qcom,cmb-element-bits = <64>; 7956 qcom,cmb-msrs-num = <32>; 7957 7958 out-ports { 7959 port { 7960 swao_prio2_tpdm_out: endpoint { 7961 remote-endpoint = <&aoss_tpda_in2>; 7962 }; 7963 }; 7964 }; 7965 }; 7966 7967 tpdm@11c0c000 { 7968 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7969 reg = <0x0 0x11c0c000 0x0 0x1000>; 7970 7971 clocks = <&aoss_qmp>; 7972 clock-names = "apb_pclk"; 7973 label = "tpdm_swao_prio_3"; 7974 7975 qcom,cmb-element-bits = <64>; 7976 qcom,cmb-msrs-num = <32>; 7977 7978 out-ports { 7979 port { 7980 swao_prio3_tpdm_out: endpoint { 7981 remote-endpoint = <&aoss_tpda_in3>; 7982 }; 7983 }; 7984 }; 7985 }; 7986 7987 tpdm@11c0d000 { 7988 compatible = "qcom,coresight-tpdm", "arm,primecell"; 7989 reg = <0x0 0x11c0d000 0x0 0x1000>; 7990 7991 clocks = <&aoss_qmp>; 7992 clock-names = "apb_pclk"; 7993 label = "tpdm_swao"; 7994 7995 qcom,dsb-element-bits = <32>; 7996 qcom,dsb-msrs-num = <32>; 7997 7998 out-ports { 7999 port { 8000 swao_tpdm_out: endpoint { 8001 remote-endpoint = <&aoss_tpda_in5>; 8002 }; 8003 }; 8004 }; 8005 }; 8006 8007 sram@14680000 { 8008 compatible = "qcom,glymur-imem", "mmio-sram"; 8009 reg = <0x0 0x14680000 0x0 0x2c000>; 8010 ranges = <0 0 0x14680000 0x2c000>; 8011 8012 no-memory-wc; 8013 8014 #address-cells = <1>; 8015 #size-cells = <1>; 8016 8017 pil-sram@94c { 8018 compatible = "qcom,pil-reloc-info"; 8019 reg = <0x94c 0xc8>; 8020 }; 8021 }; 8022 8023 apps_smmu: iommu@15000000 { 8024 compatible = "qcom,glymur-smmu-500", 8025 "qcom,smmu-500", 8026 "arm,mmu-500"; 8027 reg = <0x0 0x15000000 0x0 0x100000>; 8028 8029 #iommu-cells = <2>; 8030 #global-interrupts = <1>; 8031 8032 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 8033 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 8034 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 8035 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 8036 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 8037 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 8038 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 8039 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 8040 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 8041 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 8042 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 8043 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 8044 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 8045 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 8046 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 8047 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 8048 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 8049 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 8050 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 8051 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 8052 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 8053 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 8054 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 8055 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 8056 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 8057 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 8058 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 8059 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 8060 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 8061 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 8062 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 8063 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 8064 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 8065 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 8066 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 8067 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 8068 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 8069 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 8070 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 8071 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 8072 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 8073 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 8074 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 8075 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 8076 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 8077 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 8078 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 8079 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 8080 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 8081 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 8082 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 8083 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 8084 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 8085 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 8086 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 8087 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 8088 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 8089 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 8090 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 8091 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 8092 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 8093 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 8094 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 8095 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 8096 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 8097 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 8098 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 8099 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 8100 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 8101 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 8102 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 8103 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 8104 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 8105 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 8106 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 8107 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 8108 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 8109 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 8110 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 8111 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 8112 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 8113 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 8114 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 8115 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 8116 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 8117 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 8118 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 8119 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 8120 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 8121 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 8122 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 8123 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 8124 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 8125 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 8126 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 8127 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 8128 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 8129 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 8130 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 8131 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 8132 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 8133 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 8134 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 8135 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 8136 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 8137 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 8138 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 8139 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 8140 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 8141 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 8142 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 8143 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 8144 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 8145 8146 dma-coherent; 8147 }; 8148 8149 pcie_smmu: iommu@15480000 { 8150 compatible = "arm,smmu-v3"; 8151 reg = <0x0 0x15480000 0x0 0x20000>; 8152 interrupts = <GIC_ESPI 4 IRQ_TYPE_LEVEL_HIGH>, 8153 <GIC_ESPI 2 IRQ_TYPE_LEVEL_HIGH>, 8154 <GIC_ESPI 0 IRQ_TYPE_LEVEL_HIGH>; 8155 interrupt-names = "eventq", "cmdq-sync", "gerror"; 8156 dma-coherent; 8157 #iommu-cells = <1>; 8158 }; 8159 8160 intc: interrupt-controller@17000000 { 8161 compatible = "arm,gic-v3"; 8162 reg = <0x0 0x17000000 0x0 0x10000>, 8163 <0x0 0x17080000 0x0 0x480000>; 8164 8165 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 8166 8167 #interrupt-cells = <3>; 8168 interrupt-controller; 8169 8170 #address-cells = <2>; 8171 #size-cells = <2>; 8172 ranges; 8173 8174 gic_its: msi-controller@17040000 { 8175 compatible = "arm,gic-v3-its"; 8176 reg = <0x0 0x17040000 0x0 0x40000>; 8177 8178 msi-controller; 8179 #msi-cells = <1>; 8180 }; 8181 }; 8182 8183 watchdog@17600000 { 8184 compatible = "qcom,apss-wdt-glymur", "qcom,kpss-wdt"; 8185 reg = <0x0 0x17600000 0x0 0x1000>; 8186 clocks = <&sleep_clk>; 8187 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 8188 }; 8189 8190 pdp0_mbox: mailbox@17610000 { 8191 compatible = "qcom,glymur-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 8192 reg = <0x0 0x17610000 0 0x8000>, <0 0x19980000 0 0x8000>; 8193 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 8194 #mbox-cells = <1>; 8195 }; 8196 8197 timer@17810000 { 8198 compatible = "arm,armv7-timer-mem"; 8199 reg = <0x0 0x17810000 0x0 0x1000>; 8200 #address-cells = <2>; 8201 #size-cells = <1>; 8202 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 8203 8204 frame@17811000 { 8205 reg = <0x0 0x17811000 0x1000>, 8206 <0x0 0x17812000 0x1000>; 8207 8208 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 8209 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 8210 8211 frame-number = <0>; 8212 }; 8213 8214 frame@17813000 { 8215 reg = <0x0 0x17813000 0x1000>; 8216 8217 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 8218 8219 frame-number = <1>; 8220 8221 status = "disabled"; 8222 }; 8223 8224 frame@17815000 { 8225 reg = <0x0 0x17815000 0x1000>; 8226 8227 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 8228 8229 frame-number = <2>; 8230 8231 status = "disabled"; 8232 }; 8233 8234 frame@17817000 { 8235 reg = <0x0 0x17817000 0x1000>; 8236 8237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 8238 8239 frame-number = <3>; 8240 8241 status = "disabled"; 8242 }; 8243 8244 frame@17819000 { 8245 reg = <0x0 0x17819000 0x1000>; 8246 8247 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 8248 8249 frame-number = <4>; 8250 8251 status = "disabled"; 8252 }; 8253 8254 frame@1781b000 { 8255 reg = <0x0 0x1781b000 0x1000>; 8256 8257 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 8258 8259 frame-number = <5>; 8260 8261 status = "disabled"; 8262 }; 8263 8264 frame@1781d000 { 8265 reg = <0x0 0x1781d000 0x1000>; 8266 8267 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 8268 8269 frame-number = <6>; 8270 8271 status = "disabled"; 8272 }; 8273 }; 8274 8275 apps_rsc: rsc@18900000 { 8276 compatible = "qcom,rpmh-rsc"; 8277 label = "apps_rsc"; 8278 reg = <0x0 0x18900000 0x0 0x10000>, 8279 <0x0 0x18910000 0x0 0x10000>, 8280 <0x0 0x18920000 0x0 0x10000>; 8281 reg-names = "drv-0", 8282 "drv-1", 8283 "drv-2"; 8284 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 8285 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 8286 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 8287 qcom,tcs-offset = <0xd00>; 8288 qcom,drv-id = <2>; 8289 qcom,tcs-config = <ACTIVE_TCS 2>, 8290 <SLEEP_TCS 3>, 8291 <WAKE_TCS 3>, 8292 <CONTROL_TCS 0>; 8293 power-domains = <&system_pd>; 8294 8295 apps_bcm_voter: bcm-voter { 8296 compatible = "qcom,bcm-voter"; 8297 }; 8298 8299 rpmhcc: clock-controller { 8300 compatible = "qcom,glymur-rpmh-clk"; 8301 8302 clocks = <&xo_board>; 8303 clock-names = "xo"; 8304 8305 #clock-cells = <1>; 8306 }; 8307 8308 rpmhpd: power-controller { 8309 compatible = "qcom,glymur-rpmhpd"; 8310 8311 operating-points-v2 = <&rpmhpd_opp_table>; 8312 8313 #power-domain-cells = <1>; 8314 8315 rpmhpd_opp_table: opp-table { 8316 compatible = "operating-points-v2"; 8317 8318 rpmhpd_opp_ret: opp-16 { 8319 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 8320 }; 8321 8322 rpmhpd_opp_min_svs: opp-48 { 8323 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 8324 }; 8325 8326 rpmhpd_opp_low_svs_d2: opp-52 { 8327 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 8328 }; 8329 8330 rpmhpd_opp_low_svs_d1: opp-56 { 8331 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 8332 }; 8333 8334 rpmhpd_opp_low_svs_d0: opp-60 { 8335 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 8336 }; 8337 8338 rpmhpd_opp_low_svs: opp-64 { 8339 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 8340 }; 8341 8342 rpmhpd_opp_low_svs_l1: opp-80 { 8343 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 8344 }; 8345 8346 rpmhpd_opp_svs: opp-128 { 8347 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 8348 }; 8349 8350 rpmhpd_opp_svs_l0: opp-144 { 8351 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 8352 }; 8353 8354 rpmhpd_opp_svs_l1: opp-192 { 8355 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 8356 }; 8357 8358 rpmhpd_opp_nom: opp-256 { 8359 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 8360 }; 8361 8362 rpmhpd_opp_nom_l1: opp-320 { 8363 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 8364 }; 8365 8366 rpmhpd_opp_nom_l2: opp-336 { 8367 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 8368 }; 8369 8370 rpmhpd_opp_turbo: opp-384 { 8371 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 8372 }; 8373 8374 rpmhpd_opp_turbo_l1: opp-416 { 8375 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 8376 }; 8377 }; 8378 }; 8379 }; 8380 8381 nsi_noc: interconnect@1d600000 { 8382 compatible = "qcom,glymur-nsinoc"; 8383 reg = <0x0 0x1d600000 0x0 0x14080>; 8384 qcom,bcm-voters = <&apps_bcm_voter>; 8385 #interconnect-cells = <2>; 8386 }; 8387 8388 oobm_ss_noc: interconnect@1f300000 { 8389 compatible = "qcom,glymur-oobm-ss-noc"; 8390 reg = <0x0 0x1f300000 0x0 0x49a00>; 8391 qcom,bcm-voters = <&apps_bcm_voter>; 8392 #interconnect-cells = <2>; 8393 }; 8394 8395 system-cache-controller@21800000 { 8396 compatible = "qcom,glymur-llcc"; 8397 reg = <0x0 0x21800000 0x0 0x100000>, 8398 <0x0 0x21a00000 0x0 0x100000>, 8399 <0x0 0x21c00000 0x0 0x100000>, 8400 <0x0 0x21e00000 0x0 0x100000>, 8401 <0x0 0x22800000 0x0 0x100000>, 8402 <0x0 0x22a00000 0x0 0x100000>, 8403 <0x0 0x22c00000 0x0 0x100000>, 8404 <0x0 0x22e00000 0x0 0x100000>, 8405 <0x0 0x23800000 0x0 0x100000>, 8406 <0x0 0x23a00000 0x0 0x100000>, 8407 <0x0 0x23c00000 0x0 0x100000>, 8408 <0x0 0x23e00000 0x0 0x100000>, 8409 <0x0 0x20400000 0x0 0x100000>, 8410 <0x0 0x20600000 0x0 0x100000>; 8411 reg-names = "llcc0_base", 8412 "llcc1_base", 8413 "llcc2_base", 8414 "llcc3_base", 8415 "llcc4_base", 8416 "llcc5_base", 8417 "llcc6_base", 8418 "llcc7_base", 8419 "llcc8_base", 8420 "llcc9_base", 8421 "llcc10_base", 8422 "llcc11_base", 8423 "llcc_broadcast_base", 8424 "llcc_broadcast_and_base"; 8425 8426 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 8427 }; 8428 8429 remoteproc_cdsp: remoteproc@32300000 { 8430 compatible = "qcom,glymur-cdsp-pas", "qcom,sm8550-cdsp-pas"; 8431 reg = <0x0 0x32300000 0x0 0x10000>; 8432 8433 iommus = <&apps_smmu 0x2400 0x400>; 8434 8435 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 8436 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 8437 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 8438 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 8439 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 8440 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 8441 interrupt-names = "wdog", 8442 "fatal", 8443 "ready", 8444 "handover", 8445 "stop-ack", 8446 "shutdown-ack"; 8447 8448 clocks = <&rpmhcc RPMH_CXO_CLK>; 8449 clock-names = "xo"; 8450 8451 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 8452 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 8453 8454 power-domains = <&rpmhpd RPMHPD_CX>, 8455 <&rpmhpd RPMHPD_MXC>, 8456 <&rpmhpd RPMHPD_NSP>; 8457 power-domain-names = "cx", 8458 "mxc", 8459 "nsp"; 8460 8461 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 8462 qcom,qmp = <&aoss_qmp>; 8463 qcom,smem-states = <&smp2p_cdsp_out 0>; 8464 qcom,smem-state-names = "stop"; 8465 8466 status = "disabled"; 8467 8468 glink-edge { 8469 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 8470 IPCC_MPROC_SIGNAL_GLINK_QMP 8471 IRQ_TYPE_EDGE_RISING>; 8472 mboxes = <&ipcc IPCC_MPROC_CDSP 8473 IPCC_MPROC_SIGNAL_GLINK_QMP>; 8474 qcom,remote-pid = <5>; 8475 label = "cdsp"; 8476 8477 fastrpc { 8478 compatible = "qcom,glymur-fastrpc", "qcom,kaanapali-fastrpc"; 8479 qcom,glink-channels = "fastrpcglink-apps-dsp"; 8480 label = "cdsp"; 8481 #address-cells = <1>; 8482 #size-cells = <0>; 8483 8484 compute-cb@1 { 8485 compatible = "qcom,fastrpc-compute-cb"; 8486 reg = <1>; 8487 8488 iommus = <&apps_smmu 0x2401 0x440>, 8489 <&apps_smmu 0x1961 0x0>, 8490 <&apps_smmu 0x19c1 0x0>; 8491 dma-coherent; 8492 }; 8493 8494 compute-cb@2 { 8495 compatible = "qcom,fastrpc-compute-cb"; 8496 reg = <2>; 8497 8498 iommus = <&apps_smmu 0x2402 0x440>, 8499 <&apps_smmu 0x1962 0x0>, 8500 <&apps_smmu 0x19c2 0x0>; 8501 dma-coherent; 8502 }; 8503 8504 compute-cb@3 { 8505 compatible = "qcom,fastrpc-compute-cb"; 8506 reg = <3>; 8507 8508 iommus = <&apps_smmu 0x2403 0x440>, 8509 <&apps_smmu 0x1963 0x0>, 8510 <&apps_smmu 0x19c3 0x0>; 8511 dma-coherent; 8512 }; 8513 8514 compute-cb@4 { 8515 compatible = "qcom,fastrpc-compute-cb"; 8516 reg = <4>; 8517 8518 iommus = <&apps_smmu 0x2404 0x440>, 8519 <&apps_smmu 0x1964 0x0>, 8520 <&apps_smmu 0x19c4 0x0>; 8521 dma-coherent; 8522 }; 8523 8524 compute-cb@5 { 8525 compatible = "qcom,fastrpc-compute-cb"; 8526 reg = <5>; 8527 8528 iommus = <&apps_smmu 0x2405 0x440>, 8529 <&apps_smmu 0x1965 0x0>, 8530 <&apps_smmu 0x19c5 0x0>; 8531 dma-coherent; 8532 }; 8533 8534 compute-cb@6 { 8535 compatible = "qcom,fastrpc-compute-cb"; 8536 reg = <6>; 8537 8538 iommus = <&apps_smmu 0x2406 0x440>, 8539 <&apps_smmu 0x1966 0x0>, 8540 <&apps_smmu 0x19c6 0x0>; 8541 dma-coherent; 8542 }; 8543 8544 compute-cb@7 { 8545 compatible = "qcom,fastrpc-compute-cb"; 8546 reg = <7>; 8547 8548 iommus = <&apps_smmu 0x2407 0x440>, 8549 <&apps_smmu 0x1967 0x0>, 8550 <&apps_smmu 0x19c7 0x0>; 8551 dma-coherent; 8552 }; 8553 8554 compute-cb@8 { 8555 compatible = "qcom,fastrpc-compute-cb"; 8556 reg = <8>; 8557 8558 iommus = <&apps_smmu 0x2408 0x440>, 8559 <&apps_smmu 0x1968 0x0>, 8560 <&apps_smmu 0x19c8 0x0>; 8561 dma-coherent; 8562 }; 8563 8564 /* note: compute-cb@9 is secure */ 8565 8566 compute-cb@10 { 8567 compatible = "qcom,fastrpc-compute-cb"; 8568 reg = <10>; 8569 8570 iommus = <&apps_smmu 0x240c 0x440>, 8571 <&apps_smmu 0x196c 0x0>, 8572 <&apps_smmu 0x19cc 0x0>; 8573 dma-coherent; 8574 }; 8575 8576 compute-cb@11 { 8577 compatible = "qcom,fastrpc-compute-cb"; 8578 reg = <11>; 8579 8580 iommus = <&apps_smmu 0x240d 0x440>, 8581 <&apps_smmu 0x196d 0x0>, 8582 <&apps_smmu 0x19cd 0x0>; 8583 dma-coherent; 8584 }; 8585 8586 compute-cb@12 { 8587 compatible = "qcom,fastrpc-compute-cb"; 8588 reg = <12>; 8589 8590 iommus = <&apps_smmu 0x240e 0x440>, 8591 <&apps_smmu 0x196e 0x0>, 8592 <&apps_smmu 0x19ce 0x0>; 8593 dma-coherent; 8594 }; 8595 }; 8596 }; 8597 }; 8598 8599 nsp_noc: interconnect@320c0000 { 8600 compatible = "qcom,glymur-nsp-noc"; 8601 reg = <0x0 0x320c0000 0x0 0x21280>; 8602 qcom,bcm-voters = <&apps_bcm_voter>; 8603 #interconnect-cells = <2>; 8604 }; 8605 8606 qfprom: efuse@361c8000 { 8607 compatible = "qcom,glymur-qfprom", "qcom,qfprom"; 8608 reg = <0x0 0x361c8000 0x0 0x1000>; 8609 #address-cells = <1>; 8610 #size-cells = <1>; 8611 8612 gpu_speed_bin: gpu-speed-bin@138 { 8613 reg = <0x138 0x2>; 8614 bits = <0 9>; 8615 }; 8616 }; 8617 8618 imem: sram@81e08600 { 8619 compatible = "mmio-sram"; 8620 reg = <0x0 0x81e08600 0x0 0x300>; 8621 8622 #address-cells = <1>; 8623 #size-cells = <1>; 8624 ranges = <0x0 0x0 0x81e08600 0x300>; 8625 8626 cpu_scp_lpri0: scp-sram-section@0 { 8627 compatible = "arm,scmi-shmem"; 8628 reg = <0x0 0x180>; 8629 }; 8630 8631 cpu_scp_lpri1: scp-sram-section@180 { 8632 compatible = "arm,scmi-shmem"; 8633 reg = <0x180 0x180>; 8634 }; 8635 }; 8636 }; 8637 8638 timer { 8639 compatible = "arm,armv8-timer"; 8640 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8641 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8642 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8643 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 8644 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 8645 }; 8646 8647 thermal_zones: thermal-zones { 8648 aoss-0-thermal { 8649 thermal-sensors = <&tsens0 0>; 8650 8651 trips { 8652 aoss-0-critical { 8653 temperature = <115000>; 8654 hysteresis = <1000>; 8655 type = "critical"; 8656 }; 8657 }; 8658 }; 8659 8660 cpu-0-0-0-thermal { 8661 thermal-sensors = <&tsens0 1>; 8662 8663 trips { 8664 cpu-0-0-0-critical { 8665 temperature = <115000>; 8666 hysteresis = <1000>; 8667 type = "critical"; 8668 }; 8669 }; 8670 }; 8671 8672 cpu-0-0-1-thermal { 8673 thermal-sensors = <&tsens0 2>; 8674 8675 trips { 8676 cpu-0-0-1-critical { 8677 temperature = <115000>; 8678 hysteresis = <1000>; 8679 type = "critical"; 8680 }; 8681 }; 8682 }; 8683 8684 cpu-0-1-0-thermal { 8685 thermal-sensors = <&tsens0 3>; 8686 8687 trips { 8688 cpu-0-1-0-critical { 8689 temperature = <115000>; 8690 hysteresis = <1000>; 8691 type = "critical"; 8692 }; 8693 }; 8694 }; 8695 8696 cpu-0-1-1-thermal { 8697 thermal-sensors = <&tsens0 4>; 8698 8699 trips { 8700 cpu-0-1-1-critical { 8701 temperature = <115000>; 8702 hysteresis = <1000>; 8703 type = "critical"; 8704 }; 8705 }; 8706 }; 8707 8708 cpu-0-2-0-thermal { 8709 thermal-sensors = <&tsens0 5>; 8710 8711 trips { 8712 cpu-0-2-0-critical { 8713 temperature = <115000>; 8714 hysteresis = <1000>; 8715 type = "critical"; 8716 }; 8717 }; 8718 }; 8719 8720 cpu-0-2-1-thermal { 8721 thermal-sensors = <&tsens0 6>; 8722 8723 trips { 8724 cpu-0-2-1-critical { 8725 temperature = <115000>; 8726 hysteresis = <1000>; 8727 type = "critical"; 8728 }; 8729 }; 8730 }; 8731 8732 cpu-0-3-0-thermal { 8733 thermal-sensors = <&tsens0 7>; 8734 8735 trips { 8736 cpu-0-3-0-critical { 8737 temperature = <115000>; 8738 hysteresis = <1000>; 8739 type = "critical"; 8740 }; 8741 }; 8742 }; 8743 8744 cpu-0-3-1-thermal { 8745 thermal-sensors = <&tsens0 8>; 8746 8747 trips { 8748 cpu-0-3-1-critical { 8749 temperature = <115000>; 8750 hysteresis = <1000>; 8751 type = "critical"; 8752 }; 8753 }; 8754 }; 8755 8756 cpu-0-4-0-thermal { 8757 thermal-sensors = <&tsens0 9>; 8758 8759 trips { 8760 cpu-0-4-0-critical { 8761 temperature = <115000>; 8762 hysteresis = <1000>; 8763 type = "critical"; 8764 }; 8765 }; 8766 }; 8767 8768 cpu-0-4-1-thermal { 8769 thermal-sensors = <&tsens0 10>; 8770 8771 trips { 8772 cpu-0-4-1-critical { 8773 temperature = <115000>; 8774 hysteresis = <1000>; 8775 type = "critical"; 8776 }; 8777 }; 8778 }; 8779 8780 cpu-0-5-0-thermal { 8781 thermal-sensors = <&tsens0 11>; 8782 8783 trips { 8784 cpu-0-5-0-critical { 8785 temperature = <115000>; 8786 hysteresis = <1000>; 8787 type = "critical"; 8788 }; 8789 }; 8790 }; 8791 8792 cpu-0-5-1-thermal { 8793 thermal-sensors = <&tsens0 12>; 8794 8795 trips { 8796 cpu-0-5-1-critical { 8797 temperature = <115000>; 8798 hysteresis = <1000>; 8799 type = "critical"; 8800 }; 8801 }; 8802 }; 8803 8804 aoss-1-thermal { 8805 thermal-sensors = <&tsens1 0>; 8806 8807 trips { 8808 aoss-1-critical { 8809 temperature = <115000>; 8810 hysteresis = <1000>; 8811 type = "critical"; 8812 }; 8813 }; 8814 }; 8815 8816 cpullc-0-0-thermal { 8817 thermal-sensors = <&tsens1 1>; 8818 8819 trips { 8820 cpullc-0-0-critical { 8821 temperature = <115000>; 8822 hysteresis = <1000>; 8823 type = "critical"; 8824 }; 8825 }; 8826 }; 8827 8828 cpullc-0-1-thermal { 8829 thermal-sensors = <&tsens1 2>; 8830 8831 trips { 8832 cpullc-0-1-critical { 8833 temperature = <115000>; 8834 hysteresis = <1000>; 8835 type = "critical"; 8836 }; 8837 }; 8838 }; 8839 8840 qmx-0-0-thermal { 8841 thermal-sensors = <&tsens1 3>; 8842 8843 trips { 8844 qmx-0-0-critical { 8845 temperature = <115000>; 8846 hysteresis = <1000>; 8847 type = "critical"; 8848 }; 8849 }; 8850 }; 8851 8852 qmx-0-1-thermal { 8853 thermal-sensors = <&tsens1 4>; 8854 8855 trips { 8856 qmx-0-1-critical { 8857 temperature = <115000>; 8858 hysteresis = <1000>; 8859 type = "critical"; 8860 }; 8861 }; 8862 }; 8863 8864 qmx-0-2-thermal { 8865 thermal-sensors = <&tsens1 5>; 8866 8867 trips { 8868 qmx-0-2-critical { 8869 temperature = <115000>; 8870 hysteresis = <1000>; 8871 type = "critical"; 8872 }; 8873 }; 8874 }; 8875 8876 ddr-0-thermal { 8877 thermal-sensors = <&tsens1 6>; 8878 8879 trips { 8880 ddr-0-critical { 8881 temperature = <115000>; 8882 hysteresis = <1000>; 8883 type = "critical"; 8884 }; 8885 }; 8886 }; 8887 8888 thermal_video_0: video-0-thermal { 8889 thermal-sensors = <&tsens1 7>; 8890 8891 trips { 8892 video-0-critical { 8893 temperature = <115000>; 8894 hysteresis = <1000>; 8895 type = "critical"; 8896 }; 8897 }; 8898 }; 8899 8900 thermal_video_1: video-1-thermal { 8901 thermal-sensors = <&tsens1 8>; 8902 8903 trips { 8904 video-1-critical { 8905 temperature = <115000>; 8906 hysteresis = <1000>; 8907 type = "critical"; 8908 }; 8909 }; 8910 }; 8911 8912 aoss-2-thermal { 8913 thermal-sensors = <&tsens2 0>; 8914 8915 trips { 8916 aoss-2-critical { 8917 temperature = <115000>; 8918 hysteresis = <1000>; 8919 type = "critical"; 8920 }; 8921 }; 8922 }; 8923 8924 cpu-1-0-0-thermal { 8925 thermal-sensors = <&tsens2 1>; 8926 8927 trips { 8928 cpu-1-0-0-critical { 8929 temperature = <115000>; 8930 hysteresis = <1000>; 8931 type = "critical"; 8932 }; 8933 }; 8934 }; 8935 8936 cpu-1-0-1-thermal { 8937 thermal-sensors = <&tsens2 2>; 8938 8939 trips { 8940 cpu-1-0-1-critical { 8941 temperature = <115000>; 8942 hysteresis = <1000>; 8943 type = "critical"; 8944 }; 8945 }; 8946 }; 8947 8948 cpu-1-1-0-thermal { 8949 thermal-sensors = <&tsens2 3>; 8950 8951 trips { 8952 cpu-1-1-0-critical { 8953 temperature = <115000>; 8954 hysteresis = <1000>; 8955 type = "critical"; 8956 }; 8957 }; 8958 }; 8959 8960 cpu-1-1-1-thermal { 8961 thermal-sensors = <&tsens2 4>; 8962 8963 trips { 8964 cpu-1-1-1-critical { 8965 temperature = <115000>; 8966 hysteresis = <1000>; 8967 type = "critical"; 8968 }; 8969 }; 8970 }; 8971 8972 cpu-1-2-0-thermal { 8973 thermal-sensors = <&tsens2 5>; 8974 8975 trips { 8976 cpu-1-2-0-critical { 8977 temperature = <115000>; 8978 hysteresis = <1000>; 8979 type = "critical"; 8980 }; 8981 }; 8982 }; 8983 8984 cpu-1-2-1-thermal { 8985 thermal-sensors = <&tsens2 6>; 8986 8987 trips { 8988 cpu-1-2-1-critical { 8989 temperature = <115000>; 8990 hysteresis = <1000>; 8991 type = "critical"; 8992 }; 8993 }; 8994 }; 8995 8996 cpu-1-3-0-thermal { 8997 thermal-sensors = <&tsens2 7>; 8998 8999 trips { 9000 cpu-1-3-0-critical { 9001 temperature = <115000>; 9002 hysteresis = <1000>; 9003 type = "critical"; 9004 }; 9005 }; 9006 }; 9007 9008 cpu-1-3-1-thermal { 9009 thermal-sensors = <&tsens2 8>; 9010 9011 trips { 9012 cpu-1-3-1-critical { 9013 temperature = <115000>; 9014 hysteresis = <1000>; 9015 type = "critical"; 9016 }; 9017 }; 9018 }; 9019 9020 cpu-1-4-0-thermal { 9021 thermal-sensors = <&tsens2 9>; 9022 9023 trips { 9024 cpu-1-4-0-critical { 9025 temperature = <115000>; 9026 hysteresis = <1000>; 9027 type = "critical"; 9028 }; 9029 }; 9030 }; 9031 9032 cpu-1-4-1-thermal { 9033 thermal-sensors = <&tsens2 10>; 9034 9035 trips { 9036 cpu-1-4-1-critical { 9037 temperature = <115000>; 9038 hysteresis = <1000>; 9039 type = "critical"; 9040 }; 9041 }; 9042 }; 9043 9044 cpu-1-5-0-thermal { 9045 thermal-sensors = <&tsens2 11>; 9046 9047 trips { 9048 cpu-1-5-0-critical { 9049 temperature = <115000>; 9050 hysteresis = <1000>; 9051 type = "critical"; 9052 }; 9053 }; 9054 }; 9055 9056 cpu-1-5-1-thermal { 9057 thermal-sensors = <&tsens2 12>; 9058 9059 trips { 9060 cpu-1-5-1-critical { 9061 temperature = <115000>; 9062 hysteresis = <1000>; 9063 type = "critical"; 9064 }; 9065 }; 9066 }; 9067 9068 aoss-3-thermal { 9069 thermal-sensors = <&tsens3 0>; 9070 9071 trips { 9072 aoss-3-critical { 9073 temperature = <115000>; 9074 hysteresis = <1000>; 9075 type = "critical"; 9076 }; 9077 }; 9078 }; 9079 9080 cpullc-1-0-thermal { 9081 thermal-sensors = <&tsens3 1>; 9082 9083 trips { 9084 cpullc-1-0-critical { 9085 temperature = <115000>; 9086 hysteresis = <1000>; 9087 type = "critical"; 9088 }; 9089 }; 9090 }; 9091 9092 cpullc-1-1-thermal { 9093 thermal-sensors = <&tsens3 2>; 9094 9095 trips { 9096 cpullc-1-1-critical { 9097 temperature = <115000>; 9098 hysteresis = <1000>; 9099 type = "critical"; 9100 }; 9101 }; 9102 }; 9103 9104 qmx-1-0-thermal { 9105 thermal-sensors = <&tsens3 3>; 9106 9107 trips { 9108 qmx-1-0-critical { 9109 temperature = <115000>; 9110 hysteresis = <1000>; 9111 type = "critical"; 9112 }; 9113 }; 9114 }; 9115 9116 qmx-1-1-thermal { 9117 thermal-sensors = <&tsens3 4>; 9118 9119 trips { 9120 qmx-1-1-critical { 9121 temperature = <115000>; 9122 hysteresis = <1000>; 9123 type = "critical"; 9124 }; 9125 }; 9126 }; 9127 9128 qmx-1-2-thermal { 9129 thermal-sensors = <&tsens3 5>; 9130 9131 trips { 9132 qmx-1-2-critical { 9133 temperature = <115000>; 9134 hysteresis = <1000>; 9135 type = "critical"; 9136 }; 9137 }; 9138 }; 9139 9140 qmx-1-3-thermal { 9141 thermal-sensors = <&tsens3 6>; 9142 9143 trips { 9144 qmx-1-3-critical { 9145 temperature = <115000>; 9146 hysteresis = <1000>; 9147 type = "critical"; 9148 }; 9149 }; 9150 }; 9151 9152 qmx-1-4-thermal { 9153 thermal-sensors = <&tsens3 7>; 9154 9155 trips { 9156 qmx-1-4-critical { 9157 temperature = <115000>; 9158 hysteresis = <1000>; 9159 type = "critical"; 9160 }; 9161 }; 9162 }; 9163 9164 aoss-4-thermal { 9165 thermal-sensors = <&tsens4 0>; 9166 9167 trips { 9168 aoss-4-critical { 9169 temperature = <115000>; 9170 hysteresis = <1000>; 9171 type = "critical"; 9172 }; 9173 }; 9174 }; 9175 9176 thermal_cpu_2_0_0: cpu-2-0-0-thermal { 9177 thermal-sensors = <&tsens4 1>; 9178 9179 trips { 9180 cpu-2-0-0-critical { 9181 temperature = <115000>; 9182 hysteresis = <1000>; 9183 type = "critical"; 9184 }; 9185 }; 9186 }; 9187 9188 thermal_cpu_2_0_1: cpu-2-0-1-thermal { 9189 thermal-sensors = <&tsens4 2>; 9190 9191 trips { 9192 cpu-2-0-1-critical { 9193 temperature = <115000>; 9194 hysteresis = <1000>; 9195 type = "critical"; 9196 }; 9197 }; 9198 }; 9199 9200 thermal_cpu_2_1_0: cpu-2-1-0-thermal { 9201 thermal-sensors = <&tsens4 3>; 9202 9203 trips { 9204 cpu-2-1-0-critical { 9205 temperature = <115000>; 9206 hysteresis = <1000>; 9207 type = "critical"; 9208 }; 9209 }; 9210 }; 9211 9212 thermal_cpu_2_1_1: cpu-2-1-1-thermal { 9213 thermal-sensors = <&tsens4 4>; 9214 9215 trips { 9216 cpu-2-1-1-critical { 9217 temperature = <115000>; 9218 hysteresis = <1000>; 9219 type = "critical"; 9220 }; 9221 }; 9222 }; 9223 9224 thermal_cpu_2_2_0: cpu-2-2-0-thermal { 9225 thermal-sensors = <&tsens4 5>; 9226 9227 trips { 9228 cpu-2-2-0-critical { 9229 temperature = <115000>; 9230 hysteresis = <1000>; 9231 type = "critical"; 9232 }; 9233 }; 9234 }; 9235 9236 thermal_cpu_2_2_1: cpu-2-2-1-thermal { 9237 thermal-sensors = <&tsens4 6>; 9238 9239 trips { 9240 cpu-2-2-1-critical { 9241 temperature = <115000>; 9242 hysteresis = <1000>; 9243 type = "critical"; 9244 }; 9245 }; 9246 }; 9247 9248 thermal_cpu_2_3_0: cpu-2-3-0-thermal { 9249 thermal-sensors = <&tsens4 7>; 9250 9251 trips { 9252 cpu-2-3-0-critical { 9253 temperature = <115000>; 9254 hysteresis = <1000>; 9255 type = "critical"; 9256 }; 9257 }; 9258 }; 9259 9260 thermal_cpu_2_3_1: cpu-2-3-1-thermal { 9261 thermal-sensors = <&tsens4 8>; 9262 9263 trips { 9264 cpu-2-3-1-critical { 9265 temperature = <115000>; 9266 hysteresis = <1000>; 9267 type = "critical"; 9268 }; 9269 }; 9270 }; 9271 9272 thermal_cpu_2_4_0: cpu-2-4-0-thermal { 9273 thermal-sensors = <&tsens4 9>; 9274 9275 trips { 9276 cpu-2-4-0-critical { 9277 temperature = <115000>; 9278 hysteresis = <1000>; 9279 type = "critical"; 9280 }; 9281 }; 9282 }; 9283 9284 thermal_cpu_2_4_1: cpu-2-4-1-thermal { 9285 thermal-sensors = <&tsens4 10>; 9286 9287 trips { 9288 cpu-2-4-1-critical { 9289 temperature = <115000>; 9290 hysteresis = <1000>; 9291 type = "critical"; 9292 }; 9293 }; 9294 }; 9295 9296 thermal_cpu_2_5_0: cpu-2-5-0-thermal { 9297 thermal-sensors = <&tsens4 11>; 9298 9299 trips { 9300 cpu-2-5-0-critical { 9301 temperature = <115000>; 9302 hysteresis = <1000>; 9303 type = "critical"; 9304 }; 9305 }; 9306 }; 9307 9308 thermal_cpu_2_5_1: cpu-2-5-1-thermal { 9309 thermal-sensors = <&tsens4 12>; 9310 9311 trips { 9312 cpu-2-5-1-critical { 9313 temperature = <115000>; 9314 hysteresis = <1000>; 9315 type = "critical"; 9316 }; 9317 }; 9318 }; 9319 9320 aoss-5-thermal { 9321 thermal-sensors = <&tsens5 0>; 9322 9323 trips { 9324 aoss-5-critical { 9325 temperature = <115000>; 9326 hysteresis = <1000>; 9327 type = "critical"; 9328 }; 9329 }; 9330 }; 9331 9332 thermal_cpullc_2_0: cpullc-2-0-thermal { 9333 thermal-sensors = <&tsens5 1>; 9334 9335 trips { 9336 cpullc-2-0-critical { 9337 temperature = <115000>; 9338 hysteresis = <1000>; 9339 type = "critical"; 9340 }; 9341 }; 9342 }; 9343 9344 thermal_cpuillc_2_1: cpuillc-2-1-thermal { 9345 thermal-sensors = <&tsens5 2>; 9346 9347 trips { 9348 cpullc-2-1-critical { 9349 temperature = <115000>; 9350 hysteresis = <1000>; 9351 type = "critical"; 9352 }; 9353 }; 9354 }; 9355 9356 thermal_qmx_2_0: qmx-2-0-thermal { 9357 thermal-sensors = <&tsens5 3>; 9358 9359 trips { 9360 qmx-2-0-critical { 9361 temperature = <115000>; 9362 hysteresis = <1000>; 9363 type = "critical"; 9364 }; 9365 }; 9366 }; 9367 9368 thermal_qmx_2_1: qmx-2-1-thermal { 9369 thermal-sensors = <&tsens5 4>; 9370 9371 trips { 9372 qmx-2-1-critical { 9373 temperature = <115000>; 9374 hysteresis = <1000>; 9375 type = "critical"; 9376 }; 9377 }; 9378 }; 9379 9380 thermal_qmx_2_2: qmx-2-2-thermal { 9381 thermal-sensors = <&tsens5 5>; 9382 9383 trips { 9384 qmx-2-2-critical { 9385 temperature = <115000>; 9386 hysteresis = <1000>; 9387 type = "critical"; 9388 }; 9389 }; 9390 }; 9391 9392 thermal_qmx_2_3: qmx-2-3-thermal { 9393 thermal-sensors = <&tsens5 6>; 9394 9395 trips { 9396 qmx-2-3-critical { 9397 temperature = <115000>; 9398 hysteresis = <1000>; 9399 type = "critical"; 9400 }; 9401 }; 9402 }; 9403 9404 thermal_qmx_2_4: qmx-2-4-thermal { 9405 thermal-sensors = <&tsens5 7>; 9406 9407 trips { 9408 qmx-2-4-critical { 9409 temperature = <115000>; 9410 hysteresis = <1000>; 9411 type = "critical"; 9412 }; 9413 }; 9414 }; 9415 9416 thermal_aoss_6: aoss-6-thermal { 9417 thermal-sensors = <&tsens6 0>; 9418 9419 trips { 9420 aoss-6-critical { 9421 temperature = <115000>; 9422 hysteresis = <1000>; 9423 type = "critical"; 9424 }; 9425 }; 9426 }; 9427 9428 thermal_nsphvx_0: nsphvx-0-thermal { 9429 thermal-sensors = <&tsens6 1>; 9430 9431 trips { 9432 nsphvx-0-critical { 9433 temperature = <115000>; 9434 hysteresis = <1000>; 9435 type = "critical"; 9436 }; 9437 }; 9438 }; 9439 9440 thermal_nsphvx_1: nsphvx-1-thermal { 9441 thermal-sensors = <&tsens6 2>; 9442 9443 trips { 9444 nsphvx-1-critical { 9445 temperature = <115000>; 9446 hysteresis = <1000>; 9447 type = "critical"; 9448 }; 9449 }; 9450 }; 9451 9452 thermal_nsphvx_2: nsphvx-2-thermal { 9453 thermal-sensors = <&tsens6 3>; 9454 9455 trips { 9456 nsphvx-2-critical { 9457 temperature = <115000>; 9458 hysteresis = <1000>; 9459 type = "critical"; 9460 }; 9461 }; 9462 }; 9463 9464 thermal_nsphvx_3: nsphvx-3-thermal { 9465 thermal-sensors = <&tsens6 4>; 9466 9467 trips { 9468 nsphvx-3-critical { 9469 temperature = <115000>; 9470 hysteresis = <1000>; 9471 type = "critical"; 9472 }; 9473 }; 9474 }; 9475 9476 thermal_nsphmx_0: nsphmx-0-thermal { 9477 thermal-sensors = <&tsens6 5>; 9478 9479 trips { 9480 nsphmx-0-critical { 9481 temperature = <115000>; 9482 hysteresis = <1000>; 9483 type = "critical"; 9484 }; 9485 }; 9486 }; 9487 9488 thermal_nsphmx_1: nsphmx-1-thermal { 9489 thermal-sensors = <&tsens6 6>; 9490 9491 trips { 9492 nsphmx-1-critical { 9493 temperature = <115000>; 9494 hysteresis = <1000>; 9495 type = "critical"; 9496 }; 9497 }; 9498 }; 9499 9500 thermal_nsphmx_2: nsphmx-2-thermal { 9501 thermal-sensors = <&tsens6 7>; 9502 9503 trips { 9504 nsphmx-2-critical { 9505 temperature = <115000>; 9506 hysteresis = <1000>; 9507 type = "critical"; 9508 }; 9509 }; 9510 }; 9511 9512 thermal_nsphmx_3: nsphmx-3-thermal { 9513 thermal-sensors = <&tsens6 8>; 9514 9515 trips { 9516 nsphmx-3-critical { 9517 temperature = <115000>; 9518 hysteresis = <1000>; 9519 type = "critical"; 9520 }; 9521 }; 9522 }; 9523 9524 thermal_camera_0: camera-0-thermal { 9525 thermal-sensors = <&tsens6 9>; 9526 9527 trips { 9528 camera-0-critical { 9529 temperature = <115000>; 9530 hysteresis = <1000>; 9531 type = "critical"; 9532 }; 9533 }; 9534 }; 9535 9536 thermal_camera_1: camera-1-thermal { 9537 thermal-sensors = <&tsens6 10>; 9538 9539 trips { 9540 camera-1-critical { 9541 temperature = <115000>; 9542 hysteresis = <1000>; 9543 type = "critical"; 9544 }; 9545 }; 9546 }; 9547 9548 thermal_ddr_1: ddr-1-thermal { 9549 thermal-sensors = <&tsens6 11>; 9550 9551 trips { 9552 ddr-1-critical { 9553 temperature = <115000>; 9554 hysteresis = <1000>; 9555 type = "critical"; 9556 }; 9557 }; 9558 }; 9559 9560 thermal_ddr_2: ddr-2-thermal { 9561 thermal-sensors = <&tsens6 12>; 9562 9563 trips { 9564 ddr-2-critical { 9565 temperature = <115000>; 9566 hysteresis = <1000>; 9567 type = "critical"; 9568 }; 9569 }; 9570 }; 9571 9572 thermal_aoss_7: aoss-7-thermal { 9573 thermal-sensors = <&tsens7 0>; 9574 9575 trips { 9576 aoss-7-critical { 9577 temperature = <115000>; 9578 hysteresis = <1000>; 9579 type = "critical"; 9580 }; 9581 }; 9582 }; 9583 9584 thermal_gpu_0_0: gpu-0-0-thermal { 9585 polling-delay-passive = <100>; 9586 9587 thermal-sensors = <&tsens7 1>; 9588 9589 cooling-maps { 9590 map0 { 9591 trip = <&gpu00_alert0>; 9592 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9593 }; 9594 }; 9595 9596 trips { 9597 gpu00_alert0: trip-point0 { 9598 temperature = <95000>; 9599 hysteresis = <1000>; 9600 type = "passive"; 9601 }; 9602 9603 gpu-0-0-critical { 9604 temperature = <115000>; 9605 hysteresis = <1000>; 9606 type = "critical"; 9607 }; 9608 }; 9609 9610 }; 9611 9612 thermal_gpu_0_1: gpu-0-1-thermal { 9613 polling-delay-passive = <100>; 9614 9615 thermal-sensors = <&tsens7 2>; 9616 9617 cooling-maps { 9618 map0 { 9619 trip = <&gpu01_alert0>; 9620 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9621 }; 9622 }; 9623 9624 trips { 9625 gpu01_alert0: trip-point0 { 9626 temperature = <95000>; 9627 hysteresis = <1000>; 9628 type = "passive"; 9629 }; 9630 9631 gpu-0-1-critical { 9632 temperature = <115000>; 9633 hysteresis = <1000>; 9634 type = "critical"; 9635 }; 9636 }; 9637 }; 9638 9639 thermal_gpu_0_2: gpu-0-2-thermal { 9640 polling-delay-passive = <100>; 9641 9642 thermal-sensors = <&tsens7 3>; 9643 9644 cooling-maps { 9645 map0 { 9646 trip = <&gpu02_alert0>; 9647 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9648 }; 9649 }; 9650 9651 trips { 9652 gpu02_alert0: trip-point0 { 9653 temperature = <95000>; 9654 hysteresis = <1000>; 9655 type = "passive"; 9656 }; 9657 9658 gpu-0-2-critical { 9659 temperature = <115000>; 9660 hysteresis = <1000>; 9661 type = "critical"; 9662 }; 9663 }; 9664 }; 9665 9666 thermal_gpu_1_0: gpu-1-0-thermal { 9667 polling-delay-passive = <100>; 9668 9669 thermal-sensors = <&tsens7 4>; 9670 9671 cooling-maps { 9672 map0 { 9673 trip = <&gpu10_alert0>; 9674 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9675 }; 9676 }; 9677 9678 trips { 9679 gpu10_alert0: trip-point0 { 9680 temperature = <95000>; 9681 hysteresis = <1000>; 9682 type = "passive"; 9683 }; 9684 9685 gpu-1-0-critical { 9686 temperature = <115000>; 9687 hysteresis = <1000>; 9688 type = "critical"; 9689 }; 9690 }; 9691 }; 9692 9693 thermal_gpu_1_1: gpu-1-1-thermal { 9694 polling-delay-passive = <100>; 9695 9696 thermal-sensors = <&tsens7 5>; 9697 9698 cooling-maps { 9699 map0 { 9700 trip = <&gpu11_alert0>; 9701 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9702 }; 9703 }; 9704 9705 trips { 9706 gpu11_alert0: trip-point0 { 9707 temperature = <95000>; 9708 hysteresis = <1000>; 9709 type = "passive"; 9710 }; 9711 9712 gpu-1-1-critical { 9713 temperature = <115000>; 9714 hysteresis = <1000>; 9715 type = "critical"; 9716 }; 9717 }; 9718 }; 9719 9720 thermal_gpu_1_2: gpu-1-2-thermal { 9721 polling-delay-passive = <100>; 9722 9723 thermal-sensors = <&tsens7 6>; 9724 9725 cooling-maps { 9726 map0 { 9727 trip = <&gpu12_alert0>; 9728 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9729 }; 9730 }; 9731 9732 trips { 9733 gpu12_alert0: trip-point0 { 9734 temperature = <95000>; 9735 hysteresis = <1000>; 9736 type = "passive"; 9737 }; 9738 9739 gpu-1-2-critical { 9740 temperature = <115000>; 9741 hysteresis = <1000>; 9742 type = "critical"; 9743 }; 9744 }; 9745 }; 9746 9747 thermal_gpu_2_0: gpu-2-0-thermal { 9748 polling-delay-passive = <100>; 9749 9750 thermal-sensors = <&tsens7 7>; 9751 9752 cooling-maps { 9753 map0 { 9754 trip = <&gpu20_alert0>; 9755 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9756 }; 9757 }; 9758 9759 trips { 9760 gpu20_alert0: trip-point0 { 9761 temperature = <95000>; 9762 hysteresis = <1000>; 9763 type = "passive"; 9764 }; 9765 9766 gpu-2-0-critical { 9767 temperature = <115000>; 9768 hysteresis = <1000>; 9769 type = "critical"; 9770 }; 9771 }; 9772 }; 9773 9774 thermal_gpu_2_1: gpu-2-1-thermal { 9775 polling-delay-passive = <100>; 9776 9777 thermal-sensors = <&tsens7 8>; 9778 9779 cooling-maps { 9780 map0 { 9781 trip = <&gpu21_alert0>; 9782 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9783 }; 9784 }; 9785 9786 trips { 9787 gpu21_alert0: trip-point0 { 9788 temperature = <95000>; 9789 hysteresis = <1000>; 9790 type = "passive"; 9791 }; 9792 9793 gpu-2-1-critical { 9794 temperature = <115000>; 9795 hysteresis = <1000>; 9796 type = "critical"; 9797 }; 9798 }; 9799 }; 9800 9801 thermal_gpu_2_2: gpu-2-2-thermal { 9802 polling-delay-passive = <100>; 9803 9804 thermal-sensors = <&tsens7 9>; 9805 9806 cooling-maps { 9807 map0 { 9808 trip = <&gpu22_alert0>; 9809 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9810 }; 9811 }; 9812 9813 trips { 9814 gpu22_alert0: trip-point0 { 9815 temperature = <95000>; 9816 hysteresis = <1000>; 9817 type = "passive"; 9818 }; 9819 9820 gpu-2-2-critical { 9821 temperature = <115000>; 9822 hysteresis = <1000>; 9823 type = "critical"; 9824 }; 9825 }; 9826 }; 9827 9828 thermal_gpu_3_0: gpu-3-0-thermal { 9829 polling-delay-passive = <100>; 9830 9831 thermal-sensors = <&tsens7 10>; 9832 9833 cooling-maps { 9834 map0 { 9835 trip = <&gpu30_alert0>; 9836 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9837 }; 9838 }; 9839 9840 trips { 9841 gpu30_alert0: trip-point0 { 9842 temperature = <95000>; 9843 hysteresis = <1000>; 9844 type = "passive"; 9845 }; 9846 9847 gpu-3-0-critical { 9848 temperature = <115000>; 9849 hysteresis = <1000>; 9850 type = "critical"; 9851 }; 9852 }; 9853 }; 9854 9855 thermal_gpu_3_1: gpu-3-1-thermal { 9856 polling-delay-passive = <100>; 9857 9858 thermal-sensors = <&tsens7 11>; 9859 9860 cooling-maps { 9861 map0 { 9862 trip = <&gpu31_alert0>; 9863 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9864 }; 9865 }; 9866 9867 trips { 9868 gpu31_alert0: trip-point0 { 9869 temperature = <95000>; 9870 hysteresis = <1000>; 9871 type = "passive"; 9872 }; 9873 9874 gpu-3-1-critical { 9875 temperature = <115000>; 9876 hysteresis = <1000>; 9877 type = "critical"; 9878 }; 9879 }; 9880 }; 9881 9882 thermal_gpu_3_2: gpu-3-2-thermal { 9883 polling-delay-passive = <100>; 9884 9885 thermal-sensors = <&tsens7 12>; 9886 9887 cooling-maps { 9888 map0 { 9889 trip = <&gpu32_alert0>; 9890 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9891 }; 9892 }; 9893 9894 trips { 9895 gpu32_alert0: trip-point0 { 9896 temperature = <95000>; 9897 hysteresis = <1000>; 9898 type = "passive"; 9899 }; 9900 9901 gpu-3-2-critical { 9902 temperature = <115000>; 9903 hysteresis = <1000>; 9904 type = "critical"; 9905 }; 9906 }; 9907 }; 9908 9909 thermal_gpuss_0: gpuss-0-thermal { 9910 polling-delay-passive = <100>; 9911 9912 thermal-sensors = <&tsens7 13>; 9913 9914 cooling-maps { 9915 map0 { 9916 trip = <&gpuss0_alert0>; 9917 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9918 }; 9919 }; 9920 9921 trips { 9922 gpuss0_alert0: trip-point0 { 9923 temperature = <95000>; 9924 hysteresis = <1000>; 9925 type = "passive"; 9926 }; 9927 9928 gpuss-0-critical { 9929 temperature = <115000>; 9930 hysteresis = <1000>; 9931 type = "critical"; 9932 }; 9933 }; 9934 }; 9935 9936 thermal_gpuss_1: gpuss-1-thermal { 9937 polling-delay-passive = <100>; 9938 9939 thermal-sensors = <&tsens7 14>; 9940 9941 cooling-maps { 9942 map0 { 9943 trip = <&gpuss1_alert0>; 9944 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 9945 }; 9946 }; 9947 9948 trips { 9949 gpuss1_alert0: trip-point0 { 9950 temperature = <95000>; 9951 hysteresis = <1000>; 9952 type = "passive"; 9953 }; 9954 9955 gpuss-1-critical { 9956 temperature = <115000>; 9957 hysteresis = <1000>; 9958 type = "critical"; 9959 }; 9960 }; 9961 }; 9962 }; 9963 9964 tpdm-cdsp-llm { 9965 compatible = "qcom,coresight-static-tpdm"; 9966 qcom,cmb-element-bits = <32>; 9967 9968 out-ports { 9969 port { 9970 cdsp_llm_tpdm_out: endpoint { 9971 remote-endpoint = <&cdsp_tpda_in1>; 9972 }; 9973 }; 9974 }; 9975 }; 9976 9977 tpdm-cdsp-llm2 { 9978 compatible = "qcom,coresight-static-tpdm"; 9979 qcom,cmb-element-bits = <32>; 9980 9981 out-ports { 9982 port { 9983 cdsp_llm2_tpdm_out: endpoint { 9984 remote-endpoint = <&cdsp_tpda_in2>; 9985 }; 9986 }; 9987 }; 9988 }; 9989 9990 tpdm-cdsp-cmsr { 9991 compatible = "qcom,coresight-static-tpdm"; 9992 9993 qcom,cmb-element-bits = <32>; 9994 qcom,dsb-element-bits = <32>; 9995 9996 out-ports { 9997 port { 9998 cdsp_cmsr_tpdm_out: endpoint { 9999 remote-endpoint = <&cdsp_tpda_in3>; 10000 }; 10001 }; 10002 }; 10003 }; 10004 10005 tpdm-cdsp-cmsr2 { 10006 compatible = "qcom,coresight-static-tpdm"; 10007 10008 qcom,cmb-element-bits = <32>; 10009 qcom,dsb-element-bits = <32>; 10010 10011 out-ports { 10012 port { 10013 cdsp_cmsr2_tpdm_out: endpoint { 10014 remote-endpoint = <&cdsp_tpda_in4>; 10015 }; 10016 }; 10017 }; 10018 }; 10019}; 10020