1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 - 2025 Intel Corporation
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/bitfield.h>
8 #include <linux/bits.h>
9 #include <linux/bug.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
12 #include <linux/firmware.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/list.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/property.h>
20 #include <linux/scatterlist.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <linux/vmalloc.h>
24
25 #include <media/ipu-bridge.h>
26
27 #include "abi/ipu7_fw_common_abi.h"
28
29 #include "ipu7.h"
30 #include "ipu7-bus.h"
31 #include "ipu7-buttress.h"
32 #include "ipu7-buttress-regs.h"
33 #include "ipu7-cpd.h"
34 #include "ipu7-dma.h"
35 #include "ipu7-isys-csi2-regs.h"
36 #include "ipu7-mmu.h"
37 #include "ipu7-platform-regs.h"
38
39 #define IPU_PCI_BAR 0
40 #define IPU_PCI_PBBAR 4
41
42 static const unsigned int ipu7_csi_offsets[] = {
43 IPU_CSI_PORT_A_ADDR_OFFSET,
44 IPU_CSI_PORT_B_ADDR_OFFSET,
45 IPU_CSI_PORT_C_ADDR_OFFSET,
46 IPU_CSI_PORT_D_ADDR_OFFSET,
47 };
48
49 static struct ipu_isys_internal_pdata ipu7p5_isys_ipdata = {
50 .csi2 = {
51 .gpreg = IS_IO_CSI2_GPREGS_BASE,
52 },
53 .hw_variant = {
54 .offset = IPU_UNIFIED_OFFSET,
55 .nr_mmus = IPU7P5_IS_MMU_NUM,
56 .mmu_hw = {
57 {
58 .name = "IS_FW_RD",
59 .offset = IPU7P5_IS_MMU_FW_RD_OFFSET,
60 .zlx_offset = IPU7P5_IS_ZLX_UC_RD_OFFSET,
61 .uao_offset = IPU7P5_IS_UAO_UC_RD_OFFSET,
62 .info_bits = 0x20005101,
63 .refill = 0x00002726,
64 .collapse_en_bitmap = 0x1,
65 .at_sp_arb_cfg = 0x1,
66 .l1_block = IPU7P5_IS_MMU_FW_RD_L1_BLOCKNR_REG,
67 .l2_block = IPU7P5_IS_MMU_FW_RD_L2_BLOCKNR_REG,
68 .nr_l1streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM,
69 .nr_l2streams = IPU7P5_IS_MMU_FW_RD_STREAM_NUM,
70 .l1_block_sz = {
71 0x0, 0x8, 0xa,
72 },
73 .l2_block_sz = {
74 0x0, 0x2, 0x4,
75 },
76 .zlx_nr = IPU7P5_IS_ZLX_UC_RD_NUM,
77 .zlx_axi_pool = {
78 0x00000f30,
79 },
80 .zlx_en = {
81 0, 1, 0, 0
82 },
83 .zlx_conf = {
84 0x0,
85 },
86 .uao_p_num = IPU7P5_IS_UAO_UC_RD_PLANENUM,
87 .uao_p2tlb = {
88 0x00000049,
89 0x0000004c,
90 0x0000004d,
91 0x00000000,
92 },
93 },
94 {
95 .name = "IS_FW_WR",
96 .offset = IPU7P5_IS_MMU_FW_WR_OFFSET,
97 .zlx_offset = IPU7P5_IS_ZLX_UC_WR_OFFSET,
98 .uao_offset = IPU7P5_IS_UAO_UC_WR_OFFSET,
99 .info_bits = 0x20005001,
100 .refill = 0x00002524,
101 .collapse_en_bitmap = 0x1,
102 .at_sp_arb_cfg = 0x1,
103 .l1_block = IPU7P5_IS_MMU_FW_WR_L1_BLOCKNR_REG,
104 .l2_block = IPU7P5_IS_MMU_FW_WR_L2_BLOCKNR_REG,
105 .nr_l1streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM,
106 .nr_l2streams = IPU7P5_IS_MMU_FW_WR_STREAM_NUM,
107 .l1_block_sz = {
108 0x0, 0x8, 0xa,
109 },
110 .l2_block_sz = {
111 0x0, 0x2, 0x4,
112 },
113 .zlx_nr = IPU7P5_IS_ZLX_UC_WR_NUM,
114 .zlx_axi_pool = {
115 0x00000f20,
116 },
117 .zlx_en = {
118 0, 1, 1, 0,
119 },
120 .zlx_conf = {
121 0x0,
122 0x00010101,
123 0x00010101,
124 0x0,
125 },
126 .uao_p_num = IPU7P5_IS_UAO_UC_WR_PLANENUM,
127 .uao_p2tlb = {
128 0x00000049,
129 0x0000004a,
130 0x0000004b,
131 0x00000000,
132 },
133 },
134 {
135 .name = "IS_DATA_WR_ISOC",
136 .offset = IPU7P5_IS_MMU_M0_OFFSET,
137 .zlx_offset = IPU7P5_IS_ZLX_M0_OFFSET,
138 .uao_offset = IPU7P5_IS_UAO_M0_WR_OFFSET,
139 .info_bits = 0x20004e01,
140 .refill = 0x00002120,
141 .collapse_en_bitmap = 0x1,
142 .at_sp_arb_cfg = 0x1,
143 .l1_block = IPU7P5_IS_MMU_M0_L1_BLOCKNR_REG,
144 .l2_block = IPU7P5_IS_MMU_M0_L2_BLOCKNR_REG,
145 .nr_l1streams = IPU7P5_IS_MMU_M0_STREAM_NUM,
146 .nr_l2streams = IPU7P5_IS_MMU_M0_STREAM_NUM,
147 .l1_block_sz = {
148 0x00000000,
149 0x00000002,
150 0x00000004,
151 0x00000006,
152 0x00000008,
153 0x0000000a,
154 0x0000000c,
155 0x0000000e,
156 0x00000010,
157 0x00000012,
158 0x00000014,
159 0x00000016,
160 0x00000018,
161 0x0000001a,
162 0x0000001c,
163 0x0000001e,
164 },
165 .l2_block_sz = {
166 0x00000000,
167 0x00000002,
168 0x00000004,
169 0x00000006,
170 0x00000008,
171 0x0000000a,
172 0x0000000c,
173 0x0000000e,
174 0x00000010,
175 0x00000012,
176 0x00000014,
177 0x00000016,
178 0x00000018,
179 0x0000001a,
180 0x0000001c,
181 0x0000001e,
182 },
183 .zlx_nr = IPU7P5_IS_ZLX_M0_NUM,
184 .zlx_axi_pool = {
185 0x00000f10,
186 },
187 .zlx_en = {
188 1, 1, 1, 1, 1, 1, 1, 1,
189 1, 1, 1, 1, 1, 1, 1, 1,
190 },
191 .zlx_conf = {
192 0x00010103,
193 0x00010103,
194 0x00010103,
195 0x00010103,
196 0x00010103,
197 0x00010103,
198 0x00010103,
199 0x00010103,
200 0x00010103,
201 0x00010103,
202 0x00010103,
203 0x00010103,
204 0x00010103,
205 0x00010103,
206 0x00010103,
207 0x00010103,
208 },
209 .uao_p_num = IPU7P5_IS_UAO_M0_WR_PLANENUM,
210 .uao_p2tlb = {
211 0x00000041,
212 0x00000042,
213 0x00000043,
214 0x00000044,
215 0x00000041,
216 0x00000042,
217 0x00000043,
218 0x00000044,
219 0x00000041,
220 0x00000042,
221 0x00000043,
222 0x00000044,
223 0x00000041,
224 0x00000042,
225 0x00000043,
226 0x00000044,
227 },
228 },
229 {
230 .name = "IS_DATA_WR_SNOOP",
231 .offset = IPU7P5_IS_MMU_M1_OFFSET,
232 .zlx_offset = IPU7P5_IS_ZLX_M1_OFFSET,
233 .uao_offset = IPU7P5_IS_UAO_M1_WR_OFFSET,
234 .info_bits = 0x20004f01,
235 .refill = 0x00002322,
236 .collapse_en_bitmap = 0x1,
237 .at_sp_arb_cfg = 0x1,
238 .l1_block = IPU7P5_IS_MMU_M1_L1_BLOCKNR_REG,
239 .l2_block = IPU7P5_IS_MMU_M1_L2_BLOCKNR_REG,
240 .nr_l1streams = IPU7P5_IS_MMU_M1_STREAM_NUM,
241 .nr_l2streams = IPU7P5_IS_MMU_M1_STREAM_NUM,
242 .l1_block_sz = {
243 0x00000000,
244 0x00000002,
245 0x00000004,
246 0x00000006,
247 0x00000008,
248 0x0000000a,
249 0x0000000c,
250 0x0000000e,
251 0x00000010,
252 0x00000012,
253 0x00000014,
254 0x00000016,
255 0x00000018,
256 0x0000001a,
257 0x0000001c,
258 0x0000001e,
259 },
260 .l2_block_sz = {
261 0x00000000,
262 0x00000002,
263 0x00000004,
264 0x00000006,
265 0x00000008,
266 0x0000000a,
267 0x0000000c,
268 0x0000000e,
269 0x00000010,
270 0x00000012,
271 0x00000014,
272 0x00000016,
273 0x00000018,
274 0x0000001a,
275 0x0000001c,
276 0x0000001e,
277 },
278 .zlx_nr = IPU7P5_IS_ZLX_M1_NUM,
279 .zlx_axi_pool = {
280 0x00000f20,
281 },
282 .zlx_en = {
283 1, 1, 1, 1, 1, 1, 1, 1,
284 1, 1, 1, 1, 1, 1, 1, 1,
285 },
286 .zlx_conf = {
287 0x00010103,
288 0x00010103,
289 0x00010103,
290 0x00010103,
291 0x00010103,
292 0x00010103,
293 0x00010103,
294 0x00010103,
295 0x00010103,
296 0x00010103,
297 0x00010103,
298 0x00010103,
299 0x00010103,
300 0x00010103,
301 0x00010103,
302 0x00010103,
303 },
304 .uao_p_num = IPU7P5_IS_UAO_M1_WR_PLANENUM,
305 .uao_p2tlb = {
306 0x00000045,
307 0x00000046,
308 0x00000047,
309 0x00000048,
310 0x00000045,
311 0x00000046,
312 0x00000047,
313 0x00000048,
314 0x00000045,
315 0x00000046,
316 0x00000047,
317 0x00000048,
318 0x00000045,
319 0x00000046,
320 0x00000047,
321 0x00000048,
322 },
323 },
324 },
325 .cdc_fifos = 3,
326 .cdc_fifo_threshold = {6, 8, 2},
327 .dmem_offset = IPU_ISYS_DMEM_OFFSET,
328 .spc_offset = IPU_ISYS_SPC_OFFSET,
329 },
330 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN,
331 };
332
333 static struct ipu_psys_internal_pdata ipu7p5_psys_ipdata = {
334 .hw_variant = {
335 .offset = IPU_UNIFIED_OFFSET,
336 .nr_mmus = IPU7P5_PS_MMU_NUM,
337 .mmu_hw = {
338 {
339 .name = "PS_FW_RD",
340 .offset = IPU7P5_PS_MMU_FW_RD_OFFSET,
341 .zlx_offset = IPU7P5_PS_ZLX_FW_RD_OFFSET,
342 .uao_offset = IPU7P5_PS_UAO_FW_RD_OFFSET,
343 .info_bits = 0x20004001,
344 .refill = 0x00002726,
345 .collapse_en_bitmap = 0x1,
346 .at_sp_arb_cfg = 0x1,
347 .l1_block = IPU7P5_PS_MMU_FW_RD_L1_BLOCKNR_REG,
348 .l2_block = IPU7P5_PS_MMU_FW_RD_L2_BLOCKNR_REG,
349 .nr_l1streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM,
350 .nr_l2streams = IPU7P5_PS_MMU_FW_RD_STREAM_NUM,
351 .l1_block_sz = {
352 0x00000000,
353 0x00000008,
354 0x0000000a,
355 0x0000000c,
356 0x0000000d,
357 0x0000000f,
358 0x00000011,
359 0x00000012,
360 0x00000013,
361 0x00000014,
362 0x00000016,
363 0x00000018,
364 0x00000019,
365 0x0000001a,
366 0x0000001a,
367 0x0000001a,
368 },
369 .l2_block_sz = {
370 0x00000000,
371 0x00000002,
372 0x00000004,
373 0x00000006,
374 0x00000008,
375 0x0000000a,
376 0x0000000c,
377 0x0000000e,
378 0x00000010,
379 0x00000012,
380 0x00000014,
381 0x00000016,
382 0x00000018,
383 0x0000001a,
384 0x0000001c,
385 0x0000001e,
386 },
387 .zlx_nr = IPU7P5_PS_ZLX_FW_RD_NUM,
388 .zlx_axi_pool = {
389 0x00000f30,
390 },
391 .zlx_en = {
392 0, 1, 0, 0, 1, 1, 0, 0,
393 0, 1, 1, 0, 0, 0, 0, 0,
394 },
395 .zlx_conf = {
396 0x00000000,
397 0x00010101,
398 0x00000000,
399 0x00000000,
400 0x00010101,
401 0x00010101,
402 0x00000000,
403 0x00000000,
404 0x00000000,
405 0x00010101,
406 0x00010101,
407 0x00000000,
408 0x00000000,
409 0x00000000,
410 0x00000000,
411 0x00000000,
412 },
413 .uao_p_num = IPU7P5_PS_UAO_FW_RD_PLANENUM,
414 .uao_p2tlb = {
415 0x0000002e,
416 0x00000035,
417 0x00000036,
418 0x00000031,
419 0x00000037,
420 0x00000038,
421 0x00000039,
422 0x00000032,
423 0x00000033,
424 0x0000003a,
425 0x0000003b,
426 0x0000003c,
427 0x00000034,
428 0x0,
429 0x0,
430 0x0,
431 },
432 },
433 {
434 .name = "PS_FW_WR",
435 .offset = IPU7P5_PS_MMU_FW_WR_OFFSET,
436 .zlx_offset = IPU7P5_PS_ZLX_FW_WR_OFFSET,
437 .uao_offset = IPU7P5_PS_UAO_FW_WR_OFFSET,
438 .info_bits = 0x20003e01,
439 .refill = 0x00002322,
440 .collapse_en_bitmap = 0x1,
441 .at_sp_arb_cfg = 0x1,
442 .l1_block = IPU7P5_PS_MMU_FW_WR_L1_BLOCKNR_REG,
443 .l2_block = IPU7P5_PS_MMU_FW_WR_L2_BLOCKNR_REG,
444 .nr_l1streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM,
445 .nr_l2streams = IPU7P5_PS_MMU_FW_WR_STREAM_NUM,
446 .l1_block_sz = {
447 0x00000000,
448 0x00000008,
449 0x0000000a,
450 0x0000000c,
451 0x0000000d,
452 0x0000000e,
453 0x0000000f,
454 0x00000010,
455 0x00000010,
456 0x00000010,
457 },
458 .l2_block_sz = {
459 0x00000000,
460 0x00000002,
461 0x00000004,
462 0x00000006,
463 0x00000008,
464 0x0000000a,
465 0x0000000c,
466 0x0000000e,
467 0x00000010,
468 0x00000012,
469 },
470 .zlx_nr = IPU7P5_PS_ZLX_FW_WR_NUM,
471 .zlx_axi_pool = {
472 0x00000f20,
473 },
474 .zlx_en = {
475 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
476 },
477 .zlx_conf = {
478 0x00000000,
479 0x00010101,
480 0x00010101,
481 0x00000000,
482 0x00000000,
483 0x00000000,
484 0x00000000,
485 0x00000000,
486 0x00000000,
487 0x00000000,
488 },
489 .uao_p_num = IPU7P5_PS_UAO_FW_WR_PLANENUM,
490 .uao_p2tlb = {
491 0x0000002e,
492 0x0000002f,
493 0x00000030,
494 0x00000031,
495 0x00000032,
496 0x00000033,
497 0x00000034,
498 0x0,
499 0x0,
500 0x0,
501 },
502 },
503 {
504 .name = "PS_DATA_RD",
505 .offset = IPU7P5_PS_MMU_SRT_RD_OFFSET,
506 .zlx_offset = IPU7P5_PS_ZLX_DATA_RD_OFFSET,
507 .uao_offset = IPU7P5_PS_UAO_SRT_RD_OFFSET,
508 .info_bits = 0x20003f01,
509 .refill = 0x00002524,
510 .collapse_en_bitmap = 0x1,
511 .at_sp_arb_cfg = 0x1,
512 .l1_block = IPU7P5_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
513 .l2_block = IPU7P5_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
514 .nr_l1streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM,
515 .nr_l2streams = IPU7P5_PS_MMU_SRT_RD_STREAM_NUM,
516 .l1_block_sz = {
517 0x00000000,
518 0x00000004,
519 0x00000006,
520 0x00000008,
521 0x0000000b,
522 0x0000000d,
523 0x0000000f,
524 0x00000013,
525 0x00000017,
526 0x00000019,
527 0x0000001b,
528 0x0000001d,
529 0x0000001f,
530 0x0000002b,
531 0x00000033,
532 0x0000003f,
533 0x00000047,
534 0x00000049,
535 0x0000004b,
536 0x0000004c,
537 0x0000004d,
538 0x0000004e,
539 },
540 .l2_block_sz = {
541 0x00000000,
542 0x00000002,
543 0x00000004,
544 0x00000006,
545 0x00000008,
546 0x0000000a,
547 0x0000000c,
548 0x0000000e,
549 0x00000010,
550 0x00000012,
551 0x00000014,
552 0x00000016,
553 0x00000018,
554 0x0000001a,
555 0x0000001c,
556 0x0000001e,
557 0x00000020,
558 0x00000022,
559 0x00000024,
560 0x00000026,
561 0x00000028,
562 0x0000002a,
563 },
564 .zlx_nr = IPU7P5_PS_ZLX_DATA_RD_NUM,
565 .zlx_axi_pool = {
566 0x00000f30,
567 },
568 .zlx_en = {
569 1, 1, 1, 1, 1, 1, 1, 1,
570 1, 1, 1, 1, 1, 1, 1, 1,
571 1, 1, 0, 0, 0, 0,
572 },
573 .zlx_conf = {
574 0x00030303,
575 0x00010101,
576 0x00010101,
577 0x00030202,
578 0x00010101,
579 0x00010101,
580 0x00030303,
581 0x00030303,
582 0x00010101,
583 0x00030800,
584 0x00030500,
585 0x00020101,
586 0x00042000,
587 0x00031000,
588 0x00042000,
589 0x00031000,
590 0x00020400,
591 0x00010101,
592 0x00000000,
593 0x00000000,
594 0x00000000,
595 0x00000000,
596 },
597 .uao_p_num = IPU7P5_PS_UAO_SRT_RD_PLANENUM,
598 .uao_p2tlb = {
599 0x0000001c,
600 0x0000001d,
601 0x0000001e,
602 0x0000001f,
603 0x00000020,
604 0x00000021,
605 0x00000022,
606 0x00000023,
607 0x00000024,
608 0x00000025,
609 0x00000026,
610 0x00000027,
611 0x00000028,
612 0x00000029,
613 0x0000002a,
614 0x0000002b,
615 0x0000002c,
616 0x0000002d,
617 0x00000000,
618 0x00000000,
619 0x00000000,
620 0x00000000,
621 },
622 },
623 {
624 .name = "PS_DATA_WR",
625 .offset = IPU7P5_PS_MMU_SRT_WR_OFFSET,
626 .zlx_offset = IPU7P5_PS_ZLX_DATA_WR_OFFSET,
627 .uao_offset = IPU7P5_PS_UAO_SRT_WR_OFFSET,
628 .info_bits = 0x20003d01,
629 .refill = 0x00002120,
630 .collapse_en_bitmap = 0x1,
631 .at_sp_arb_cfg = 0x1,
632 .l1_block = IPU7P5_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
633 .l2_block = IPU7P5_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
634 .nr_l1streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM,
635 .nr_l2streams = IPU7P5_PS_MMU_SRT_WR_STREAM_NUM,
636 .l1_block_sz = {
637 0x00000000,
638 0x00000002,
639 0x00000006,
640 0x0000000a,
641 0x0000000c,
642 0x0000000e,
643 0x00000010,
644 0x00000012,
645 0x00000014,
646 0x00000016,
647 0x00000018,
648 0x0000001a,
649 0x0000001c,
650 0x0000001e,
651 0x00000020,
652 0x00000022,
653 0x00000024,
654 0x00000028,
655 0x0000002a,
656 0x00000036,
657 0x0000003e,
658 0x00000040,
659 0x00000042,
660 0x0000004e,
661 0x00000056,
662 0x0000005c,
663 0x00000068,
664 0x00000070,
665 0x00000076,
666 0x00000077,
667 0x00000078,
668 0x00000079,
669 },
670 .l2_block_sz = {
671 0x00000000,
672 0x00000002,
673 0x00000006,
674 0x0000000a,
675 0x0000000c,
676 0x0000000e,
677 0x00000010,
678 0x00000012,
679 0x00000014,
680 0x00000016,
681 0x00000018,
682 0x0000001a,
683 0x0000001c,
684 0x0000001e,
685 0x00000020,
686 0x00000022,
687 0x00000024,
688 0x00000028,
689 0x0000002a,
690 0x00000036,
691 0x0000003e,
692 0x00000040,
693 0x00000042,
694 0x0000004e,
695 0x00000056,
696 0x0000005c,
697 0x00000068,
698 0x00000070,
699 0x00000076,
700 0x00000077,
701 0x00000078,
702 0x00000079,
703 },
704 .zlx_nr = IPU7P5_PS_ZLX_DATA_WR_NUM,
705 .zlx_axi_pool = {
706 0x00000f50,
707 },
708 .zlx_en = {
709 1, 1, 1, 1, 1, 1, 1, 1,
710 0, 0, 1, 1, 1, 1, 1, 1,
711 1, 1, 1, 1, 1, 1, 1, 1,
712 1, 1, 1, 1, 0, 0, 0, 0,
713 },
714 .zlx_conf = {
715 0x00010102,
716 0x00030103,
717 0x00030103,
718 0x00010101,
719 0x00010101,
720 0x00030101,
721 0x00010101,
722 0x38010101,
723 0x00000000,
724 0x00000000,
725 0x38010101,
726 0x38010101,
727 0x38010101,
728 0x38010101,
729 0x38010101,
730 0x38010101,
731 0x00030303,
732 0x00010101,
733 0x00042000,
734 0x00031000,
735 0x00010101,
736 0x00010101,
737 0x00042000,
738 0x00031000,
739 0x00031000,
740 0x00042000,
741 0x00031000,
742 0x00031000,
743 0x00000000,
744 0x00000000,
745 0x00000000,
746 0x00000000,
747 },
748 .uao_p_num = IPU7P5_PS_UAO_SRT_WR_PLANENUM,
749 .uao_p2tlb = {
750 0x00000000,
751 0x00000001,
752 0x00000002,
753 0x00000003,
754 0x00000004,
755 0x00000005,
756 0x00000006,
757 0x00000007,
758 0x00000008,
759 0x00000009,
760 0x0000000a,
761 0x0000000b,
762 0x0000000c,
763 0x0000000d,
764 0x0000000e,
765 0x0000000f,
766 0x00000010,
767 0x00000011,
768 0x00000012,
769 0x00000013,
770 0x00000014,
771 0x00000015,
772 0x00000016,
773 0x00000017,
774 0x00000018,
775 0x00000019,
776 0x0000001a,
777 0x0000001b,
778 0x00000000,
779 0x00000000,
780 0x00000000,
781 0x00000000,
782 },
783 },
784 },
785 .dmem_offset = IPU_PSYS_DMEM_OFFSET,
786 },
787 };
788
789 static struct ipu_isys_internal_pdata ipu7_isys_ipdata = {
790 .csi2 = {
791 .gpreg = IS_IO_CSI2_GPREGS_BASE,
792 },
793 .hw_variant = {
794 .offset = IPU_UNIFIED_OFFSET,
795 .nr_mmus = IPU7_IS_MMU_NUM,
796 .mmu_hw = {
797 {
798 .name = "IS_FW_RD",
799 .offset = IPU7_IS_MMU_FW_RD_OFFSET,
800 .zlx_offset = IPU7_IS_ZLX_UC_RD_OFFSET,
801 .uao_offset = IPU7_IS_UAO_UC_RD_OFFSET,
802 .info_bits = 0x20006701,
803 .refill = 0x00002726,
804 .collapse_en_bitmap = 0x0,
805 .l1_block = IPU7_IS_MMU_FW_RD_L1_BLOCKNR_REG,
806 .l2_block = IPU7_IS_MMU_FW_RD_L2_BLOCKNR_REG,
807 .nr_l1streams = IPU7_IS_MMU_FW_RD_STREAM_NUM,
808 .nr_l2streams = IPU7_IS_MMU_FW_RD_STREAM_NUM,
809 .l1_block_sz = {
810 0x0, 0x8, 0xa,
811 },
812 .l2_block_sz = {
813 0x0, 0x2, 0x4,
814 },
815 .zlx_nr = IPU7_IS_ZLX_UC_RD_NUM,
816 .zlx_axi_pool = {
817 0x00000f30,
818 },
819 .zlx_en = {
820 0, 0, 0, 0
821 },
822 .zlx_conf = {
823 0x0, 0x0, 0x0, 0x0,
824 },
825 .uao_p_num = IPU7_IS_UAO_UC_RD_PLANENUM,
826 .uao_p2tlb = {
827 0x00000061,
828 0x00000064,
829 0x00000065,
830 },
831 },
832 {
833 .name = "IS_FW_WR",
834 .offset = IPU7_IS_MMU_FW_WR_OFFSET,
835 .zlx_offset = IPU7_IS_ZLX_UC_WR_OFFSET,
836 .uao_offset = IPU7_IS_UAO_UC_WR_OFFSET,
837 .info_bits = 0x20006801,
838 .refill = 0x00002524,
839 .collapse_en_bitmap = 0x0,
840 .l1_block = IPU7_IS_MMU_FW_WR_L1_BLOCKNR_REG,
841 .l2_block = IPU7_IS_MMU_FW_WR_L2_BLOCKNR_REG,
842 .nr_l1streams = IPU7_IS_MMU_FW_WR_STREAM_NUM,
843 .nr_l2streams = IPU7_IS_MMU_FW_WR_STREAM_NUM,
844 .l1_block_sz = {
845 0x0, 0x8, 0xa,
846 },
847 .l2_block_sz = {
848 0x0, 0x2, 0x4,
849 },
850 .zlx_nr = IPU7_IS_ZLX_UC_WR_NUM,
851 .zlx_axi_pool = {
852 0x00000f20,
853 },
854 .zlx_en = {
855 0, 1, 1, 0,
856 },
857 .zlx_conf = {
858 0x0,
859 0x00010101,
860 0x00010101,
861 },
862 .uao_p_num = IPU7_IS_UAO_UC_WR_PLANENUM,
863 .uao_p2tlb = {
864 0x00000061,
865 0x00000062,
866 0x00000063,
867 },
868 },
869 {
870 .name = "IS_DATA_WR_ISOC",
871 .offset = IPU7_IS_MMU_M0_OFFSET,
872 .zlx_offset = IPU7_IS_ZLX_M0_OFFSET,
873 .uao_offset = IPU7_IS_UAO_M0_WR_OFFSET,
874 .info_bits = 0x20006601,
875 .refill = 0x00002120,
876 .collapse_en_bitmap = 0x0,
877 .l1_block = IPU7_IS_MMU_M0_L1_BLOCKNR_REG,
878 .l2_block = IPU7_IS_MMU_M0_L2_BLOCKNR_REG,
879 .nr_l1streams = IPU7_IS_MMU_M0_STREAM_NUM,
880 .nr_l2streams = IPU7_IS_MMU_M0_STREAM_NUM,
881 .l1_block_sz = {
882 0x0, 0x3, 0x6, 0x8, 0xa, 0xc, 0xe, 0x10,
883 },
884 .l2_block_sz = {
885 0x0, 0x2, 0x4, 0x6, 0x8, 0xa, 0xc, 0xe,
886 },
887 .zlx_nr = IPU7_IS_ZLX_M0_NUM,
888 .zlx_axi_pool = {
889 0x00000f10,
890 },
891 .zlx_en = {
892 1, 1, 1, 1, 1, 1, 1, 1,
893 },
894 .zlx_conf = {
895 0x00010103,
896 0x00010103,
897 0x00010101,
898 0x00010101,
899 0x00010101,
900 0x00010101,
901 0x00010101,
902 0x00010101,
903 },
904 .uao_p_num = IPU7_IS_UAO_M0_WR_PLANENUM,
905 .uao_p2tlb = {
906 0x00000049,
907 0x0000004a,
908 0x0000004b,
909 0x0000004c,
910 0x0000004d,
911 0x0000004e,
912 0x0000004f,
913 0x00000050,
914 },
915 },
916 {
917 .name = "IS_DATA_WR_SNOOP",
918 .offset = IPU7_IS_MMU_M1_OFFSET,
919 .zlx_offset = IPU7_IS_ZLX_M1_OFFSET,
920 .uao_offset = IPU7_IS_UAO_M1_WR_OFFSET,
921 .info_bits = 0x20006901,
922 .refill = 0x00002322,
923 .collapse_en_bitmap = 0x0,
924 .l1_block = IPU7_IS_MMU_M1_L1_BLOCKNR_REG,
925 .l2_block = IPU7_IS_MMU_M1_L2_BLOCKNR_REG,
926 .nr_l1streams = IPU7_IS_MMU_M1_STREAM_NUM,
927 .nr_l2streams = IPU7_IS_MMU_M1_STREAM_NUM,
928 .l1_block_sz = {
929 0x0, 0x3, 0x6, 0x9, 0xc,
930 0xe, 0x10, 0x12, 0x14, 0x16,
931 0x18, 0x1a, 0x1c, 0x1e, 0x20,
932 0x22,
933 },
934 .l2_block_sz = {
935 0x0, 0x2, 0x4, 0x6, 0x8,
936 0xa, 0xc, 0xe, 0x10, 0x12,
937 0x14, 0x16, 0x18, 0x1a, 0x1c,
938 0x1e,
939 },
940 .zlx_nr = IPU7_IS_ZLX_M1_NUM,
941 .zlx_axi_pool = {
942 0x00000f20,
943 },
944 .zlx_en = {
945 1, 1, 1, 1, 1, 1, 1, 1,
946 1, 1, 1, 1, 1, 1, 1, 1,
947 },
948 .zlx_conf = {
949 0x00010103,
950 0x00010103,
951 0x00010103,
952 0x00010103,
953 0x00010103,
954 0x00010103,
955 0x00010103,
956 0x00010103,
957 0x00010101,
958 0x00010101,
959 0x00010101,
960 0x00010101,
961 0x00010101,
962 0x00010101,
963 0x00010101,
964 0x00010101,
965 },
966 .uao_p_num = IPU7_IS_UAO_M1_WR_PLANENUM,
967 .uao_p2tlb = {
968 0x00000051,
969 0x00000052,
970 0x00000053,
971 0x00000054,
972 0x00000055,
973 0x00000056,
974 0x00000057,
975 0x00000058,
976 0x00000059,
977 0x0000005a,
978 0x0000005b,
979 0x0000005c,
980 0x0000005d,
981 0x0000005e,
982 0x0000005f,
983 0x00000060,
984 },
985 },
986 },
987 .cdc_fifos = 3,
988 .cdc_fifo_threshold = {6, 8, 2},
989 .dmem_offset = IPU_ISYS_DMEM_OFFSET,
990 .spc_offset = IPU_ISYS_SPC_OFFSET,
991 },
992 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN,
993 };
994
995 static struct ipu_psys_internal_pdata ipu7_psys_ipdata = {
996 .hw_variant = {
997 .offset = IPU_UNIFIED_OFFSET,
998 .nr_mmus = IPU7_PS_MMU_NUM,
999 .mmu_hw = {
1000 {
1001 .name = "PS_FW_RD",
1002 .offset = IPU7_PS_MMU_FW_RD_OFFSET,
1003 .zlx_offset = IPU7_PS_ZLX_FW_RD_OFFSET,
1004 .uao_offset = IPU7_PS_UAO_FW_RD_OFFSET,
1005 .info_bits = 0x20004801,
1006 .refill = 0x00002726,
1007 .collapse_en_bitmap = 0x0,
1008 .l1_block = IPU7_PS_MMU_FW_RD_L1_BLOCKNR_REG,
1009 .l2_block = IPU7_PS_MMU_FW_RD_L2_BLOCKNR_REG,
1010 .nr_l1streams = IPU7_PS_MMU_FW_RD_STREAM_NUM,
1011 .nr_l2streams = IPU7_PS_MMU_FW_RD_STREAM_NUM,
1012 .l1_block_sz = {
1013 0, 0x8, 0xa, 0xc, 0xd,
1014 0xf, 0x11, 0x12, 0x13, 0x14,
1015 0x16, 0x18, 0x19, 0x1a, 0x1a,
1016 0x1a, 0x1a, 0x1a, 0x1a, 0x1a,
1017 },
1018 .l2_block_sz = {
1019 0x0, 0x2, 0x4, 0x6, 0x8,
1020 0xa, 0xc, 0xe, 0x10, 0x12,
1021 0x14, 0x16, 0x18, 0x1a, 0x1c,
1022 0x1e, 0x20, 0x22, 0x24, 0x26,
1023 },
1024 .zlx_nr = IPU7_PS_ZLX_FW_RD_NUM,
1025 .zlx_axi_pool = {
1026 0x00000f30,
1027 },
1028 .zlx_en = {
1029 0, 0, 0, 0, 0, 0, 0, 0,
1030 0, 0, 0, 0, 0, 0, 0, 0,
1031 },
1032 .zlx_conf = {
1033 0x0,
1034 },
1035 .uao_p_num = IPU7_PS_UAO_FW_RD_PLANENUM,
1036 .uao_p2tlb = {
1037 0x00000036,
1038 0x0000003d,
1039 0x0000003e,
1040 0x00000039,
1041 0x0000003f,
1042 0x00000040,
1043 0x00000041,
1044 0x0000003a,
1045 0x0000003b,
1046 0x00000042,
1047 0x00000043,
1048 0x00000044,
1049 0x0000003c,
1050 },
1051 },
1052 {
1053 .name = "PS_FW_WR",
1054 .offset = IPU7_PS_MMU_FW_WR_OFFSET,
1055 .zlx_offset = IPU7_PS_ZLX_FW_WR_OFFSET,
1056 .uao_offset = IPU7_PS_UAO_FW_WR_OFFSET,
1057 .info_bits = 0x20004601,
1058 .refill = 0x00002322,
1059 .collapse_en_bitmap = 0x0,
1060 .l1_block = IPU7_PS_MMU_FW_WR_L1_BLOCKNR_REG,
1061 .l2_block = IPU7_PS_MMU_FW_WR_L2_BLOCKNR_REG,
1062 .nr_l1streams = IPU7_PS_MMU_FW_WR_STREAM_NUM,
1063 .nr_l2streams = IPU7_PS_MMU_FW_WR_STREAM_NUM,
1064 .l1_block_sz = {
1065 0, 0x8, 0xa, 0xc, 0xd,
1066 0xe, 0xf, 0x10, 0x10, 0x10,
1067 },
1068 .l2_block_sz = {
1069 0x0, 0x2, 0x4, 0x6, 0x8,
1070 0xa, 0xc, 0xe, 0x10, 0x12,
1071 },
1072 .zlx_nr = IPU7_PS_ZLX_FW_WR_NUM,
1073 .zlx_axi_pool = {
1074 0x00000f20,
1075 },
1076 .zlx_en = {
1077 0, 1, 1, 0, 0, 0, 0, 0,
1078 0, 0,
1079 },
1080 .zlx_conf = {
1081 0x0,
1082 0x00010101,
1083 0x00010101,
1084 },
1085 .uao_p_num = IPU7_PS_UAO_FW_WR_PLANENUM,
1086 .uao_p2tlb = {
1087 0x00000036,
1088 0x00000037,
1089 0x00000038,
1090 0x00000039,
1091 0x0000003a,
1092 0x0000003b,
1093 0x0000003c,
1094 },
1095 },
1096 {
1097 .name = "PS_DATA_RD",
1098 .offset = IPU7_PS_MMU_SRT_RD_OFFSET,
1099 .zlx_offset = IPU7_PS_ZLX_DATA_RD_OFFSET,
1100 .uao_offset = IPU7_PS_UAO_SRT_RD_OFFSET,
1101 .info_bits = 0x20004701,
1102 .refill = 0x00002120,
1103 .collapse_en_bitmap = 0x0,
1104 .l1_block = IPU7_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
1105 .l2_block = IPU7_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
1106 .nr_l1streams = IPU7_PS_MMU_SRT_RD_STREAM_NUM,
1107 .nr_l2streams = IPU7_PS_MMU_SRT_RD_STREAM_NUM,
1108 .l1_block_sz = {
1109 0x0, 0x4, 0x6, 0x8, 0xb,
1110 0xd, 0xf, 0x11, 0x13, 0x15,
1111 0x17, 0x23, 0x2b, 0x37, 0x3f,
1112 0x41, 0x43, 0x44, 0x45, 0x46,
1113 0x47, 0x48, 0x49, 0x4a, 0x4b,
1114 0x4c, 0x4d, 0x4e, 0x4f, 0x50,
1115 0x51, 0x52, 0x53, 0x55, 0x57,
1116 0x59, 0x5b, 0x5d, 0x5f, 0x61,
1117 },
1118 .l2_block_sz = {
1119 0x0, 0x2, 0x4, 0x6, 0x8,
1120 0xa, 0xc, 0xe, 0x10, 0x12,
1121 0x14, 0x16, 0x18, 0x1a, 0x1c,
1122 0x1e, 0x20, 0x22, 0x24, 0x26,
1123 0x28, 0x2a, 0x2c, 0x2e, 0x30,
1124 0x32, 0x34, 0x36, 0x38, 0x3a,
1125 0x3c, 0x3e, 0x40, 0x42, 0x44,
1126 0x46, 0x48, 0x4a, 0x4c, 0x4e,
1127 },
1128 .zlx_nr = IPU7_PS_ZLX_DATA_RD_NUM,
1129 .zlx_axi_pool = {
1130 0x00000f30,
1131 },
1132 .zlx_en = {
1133 1, 1, 1, 1, 1, 1, 1, 1,
1134 1, 1, 1, 1, 1, 1, 1, 1,
1135 0, 0, 0, 0, 0, 0, 0, 0,
1136 0, 0, 0, 0, 0, 0, 0, 0,
1137 },
1138 .zlx_conf = {
1139 0x00030303,
1140 0x00010101,
1141 0x00010101,
1142 0x00030202,
1143 0x00010101,
1144 0x00010101,
1145 0x00010101,
1146 0x00030800,
1147 0x00030500,
1148 0x00020101,
1149 0x00042000,
1150 0x00031000,
1151 0x00042000,
1152 0x00031000,
1153 0x00020400,
1154 0x00010101,
1155 },
1156 .uao_p_num = IPU7_PS_UAO_SRT_RD_PLANENUM,
1157 .uao_p2tlb = {
1158 0x00000022,
1159 0x00000023,
1160 0x00000024,
1161 0x00000025,
1162 0x00000026,
1163 0x00000027,
1164 0x00000028,
1165 0x00000029,
1166 0x0000002a,
1167 0x0000002b,
1168 0x0000002c,
1169 0x0000002d,
1170 0x0000002e,
1171 0x0000002f,
1172 0x00000030,
1173 0x00000031,
1174 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1175 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1176 0x0000001e,
1177 0x0000001f,
1178 0x00000020,
1179 0x00000021,
1180 0x00000032,
1181 0x00000033,
1182 0x00000034,
1183 0x00000035,
1184 },
1185 },
1186 {
1187 .name = "PS_DATA_WR",
1188 .offset = IPU7_PS_MMU_SRT_WR_OFFSET,
1189 .zlx_offset = IPU7_PS_ZLX_DATA_WR_OFFSET,
1190 .uao_offset = IPU7_PS_UAO_SRT_WR_OFFSET,
1191 .info_bits = 0x20004501,
1192 .refill = 0x00002120,
1193 .collapse_en_bitmap = 0x0,
1194 .l1_block = IPU7_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
1195 .l2_block = IPU7_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
1196 .nr_l1streams = IPU7_PS_MMU_SRT_WR_STREAM_NUM,
1197 .nr_l2streams = IPU7_PS_MMU_SRT_WR_STREAM_NUM,
1198 .l1_block_sz = {
1199 0x0, 0x2, 0x6, 0xa, 0xc,
1200 0xe, 0x10, 0x12, 0x14, 0x16,
1201 0x18, 0x1a, 0x1c, 0x1e, 0x20,
1202 0x22, 0x24, 0x26, 0x32, 0x3a,
1203 0x3c, 0x3e, 0x4a, 0x52, 0x58,
1204 0x64, 0x6c, 0x72, 0x7e, 0x86,
1205 0x8c, 0x8d, 0x8e, 0x8f, 0x90,
1206 0x91, 0x92, 0x94, 0x96, 0x98,
1207 },
1208 .l2_block_sz = {
1209 0x0, 0x2, 0x4, 0x6, 0x8,
1210 0xa, 0xc, 0xe, 0x10, 0x12,
1211 0x14, 0x16, 0x18, 0x1a, 0x1c,
1212 0x1e, 0x20, 0x22, 0x24, 0x26,
1213 0x28, 0x2a, 0x2c, 0x2e, 0x30,
1214 0x32, 0x34, 0x36, 0x38, 0x3a,
1215 0x3c, 0x3e, 0x40, 0x42, 0x44,
1216 0x46, 0x48, 0x4a, 0x4c, 0x4e,
1217 },
1218 .zlx_nr = IPU7_PS_ZLX_DATA_WR_NUM,
1219 .zlx_axi_pool = {
1220 0x00000f50,
1221 },
1222 .zlx_en = {
1223 1, 1, 1, 1, 1, 1, 1, 1,
1224 0, 0, 1, 1, 1, 1, 1, 1,
1225 1, 1, 1, 1, 1, 1, 1, 1,
1226 1, 1, 1, 1, 1, 1, 0, 0,
1227 },
1228 .zlx_conf = {
1229 0x00010102,
1230 0x00030103,
1231 0x00030103,
1232 0x00010101,
1233 0x00010101,
1234 0x00030101,
1235 0x00010101,
1236 0x38010101,
1237 0x0,
1238 0x0,
1239 0x38010101,
1240 0x38010101,
1241 0x38010101,
1242 0x38010101,
1243 0x38010101,
1244 0x38010101,
1245 0x00010101,
1246 0x00042000,
1247 0x00031000,
1248 0x00010101,
1249 0x00010101,
1250 0x00042000,
1251 0x00031000,
1252 0x00031000,
1253 0x00042000,
1254 0x00031000,
1255 0x00031000,
1256 0x00042000,
1257 0x00031000,
1258 0x00031000,
1259 0x0,
1260 0x0,
1261 },
1262 .uao_p_num = IPU7_PS_UAO_SRT_WR_PLANENUM,
1263 .uao_p2tlb = {
1264 0x00000000,
1265 0x00000001,
1266 0x00000002,
1267 0x00000003,
1268 0x00000004,
1269 0x00000005,
1270 0x00000006,
1271 0x00000007,
1272 0x00000008,
1273 0x00000009,
1274 0x0000000a,
1275 0x0000000b,
1276 0x0000000c,
1277 0x0000000d,
1278 0x0000000e,
1279 0x0000000f,
1280 0x00000010,
1281 0x00000011,
1282 0x00000012,
1283 0x00000013,
1284 0x00000014,
1285 0x00000015,
1286 0x00000016,
1287 0x00000017,
1288 0x00000018,
1289 0x00000019,
1290 0x0000001a,
1291 0x0000001b,
1292 0x0000001c,
1293 0x0000001d,
1294 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
1295 0x0000001e,
1296 0x0000001f,
1297 0x00000020,
1298 0x00000021,
1299 },
1300 },
1301 },
1302 .dmem_offset = IPU_PSYS_DMEM_OFFSET,
1303 },
1304 };
1305
1306 static struct ipu_isys_internal_pdata ipu8_isys_ipdata = {
1307 .csi2 = {
1308 .gpreg = IPU8_IS_IO_CSI2_GPREGS_BASE,
1309 },
1310 .hw_variant = {
1311 .offset = IPU_UNIFIED_OFFSET,
1312 .nr_mmus = IPU8_IS_MMU_NUM,
1313 .mmu_hw = {
1314 {
1315 .name = "IS_FW_RD",
1316 .offset = IPU8_IS_MMU_FW_RD_OFFSET,
1317 .zlx_offset = IPU8_IS_ZLX_UC_RD_OFFSET,
1318 .uao_offset = IPU8_IS_UAO_UC_RD_OFFSET,
1319 .info_bits = 0x20005101,
1320 .refill = 0x00002726,
1321 .collapse_en_bitmap = 0x1,
1322 .at_sp_arb_cfg = 0x1,
1323 .l1_block = IPU8_IS_MMU_FW_RD_L1_BLOCKNR_REG,
1324 .l2_block = IPU8_IS_MMU_FW_RD_L2_BLOCKNR_REG,
1325 .nr_l1streams = IPU8_IS_MMU_FW_RD_STREAM_NUM,
1326 .nr_l2streams = IPU8_IS_MMU_FW_RD_STREAM_NUM,
1327 .l1_block_sz = {
1328 0x0, 0x8, 0xa,
1329 },
1330 .l2_block_sz = {
1331 0x0, 0x2, 0x4,
1332 },
1333 .zlx_nr = IPU8_IS_ZLX_UC_RD_NUM,
1334 .zlx_axi_pool = {
1335 0x00000f30,
1336 },
1337 .zlx_en = {
1338 0, 1, 0, 0
1339 },
1340 .zlx_conf = {
1341 0, 2, 0, 0
1342 },
1343 .uao_p_num = IPU8_IS_UAO_UC_RD_PLANENUM,
1344 .uao_p2tlb = {
1345 0x00000049,
1346 0x0000004c,
1347 0x0000004d,
1348 0x00000000,
1349 },
1350 },
1351 {
1352 .name = "IS_FW_WR",
1353 .offset = IPU8_IS_MMU_FW_WR_OFFSET,
1354 .zlx_offset = IPU8_IS_ZLX_UC_WR_OFFSET,
1355 .uao_offset = IPU8_IS_UAO_UC_WR_OFFSET,
1356 .info_bits = 0x20005001,
1357 .refill = 0x00002524,
1358 .collapse_en_bitmap = 0x1,
1359 .at_sp_arb_cfg = 0x1,
1360 .l1_block = IPU8_IS_MMU_FW_WR_L1_BLOCKNR_REG,
1361 .l2_block = IPU8_IS_MMU_FW_WR_L2_BLOCKNR_REG,
1362 .nr_l1streams = IPU8_IS_MMU_FW_WR_STREAM_NUM,
1363 .nr_l2streams = IPU8_IS_MMU_FW_WR_STREAM_NUM,
1364 .l1_block_sz = {
1365 0x0, 0x8, 0xa,
1366 },
1367 .l2_block_sz = {
1368 0x0, 0x2, 0x4,
1369 },
1370 .zlx_nr = IPU8_IS_ZLX_UC_WR_NUM,
1371 .zlx_axi_pool = {
1372 0x00000f20,
1373 },
1374 .zlx_en = {
1375 0, 1, 1, 0,
1376 },
1377 .zlx_conf = {
1378 0x0,
1379 0x2,
1380 0x2,
1381 0x0,
1382 },
1383 .uao_p_num = IPU8_IS_UAO_UC_WR_PLANENUM,
1384 .uao_p2tlb = {
1385 0x00000049,
1386 0x0000004a,
1387 0x0000004b,
1388 0x00000000,
1389 },
1390 },
1391 {
1392 .name = "IS_DATA_WR_ISOC",
1393 .offset = IPU8_IS_MMU_M0_OFFSET,
1394 .zlx_offset = IPU8_IS_ZLX_M0_OFFSET,
1395 .uao_offset = IPU8_IS_UAO_M0_WR_OFFSET,
1396 .info_bits = 0x20004e01,
1397 .refill = 0x00002120,
1398 .collapse_en_bitmap = 0x1,
1399 .at_sp_arb_cfg = 0x1,
1400 .l1_block = IPU8_IS_MMU_M0_L1_BLOCKNR_REG,
1401 .l2_block = IPU8_IS_MMU_M0_L2_BLOCKNR_REG,
1402 .nr_l1streams = IPU8_IS_MMU_M0_STREAM_NUM,
1403 .nr_l2streams = IPU8_IS_MMU_M0_STREAM_NUM,
1404 .l1_block_sz = {
1405 0x00000000,
1406 0x00000002,
1407 0x00000004,
1408 0x00000006,
1409 0x00000008,
1410 0x0000000a,
1411 0x0000000c,
1412 0x0000000e,
1413 0x00000010,
1414 0x00000012,
1415 0x00000014,
1416 0x00000016,
1417 0x00000018,
1418 0x0000001a,
1419 0x0000001c,
1420 0x0000001e,
1421 },
1422 .l2_block_sz = {
1423 0x00000000,
1424 0x00000002,
1425 0x00000004,
1426 0x00000006,
1427 0x00000008,
1428 0x0000000a,
1429 0x0000000c,
1430 0x0000000e,
1431 0x00000010,
1432 0x00000012,
1433 0x00000014,
1434 0x00000016,
1435 0x00000018,
1436 0x0000001a,
1437 0x0000001c,
1438 0x0000001e,
1439 },
1440 .zlx_nr = IPU8_IS_ZLX_M0_NUM,
1441 .zlx_axi_pool = {
1442 0x00000f10,
1443 },
1444 .zlx_en = {
1445 1, 1, 1, 1, 1, 1, 1, 1,
1446 1, 1, 1, 1, 1, 1, 1, 1,
1447 },
1448 .zlx_conf = {
1449 0x3,
1450 0x3,
1451 0x3,
1452 0x3,
1453 0x3,
1454 0x3,
1455 0x3,
1456 0x3,
1457 0x3,
1458 0x3,
1459 0x3,
1460 0x3,
1461 0x3,
1462 0x3,
1463 0x3,
1464 0x3,
1465 },
1466 .uao_p_num = IPU8_IS_UAO_M0_WR_PLANENUM,
1467 .uao_p2tlb = {
1468 0x0000003b,
1469 0x0000003c,
1470 0x0000003d,
1471 0x0000003e,
1472 0x0000003b,
1473 0x0000003c,
1474 0x0000003d,
1475 0x0000003e,
1476 0x0000003b,
1477 0x0000003c,
1478 0x0000003d,
1479 0x0000003e,
1480 0x0000003b,
1481 0x0000003c,
1482 0x0000003d,
1483 0x0000003e,
1484 },
1485 },
1486 {
1487 .name = "IS_DATA_WR_SNOOP",
1488 .offset = IPU8_IS_MMU_M1_OFFSET,
1489 .zlx_offset = IPU8_IS_ZLX_M1_OFFSET,
1490 .uao_offset = IPU8_IS_UAO_M1_WR_OFFSET,
1491 .info_bits = 0x20004f01,
1492 .refill = 0x00002322,
1493 .collapse_en_bitmap = 0x1,
1494 .at_sp_arb_cfg = 0x1,
1495 .l1_block = IPU8_IS_MMU_M1_L1_BLOCKNR_REG,
1496 .l2_block = IPU8_IS_MMU_M1_L2_BLOCKNR_REG,
1497 .nr_l1streams = IPU8_IS_MMU_M1_STREAM_NUM,
1498 .nr_l2streams = IPU8_IS_MMU_M1_STREAM_NUM,
1499 .l1_block_sz = {
1500 0x00000000,
1501 0x00000002,
1502 0x00000004,
1503 0x00000006,
1504 0x00000008,
1505 0x0000000a,
1506 0x0000000c,
1507 0x0000000e,
1508 0x00000010,
1509 0x00000012,
1510 0x00000014,
1511 0x00000016,
1512 0x00000018,
1513 0x0000001a,
1514 0x0000001c,
1515 0x0000001e,
1516 },
1517 .l2_block_sz = {
1518 0x00000000,
1519 0x00000002,
1520 0x00000004,
1521 0x00000006,
1522 0x00000008,
1523 0x0000000a,
1524 0x0000000c,
1525 0x0000000e,
1526 0x00000010,
1527 0x00000012,
1528 0x00000014,
1529 0x00000016,
1530 0x00000018,
1531 0x0000001a,
1532 0x0000001c,
1533 0x0000001e,
1534 },
1535 .zlx_nr = IPU8_IS_ZLX_M1_NUM,
1536 .zlx_axi_pool = {
1537 0x00000f20,
1538 },
1539 .zlx_en = {
1540 1, 1, 1, 1, 1, 1, 1, 1,
1541 1, 1, 1, 1, 1, 1, 1, 1,
1542 },
1543 .zlx_conf = {
1544 0x3,
1545 0x3,
1546 0x3,
1547 0x3,
1548 0x3,
1549 0x3,
1550 0x3,
1551 0x3,
1552 0x3,
1553 0x3,
1554 0x3,
1555 0x3,
1556 0x3,
1557 0x3,
1558 0x3,
1559 0x3,
1560 },
1561 .uao_p_num = IPU8_IS_UAO_M1_WR_PLANENUM,
1562 .uao_p2tlb = {
1563 0x0000003f,
1564 0x00000040,
1565 0x00000041,
1566 0x00000042,
1567 0x0000003f,
1568 0x00000040,
1569 0x00000041,
1570 0x00000042,
1571 0x0000003f,
1572 0x00000040,
1573 0x00000041,
1574 0x00000042,
1575 0x0000003f,
1576 0x00000040,
1577 0x00000041,
1578 0x00000042,
1579 },
1580 },
1581 {
1582 .name = "IS_UPIPE",
1583 .offset = IPU8_IS_MMU_UPIPE_OFFSET,
1584 .zlx_offset = IPU8_IS_ZLX_UPIPE_OFFSET,
1585 .uao_offset = IPU8_IS_UAO_UPIPE_OFFSET,
1586 .info_bits = 0x20005201,
1587 .refill = 0x00002928,
1588 .collapse_en_bitmap = 0x1,
1589 .at_sp_arb_cfg = 0x1,
1590 .l1_block = IPU8_IS_MMU_UPIPE_L1_BLOCKNR_REG,
1591 .l2_block = IPU8_IS_MMU_UPIPE_L2_BLOCKNR_REG,
1592 .nr_l1streams = IPU8_IS_MMU_UPIPE_STREAM_NUM,
1593 .nr_l2streams = IPU8_IS_MMU_UPIPE_STREAM_NUM,
1594 .l1_block_sz = {
1595 0x00000000,
1596 0x00000002,
1597 0x00000004,
1598 0x00000006,
1599 0x00000008,
1600 0x0000000a,
1601 },
1602 .l2_block_sz = {
1603 0x00000000,
1604 0x00000002,
1605 0x00000004,
1606 0x00000006,
1607 0x00000008,
1608 0x0000000a,
1609 },
1610 .zlx_nr = IPU8_IS_ZLX_UPIPE_NUM,
1611 .zlx_axi_pool = {
1612 0x00000f20,
1613 },
1614 .zlx_en = {
1615 1, 1, 1, 1, 1, 1,
1616 },
1617 .zlx_conf = {
1618 0x3,
1619 0x3,
1620 0x3,
1621 0x3,
1622 0x3,
1623 0x3,
1624 },
1625 .uao_p_num = IPU8_IS_UAO_UPIPE_PLANENUM,
1626 .uao_p2tlb = {
1627 0x00000043,
1628 0x00000044,
1629 0x00000045,
1630 0x00000046,
1631 0x00000047,
1632 0x00000048,
1633 },
1634 },
1635 },
1636 .cdc_fifos = 3,
1637 .cdc_fifo_threshold = {6, 8, 2},
1638 .dmem_offset = IPU_ISYS_DMEM_OFFSET,
1639 .spc_offset = IPU_ISYS_SPC_OFFSET,
1640 },
1641 .isys_dma_overshoot = IPU_ISYS_OVERALLOC_MIN,
1642 };
1643
1644 static struct ipu_psys_internal_pdata ipu8_psys_ipdata = {
1645 .hw_variant = {
1646 .offset = IPU_UNIFIED_OFFSET,
1647 .nr_mmus = IPU8_PS_MMU_NUM,
1648 .mmu_hw = {
1649 {
1650 .name = "PS_FW_RD",
1651 .offset = IPU8_PS_MMU_FW_RD_OFFSET,
1652 .zlx_offset = IPU8_PS_ZLX_FW_RD_OFFSET,
1653 .uao_offset = IPU8_PS_UAO_FW_RD_OFFSET,
1654 .info_bits = 0x20003a01,
1655 .refill = 0x00002726,
1656 .collapse_en_bitmap = 0x1,
1657 .at_sp_arb_cfg = 0x1,
1658 .l1_block = IPU8_PS_MMU_FW_RD_L1_BLOCKNR_REG,
1659 .l2_block = IPU8_PS_MMU_FW_RD_L2_BLOCKNR_REG,
1660 .nr_l1streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
1661 .nr_l2streams = IPU8_PS_MMU_FW_RD_STREAM_NUM,
1662 .l1_block_sz = {
1663 0x00000000,
1664 0x00000008,
1665 0x0000000a,
1666 0x0000000e,
1667 0x00000010,
1668 0x00000012,
1669 0x00000014,
1670 0x00000016,
1671 0x00000018,
1672 0x00000018,
1673 0x00000018,
1674 0x00000018,
1675 },
1676 .l2_block_sz = {
1677 0x00000000,
1678 0x00000002,
1679 0x00000004,
1680 0x00000006,
1681 0x00000008,
1682 0x0000000a,
1683 0x0000000c,
1684 0x0000000e,
1685 0x00000010,
1686 0x00000012,
1687 0x00000014,
1688 0x00000016,
1689 },
1690 .zlx_nr = IPU8_PS_ZLX_FW_RD_NUM,
1691 .zlx_axi_pool = {
1692 0x00000f30,
1693 },
1694 .zlx_en = {
1695 0, 1, 0, 0, 1, 1, 0, 0,
1696 0, 0, 0, 0,
1697 },
1698 .zlx_conf = {
1699 0x0,
1700 0x2,
1701 0x0,
1702 0x0,
1703 0x2,
1704 0x2,
1705 0x0,
1706 0x0,
1707 0x0,
1708 0x0,
1709 0x0,
1710 0x0,
1711 },
1712 .uao_p_num = IPU8_PS_UAO_FW_RD_PLANENUM,
1713 .uao_p2tlb = {
1714 0x0000002d,
1715 0x00000032,
1716 0x00000033,
1717 0x00000030,
1718 0x00000034,
1719 0x00000035,
1720 0x00000036,
1721 0x00000031,
1722 0x0,
1723 0x0,
1724 0x0,
1725 0x0,
1726 },
1727 },
1728 {
1729 .name = "PS_FW_WR",
1730 .offset = IPU8_PS_MMU_FW_WR_OFFSET,
1731 .zlx_offset = IPU8_PS_ZLX_FW_WR_OFFSET,
1732 .uao_offset = IPU8_PS_UAO_FW_WR_OFFSET,
1733 .info_bits = 0x20003901,
1734 .refill = 0x00002524,
1735 .collapse_en_bitmap = 0x1,
1736 .at_sp_arb_cfg = 0x1,
1737 .l1_block = IPU8_PS_MMU_FW_WR_L1_BLOCKNR_REG,
1738 .l2_block = IPU8_PS_MMU_FW_WR_L2_BLOCKNR_REG,
1739 .nr_l1streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
1740 .nr_l2streams = IPU8_PS_MMU_FW_WR_STREAM_NUM,
1741 .l1_block_sz = {
1742 0x00000000,
1743 0x00000008,
1744 0x0000000a,
1745 0x0000000c,
1746 0x0000000e,
1747 0x00000010,
1748 0x00000010,
1749 0x00000010,
1750 },
1751 .l2_block_sz = {
1752 0x00000000,
1753 0x00000002,
1754 0x00000004,
1755 0x00000006,
1756 0x00000008,
1757 0x0000000a,
1758 0x0000000c,
1759 0x0000000e,
1760 },
1761 .zlx_nr = IPU8_PS_ZLX_FW_WR_NUM,
1762 .zlx_axi_pool = {
1763 0x00000f20,
1764 },
1765 .zlx_en = {
1766 0, 1, 1, 0, 0, 0, 0, 0,
1767 },
1768 .zlx_conf = {
1769 0x0, 0x2, 0x2, 0x0,
1770 0x0, 0x0, 0x0, 0x0,
1771 },
1772 .uao_p_num = IPU8_PS_UAO_FW_WR_PLANENUM,
1773 .uao_p2tlb = {
1774 0x0000002d,
1775 0x0000002e,
1776 0x0000002f,
1777 0x00000030,
1778 0x00000031,
1779 0x0,
1780 0x0,
1781 0x0,
1782 },
1783 },
1784 {
1785 .name = "PS_DATA_RD",
1786 .offset = IPU8_PS_MMU_SRT_RD_OFFSET,
1787 .zlx_offset = IPU8_PS_ZLX_DATA_RD_OFFSET,
1788 .uao_offset = IPU8_PS_UAO_SRT_RD_OFFSET,
1789 .info_bits = 0x20003801,
1790 .refill = 0x00002322,
1791 .collapse_en_bitmap = 0x1,
1792 .at_sp_arb_cfg = 0x1,
1793 .l1_block = IPU8_PS_MMU_SRT_RD_L1_BLOCKNR_REG,
1794 .l2_block = IPU8_PS_MMU_SRT_RD_L2_BLOCKNR_REG,
1795 .nr_l1streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
1796 .nr_l2streams = IPU8_PS_MMU_SRT_RD_STREAM_NUM,
1797 .l1_block_sz = {
1798 0x00000000,
1799 0x00000004,
1800 0x00000006,
1801 0x00000008,
1802 0x0000000c,
1803 0x0000000e,
1804 0x00000010,
1805 0x00000014,
1806 0x00000018,
1807 0x0000001c,
1808 0x0000001e,
1809 0x00000022,
1810 0x00000024,
1811 0x00000026,
1812 0x00000028,
1813 0x0000002a,
1814 0x0000002c,
1815 0x0000002e,
1816 0x00000030,
1817 0x00000032,
1818 0x00000036,
1819 0x0000003a,
1820 0x0000003c,
1821 0x0000003c,
1822 0x0000003c,
1823 0x0000003c,
1824 },
1825 .l2_block_sz = {
1826 0x00000000,
1827 0x00000002,
1828 0x00000004,
1829 0x00000006,
1830 0x00000008,
1831 0x0000000a,
1832 0x0000000c,
1833 0x0000000e,
1834 0x00000010,
1835 0x00000012,
1836 0x00000014,
1837 0x00000016,
1838 0x00000018,
1839 0x0000001a,
1840 0x0000001c,
1841 0x0000001e,
1842 0x00000020,
1843 0x00000022,
1844 0x00000024,
1845 0x00000026,
1846 0x00000028,
1847 0x0000002a,
1848 0x0000002c,
1849 0x0000002e,
1850 0x00000030,
1851 0x00000032,
1852 },
1853 .zlx_nr = IPU8_PS_ZLX_DATA_RD_NUM,
1854 .zlx_axi_pool = {
1855 0x00000f30,
1856 },
1857 .zlx_en = {
1858 1, 1, 1, 1, 1, 1, 1, 1,
1859 1, 1, 1, 1, 1, 1, 1, 1,
1860 1, 1, 1, 1, 1, 1, 0, 0,
1861 0, 0,
1862 },
1863 .zlx_conf = {
1864 0x6, 0x3, 0x3, 0x6,
1865 0x2, 0x2, 0x6, 0x6,
1866 0x6, 0x3, 0x6, 0x3,
1867 0x3, 0x2, 0x2, 0x2,
1868 0x2, 0x2, 0x2, 0x6,
1869 0x6, 0x3, 0x0, 0x0,
1870 0x0, 0x0,
1871 },
1872 .uao_p_num = IPU8_PS_UAO_SRT_RD_PLANENUM,
1873 .uao_p2tlb = {
1874 0x00000017,
1875 0x00000018,
1876 0x00000019,
1877 0x0000001a,
1878 0x0000001b,
1879 0x0000001c,
1880 0x0000001d,
1881 0x0000001e,
1882 0x0000001f,
1883 0x00000020,
1884 0x00000021,
1885 0x00000022,
1886 0x00000023,
1887 0x00000024,
1888 0x00000025,
1889 0x00000026,
1890 0x00000027,
1891 0x00000028,
1892 0x00000029,
1893 0x0000002a,
1894 0x0000002b,
1895 0x0000002c,
1896 0x0,
1897 0x0,
1898 0x0,
1899 0x0,
1900 },
1901 },
1902 {
1903 .name = "PS_DATA_WR",
1904 .offset = IPU8_PS_MMU_SRT_WR_OFFSET,
1905 .zlx_offset = IPU8_PS_ZLX_DATA_WR_OFFSET,
1906 .uao_offset = IPU8_PS_UAO_SRT_WR_OFFSET,
1907 .info_bits = 0x20003701,
1908 .refill = 0x00002120,
1909 .collapse_en_bitmap = 0x1,
1910 .at_sp_arb_cfg = 0x1,
1911 .l1_block = IPU8_PS_MMU_SRT_WR_L1_BLOCKNR_REG,
1912 .l2_block = IPU8_PS_MMU_SRT_WR_L2_BLOCKNR_REG,
1913 .nr_l1streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
1914 .nr_l2streams = IPU8_PS_MMU_SRT_WR_STREAM_NUM,
1915 .l1_block_sz = {
1916 0x00000000,
1917 0x00000002,
1918 0x00000006,
1919 0x00000008,
1920 0x0000000a,
1921 0x0000000c,
1922 0x0000000e,
1923 0x00000010,
1924 0x00000012,
1925 0x00000014,
1926 0x00000016,
1927 0x00000018,
1928 0x0000001c,
1929 0x0000001e,
1930 0x00000022,
1931 0x00000024,
1932 0x00000028,
1933 0x0000002a,
1934 0x0000002e,
1935 0x00000030,
1936 0x00000032,
1937 0x00000036,
1938 0x00000038,
1939 0x0000003a,
1940 0x0000003a,
1941 0x0000003a,
1942 },
1943 .l2_block_sz = {
1944 0x00000000,
1945 0x00000002,
1946 0x00000004,
1947 0x00000006,
1948 0x00000008,
1949 0x0000000a,
1950 0x0000000c,
1951 0x0000000e,
1952 0x00000010,
1953 0x00000012,
1954 0x00000014,
1955 0x00000016,
1956 0x00000018,
1957 0x0000001a,
1958 0x0000001c,
1959 0x0000001e,
1960 0x00000020,
1961 0x00000022,
1962 0x00000024,
1963 0x00000026,
1964 0x00000028,
1965 0x0000002a,
1966 0x0000002c,
1967 0x0000002e,
1968 0x00000030,
1969 0x00000032,
1970 },
1971 .zlx_nr = IPU8_PS_ZLX_DATA_WR_NUM,
1972 .zlx_axi_pool = {
1973 0x00000f50,
1974 },
1975 .zlx_en = {
1976 1, 1, 1, 0, 1, 1, 1, 1,
1977 1, 1, 1, 1, 1, 1, 1, 1,
1978 1, 1, 1, 1, 1, 1, 1, 0,
1979 0, 0,
1980 },
1981 .zlx_conf = {
1982 0x3,
1983 0x6,
1984 0x38000002,
1985 0x38000000,
1986 0x3,
1987 0x38000002,
1988 0x38000002,
1989 0x38000002,
1990 0x38000002,
1991 0x38000002,
1992 0x38000002,
1993 0x6,
1994 0x3,
1995 0x6,
1996 0x3,
1997 0x6,
1998 0x3,
1999 0x6,
2000 0x3,
2001 0x3,
2002 0x6,
2003 0x3,
2004 0x3,
2005 0x0,
2006 0x0,
2007 0x0,
2008 },
2009 .uao_p_num = IPU8_PS_UAO_SRT_WR_PLANENUM,
2010 .uao_p2tlb = {
2011 0x00000000,
2012 0x00000001,
2013 0x00000002,
2014 0x00000003,
2015 0x00000004,
2016 0x00000005,
2017 0x00000006,
2018 0x00000007,
2019 0x00000008,
2020 0x00000009,
2021 0x0000000a,
2022 0x0000000b,
2023 0x0000000c,
2024 0x0000000d,
2025 0x0000000e,
2026 0x0000000f,
2027 0x00000010,
2028 0x00000011,
2029 0x00000012,
2030 0x00000013,
2031 0x00000014,
2032 0x00000015,
2033 0x00000016,
2034 0x00000000,
2035 0x00000000,
2036 0x00000000,
2037 },
2038 },
2039 },
2040 .dmem_offset = IPU_PSYS_DMEM_OFFSET,
2041 },
2042 };
2043
2044 static const struct ipu_buttress_ctrl ipu7_isys_buttress_ctrl = {
2045 .subsys_id = IPU_IS,
2046 .ratio = IPU7_IS_FREQ_CTL_DEFAULT_RATIO,
2047 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT,
2048 .cdyn = IPU_FREQ_CTL_CDYN,
2049 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT,
2050 .freq_ctl = BUTTRESS_REG_IS_WORKPOINT_REQ,
2051 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT,
2052 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK,
2053 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE,
2054 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE,
2055 .ovrd_clk = BUTTRESS_OVERRIDE_IS_CLK,
2056 .own_clk_ack = BUTTRESS_OWN_ACK_IS_CLK,
2057 };
2058
2059 static const struct ipu_buttress_ctrl ipu7_psys_buttress_ctrl = {
2060 .subsys_id = IPU_PS,
2061 .ratio = IPU7_PS_FREQ_CTL_DEFAULT_RATIO,
2062 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT,
2063 .cdyn = IPU_FREQ_CTL_CDYN,
2064 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT,
2065 .freq_ctl = BUTTRESS_REG_PS_WORKPOINT_REQ,
2066 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT,
2067 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK,
2068 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE,
2069 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE,
2070 .ovrd_clk = BUTTRESS_OVERRIDE_PS_CLK,
2071 .own_clk_ack = BUTTRESS_OWN_ACK_PS_CLK,
2072 };
2073
2074 static const struct ipu_buttress_ctrl ipu8_isys_buttress_ctrl = {
2075 .subsys_id = IPU_IS,
2076 .ratio = IPU8_IS_FREQ_CTL_DEFAULT_RATIO,
2077 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT,
2078 .cdyn = IPU_FREQ_CTL_CDYN,
2079 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT,
2080 .freq_ctl = BUTTRESS_REG_IS_WORKPOINT_REQ,
2081 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_IS_PWR_SHIFT,
2082 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_IS_PWR_MASK,
2083 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE,
2084 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE,
2085 };
2086
2087 static const struct ipu_buttress_ctrl ipu8_psys_buttress_ctrl = {
2088 .subsys_id = IPU_PS,
2089 .ratio = IPU8_PS_FREQ_CTL_DEFAULT_RATIO,
2090 .ratio_shift = IPU_FREQ_CTL_RATIO_SHIFT,
2091 .cdyn = IPU_FREQ_CTL_CDYN,
2092 .cdyn_shift = IPU_FREQ_CTL_CDYN_SHIFT,
2093 .freq_ctl = BUTTRESS_REG_PS_WORKPOINT_REQ,
2094 .pwr_sts_shift = IPU_BUTTRESS_PWR_STATE_PS_PWR_SHIFT,
2095 .pwr_sts_mask = IPU_BUTTRESS_PWR_STATE_PS_PWR_MASK,
2096 .pwr_sts_on = IPU_BUTTRESS_PWR_STATE_UP_DONE,
2097 .pwr_sts_off = IPU_BUTTRESS_PWR_STATE_DN_DONE,
2098 .own_clk_ack = BUTTRESS_OWN_ACK_PS_PLL,
2099 };
2100
ipu_internal_pdata_init(struct ipu_isys_internal_pdata * isys_ipdata,struct ipu_psys_internal_pdata * psys_ipdata)2101 void ipu_internal_pdata_init(struct ipu_isys_internal_pdata *isys_ipdata,
2102 struct ipu_psys_internal_pdata *psys_ipdata)
2103 {
2104 isys_ipdata->csi2.nports = ARRAY_SIZE(ipu7_csi_offsets);
2105 isys_ipdata->csi2.offsets = ipu7_csi_offsets;
2106 isys_ipdata->num_parallel_streams = IPU7_ISYS_NUM_STREAMS;
2107 psys_ipdata->hw_variant.spc_offset = IPU7_PSYS_SPC_OFFSET;
2108 }
2109
ipu7_isys_check_fwnode_graph(struct fwnode_handle * fwnode)2110 static int ipu7_isys_check_fwnode_graph(struct fwnode_handle *fwnode)
2111 {
2112 struct fwnode_handle *endpoint;
2113
2114 if (IS_ERR_OR_NULL(fwnode))
2115 return -EINVAL;
2116
2117 endpoint = fwnode_graph_get_next_endpoint(fwnode, NULL);
2118 if (endpoint) {
2119 fwnode_handle_put(endpoint);
2120 return 0;
2121 }
2122
2123 return ipu7_isys_check_fwnode_graph(fwnode->secondary);
2124 }
2125
2126 static struct ipu7_bus_device *
ipu7_isys_init(struct pci_dev * pdev,struct device * parent,const struct ipu_buttress_ctrl * ctrl,void __iomem * base,const struct ipu_isys_internal_pdata * ipdata,unsigned int nr)2127 ipu7_isys_init(struct pci_dev *pdev, struct device *parent,
2128 const struct ipu_buttress_ctrl *ctrl, void __iomem *base,
2129 const struct ipu_isys_internal_pdata *ipdata,
2130 unsigned int nr)
2131 {
2132 struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
2133 struct ipu7_bus_device *isys_adev;
2134 struct device *dev = &pdev->dev;
2135 struct ipu7_isys_pdata *pdata;
2136 int ret;
2137
2138 ret = ipu7_isys_check_fwnode_graph(fwnode);
2139 if (ret) {
2140 if (fwnode && !IS_ERR_OR_NULL(fwnode->secondary)) {
2141 dev_err(dev,
2142 "fwnode graph has no endpoints connection\n");
2143 return ERR_PTR(-EINVAL);
2144 }
2145
2146 ret = ipu_bridge_init(dev, ipu_bridge_parse_ssdb);
2147 if (ret) {
2148 dev_err_probe(dev, ret, "IPU bridge init failed\n");
2149 return ERR_PTR(ret);
2150 }
2151 }
2152
2153 pdata = kzalloc_obj(*pdata);
2154 if (!pdata)
2155 return ERR_PTR(-ENOMEM);
2156
2157 pdata->base = base;
2158 pdata->ipdata = ipdata;
2159
2160 isys_adev = ipu7_bus_initialize_device(pdev, parent, pdata, ctrl,
2161 IPU_ISYS_NAME);
2162 if (IS_ERR(isys_adev)) {
2163 dev_err_probe(dev, PTR_ERR(isys_adev),
2164 "ipu7_bus_initialize_device isys failed\n");
2165 kfree(pdata);
2166 return ERR_CAST(isys_adev);
2167 }
2168
2169 isys_adev->mmu = ipu7_mmu_init(dev, base, ISYS_MMID,
2170 &ipdata->hw_variant);
2171 if (IS_ERR(isys_adev->mmu)) {
2172 dev_err_probe(dev, PTR_ERR(isys_adev->mmu),
2173 "ipu7_mmu_init(isys_adev->mmu) failed\n");
2174 put_device(&isys_adev->auxdev.dev);
2175 kfree(pdata);
2176 return ERR_CAST(isys_adev->mmu);
2177 }
2178
2179 isys_adev->mmu->dev = &isys_adev->auxdev.dev;
2180 isys_adev->subsys = IPU_IS;
2181
2182 ret = ipu7_bus_add_device(isys_adev);
2183 if (ret) {
2184 kfree(pdata);
2185 return ERR_PTR(ret);
2186 }
2187
2188 return isys_adev;
2189 }
2190
2191 static struct ipu7_bus_device *
ipu7_psys_init(struct pci_dev * pdev,struct device * parent,const struct ipu_buttress_ctrl * ctrl,void __iomem * base,const struct ipu_psys_internal_pdata * ipdata,unsigned int nr)2192 ipu7_psys_init(struct pci_dev *pdev, struct device *parent,
2193 const struct ipu_buttress_ctrl *ctrl, void __iomem *base,
2194 const struct ipu_psys_internal_pdata *ipdata, unsigned int nr)
2195 {
2196 struct ipu7_bus_device *psys_adev;
2197 struct ipu7_psys_pdata *pdata;
2198 int ret;
2199
2200 pdata = kzalloc_obj(*pdata);
2201 if (!pdata)
2202 return ERR_PTR(-ENOMEM);
2203
2204 pdata->base = base;
2205 pdata->ipdata = ipdata;
2206
2207 psys_adev = ipu7_bus_initialize_device(pdev, parent, pdata, ctrl,
2208 IPU_PSYS_NAME);
2209 if (IS_ERR(psys_adev)) {
2210 dev_err_probe(&pdev->dev, PTR_ERR(psys_adev),
2211 "ipu7_bus_initialize_device psys failed\n");
2212 kfree(pdata);
2213 return ERR_CAST(psys_adev);
2214 }
2215
2216 psys_adev->mmu = ipu7_mmu_init(&pdev->dev, base, PSYS_MMID,
2217 &ipdata->hw_variant);
2218 if (IS_ERR(psys_adev->mmu)) {
2219 dev_err_probe(&pdev->dev, PTR_ERR(psys_adev->mmu),
2220 "ipu7_mmu_init(psys_adev->mmu) failed\n");
2221 put_device(&psys_adev->auxdev.dev);
2222 kfree(pdata);
2223 return ERR_CAST(psys_adev->mmu);
2224 }
2225
2226 psys_adev->mmu->dev = &psys_adev->auxdev.dev;
2227 psys_adev->subsys = IPU_PS;
2228
2229 ret = ipu7_bus_add_device(psys_adev);
2230 if (ret) {
2231 kfree(pdata);
2232 return ERR_PTR(ret);
2233 }
2234
2235 return psys_adev;
2236 }
2237
2238 static struct ia_gofo_msg_log_info_ts fw_error_log[IPU_SUBSYS_NUM];
ipu7_dump_fw_error_log(const struct ipu7_bus_device * adev)2239 void ipu7_dump_fw_error_log(const struct ipu7_bus_device *adev)
2240 {
2241 void __iomem *reg = adev->isp->base + ((adev->subsys == IPU_IS) ?
2242 BUTTRESS_REG_FW_GP24 :
2243 BUTTRESS_REG_FW_GP8);
2244
2245 memcpy_fromio(&fw_error_log[adev->subsys], reg,
2246 sizeof(fw_error_log[adev->subsys]));
2247 }
2248 EXPORT_SYMBOL_NS_GPL(ipu7_dump_fw_error_log, "INTEL_IPU7");
2249
ipu7_pci_config_setup(struct pci_dev * dev)2250 static void ipu7_pci_config_setup(struct pci_dev *dev)
2251 {
2252 u16 pci_command;
2253
2254 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2255 pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
2256 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2257 }
2258
ipu7_map_fw_code_region(struct ipu7_bus_device * sys,void * data,size_t size)2259 static int ipu7_map_fw_code_region(struct ipu7_bus_device *sys,
2260 void *data, size_t size)
2261 {
2262 struct device *dev = &sys->auxdev.dev;
2263 struct ipu7_bus_device *adev = to_ipu7_bus_device(dev);
2264 struct sg_table *sgt = &sys->fw_sgt;
2265 struct ipu7_device *isp = adev->isp;
2266 struct pci_dev *pdev = isp->pdev;
2267 unsigned long n_pages, i;
2268 unsigned long attr = 0;
2269 struct page **pages;
2270 int ret;
2271
2272 n_pages = PFN_UP(size);
2273
2274 pages = kmalloc_objs(*pages, n_pages);
2275 if (!pages)
2276 return -ENOMEM;
2277
2278 for (i = 0; i < n_pages; i++) {
2279 struct page *p = vmalloc_to_page(data);
2280
2281 if (!p) {
2282 ret = -ENODEV;
2283 goto out;
2284 }
2285
2286 pages[i] = p;
2287 data += PAGE_SIZE;
2288 }
2289
2290 ret = sg_alloc_table_from_pages(sgt, pages, n_pages, 0, size,
2291 GFP_KERNEL);
2292 if (ret) {
2293 ret = -ENOMEM;
2294 goto out;
2295 }
2296
2297 if (!isp->secure_mode)
2298 attr |= DMA_ATTR_RESERVE_REGION;
2299
2300 ret = dma_map_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
2301 if (ret < 0) {
2302 dev_err(dev, "map fw code[%lu pages %u nents] failed\n",
2303 n_pages, sgt->nents);
2304 ret = -ENOMEM;
2305 sg_free_table(sgt);
2306 goto out;
2307 }
2308
2309 ret = ipu7_dma_map_sgtable(sys, sgt, DMA_BIDIRECTIONAL, attr);
2310 if (ret) {
2311 dma_unmap_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
2312 sg_free_table(sgt);
2313 goto out;
2314 }
2315
2316 ipu7_dma_sync_sgtable(sys, sgt);
2317
2318 dev_dbg(dev, "fw code region mapped at 0x%pad entries %d\n",
2319 &sgt->sgl->dma_address, sgt->nents);
2320
2321 out:
2322 kfree(pages);
2323
2324 return ret;
2325 }
2326
ipu7_unmap_fw_code_region(struct ipu7_bus_device * sys)2327 static void ipu7_unmap_fw_code_region(struct ipu7_bus_device *sys)
2328 {
2329 struct pci_dev *pdev = sys->isp->pdev;
2330 struct sg_table *sgt = &sys->fw_sgt;
2331
2332 ipu7_dma_unmap_sgtable(sys, sgt, DMA_BIDIRECTIONAL, 0);
2333 dma_unmap_sgtable(&pdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
2334 sg_free_table(sgt);
2335 }
2336
ipu7_init_fw_code_region_by_sys(struct ipu7_bus_device * sys,const char * sys_name)2337 static int ipu7_init_fw_code_region_by_sys(struct ipu7_bus_device *sys,
2338 const char *sys_name)
2339 {
2340 struct device *dev = &sys->auxdev.dev;
2341 struct ipu7_device *isp = sys->isp;
2342 int ret;
2343
2344 /* Copy FW binaries to specific location. */
2345 ret = ipu7_cpd_copy_binary(isp->cpd_fw->data, sys_name,
2346 isp->fw_code_region, &sys->fw_entry);
2347 if (ret) {
2348 dev_err(dev, "%s binary not found.\n", sys_name);
2349 return ret;
2350 }
2351
2352 ret = pm_runtime_get_sync(dev);
2353 if (ret < 0) {
2354 dev_err(dev, "Failed to get runtime PM\n");
2355 return ret;
2356 }
2357
2358 ret = ipu7_mmu_hw_init(sys->mmu);
2359 if (ret) {
2360 dev_err(dev, "Failed to set mmu hw\n");
2361 pm_runtime_put(dev);
2362 return ret;
2363 }
2364
2365 /* Map code region. */
2366 ret = ipu7_map_fw_code_region(sys, isp->fw_code_region,
2367 IPU_FW_CODE_REGION_SIZE);
2368 if (ret)
2369 dev_err(dev, "Failed to map fw code region for %s.\n",
2370 sys_name);
2371
2372 ipu7_mmu_hw_cleanup(sys->mmu);
2373 pm_runtime_put(dev);
2374
2375 return ret;
2376 }
2377
ipu7_init_fw_code_region(struct ipu7_device * isp)2378 static int ipu7_init_fw_code_region(struct ipu7_device *isp)
2379 {
2380 int ret;
2381
2382 /*
2383 * Allocate and map memory for FW execution.
2384 * Not required in secure mode, in which FW runs in IMR.
2385 */
2386 isp->fw_code_region = vmalloc(IPU_FW_CODE_REGION_SIZE);
2387 if (!isp->fw_code_region)
2388 return -ENOMEM;
2389
2390 ret = ipu7_init_fw_code_region_by_sys(isp->isys, "isys");
2391 if (ret)
2392 goto fail_init;
2393
2394 ret = ipu7_init_fw_code_region_by_sys(isp->psys, "psys");
2395 if (ret)
2396 goto fail_init;
2397
2398 return 0;
2399
2400 fail_init:
2401 vfree(isp->fw_code_region);
2402
2403 return ret;
2404 }
2405
ipu7_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2406 static int ipu7_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2407 {
2408 struct ipu_buttress_ctrl *isys_ctrl = NULL, *psys_ctrl = NULL;
2409 struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
2410 const struct ipu_buttress_ctrl *isys_buttress_ctrl;
2411 const struct ipu_buttress_ctrl *psys_buttress_ctrl;
2412 struct ipu_isys_internal_pdata *isys_ipdata;
2413 struct ipu_psys_internal_pdata *psys_ipdata;
2414 unsigned int dma_mask = IPU_DMA_MASK;
2415 struct device *dev = &pdev->dev;
2416 void __iomem *isys_base = NULL;
2417 void __iomem *psys_base = NULL;
2418 phys_addr_t phys, pb_phys;
2419 struct ipu7_device *isp;
2420 u32 is_es;
2421 int ret;
2422
2423 if (!fwnode || fwnode_property_read_u32(fwnode, "is_es", &is_es))
2424 is_es = 0;
2425
2426 isp = devm_kzalloc(dev, sizeof(*isp), GFP_KERNEL);
2427 if (!isp)
2428 return -ENOMEM;
2429
2430 isp->pdev = pdev;
2431 INIT_LIST_HEAD(&isp->devices);
2432
2433 ret = pcim_enable_device(pdev);
2434 if (ret)
2435 return dev_err_probe(dev, ret, "Enable PCI device failed\n");
2436
2437 dev_info(dev, "Device 0x%x (rev: 0x%x)\n",
2438 pdev->device, pdev->revision);
2439
2440 phys = pci_resource_start(pdev, IPU_PCI_BAR);
2441 pb_phys = pci_resource_start(pdev, IPU_PCI_PBBAR);
2442 dev_info(dev, "IPU7 PCI BAR0 base %pap BAR2 base %pap\n",
2443 &phys, &pb_phys);
2444
2445 isp->base = pcim_iomap_region(pdev, IPU_PCI_BAR, IPU_NAME);
2446 if (IS_ERR(isp->base))
2447 return dev_err_probe(dev, PTR_ERR(isp->base),
2448 "Failed to I/O memory remapping bar %u\n",
2449 IPU_PCI_BAR);
2450
2451 isp->pb_base = pcim_iomap_region(pdev, IPU_PCI_PBBAR, IPU_NAME);
2452 if (IS_ERR(isp->pb_base))
2453 return dev_err_probe(dev, PTR_ERR(isp->pb_base),
2454 "Failed to I/O memory remapping bar %u\n",
2455 IPU_PCI_PBBAR);
2456
2457 dev_info(dev, "IPU7 PCI BAR0 mapped at %p\n BAR2 mapped at %p\n",
2458 isp->base, isp->pb_base);
2459
2460 pci_set_drvdata(pdev, isp);
2461 pci_set_master(pdev);
2462
2463 switch (id->device) {
2464 case IPU7_PCI_ID:
2465 isp->hw_ver = IPU_VER_7;
2466 isp->cpd_fw_name = IPU7_FIRMWARE_NAME;
2467 isys_ipdata = &ipu7_isys_ipdata;
2468 psys_ipdata = &ipu7_psys_ipdata;
2469 isys_buttress_ctrl = &ipu7_isys_buttress_ctrl;
2470 psys_buttress_ctrl = &ipu7_psys_buttress_ctrl;
2471 break;
2472 case IPU7P5_PCI_ID:
2473 isp->hw_ver = IPU_VER_7P5;
2474 isp->cpd_fw_name = IPU7P5_FIRMWARE_NAME;
2475 isys_ipdata = &ipu7p5_isys_ipdata;
2476 psys_ipdata = &ipu7p5_psys_ipdata;
2477 isys_buttress_ctrl = &ipu7_isys_buttress_ctrl;
2478 psys_buttress_ctrl = &ipu7_psys_buttress_ctrl;
2479 break;
2480 case IPU8_PCI_ID:
2481 isp->hw_ver = IPU_VER_8;
2482 isp->cpd_fw_name = IPU8_FIRMWARE_NAME;
2483 isys_ipdata = &ipu8_isys_ipdata;
2484 psys_ipdata = &ipu8_psys_ipdata;
2485 isys_buttress_ctrl = &ipu8_isys_buttress_ctrl;
2486 psys_buttress_ctrl = &ipu8_psys_buttress_ctrl;
2487 break;
2488 default:
2489 WARN(1, "Unsupported IPU device");
2490 return -ENODEV;
2491 }
2492
2493 ipu_internal_pdata_init(isys_ipdata, psys_ipdata);
2494
2495 isys_base = isp->base + isys_ipdata->hw_variant.offset;
2496 psys_base = isp->base + psys_ipdata->hw_variant.offset;
2497
2498 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(dma_mask));
2499 if (ret)
2500 return dev_err_probe(dev, ret, "Failed to set DMA mask\n");
2501
2502 dma_set_max_seg_size(dev, UINT_MAX);
2503
2504 ipu7_pci_config_setup(pdev);
2505
2506 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2507 if (ret < 0)
2508 return dev_err_probe(dev, ret, "Failed to alloc irq vector\n");
2509
2510 ret = ipu_buttress_init(isp);
2511 if (ret)
2512 goto pci_irq_free;
2513
2514 dev_info(dev, "firmware cpd file: %s\n", isp->cpd_fw_name);
2515
2516 ret = request_firmware(&isp->cpd_fw, isp->cpd_fw_name, dev);
2517 if (ret) {
2518 dev_err_probe(dev, ret,
2519 "Requesting signed firmware %s failed\n",
2520 isp->cpd_fw_name);
2521 goto buttress_exit;
2522 }
2523
2524 ret = ipu7_cpd_validate_cpd_file(isp, isp->cpd_fw->data,
2525 isp->cpd_fw->size);
2526 if (ret) {
2527 dev_err_probe(dev, ret, "Failed to validate cpd\n");
2528 goto out_ipu_bus_del_devices;
2529 }
2530
2531 isys_ctrl = devm_kmemdup(dev, isys_buttress_ctrl,
2532 sizeof(*isys_buttress_ctrl), GFP_KERNEL);
2533 if (!isys_ctrl) {
2534 ret = -ENOMEM;
2535 goto out_ipu_bus_del_devices;
2536 }
2537
2538 isp->isys = ipu7_isys_init(pdev, dev, isys_ctrl, isys_base,
2539 isys_ipdata, 0);
2540 if (IS_ERR(isp->isys)) {
2541 ret = PTR_ERR(isp->isys);
2542 goto out_ipu_bus_del_devices;
2543 }
2544
2545 psys_ctrl = devm_kmemdup(dev, psys_buttress_ctrl,
2546 sizeof(*psys_buttress_ctrl), GFP_KERNEL);
2547 if (!psys_ctrl) {
2548 ret = -ENOMEM;
2549 goto out_ipu_bus_del_devices;
2550 }
2551
2552 isp->psys = ipu7_psys_init(pdev, &isp->isys->auxdev.dev,
2553 psys_ctrl, psys_base,
2554 psys_ipdata, 0);
2555 if (IS_ERR(isp->psys)) {
2556 ret = PTR_ERR(isp->psys);
2557 goto out_ipu_bus_del_devices;
2558 }
2559
2560 ret = devm_request_threaded_irq(dev, pdev->irq,
2561 ipu_buttress_isr,
2562 ipu_buttress_isr_threaded,
2563 IRQF_SHARED, IPU_NAME, isp);
2564 if (ret)
2565 goto out_ipu_bus_del_devices;
2566
2567 if (!isp->secure_mode) {
2568 ret = ipu7_init_fw_code_region(isp);
2569 if (ret)
2570 goto out_ipu_bus_del_devices;
2571 } else {
2572 ret = pm_runtime_get_sync(&isp->psys->auxdev.dev);
2573 if (ret < 0) {
2574 dev_err(&isp->psys->auxdev.dev,
2575 "Failed to get runtime PM\n");
2576 goto out_ipu_bus_del_devices;
2577 }
2578
2579 ret = ipu7_mmu_hw_init(isp->psys->mmu);
2580 if (ret) {
2581 dev_err_probe(&isp->pdev->dev, ret,
2582 "Failed to init MMU hardware\n");
2583 goto out_ipu_bus_del_devices;
2584 }
2585
2586 ret = ipu7_map_fw_code_region(isp->psys,
2587 (void *)isp->cpd_fw->data,
2588 isp->cpd_fw->size);
2589 if (ret) {
2590 dev_err_probe(&isp->pdev->dev, ret,
2591 "failed to map fw image\n");
2592 goto out_ipu_bus_del_devices;
2593 }
2594
2595 ret = ipu_buttress_authenticate(isp);
2596 if (ret) {
2597 dev_err_probe(&isp->pdev->dev, ret,
2598 "FW authentication failed\n");
2599 goto out_ipu_bus_del_devices;
2600 }
2601
2602 ipu7_mmu_hw_cleanup(isp->psys->mmu);
2603 pm_runtime_put(&isp->psys->auxdev.dev);
2604 }
2605
2606 pm_runtime_put_noidle(dev);
2607 pm_runtime_allow(dev);
2608
2609 isp->ipu7_bus_ready_to_probe = true;
2610
2611 return 0;
2612
2613 out_ipu_bus_del_devices:
2614 if (!IS_ERR_OR_NULL(isp->isys) && isp->isys->fw_sgt.nents)
2615 ipu7_unmap_fw_code_region(isp->isys);
2616 if (!IS_ERR_OR_NULL(isp->psys) && isp->psys->fw_sgt.nents)
2617 ipu7_unmap_fw_code_region(isp->psys);
2618 if (!IS_ERR_OR_NULL(isp->psys) && !IS_ERR_OR_NULL(isp->psys->mmu))
2619 ipu7_mmu_cleanup(isp->psys->mmu);
2620 if (!IS_ERR_OR_NULL(isp->isys) && !IS_ERR_OR_NULL(isp->isys->mmu))
2621 ipu7_mmu_cleanup(isp->isys->mmu);
2622 if (!IS_ERR_OR_NULL(isp->psys))
2623 pm_runtime_put_sync(&isp->psys->auxdev.dev);
2624 ipu7_bus_del_devices(pdev);
2625 release_firmware(isp->cpd_fw);
2626 buttress_exit:
2627 ipu_buttress_exit(isp);
2628 pci_irq_free:
2629 pci_free_irq_vectors(pdev);
2630
2631 return ret;
2632 }
2633
ipu7_pci_remove(struct pci_dev * pdev)2634 static void ipu7_pci_remove(struct pci_dev *pdev)
2635 {
2636 struct ipu7_device *isp = pci_get_drvdata(pdev);
2637
2638 if (!IS_ERR_OR_NULL(isp->isys) && isp->isys->fw_sgt.nents)
2639 ipu7_unmap_fw_code_region(isp->isys);
2640 if (!IS_ERR_OR_NULL(isp->psys) && isp->psys->fw_sgt.nents)
2641 ipu7_unmap_fw_code_region(isp->psys);
2642
2643 if (!IS_ERR_OR_NULL(isp->fw_code_region))
2644 vfree(isp->fw_code_region);
2645
2646 ipu7_mmu_cleanup(isp->isys->mmu);
2647 ipu7_mmu_cleanup(isp->psys->mmu);
2648
2649 ipu7_bus_del_devices(pdev);
2650
2651 pm_runtime_forbid(&pdev->dev);
2652 pm_runtime_get_noresume(&pdev->dev);
2653
2654 ipu_buttress_exit(isp);
2655
2656 release_firmware(isp->cpd_fw);
2657 }
2658
ipu7_pci_reset_prepare(struct pci_dev * pdev)2659 static void ipu7_pci_reset_prepare(struct pci_dev *pdev)
2660 {
2661 struct ipu7_device *isp = pci_get_drvdata(pdev);
2662
2663 dev_warn(&pdev->dev, "FLR prepare\n");
2664 pm_runtime_forbid(&isp->pdev->dev);
2665 }
2666
ipu7_pci_reset_done(struct pci_dev * pdev)2667 static void ipu7_pci_reset_done(struct pci_dev *pdev)
2668 {
2669 struct ipu7_device *isp = pci_get_drvdata(pdev);
2670
2671 ipu_buttress_restore(isp);
2672 if (isp->secure_mode)
2673 ipu_buttress_reset_authentication(isp);
2674
2675 isp->ipc_reinit = true;
2676 pm_runtime_allow(&isp->pdev->dev);
2677
2678 dev_warn(&pdev->dev, "FLR completed\n");
2679 }
2680
2681 /*
2682 * PCI base driver code requires driver to provide these to enable
2683 * PCI device level PM state transitions (D0<->D3)
2684 */
ipu7_suspend(struct device * dev)2685 static int ipu7_suspend(struct device *dev)
2686 {
2687 struct pci_dev *pdev = to_pci_dev(dev);
2688
2689 synchronize_irq(pdev->irq);
2690
2691 return 0;
2692 }
2693
ipu7_resume(struct device * dev)2694 static int ipu7_resume(struct device *dev)
2695 {
2696 struct pci_dev *pdev = to_pci_dev(dev);
2697 struct ipu7_device *isp = pci_get_drvdata(pdev);
2698 struct ipu_buttress *b = &isp->buttress;
2699 int ret;
2700
2701 isp->secure_mode = ipu_buttress_get_secure_mode(isp);
2702 dev_info(dev, "IPU7 in %s mode\n",
2703 isp->secure_mode ? "secure" : "non-secure");
2704
2705 ipu_buttress_restore(isp);
2706
2707 ret = ipu_buttress_ipc_reset(isp, &b->cse);
2708 if (ret)
2709 dev_err(dev, "IPC reset protocol failed!\n");
2710
2711 ret = pm_runtime_get_sync(&isp->psys->auxdev.dev);
2712 if (ret < 0) {
2713 dev_err(dev, "Failed to get runtime PM\n");
2714 return 0;
2715 }
2716
2717 ret = ipu_buttress_authenticate(isp);
2718 if (ret)
2719 dev_err(dev, "FW authentication failed(%d)\n", ret);
2720
2721 pm_runtime_put(&isp->psys->auxdev.dev);
2722
2723 return 0;
2724 }
2725
ipu7_runtime_resume(struct device * dev)2726 static int ipu7_runtime_resume(struct device *dev)
2727 {
2728 struct pci_dev *pdev = to_pci_dev(dev);
2729 struct ipu7_device *isp = pci_get_drvdata(pdev);
2730 int ret;
2731
2732 ipu_buttress_restore(isp);
2733
2734 if (isp->ipc_reinit) {
2735 struct ipu_buttress *b = &isp->buttress;
2736
2737 isp->ipc_reinit = false;
2738 ret = ipu_buttress_ipc_reset(isp, &b->cse);
2739 if (ret)
2740 dev_err(dev, "IPC reset protocol failed!\n");
2741 }
2742
2743 return 0;
2744 }
2745
2746 static const struct dev_pm_ops ipu7_pm_ops = {
2747 SYSTEM_SLEEP_PM_OPS(&ipu7_suspend, &ipu7_resume)
2748 RUNTIME_PM_OPS(&ipu7_suspend, &ipu7_runtime_resume, NULL)
2749 };
2750
2751 static const struct pci_device_id ipu7_pci_tbl[] = {
2752 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IPU7_PCI_ID)},
2753 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, IPU7P5_PCI_ID)},
2754 {0,}
2755 };
2756 MODULE_DEVICE_TABLE(pci, ipu7_pci_tbl);
2757
2758 static const struct pci_error_handlers pci_err_handlers = {
2759 .reset_prepare = ipu7_pci_reset_prepare,
2760 .reset_done = ipu7_pci_reset_done,
2761 };
2762
2763 static struct pci_driver ipu7_pci_driver = {
2764 .name = IPU_NAME,
2765 .id_table = ipu7_pci_tbl,
2766 .probe = ipu7_pci_probe,
2767 .remove = ipu7_pci_remove,
2768 .driver = {
2769 .pm = &ipu7_pm_ops,
2770 },
2771 .err_handler = &pci_err_handlers,
2772 };
2773
2774 module_pci_driver(ipu7_pci_driver);
2775
2776 MODULE_IMPORT_NS("INTEL_IPU_BRIDGE");
2777 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
2778 MODULE_AUTHOR("Tianshu Qiu <tian.shu.qiu@intel.com>");
2779 MODULE_AUTHOR("Qingwu Zhang <qingwu.zhang@intel.com>");
2780 MODULE_AUTHOR("Intel");
2781 MODULE_LICENSE("GPL");
2782 MODULE_DESCRIPTION("Intel ipu7 pci driver");
2783