1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/delay.h>
8
9 #include <drm/drm_bridge.h>
10 #include <drm/drm_bridge_connector.h>
11 #include <drm/drm_vblank.h>
12
13 #include "msm_drv.h"
14 #include "msm_gem.h"
15 #include "msm_mmu.h"
16 #include "mdp4_kms.h"
17
mdp4_hw_init(struct msm_kms * kms)18 static int mdp4_hw_init(struct msm_kms *kms)
19 {
20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
21 struct drm_device *dev = mdp4_kms->dev;
22 u32 dmap_cfg, vg_cfg;
23 unsigned long clk;
24
25 pm_runtime_get_sync(dev->dev);
26
27 if (mdp4_kms->rev > 1) {
28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
30 }
31
32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
33
34 /* max read pending cmd config, 3 pending requests: */
35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
36
37 clk = clk_get_rate(mdp4_kms->clk);
38
39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
42 } else {
43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
45 }
46
47 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
48
49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
51
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
56
57 if (mdp4_kms->rev >= 2)
58 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
60
61 /* disable CSC matrix / YUV by default: */
62 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
64 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
65 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
66 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
68
69 if (mdp4_kms->rev > 1)
70 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
71
72 pm_runtime_put_sync(dev->dev);
73
74 return 0;
75 }
76
mdp4_enable_commit(struct msm_kms * kms)77 static void mdp4_enable_commit(struct msm_kms *kms)
78 {
79 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
80 mdp4_enable(mdp4_kms);
81 }
82
mdp4_disable_commit(struct msm_kms * kms)83 static void mdp4_disable_commit(struct msm_kms *kms)
84 {
85 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
86 mdp4_disable(mdp4_kms);
87 }
88
mdp4_flush_commit(struct msm_kms * kms,unsigned crtc_mask)89 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
90 {
91 /* TODO */
92 }
93
mdp4_wait_flush(struct msm_kms * kms,unsigned crtc_mask)94 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
95 {
96 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
97 struct drm_crtc *crtc;
98
99 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
100 mdp4_crtc_wait_for_commit_done(crtc);
101 }
102
mdp4_complete_commit(struct msm_kms * kms,unsigned crtc_mask)103 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
104 {
105 }
106
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)107 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
108 struct drm_encoder *encoder)
109 {
110 /* if we had >1 encoder, we'd need something more clever: */
111 switch (encoder->encoder_type) {
112 case DRM_MODE_ENCODER_TMDS:
113 return mdp4_dtv_round_pixclk(encoder, rate);
114 case DRM_MODE_ENCODER_LVDS:
115 case DRM_MODE_ENCODER_DSI:
116 default:
117 return rate;
118 }
119 }
120
mdp4_destroy(struct msm_kms * kms)121 static void mdp4_destroy(struct msm_kms *kms)
122 {
123 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
124 struct device *dev = mdp4_kms->dev->dev;
125
126 if (mdp4_kms->blank_cursor_iova)
127 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->vm);
128 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
129
130 if (kms->vm) {
131 struct msm_mmu *mmu = to_msm_vm(kms->vm)->mmu;
132
133 mmu->funcs->detach(mmu);
134 drm_gpuvm_put(kms->vm);
135 }
136
137 if (mdp4_kms->rpm_enabled)
138 pm_runtime_disable(dev);
139
140 mdp_kms_destroy(&mdp4_kms->base);
141 }
142
143 static const struct mdp_kms_funcs kms_funcs = {
144 .base = {
145 .hw_init = mdp4_hw_init,
146 .irq_preinstall = mdp4_irq_preinstall,
147 .irq_postinstall = mdp4_irq_postinstall,
148 .irq_uninstall = mdp4_irq_uninstall,
149 .irq = mdp4_irq,
150 .enable_vblank = mdp4_enable_vblank,
151 .disable_vblank = mdp4_disable_vblank,
152 .enable_commit = mdp4_enable_commit,
153 .disable_commit = mdp4_disable_commit,
154 .flush_commit = mdp4_flush_commit,
155 .wait_flush = mdp4_wait_flush,
156 .complete_commit = mdp4_complete_commit,
157 .round_pixclk = mdp4_round_pixclk,
158 .destroy = mdp4_destroy,
159 },
160 .set_irqmask = mdp4_set_irqmask,
161 };
162
mdp4_disable(struct mdp4_kms * mdp4_kms)163 int mdp4_disable(struct mdp4_kms *mdp4_kms)
164 {
165 DBG("");
166
167 clk_disable_unprepare(mdp4_kms->clk);
168 clk_disable_unprepare(mdp4_kms->pclk);
169 clk_disable_unprepare(mdp4_kms->lut_clk);
170 clk_disable_unprepare(mdp4_kms->axi_clk);
171
172 return 0;
173 }
174
mdp4_enable(struct mdp4_kms * mdp4_kms)175 int mdp4_enable(struct mdp4_kms *mdp4_kms)
176 {
177 DBG("");
178
179 clk_prepare_enable(mdp4_kms->clk);
180 clk_prepare_enable(mdp4_kms->pclk);
181 clk_prepare_enable(mdp4_kms->lut_clk);
182 clk_prepare_enable(mdp4_kms->axi_clk);
183
184 return 0;
185 }
186
187
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)188 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
189 int intf_type)
190 {
191 struct drm_device *dev = mdp4_kms->dev;
192 struct msm_drm_private *priv = dev->dev_private;
193 struct drm_encoder *encoder;
194 struct drm_connector *connector;
195 struct drm_bridge *next_bridge;
196 int dsi_id;
197 int ret;
198
199 switch (intf_type) {
200 case DRM_MODE_ENCODER_LVDS:
201 /*
202 * bail out early if there is no panel node (no need to
203 * initialize LCDC encoder and LVDS connector)
204 */
205 next_bridge = devm_drm_of_get_bridge(dev->dev, dev->dev->of_node, 0, 0);
206 if (IS_ERR(next_bridge)) {
207 ret = PTR_ERR(next_bridge);
208 if (ret == -ENODEV)
209 return 0;
210 return ret;
211 }
212
213 encoder = mdp4_lcdc_encoder_init(dev);
214 if (IS_ERR(encoder)) {
215 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
216 return PTR_ERR(encoder);
217 }
218
219 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
220 encoder->possible_crtcs = 1 << DMA_P;
221
222 ret = drm_bridge_attach(encoder, next_bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
223 if (ret) {
224 DRM_DEV_ERROR(dev->dev, "failed to attach LVDS panel/bridge: %d\n", ret);
225
226 return ret;
227 }
228
229 connector = drm_bridge_connector_init(dev, encoder);
230 if (IS_ERR(connector)) {
231 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
232 return PTR_ERR(connector);
233 }
234
235 break;
236 case DRM_MODE_ENCODER_TMDS:
237 encoder = mdp4_dtv_encoder_init(dev);
238 if (IS_ERR(encoder)) {
239 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
240 return PTR_ERR(encoder);
241 }
242
243 /* DTV can be hooked to DMA_E: */
244 encoder->possible_crtcs = 1 << 1;
245
246 if (priv->kms->hdmi) {
247 /* Construct bridge/connector for HDMI: */
248 ret = msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder);
249 if (ret) {
250 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
251 return ret;
252 }
253 }
254
255 break;
256 case DRM_MODE_ENCODER_DSI:
257 /* only DSI1 supported for now */
258 dsi_id = 0;
259
260 if (!priv->kms->dsi[dsi_id])
261 break;
262
263 encoder = mdp4_dsi_encoder_init(dev);
264 if (IS_ERR(encoder)) {
265 ret = PTR_ERR(encoder);
266 DRM_DEV_ERROR(dev->dev,
267 "failed to construct DSI encoder: %d\n", ret);
268 return ret;
269 }
270
271 /* TODO: Add DMA_S later? */
272 encoder->possible_crtcs = 1 << DMA_P;
273
274 ret = msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder);
275 if (ret) {
276 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
277 ret);
278 return ret;
279 }
280
281 break;
282 default:
283 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
284 return -EINVAL;
285 }
286
287 return 0;
288 }
289
modeset_init(struct mdp4_kms * mdp4_kms)290 static int modeset_init(struct mdp4_kms *mdp4_kms)
291 {
292 struct drm_device *dev = mdp4_kms->dev;
293 struct drm_plane *plane;
294 struct drm_crtc *crtc;
295 int i, ret;
296 static const enum mdp4_pipe rgb_planes[] = {
297 RGB1, RGB2,
298 };
299 static const enum mdp4_pipe vg_planes[] = {
300 VG1, VG2,
301 };
302 static const enum mdp4_dma mdp4_crtcs[] = {
303 DMA_P, DMA_E,
304 };
305 static const char * const mdp4_crtc_names[] = {
306 "DMA_P", "DMA_E",
307 };
308 static const int mdp4_intfs[] = {
309 DRM_MODE_ENCODER_LVDS,
310 DRM_MODE_ENCODER_DSI,
311 DRM_MODE_ENCODER_TMDS,
312 };
313
314 /* construct non-private planes: */
315 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
316 plane = mdp4_plane_init(dev, vg_planes[i], false);
317 if (IS_ERR(plane)) {
318 DRM_DEV_ERROR(dev->dev,
319 "failed to construct plane for VG%d\n", i + 1);
320 ret = PTR_ERR(plane);
321 goto fail;
322 }
323 }
324
325 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
326 plane = mdp4_plane_init(dev, rgb_planes[i], true);
327 if (IS_ERR(plane)) {
328 DRM_DEV_ERROR(dev->dev,
329 "failed to construct plane for RGB%d\n", i + 1);
330 ret = PTR_ERR(plane);
331 goto fail;
332 }
333
334 crtc = mdp4_crtc_init(dev, plane, i,
335 mdp4_crtcs[i]);
336 if (IS_ERR(crtc)) {
337 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
338 mdp4_crtc_names[i]);
339 ret = PTR_ERR(crtc);
340 goto fail;
341 }
342 }
343
344 /*
345 * we currently set up two relatively fixed paths:
346 *
347 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
348 * or
349 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
350 *
351 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
352 */
353
354 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
355 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
356 if (ret) {
357 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
358 i, ret);
359 goto fail;
360 }
361 }
362
363 return 0;
364
365 fail:
366 return ret;
367 }
368
read_mdp_hw_revision(struct mdp4_kms * mdp4_kms,u32 * major,u32 * minor)369 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
370 u32 *major, u32 *minor)
371 {
372 struct drm_device *dev = mdp4_kms->dev;
373 u32 version;
374
375 mdp4_enable(mdp4_kms);
376 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
377 mdp4_disable(mdp4_kms);
378
379 *major = FIELD(version, MDP4_VERSION_MAJOR);
380 *minor = FIELD(version, MDP4_VERSION_MINOR);
381
382 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
383 }
384
mdp4_kms_init(struct drm_device * dev)385 static int mdp4_kms_init(struct drm_device *dev)
386 {
387 struct msm_drm_private *priv = dev->dev_private;
388 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms));
389 struct msm_kms *kms = NULL;
390 struct drm_gpuvm *vm;
391 int ret;
392 u32 major, minor;
393 unsigned long max_clk;
394
395 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
396 max_clk = 266667000;
397
398 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
399 if (ret) {
400 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
401 return ret;
402 }
403
404 kms = priv->kms;
405
406 mdp4_kms->dev = dev;
407
408 if (mdp4_kms->vdd) {
409 ret = regulator_enable(mdp4_kms->vdd);
410 if (ret) {
411 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
412 return ret;
413 }
414 }
415
416 clk_set_rate(mdp4_kms->clk, max_clk);
417
418 read_mdp_hw_revision(mdp4_kms, &major, &minor);
419
420 if (major != 4) {
421 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
422 major, minor);
423 ret = -ENXIO;
424 return ret;
425 }
426
427 mdp4_kms->rev = minor;
428
429 if (mdp4_kms->rev >= 2) {
430 if (!mdp4_kms->lut_clk) {
431 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
432 ret = -ENODEV;
433 return ret;
434 }
435 clk_set_rate(mdp4_kms->lut_clk, max_clk);
436 }
437
438 pm_runtime_enable(dev->dev);
439 mdp4_kms->rpm_enabled = true;
440
441 /* make sure things are off before attaching iommu (bootloader could
442 * have left things on, in which case we'll start getting faults if
443 * we don't disable):
444 */
445 mdp4_enable(mdp4_kms);
446 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
447 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
448 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
449 mdp4_disable(mdp4_kms);
450 mdelay(16);
451
452 vm = msm_kms_init_vm(mdp4_kms->dev, NULL);
453 if (IS_ERR(vm)) {
454 ret = PTR_ERR(vm);
455 return ret;
456 }
457
458 kms->vm = vm;
459
460 ret = modeset_init(mdp4_kms);
461 if (ret) {
462 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
463 return ret;
464 }
465
466 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT, NULL);
467 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
468 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
469 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
470 mdp4_kms->blank_cursor_bo = NULL;
471 return ret;
472 }
473
474 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->vm,
475 &mdp4_kms->blank_cursor_iova);
476 if (ret) {
477 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
478 return ret;
479 }
480
481 dev->mode_config.min_width = 0;
482 dev->mode_config.min_height = 0;
483 dev->mode_config.max_width = 2048;
484 dev->mode_config.max_height = 2048;
485
486 return 0;
487 }
488
489 static const struct dev_pm_ops mdp4_pm_ops = {
490 .prepare = msm_kms_pm_prepare,
491 .complete = msm_kms_pm_complete,
492 };
493
mdp4_probe(struct platform_device * pdev)494 static int mdp4_probe(struct platform_device *pdev)
495 {
496 struct device *dev = &pdev->dev;
497 struct mdp4_kms *mdp4_kms;
498 int irq;
499
500 mdp4_kms = devm_kzalloc(dev, sizeof(*mdp4_kms), GFP_KERNEL);
501 if (!mdp4_kms)
502 return -ENOMEM;
503
504 mdp4_kms->mmio = msm_ioremap(pdev, NULL);
505 if (IS_ERR(mdp4_kms->mmio))
506 return PTR_ERR(mdp4_kms->mmio);
507
508 irq = platform_get_irq(pdev, 0);
509 if (irq < 0)
510 return dev_err_probe(dev, irq, "failed to get irq\n");
511
512 mdp4_kms->base.base.irq = irq;
513
514 /* NOTE: driver for this regulator still missing upstream.. use
515 * _get_exclusive() and ignore the error if it does not exist
516 * (and hope that the bootloader left it on for us)
517 */
518 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
519 if (IS_ERR(mdp4_kms->vdd))
520 mdp4_kms->vdd = NULL;
521
522 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
523 if (IS_ERR(mdp4_kms->clk))
524 return dev_err_probe(dev, PTR_ERR(mdp4_kms->clk), "failed to get core_clk\n");
525
526 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
527 if (IS_ERR(mdp4_kms->pclk))
528 mdp4_kms->pclk = NULL;
529
530 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
531 if (IS_ERR(mdp4_kms->axi_clk))
532 return dev_err_probe(dev, PTR_ERR(mdp4_kms->axi_clk), "failed to get axi_clk\n");
533
534 /*
535 * This is required for revn >= 2. Handle errors here and let the kms
536 * init bail out if the clock is not provided.
537 */
538 mdp4_kms->lut_clk = devm_clk_get_optional(&pdev->dev, "lut_clk");
539 if (IS_ERR(mdp4_kms->lut_clk))
540 return dev_err_probe(dev, PTR_ERR(mdp4_kms->lut_clk), "failed to get lut_clk\n");
541
542 return msm_drv_probe(&pdev->dev, mdp4_kms_init, &mdp4_kms->base.base);
543 }
544
mdp4_remove(struct platform_device * pdev)545 static void mdp4_remove(struct platform_device *pdev)
546 {
547 component_master_del(&pdev->dev, &msm_drm_ops);
548 }
549
550 static const struct of_device_id mdp4_dt_match[] = {
551 { .compatible = "qcom,mdp4" },
552 { /* sentinel */ }
553 };
554 MODULE_DEVICE_TABLE(of, mdp4_dt_match);
555
556 static struct platform_driver mdp4_platform_driver = {
557 .probe = mdp4_probe,
558 .remove = mdp4_remove,
559 .shutdown = msm_kms_shutdown,
560 .driver = {
561 .name = "mdp4",
562 .of_match_table = mdp4_dt_match,
563 .pm = &mdp4_pm_ops,
564 },
565 };
566
msm_mdp4_register(void)567 void __init msm_mdp4_register(void)
568 {
569 platform_driver_register(&mdp4_platform_driver);
570 }
571
msm_mdp4_unregister(void)572 void __exit msm_mdp4_unregister(void)
573 {
574 platform_driver_unregister(&mdp4_platform_driver);
575 }
576