1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h> 8#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-ccu.h> 10#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h> 11#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 12#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> 13#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a55"; 26 device_type = "cpu"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@100 { 32 compatible = "arm,cortex-a55"; 33 device_type = "cpu"; 34 reg = <0x100>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@200 { 39 compatible = "arm,cortex-a55"; 40 device_type = "cpu"; 41 reg = <0x200>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 device_type = "cpu"; 48 reg = <0x300>; 49 enable-method = "psci"; 50 }; 51 52 cpu4: cpu@400 { 53 compatible = "arm,cortex-a55"; 54 device_type = "cpu"; 55 reg = <0x400>; 56 enable-method = "psci"; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a55"; 61 device_type = "cpu"; 62 reg = <0x500>; 63 enable-method = "psci"; 64 }; 65 66 cpu6: cpu@600 { 67 compatible = "arm,cortex-a55"; 68 device_type = "cpu"; 69 reg = <0x600>; 70 enable-method = "psci"; 71 }; 72 73 cpu7: cpu@700 { 74 compatible = "arm,cortex-a55"; 75 device_type = "cpu"; 76 reg = <0x700>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 osc24M: osc24M-clk { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 clock-output-names = "osc24M"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 91 }; 92 93 psci { 94 compatible = "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 arm,no-tick-in-suspend; 101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; 106 }; 107 108 soc { 109 compatible = "simple-bus"; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0x0 0x0 0x0 0x40000000>; 113 114 gpu: gpu@1800000 { 115 compatible = "allwinner,sun55i-a523-mali", 116 "arm,mali-valhall-jm"; 117 reg = <0x1800000 0x10000>; 118 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 121 interrupt-names = "job", "mmu", "gpu"; 122 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 123 clock-names = "core", "bus"; 124 power-domains = <&pck600 PD_GPU>; 125 resets = <&ccu RST_BUS_GPU>; 126 status = "disabled"; 127 }; 128 129 pio: pinctrl@2000000 { 130 compatible = "allwinner,sun55i-a523-pinctrl"; 131 reg = <0x2000000 0x800>; 132 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 143 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 144 clock-names = "apb", "hosc", "losc"; 145 gpio-controller; 146 #gpio-cells = <3>; 147 interrupt-controller; 148 #interrupt-cells = <3>; 149 150 /omit-if-no-ref/ 151 i2s2_pi_pins: i2s2-pi-pins { 152 pins = "PI2", "PI3", "PI4", "PI5"; 153 allwinner,pinmux = <5>; 154 function = "i2s2"; 155 bias-disable; 156 }; 157 158 /omit-if-no-ref/ 159 ledc_ph_pin: ledc-ph-pin { 160 pins = "PH19"; 161 function = "ledc"; 162 allwinner,pinmux = <5>; 163 }; 164 165 mmc0_pins: mmc0-pins { 166 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 167 allwinner,pinmux = <2>; 168 function = "mmc0"; 169 drive-strength = <30>; 170 bias-pull-up; 171 }; 172 173 /omit-if-no-ref/ 174 mmc1_pins: mmc1-pins { 175 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 176 allwinner,pinmux = <2>; 177 function = "mmc1"; 178 drive-strength = <30>; 179 bias-pull-up; 180 }; 181 182 mmc2_pins: mmc2-pins { 183 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 184 "PC9", "PC10", "PC11", "PC13", "PC14", 185 "PC15", "PC16"; 186 allwinner,pinmux = <3>; 187 function = "mmc2"; 188 drive-strength = <30>; 189 bias-pull-up; 190 }; 191 192 rgmii0_pins: rgmii0-pins { 193 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 194 "PH5", "PH6", "PH7", "PH9", "PH10", 195 "PH14", "PH15", "PH16", "PH17", "PH18"; 196 allwinner,pinmux = <5>; 197 function = "gmac0"; 198 drive-strength = <40>; 199 bias-disable; 200 }; 201 202 rgmii1_pins: rgmii1-pins { 203 pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", 204 "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", 205 "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; 206 allwinner,pinmux = <5>; 207 function = "gmac1"; 208 drive-strength = <40>; 209 bias-disable; 210 }; 211 212 /omit-if-no-ref/ 213 spdif_out_pb_pin: spdif-pb-pin { 214 pins = "PB8"; 215 function = "spdif"; 216 allwinner,pinmux = <2>; 217 }; 218 219 /omit-if-no-ref/ 220 spdif_out_pi_pin: spdif-pi-pin { 221 pins = "PI10"; 222 function = "spdif"; 223 allwinner,pinmux = <2>; 224 }; 225 226 /omit-if-no-ref/ 227 spi0_pc_pins: spi0-pc-pins { 228 pins = "PC2", "PC4", "PC12"; 229 function = "spi0"; 230 allwinner,pinmux = <4>; 231 }; 232 233 /omit-if-no-ref/ 234 spi0_pj_pins: spi0-pj-pins { 235 pins = "PJ21", "PJ22", "PJ23"; 236 function = "spi0"; 237 allwinner,pinmux = <5>; 238 }; 239 240 /omit-if-no-ref/ 241 spi0_cs0_pc_pin: spi0-cs0-pc-pin { 242 pins = "PC3"; 243 function = "spi0"; 244 allwinner,pinmux = <4>; 245 }; 246 247 /omit-if-no-ref/ 248 spi0_cs0_pj_pin: spi0-cs0-pj-pin { 249 pins = "PJ20"; 250 function = "spi0"; 251 allwinner,pinmux = <5>; 252 }; 253 254 /omit-if-no-ref/ 255 spi0_cs1_pc_pin: spi0-cs1-pc-pin { 256 pins = "PC7"; 257 function = "spi0"; 258 allwinner,pinmux = <4>; 259 }; 260 261 /omit-if-no-ref/ 262 spi0_cs1_pj_pin: spi0-cs1-pj-pin { 263 pins = "PJ24"; 264 function = "spi0"; 265 allwinner,pinmux = <5>; 266 }; 267 268 /omit-if-no-ref/ 269 spi0_hold_pc_pin: spi0-hold-pc-pin { 270 /* conflicts with eMMC D7 */ 271 pins = "PC16"; 272 function = "spi0"; 273 allwinner,pinmux = <4>; 274 }; 275 276 /omit-if-no-ref/ 277 spi0_hold_pj_pin: spi0-hold-pj-pin { 278 pins = "PJ26"; 279 function = "spi0"; 280 allwinner,pinmux = <5>; 281 }; 282 283 /omit-if-no-ref/ 284 spi0_wp_pc_pin: spi0-wp-pc-pin { 285 /* conflicts with eMMC D2 */ 286 pins = "PC15"; 287 function = "spi0"; 288 allwinner,pinmux = <4>; 289 }; 290 291 /omit-if-no-ref/ 292 spi0_wp_pj_pin: spi0-wp-pj-pin { 293 pins = "PJ25"; 294 function = "spi0"; 295 allwinner,pinmux = <5>; 296 }; 297 298 uart0_pb_pins: uart0-pb-pins { 299 pins = "PB9", "PB10"; 300 allwinner,pinmux = <2>; 301 function = "uart0"; 302 }; 303 304 /omit-if-no-ref/ 305 uart1_pins: uart1-pins { 306 pins = "PG6", "PG7"; 307 function = "uart1"; 308 allwinner,pinmux = <2>; 309 }; 310 311 /omit-if-no-ref/ 312 uart1_rts_cts_pins: uart1-rts-cts-pins { 313 pins = "PG8", "PG9"; 314 function = "uart1"; 315 allwinner,pinmux = <2>; 316 }; 317 }; 318 319 ccu: clock-controller@2001000 { 320 compatible = "allwinner,sun55i-a523-ccu"; 321 reg = <0x02001000 0x1000>; 322 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 323 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 324 clock-names = "hosc", "losc", 325 "iosc", "losc-fanout"; 326 #clock-cells = <1>; 327 #reset-cells = <1>; 328 }; 329 330 ledc: led-controller@2008000 { 331 compatible = "allwinner,sun55i-a523-ledc", 332 "allwinner,sun50i-a100-ledc"; 333 reg = <0x02008000 0x400>; 334 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 335 clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; 336 clock-names = "bus", "mod"; 337 resets = <&ccu RST_BUS_LEDC>; 338 dmas = <&dma 42>; 339 dma-names = "tx"; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 status = "disabled"; 343 }; 344 345 gpadc: adc@2009000 { 346 compatible = "allwinner,sun55i-a523-gpadc"; 347 reg = <0x2009000 0x400>; 348 clocks = <&ccu CLK_BUS_GPADC0>, <&ccu CLK_GPADC0>; 349 clock-names = "bus", "mod"; 350 resets = <&ccu RST_BUS_GPADC0>; 351 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 352 #io-channel-cells = <1>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 status = "disabled"; 356 }; 357 358 wdt: watchdog@2050000 { 359 compatible = "allwinner,sun55i-a523-wdt"; 360 reg = <0x2050000 0x20>; 361 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 363 clock-names = "hosc", "losc"; 364 status = "okay"; 365 }; 366 367 uart0: serial@2500000 { 368 compatible = "snps,dw-apb-uart"; 369 reg = <0x02500000 0x400>; 370 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 371 reg-shift = <2>; 372 reg-io-width = <4>; 373 clocks = <&ccu CLK_BUS_UART0>; 374 resets = <&ccu RST_BUS_UART0>; 375 dmas = <&dma 14>, <&dma 14>; 376 dma-names = "tx", "rx"; 377 status = "disabled"; 378 }; 379 380 uart1: serial@2500400 { 381 compatible = "snps,dw-apb-uart"; 382 reg = <0x02500400 0x400>; 383 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 384 reg-shift = <2>; 385 reg-io-width = <4>; 386 clocks = <&ccu CLK_BUS_UART1>; 387 resets = <&ccu RST_BUS_UART1>; 388 dmas = <&dma 15>, <&dma 15>; 389 dma-names = "tx", "rx"; 390 status = "disabled"; 391 }; 392 393 uart2: serial@2500800 { 394 compatible = "snps,dw-apb-uart"; 395 reg = <0x02500800 0x400>; 396 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 397 reg-shift = <2>; 398 reg-io-width = <4>; 399 clocks = <&ccu CLK_BUS_UART2>; 400 resets = <&ccu RST_BUS_UART2>; 401 dmas = <&dma 16>, <&dma 16>; 402 dma-names = "tx", "rx"; 403 status = "disabled"; 404 }; 405 406 uart3: serial@2500c00 { 407 compatible = "snps,dw-apb-uart"; 408 reg = <0x02500c00 0x400>; 409 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 410 reg-shift = <2>; 411 reg-io-width = <4>; 412 clocks = <&ccu CLK_BUS_UART3>; 413 resets = <&ccu RST_BUS_UART3>; 414 dmas = <&dma 17>, <&dma 17>; 415 dma-names = "tx", "rx"; 416 status = "disabled"; 417 }; 418 419 uart4: serial@2501000 { 420 compatible = "snps,dw-apb-uart"; 421 reg = <0x02501000 0x400>; 422 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 423 reg-shift = <2>; 424 reg-io-width = <4>; 425 clocks = <&ccu CLK_BUS_UART4>; 426 resets = <&ccu RST_BUS_UART4>; 427 dmas = <&dma 18>, <&dma 18>; 428 dma-names = "tx", "rx"; 429 status = "disabled"; 430 }; 431 432 uart5: serial@2501400 { 433 compatible = "snps,dw-apb-uart"; 434 reg = <0x02501400 0x400>; 435 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 436 reg-shift = <2>; 437 reg-io-width = <4>; 438 clocks = <&ccu CLK_BUS_UART5>; 439 resets = <&ccu RST_BUS_UART5>; 440 dmas = <&dma 19>, <&dma 19>; 441 dma-names = "tx", "rx"; 442 status = "disabled"; 443 }; 444 445 uart6: serial@2501800 { 446 compatible = "snps,dw-apb-uart"; 447 reg = <0x02501800 0x400>; 448 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 449 reg-shift = <2>; 450 reg-io-width = <4>; 451 clocks = <&ccu CLK_BUS_UART6>; 452 resets = <&ccu RST_BUS_UART6>; 453 dmas = <&dma 20>, <&dma 20>; 454 dma-names = "tx", "rx"; 455 status = "disabled"; 456 }; 457 458 uart7: serial@2501c00 { 459 compatible = "snps,dw-apb-uart"; 460 reg = <0x02501c00 0x400>; 461 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 462 reg-shift = <2>; 463 reg-io-width = <4>; 464 clocks = <&ccu CLK_BUS_UART7>; 465 resets = <&ccu RST_BUS_UART7>; 466 dmas = <&dma 21>, <&dma 21>; 467 dma-names = "tx", "rx"; 468 status = "disabled"; 469 }; 470 471 i2c0: i2c@2502000 { 472 compatible = "allwinner,sun55i-a523-i2c", 473 "allwinner,sun8i-v536-i2c", 474 "allwinner,sun6i-a31-i2c"; 475 reg = <0x2502000 0x400>; 476 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_I2C0>; 478 resets = <&ccu RST_BUS_I2C0>; 479 dmas = <&dma 43>, <&dma 43>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 }; 485 486 i2c1: i2c@2502400 { 487 compatible = "allwinner,sun55i-a523-i2c", 488 "allwinner,sun8i-v536-i2c", 489 "allwinner,sun6i-a31-i2c"; 490 reg = <0x2502400 0x400>; 491 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_I2C1>; 493 resets = <&ccu RST_BUS_I2C1>; 494 dmas = <&dma 44>, <&dma 44>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 }; 500 501 i2c2: i2c@2502800 { 502 compatible = "allwinner,sun55i-a523-i2c", 503 "allwinner,sun8i-v536-i2c", 504 "allwinner,sun6i-a31-i2c"; 505 reg = <0x2502800 0x400>; 506 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_I2C2>; 508 resets = <&ccu RST_BUS_I2C2>; 509 dmas = <&dma 45>, <&dma 45>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 }; 515 516 i2c3: i2c@2502c00 { 517 compatible = "allwinner,sun55i-a523-i2c", 518 "allwinner,sun8i-v536-i2c", 519 "allwinner,sun6i-a31-i2c"; 520 reg = <0x2502c00 0x400>; 521 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&ccu CLK_BUS_I2C3>; 523 resets = <&ccu RST_BUS_I2C3>; 524 dmas = <&dma 46>, <&dma 46>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 }; 530 531 i2c4: i2c@2503000 { 532 compatible = "allwinner,sun55i-a523-i2c", 533 "allwinner,sun8i-v536-i2c", 534 "allwinner,sun6i-a31-i2c"; 535 reg = <0x2503000 0x400>; 536 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&ccu CLK_BUS_I2C4>; 538 resets = <&ccu RST_BUS_I2C4>; 539 dmas = <&dma 47>, <&dma 47>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 }; 545 546 i2c5: i2c@2503400 { 547 compatible = "allwinner,sun55i-a523-i2c", 548 "allwinner,sun8i-v536-i2c", 549 "allwinner,sun6i-a31-i2c"; 550 reg = <0x2503400 0x400>; 551 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&ccu CLK_BUS_I2C5>; 553 resets = <&ccu RST_BUS_I2C5>; 554 dmas = <&dma 48>, <&dma 48>; 555 dma-names = "rx", "tx"; 556 status = "disabled"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 }; 560 561 syscon: syscon@3000000 { 562 compatible = "allwinner,sun55i-a523-system-control", 563 "allwinner,sun50i-a64-system-control"; 564 reg = <0x03000000 0x1000>; 565 #address-cells = <1>; 566 #size-cells = <1>; 567 ranges; 568 }; 569 570 dma: dma-controller@3002000 { 571 compatible = "allwinner,sun55i-a523-dma", 572 "allwinner,sun50i-a100-dma"; 573 reg = <0x03002000 0x1000>; 574 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 576 clock-names = "bus", "mbus"; 577 dma-channels = <16>; 578 dma-requests = <54>; 579 resets = <&ccu RST_BUS_DMA>; 580 #dma-cells = <1>; 581 }; 582 583 sid: efuse@3006000 { 584 compatible = "allwinner,sun55i-a523-sid", 585 "allwinner,sun50i-a64-sid"; 586 reg = <0x03006000 0x1000>; 587 #address-cells = <1>; 588 #size-cells = <1>; 589 }; 590 591 gic: interrupt-controller@3400000 { 592 compatible = "arm,gic-v3"; 593 #address-cells = <1>; 594 #interrupt-cells = <3>; 595 #size-cells = <1>; 596 ranges; 597 interrupt-controller; 598 reg = <0x3400000 0x10000>, 599 <0x3460000 0x100000>; 600 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 601 dma-noncoherent; 602 603 its: msi-controller@3440000 { 604 compatible = "arm,gic-v3-its"; 605 reg = <0x3440000 0x20000>; 606 msi-controller; 607 #msi-cells = <1>; 608 dma-noncoherent; 609 }; 610 }; 611 612 mmc0: mmc@4020000 { 613 compatible = "allwinner,sun55i-a523-mmc", 614 "allwinner,sun20i-d1-mmc"; 615 reg = <0x04020000 0x1000>; 616 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 617 clock-names = "ahb", "mmc"; 618 resets = <&ccu RST_BUS_MMC0>; 619 reset-names = "ahb"; 620 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 621 pinctrl-names = "default"; 622 pinctrl-0 = <&mmc0_pins>; 623 status = "disabled"; 624 625 max-frequency = <150000000>; 626 cap-sd-highspeed; 627 cap-mmc-highspeed; 628 cap-sdio-irq; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 }; 632 633 mmc1: mmc@4021000 { 634 compatible = "allwinner,sun55i-a523-mmc", 635 "allwinner,sun20i-d1-mmc"; 636 reg = <0x04021000 0x1000>; 637 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 638 clock-names = "ahb", "mmc"; 639 resets = <&ccu RST_BUS_MMC1>; 640 reset-names = "ahb"; 641 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&mmc1_pins>; 644 status = "disabled"; 645 646 max-frequency = <150000000>; 647 cap-sd-highspeed; 648 cap-mmc-highspeed; 649 cap-sdio-irq; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 }; 653 654 mmc2: mmc@4022000 { 655 compatible = "allwinner,sun55i-a523-mmc", 656 "allwinner,sun20i-d1-mmc"; 657 reg = <0x04022000 0x1000>; 658 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 659 clock-names = "ahb", "mmc"; 660 resets = <&ccu RST_BUS_MMC2>; 661 reset-names = "ahb"; 662 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&mmc2_pins>; 665 status = "disabled"; 666 667 max-frequency = <150000000>; 668 cap-sd-highspeed; 669 cap-mmc-highspeed; 670 cap-sdio-irq; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 }; 674 675 spi0: spi@4025000 { 676 compatible = "allwinner,sun55i-a523-spi"; 677 reg = <0x04025000 0x1000>; 678 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 680 clock-names = "ahb", "mod"; 681 dmas = <&dma 22>, <&dma 22>; 682 dma-names = "rx", "tx"; 683 resets = <&ccu RST_BUS_SPI0>; 684 status = "disabled"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 }; 688 689 spi1: spi@4026000 { 690 compatible = "allwinner,sun55i-a523-spi-dbi", 691 "allwinner,sun55i-a523-spi"; 692 reg = <0x04026000 0x1000>; 693 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 694 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 695 clock-names = "ahb", "mod"; 696 dmas = <&dma 23>, <&dma 23>; 697 dma-names = "rx", "tx"; 698 resets = <&ccu RST_BUS_SPI1>; 699 status = "disabled"; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 }; 703 704 spi2: spi@4027000 { 705 compatible = "allwinner,sun55i-a523-spi"; 706 reg = <0x04027000 0x1000>; 707 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 709 clock-names = "ahb", "mod"; 710 dmas = <&dma 24>, <&dma 24>; 711 dma-names = "rx", "tx"; 712 resets = <&ccu RST_BUS_SPI2>; 713 status = "disabled"; 714 #address-cells = <1>; 715 #size-cells = <0>; 716 }; 717 718 usb_otg: usb@4100000 { 719 compatible = "allwinner,sun55i-a523-musb", 720 "allwinner,sun8i-a33-musb"; 721 reg = <0x4100000 0x400>; 722 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-names = "mc"; 724 clocks = <&ccu CLK_BUS_OTG>; 725 resets = <&ccu RST_BUS_OTG>; 726 extcon = <&usbphy 0>; 727 phys = <&usbphy 0>; 728 phy-names = "usb"; 729 status = "disabled"; 730 }; 731 732 usbphy: phy@4100400 { 733 compatible = "allwinner,sun55i-a523-usb-phy", 734 "allwinner,sun20i-d1-usb-phy"; 735 reg = <0x4100400 0x100>, 736 <0x4101800 0x100>, 737 <0x4200800 0x100>; 738 reg-names = "phy_ctrl", 739 "pmu0", 740 "pmu1"; 741 clocks = <&osc24M>, 742 <&osc24M>; 743 clock-names = "usb0_phy", 744 "usb1_phy"; 745 resets = <&ccu RST_USB_PHY0>, 746 <&ccu RST_USB_PHY1>; 747 reset-names = "usb0_reset", 748 "usb1_reset"; 749 status = "disabled"; 750 #phy-cells = <1>; 751 }; 752 753 ehci0: usb@4101000 { 754 compatible = "allwinner,sun55i-a523-ehci", 755 "generic-ehci"; 756 reg = <0x4101000 0x100>; 757 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&ccu CLK_BUS_OHCI0>, 759 <&ccu CLK_BUS_EHCI0>, 760 <&ccu CLK_USB_OHCI0>; 761 resets = <&ccu RST_BUS_OHCI0>, 762 <&ccu RST_BUS_EHCI0>; 763 phys = <&usbphy 0>; 764 phy-names = "usb"; 765 status = "disabled"; 766 }; 767 768 ohci0: usb@4101400 { 769 compatible = "allwinner,sun55i-a523-ohci", 770 "generic-ohci"; 771 reg = <0x4101400 0x100>; 772 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&ccu CLK_BUS_OHCI0>, 774 <&ccu CLK_USB_OHCI0>; 775 resets = <&ccu RST_BUS_OHCI0>; 776 phys = <&usbphy 0>; 777 phy-names = "usb"; 778 status = "disabled"; 779 }; 780 781 ehci1: usb@4200000 { 782 compatible = "allwinner,sun55i-a523-ehci", 783 "generic-ehci"; 784 reg = <0x4200000 0x100>; 785 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_OHCI1>, 787 <&ccu CLK_BUS_EHCI1>, 788 <&ccu CLK_USB_OHCI1>; 789 resets = <&ccu RST_BUS_OHCI1>, 790 <&ccu RST_BUS_EHCI1>; 791 phys = <&usbphy 1>; 792 phy-names = "usb"; 793 status = "disabled"; 794 }; 795 796 ohci1: usb@4200400 { 797 compatible = "allwinner,sun55i-a523-ohci", 798 "generic-ohci"; 799 reg = <0x4200400 0x100>; 800 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 801 clocks = <&ccu CLK_BUS_OHCI1>, 802 <&ccu CLK_USB_OHCI1>; 803 resets = <&ccu RST_BUS_OHCI1>; 804 phys = <&usbphy 1>; 805 phy-names = "usb"; 806 status = "disabled"; 807 }; 808 809 gmac0: ethernet@4500000 { 810 compatible = "allwinner,sun55i-a523-gmac0", 811 "allwinner,sun50i-a64-emac"; 812 reg = <0x04500000 0x10000>; 813 clocks = <&ccu CLK_BUS_EMAC0>; 814 clock-names = "stmmaceth"; 815 resets = <&ccu RST_BUS_EMAC0>; 816 reset-names = "stmmaceth"; 817 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 818 interrupt-names = "macirq"; 819 pinctrl-names = "default"; 820 pinctrl-0 = <&rgmii0_pins>; 821 syscon = <&syscon>; 822 status = "disabled"; 823 824 mdio0: mdio { 825 compatible = "snps,dwmac-mdio"; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 }; 829 }; 830 831 gmac1: ethernet@4510000 { 832 compatible = "allwinner,sun55i-a523-gmac200", 833 "snps,dwmac-4.20a"; 834 reg = <0x04510000 0x10000>; 835 clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; 836 clock-names = "stmmaceth", "mbus"; 837 resets = <&ccu RST_BUS_EMAC1>; 838 reset-names = "stmmaceth"; 839 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "macirq"; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&rgmii1_pins>; 843 power-domains = <&pck600 PD_VO1>; 844 syscon = <&syscon>; 845 snps,fixed-burst; 846 snps,axi-config = <&gmac1_stmmac_axi_setup>; 847 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 848 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 849 status = "disabled"; 850 851 mdio1: mdio { 852 compatible = "snps,dwmac-mdio"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 }; 856 857 gmac1_mtl_rx_setup: rx-queues-config { 858 snps,rx-queues-to-use = <1>; 859 860 queue0 {}; 861 }; 862 863 gmac1_stmmac_axi_setup: stmmac-axi-config { 864 snps,wr_osr_lmt = <0xf>; 865 snps,rd_osr_lmt = <0xf>; 866 snps,blen = <256 128 64 32 16 8 4>; 867 }; 868 869 gmac1_mtl_tx_setup: tx-queues-config { 870 snps,tx-queues-to-use = <1>; 871 872 queue0 {}; 873 }; 874 }; 875 876 ppu: power-controller@7001400 { 877 compatible = "allwinner,sun55i-a523-ppu"; 878 reg = <0x07001400 0x400>; 879 clocks = <&r_ccu CLK_BUS_R_PPU1>; 880 resets = <&r_ccu RST_BUS_R_PPU1>; 881 #power-domain-cells = <1>; 882 }; 883 884 r_ccu: clock-controller@7010000 { 885 compatible = "allwinner,sun55i-a523-r-ccu"; 886 reg = <0x7010000 0x250>; 887 clocks = <&osc24M>, 888 <&rtc CLK_OSC32K>, 889 <&rtc CLK_IOSC>, 890 <&ccu CLK_PLL_PERIPH0_200M>, 891 <&ccu CLK_PLL_AUDIO0_4X>; 892 clock-names = "hosc", 893 "losc", 894 "iosc", 895 "pll-periph", 896 "pll-audio"; 897 #clock-cells = <1>; 898 #reset-cells = <1>; 899 assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; 900 assigned-clock-rates = <200000000>, <100000000>; 901 }; 902 903 nmi_intc: interrupt-controller@7010320 { 904 compatible = "allwinner,sun55i-a523-nmi"; 905 reg = <0x07010320 0xc>; 906 interrupt-controller; 907 #interrupt-cells = <2>; 908 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 909 }; 910 911 r_pio: pinctrl@7022000 { 912 compatible = "allwinner,sun55i-a523-r-pinctrl"; 913 reg = <0x7022000 0x800>; 914 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 916 clocks = <&r_ccu CLK_R_APB0>, 917 <&osc24M>, 918 <&rtc CLK_OSC32K>; 919 clock-names = "apb", "hosc", "losc"; 920 gpio-controller; 921 #gpio-cells = <3>; 922 interrupt-controller; 923 #interrupt-cells = <3>; 924 925 r_i2c_pins: r-i2c-pins { 926 pins = "PL0" ,"PL1"; 927 allwinner,pinmux = <2>; 928 function = "r_i2c0"; 929 }; 930 }; 931 932 pck600: power-controller@7060000 { 933 compatible = "allwinner,sun55i-a523-pck-600"; 934 reg = <0x07060000 0x8000>; 935 clocks = <&r_ccu CLK_BUS_R_PPU0>; 936 resets = <&r_ccu RST_BUS_R_PPU0>; 937 #power-domain-cells = <1>; 938 }; 939 940 r_i2c0: i2c@7081400 { 941 compatible = "allwinner,sun55i-a523-i2c", 942 "allwinner,sun8i-v536-i2c", 943 "allwinner,sun6i-a31-i2c"; 944 reg = <0x07081400 0x400>; 945 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 946 clocks = <&r_ccu CLK_BUS_R_I2C0>; 947 dmas = <&dma 49>, <&dma 49>; 948 dma-names = "rx", "tx"; 949 resets = <&r_ccu RST_BUS_R_I2C0>; 950 pinctrl-names = "default"; 951 pinctrl-0 = <&r_i2c_pins>; 952 status = "disabled"; 953 954 #address-cells = <1>; 955 #size-cells = <0>; 956 }; 957 958 rtc: rtc@7090000 { 959 compatible = "allwinner,sun55i-a523-rtc", 960 "allwinner,sun50i-r329-rtc"; 961 reg = <0x7090000 0x400>; 962 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&r_ccu CLK_BUS_R_RTC>, 964 <&osc24M>, 965 <&r_ccu CLK_R_AHB>; 966 clock-names = "bus", "hosc", "ahb"; 967 #clock-cells = <1>; 968 }; 969 970 r_spi0: spi@7092000 { 971 compatible = "allwinner,sun55i-a523-spi"; 972 reg = <0x07092000 0x1000>; 973 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 974 clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>; 975 clock-names = "ahb", "mod"; 976 dmas = <&mcu_dma 13>, <&mcu_dma 13>; 977 dma-names = "rx", "tx"; 978 resets = <&r_ccu RST_BUS_R_SPI>; 979 status = "disabled"; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 }; 983 984 mcu_ccu: clock-controller@7102000 { 985 compatible = "allwinner,sun55i-a523-mcu-ccu"; 986 reg = <0x7102000 0x200>; 987 clocks = <&osc24M>, 988 <&rtc CLK_OSC32K>, 989 <&rtc CLK_IOSC>, 990 <&ccu CLK_PLL_AUDIO0_4X>, 991 <&ccu CLK_PLL_PERIPH0_300M>, 992 <&ccu CLK_DSP>, 993 <&ccu CLK_MBUS>, 994 <&r_ccu CLK_R_AHB>, 995 <&r_ccu CLK_R_APB0>; 996 clock-names = "hosc", 997 "losc", 998 "iosc", 999 "pll-audio0-4x", 1000 "pll-periph0-300m", 1001 "dsp", 1002 "mbus", 1003 "r-ahb", 1004 "r-apb0"; 1005 #clock-cells = <1>; 1006 #reset-cells = <1>; 1007 }; 1008 1009 i2s0: i2s@7112000 { 1010 compatible = "allwinner,sun55i-a523-i2s", 1011 "allwinner,sun50i-r329-i2s"; 1012 reg = <0x07112000 0x1000>; 1013 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&mcu_ccu CLK_BUS_MCU_I2S0>, <&mcu_ccu CLK_MCU_I2S0>; 1015 clock-names = "apb", "mod"; 1016 resets = <&mcu_ccu RST_BUS_MCU_I2S0>; 1017 dmas = <&mcu_dma 3>, <&mcu_dma 3>; 1018 dma-names = "rx", "tx"; 1019 #sound-dai-cells = <0>; 1020 status = "disabled"; 1021 }; 1022 1023 i2s1: i2s@7113000 { 1024 compatible = "allwinner,sun55i-a523-i2s", 1025 "allwinner,sun50i-r329-i2s"; 1026 reg = <0x07113000 0x1000>; 1027 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1028 clocks = <&mcu_ccu CLK_BUS_MCU_I2S1>, <&mcu_ccu CLK_MCU_I2S1>; 1029 clock-names = "apb", "mod"; 1030 resets = <&mcu_ccu RST_BUS_MCU_I2S1>; 1031 dmas = <&mcu_dma 4>, <&mcu_dma 4>; 1032 dma-names = "rx", "tx"; 1033 #sound-dai-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 i2s2: i2s@7114000 { 1038 compatible = "allwinner,sun55i-a523-i2s", 1039 "allwinner,sun50i-r329-i2s"; 1040 reg = <0x07114000 0x1000>; 1041 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&mcu_ccu CLK_BUS_MCU_I2S2>, <&mcu_ccu CLK_MCU_I2S2>; 1043 clock-names = "apb", "mod"; 1044 resets = <&mcu_ccu RST_BUS_MCU_I2S2>; 1045 dmas = <&mcu_dma 5>, <&mcu_dma 5>; 1046 dma-names = "rx", "tx"; 1047 #sound-dai-cells = <0>; 1048 status = "disabled"; 1049 }; 1050 1051 i2s3: i2s@7115000 { 1052 compatible = "allwinner,sun55i-a523-i2s", 1053 "allwinner,sun50i-r329-i2s"; 1054 reg = <0x07115000 0x1000>; 1055 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1056 clocks = <&mcu_ccu CLK_BUS_MCU_I2S3>, <&mcu_ccu CLK_MCU_I2S3>; 1057 clock-names = "apb", "mod"; 1058 resets = <&mcu_ccu RST_BUS_MCU_I2S3>; 1059 dmas = <&mcu_dma 6>, <&mcu_dma 6>; 1060 dma-names = "rx", "tx"; 1061 #sound-dai-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 spdif: spdif@7116000 { 1066 compatible = "allwinner,sun55i-a523-spdif"; 1067 reg = <0x07116000 0x400>; 1068 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&mcu_ccu CLK_BUS_MCU_SPDIF>, 1070 <&mcu_ccu CLK_MCU_SPDIF_TX>, 1071 <&mcu_ccu CLK_MCU_SPDIF_RX>; 1072 clock-names = "apb", "tx", "rx"; 1073 resets = <&mcu_ccu RST_BUS_MCU_SPDIF>; 1074 dmas = <&mcu_dma 2>, <&mcu_dma 2>; 1075 dma-names = "rx", "tx"; 1076 #sound-dai-cells = <0>; 1077 status = "disabled"; 1078 }; 1079 1080 mcu_dma: dma-controller@7121000 { 1081 compatible = "allwinner,sun55i-a523-mcu-dma", 1082 "allwinner,sun50i-a100-dma"; 1083 reg = <0x07121000 0x1000>; 1084 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&mcu_ccu CLK_BUS_MCU_DMA>, <&mcu_ccu CLK_MCU_MBUS_DMA>; 1086 clock-names = "bus", "mbus"; 1087 dma-channels = <16>; 1088 dma-requests = <15>; 1089 resets = <&mcu_ccu RST_BUS_MCU_DMA>; 1090 #dma-cells = <1>; 1091 }; 1092 1093 npu: npu@7122000 { 1094 compatible = "vivante,gc"; 1095 reg = <0x07122000 0x1000>; 1096 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, 1098 <&ccu CLK_NPU>, 1099 <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; 1100 clock-names = "bus", "core", "reg"; 1101 resets = <&mcu_ccu RST_BUS_MCU_NPU>; 1102 power-domains = <&ppu PD_NPU>; 1103 }; 1104 }; 1105}; 1106