1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2// Copyright (C) 2023-2024 Arm Ltd. 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun6i-rtc.h> 6#include <dt-bindings/clock/sun55i-a523-ccu.h> 7#include <dt-bindings/clock/sun55i-a523-mcu-ccu.h> 8#include <dt-bindings/clock/sun55i-a523-r-ccu.h> 9#include <dt-bindings/reset/sun55i-a523-ccu.h> 10#include <dt-bindings/reset/sun55i-a523-mcu-ccu.h> 11#include <dt-bindings/reset/sun55i-a523-r-ccu.h> 12#include <dt-bindings/power/allwinner,sun55i-a523-ppu.h> 13#include <dt-bindings/power/allwinner,sun55i-a523-pck-600.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a55"; 26 device_type = "cpu"; 27 reg = <0x000>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@100 { 32 compatible = "arm,cortex-a55"; 33 device_type = "cpu"; 34 reg = <0x100>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@200 { 39 compatible = "arm,cortex-a55"; 40 device_type = "cpu"; 41 reg = <0x200>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@300 { 46 compatible = "arm,cortex-a55"; 47 device_type = "cpu"; 48 reg = <0x300>; 49 enable-method = "psci"; 50 }; 51 52 cpu4: cpu@400 { 53 compatible = "arm,cortex-a55"; 54 device_type = "cpu"; 55 reg = <0x400>; 56 enable-method = "psci"; 57 }; 58 59 cpu5: cpu@500 { 60 compatible = "arm,cortex-a55"; 61 device_type = "cpu"; 62 reg = <0x500>; 63 enable-method = "psci"; 64 }; 65 66 cpu6: cpu@600 { 67 compatible = "arm,cortex-a55"; 68 device_type = "cpu"; 69 reg = <0x600>; 70 enable-method = "psci"; 71 }; 72 73 cpu7: cpu@700 { 74 compatible = "arm,cortex-a55"; 75 device_type = "cpu"; 76 reg = <0x700>; 77 enable-method = "psci"; 78 }; 79 }; 80 81 osc24M: osc24M-clk { 82 #clock-cells = <0>; 83 compatible = "fixed-clock"; 84 clock-frequency = <24000000>; 85 clock-output-names = "osc24M"; 86 }; 87 88 pmu { 89 compatible = "arm,cortex-a55-pmu"; 90 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 91 }; 92 93 psci { 94 compatible = "arm,psci-0.2"; 95 method = "smc"; 96 }; 97 98 timer { 99 compatible = "arm,armv8-timer"; 100 arm,no-tick-in-suspend; 101 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 102 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 103 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 104 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x0 0x0 0x40000000>; 112 113 gpu: gpu@1800000 { 114 compatible = "allwinner,sun55i-a523-mali", 115 "arm,mali-valhall-jm"; 116 reg = <0x1800000 0x10000>; 117 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 120 interrupt-names = "job", "mmu", "gpu"; 121 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 122 clock-names = "core", "bus"; 123 power-domains = <&pck600 PD_GPU>; 124 resets = <&ccu RST_BUS_GPU>; 125 status = "disabled"; 126 }; 127 128 pio: pinctrl@2000000 { 129 compatible = "allwinner,sun55i-a523-pinctrl"; 130 reg = <0x2000000 0x800>; 131 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 142 clock-names = "apb", "hosc", "losc"; 143 gpio-controller; 144 #gpio-cells = <3>; 145 interrupt-controller; 146 #interrupt-cells = <3>; 147 148 /omit-if-no-ref/ 149 i2s2_pi_pins: i2s2-pi-pins { 150 pins = "PI2", "PI3", "PI4", "PI5"; 151 allwinner,pinmux = <5>; 152 function = "i2s2"; 153 bias-disable; 154 }; 155 156 /omit-if-no-ref/ 157 ledc_ph_pin: ledc-ph-pin { 158 pins = "PH19"; 159 function = "ledc"; 160 allwinner,pinmux = <5>; 161 }; 162 163 mmc0_pins: mmc0-pins { 164 pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; 165 allwinner,pinmux = <2>; 166 function = "mmc0"; 167 drive-strength = <30>; 168 bias-pull-up; 169 }; 170 171 /omit-if-no-ref/ 172 mmc1_pins: mmc1-pins { 173 pins = "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; 174 allwinner,pinmux = <2>; 175 function = "mmc1"; 176 drive-strength = <30>; 177 bias-pull-up; 178 }; 179 180 mmc2_pins: mmc2-pins { 181 pins = "PC0", "PC1" ,"PC5", "PC6", "PC8", 182 "PC9", "PC10", "PC11", "PC13", "PC14", 183 "PC15", "PC16"; 184 allwinner,pinmux = <3>; 185 function = "mmc2"; 186 drive-strength = <30>; 187 bias-pull-up; 188 }; 189 190 rgmii0_pins: rgmii0-pins { 191 pins = "PH0", "PH1", "PH2", "PH3", "PH4", 192 "PH5", "PH6", "PH7", "PH9", "PH10", 193 "PH14", "PH15", "PH16", "PH17", "PH18"; 194 allwinner,pinmux = <5>; 195 function = "gmac0"; 196 drive-strength = <40>; 197 bias-disable; 198 }; 199 200 rgmii1_pins: rgmii1-pins { 201 pins = "PJ0", "PJ1", "PJ2", "PJ3", "PJ4", 202 "PJ5", "PJ6", "PJ7", "PJ8", "PJ9", 203 "PJ11", "PJ12", "PJ13", "PJ14", "PJ15"; 204 allwinner,pinmux = <5>; 205 function = "gmac1"; 206 drive-strength = <40>; 207 bias-disable; 208 }; 209 210 /omit-if-no-ref/ 211 spdif_out_pb_pin: spdif-pb-pin { 212 pins = "PB8"; 213 function = "spdif"; 214 allwinner,pinmux = <2>; 215 }; 216 217 /omit-if-no-ref/ 218 spdif_out_pi_pin: spdif-pi-pin { 219 pins = "PI10"; 220 function = "spdif"; 221 allwinner,pinmux = <2>; 222 }; 223 224 /omit-if-no-ref/ 225 spi0_pc_pins: spi0-pc-pins { 226 pins = "PC2", "PC4", "PC12"; 227 function = "spi0"; 228 allwinner,pinmux = <4>; 229 }; 230 231 /omit-if-no-ref/ 232 spi0_pj_pins: spi0-pj-pins { 233 pins = "PJ21", "PJ22", "PJ23"; 234 function = "spi0"; 235 allwinner,pinmux = <5>; 236 }; 237 238 /omit-if-no-ref/ 239 spi0_cs0_pc_pin: spi0-cs0-pc-pin { 240 pins = "PC3"; 241 function = "spi0"; 242 allwinner,pinmux = <4>; 243 }; 244 245 /omit-if-no-ref/ 246 spi0_cs0_pj_pin: spi0-cs0-pj-pin { 247 pins = "PJ20"; 248 function = "spi0"; 249 allwinner,pinmux = <5>; 250 }; 251 252 /omit-if-no-ref/ 253 spi0_cs1_pc_pin: spi0-cs1-pc-pin { 254 pins = "PC7"; 255 function = "spi0"; 256 allwinner,pinmux = <4>; 257 }; 258 259 /omit-if-no-ref/ 260 spi0_cs1_pj_pin: spi0-cs1-pj-pin { 261 pins = "PJ24"; 262 function = "spi0"; 263 allwinner,pinmux = <5>; 264 }; 265 266 /omit-if-no-ref/ 267 spi0_hold_pc_pin: spi0-hold-pc-pin { 268 /* conflicts with eMMC D7 */ 269 pins = "PC16"; 270 function = "spi0"; 271 allwinner,pinmux = <4>; 272 }; 273 274 /omit-if-no-ref/ 275 spi0_hold_pj_pin: spi0-hold-pj-pin { 276 pins = "PJ26"; 277 function = "spi0"; 278 allwinner,pinmux = <5>; 279 }; 280 281 /omit-if-no-ref/ 282 spi0_wp_pc_pin: spi0-wp-pc-pin { 283 /* conflicts with eMMC D2 */ 284 pins = "PC15"; 285 function = "spi0"; 286 allwinner,pinmux = <4>; 287 }; 288 289 /omit-if-no-ref/ 290 spi0_wp_pj_pin: spi0-wp-pj-pin { 291 pins = "PJ25"; 292 function = "spi0"; 293 allwinner,pinmux = <5>; 294 }; 295 296 uart0_pb_pins: uart0-pb-pins { 297 pins = "PB9", "PB10"; 298 allwinner,pinmux = <2>; 299 function = "uart0"; 300 }; 301 302 /omit-if-no-ref/ 303 uart1_pins: uart1-pins { 304 pins = "PG6", "PG7"; 305 function = "uart1"; 306 allwinner,pinmux = <2>; 307 }; 308 309 /omit-if-no-ref/ 310 uart1_rts_cts_pins: uart1-rts-cts-pins { 311 pins = "PG8", "PG9"; 312 function = "uart1"; 313 allwinner,pinmux = <2>; 314 }; 315 }; 316 317 ccu: clock-controller@2001000 { 318 compatible = "allwinner,sun55i-a523-ccu"; 319 reg = <0x02001000 0x1000>; 320 clocks = <&osc24M>, <&rtc CLK_OSC32K>, 321 <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; 322 clock-names = "hosc", "losc", 323 "iosc", "losc-fanout"; 324 #clock-cells = <1>; 325 #reset-cells = <1>; 326 }; 327 328 ledc: led-controller@2008000 { 329 compatible = "allwinner,sun55i-a523-ledc", 330 "allwinner,sun50i-a100-ledc"; 331 reg = <0x02008000 0x400>; 332 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 333 clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; 334 clock-names = "bus", "mod"; 335 resets = <&ccu RST_BUS_LEDC>; 336 dmas = <&dma 42>; 337 dma-names = "tx"; 338 #address-cells = <1>; 339 #size-cells = <0>; 340 status = "disabled"; 341 }; 342 343 wdt: watchdog@2050000 { 344 compatible = "allwinner,sun55i-a523-wdt"; 345 reg = <0x2050000 0x20>; 346 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&osc24M>, <&rtc CLK_OSC32K>; 348 clock-names = "hosc", "losc"; 349 status = "okay"; 350 }; 351 352 uart0: serial@2500000 { 353 compatible = "snps,dw-apb-uart"; 354 reg = <0x02500000 0x400>; 355 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 356 reg-shift = <2>; 357 reg-io-width = <4>; 358 clocks = <&ccu CLK_BUS_UART0>; 359 resets = <&ccu RST_BUS_UART0>; 360 dmas = <&dma 14>, <&dma 14>; 361 dma-names = "tx", "rx"; 362 status = "disabled"; 363 }; 364 365 uart1: serial@2500400 { 366 compatible = "snps,dw-apb-uart"; 367 reg = <0x02500400 0x400>; 368 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 369 reg-shift = <2>; 370 reg-io-width = <4>; 371 clocks = <&ccu CLK_BUS_UART1>; 372 resets = <&ccu RST_BUS_UART1>; 373 dmas = <&dma 15>, <&dma 15>; 374 dma-names = "tx", "rx"; 375 status = "disabled"; 376 }; 377 378 uart2: serial@2500800 { 379 compatible = "snps,dw-apb-uart"; 380 reg = <0x02500800 0x400>; 381 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 382 reg-shift = <2>; 383 reg-io-width = <4>; 384 clocks = <&ccu CLK_BUS_UART2>; 385 resets = <&ccu RST_BUS_UART2>; 386 dmas = <&dma 16>, <&dma 16>; 387 dma-names = "tx", "rx"; 388 status = "disabled"; 389 }; 390 391 uart3: serial@2500c00 { 392 compatible = "snps,dw-apb-uart"; 393 reg = <0x02500c00 0x400>; 394 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 395 reg-shift = <2>; 396 reg-io-width = <4>; 397 clocks = <&ccu CLK_BUS_UART3>; 398 resets = <&ccu RST_BUS_UART3>; 399 dmas = <&dma 17>, <&dma 17>; 400 dma-names = "tx", "rx"; 401 status = "disabled"; 402 }; 403 404 uart4: serial@2501000 { 405 compatible = "snps,dw-apb-uart"; 406 reg = <0x02501000 0x400>; 407 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 408 reg-shift = <2>; 409 reg-io-width = <4>; 410 clocks = <&ccu CLK_BUS_UART4>; 411 resets = <&ccu RST_BUS_UART4>; 412 dmas = <&dma 18>, <&dma 18>; 413 dma-names = "tx", "rx"; 414 status = "disabled"; 415 }; 416 417 uart5: serial@2501400 { 418 compatible = "snps,dw-apb-uart"; 419 reg = <0x02501400 0x400>; 420 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 421 reg-shift = <2>; 422 reg-io-width = <4>; 423 clocks = <&ccu CLK_BUS_UART5>; 424 resets = <&ccu RST_BUS_UART5>; 425 dmas = <&dma 19>, <&dma 19>; 426 dma-names = "tx", "rx"; 427 status = "disabled"; 428 }; 429 430 uart6: serial@2501800 { 431 compatible = "snps,dw-apb-uart"; 432 reg = <0x02501800 0x400>; 433 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 434 reg-shift = <2>; 435 reg-io-width = <4>; 436 clocks = <&ccu CLK_BUS_UART6>; 437 resets = <&ccu RST_BUS_UART6>; 438 dmas = <&dma 20>, <&dma 20>; 439 dma-names = "tx", "rx"; 440 status = "disabled"; 441 }; 442 443 uart7: serial@2501c00 { 444 compatible = "snps,dw-apb-uart"; 445 reg = <0x02501c00 0x400>; 446 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 clocks = <&ccu CLK_BUS_UART7>; 450 resets = <&ccu RST_BUS_UART7>; 451 dmas = <&dma 21>, <&dma 21>; 452 dma-names = "tx", "rx"; 453 status = "disabled"; 454 }; 455 456 i2c0: i2c@2502000 { 457 compatible = "allwinner,sun55i-a523-i2c", 458 "allwinner,sun8i-v536-i2c", 459 "allwinner,sun6i-a31-i2c"; 460 reg = <0x2502000 0x400>; 461 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&ccu CLK_BUS_I2C0>; 463 resets = <&ccu RST_BUS_I2C0>; 464 dmas = <&dma 43>, <&dma 43>; 465 dma-names = "rx", "tx"; 466 status = "disabled"; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 }; 470 471 i2c1: i2c@2502400 { 472 compatible = "allwinner,sun55i-a523-i2c", 473 "allwinner,sun8i-v536-i2c", 474 "allwinner,sun6i-a31-i2c"; 475 reg = <0x2502400 0x400>; 476 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&ccu CLK_BUS_I2C1>; 478 resets = <&ccu RST_BUS_I2C1>; 479 dmas = <&dma 44>, <&dma 44>; 480 dma-names = "rx", "tx"; 481 status = "disabled"; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 }; 485 486 i2c2: i2c@2502800 { 487 compatible = "allwinner,sun55i-a523-i2c", 488 "allwinner,sun8i-v536-i2c", 489 "allwinner,sun6i-a31-i2c"; 490 reg = <0x2502800 0x400>; 491 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 492 clocks = <&ccu CLK_BUS_I2C2>; 493 resets = <&ccu RST_BUS_I2C2>; 494 dmas = <&dma 45>, <&dma 45>; 495 dma-names = "rx", "tx"; 496 status = "disabled"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 }; 500 501 i2c3: i2c@2502c00 { 502 compatible = "allwinner,sun55i-a523-i2c", 503 "allwinner,sun8i-v536-i2c", 504 "allwinner,sun6i-a31-i2c"; 505 reg = <0x2502c00 0x400>; 506 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_I2C3>; 508 resets = <&ccu RST_BUS_I2C3>; 509 dmas = <&dma 46>, <&dma 46>; 510 dma-names = "rx", "tx"; 511 status = "disabled"; 512 #address-cells = <1>; 513 #size-cells = <0>; 514 }; 515 516 i2c4: i2c@2503000 { 517 compatible = "allwinner,sun55i-a523-i2c", 518 "allwinner,sun8i-v536-i2c", 519 "allwinner,sun6i-a31-i2c"; 520 reg = <0x2503000 0x400>; 521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&ccu CLK_BUS_I2C4>; 523 resets = <&ccu RST_BUS_I2C4>; 524 dmas = <&dma 47>, <&dma 47>; 525 dma-names = "rx", "tx"; 526 status = "disabled"; 527 #address-cells = <1>; 528 #size-cells = <0>; 529 }; 530 531 i2c5: i2c@2503400 { 532 compatible = "allwinner,sun55i-a523-i2c", 533 "allwinner,sun8i-v536-i2c", 534 "allwinner,sun6i-a31-i2c"; 535 reg = <0x2503400 0x400>; 536 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 537 clocks = <&ccu CLK_BUS_I2C5>; 538 resets = <&ccu RST_BUS_I2C5>; 539 dmas = <&dma 48>, <&dma 48>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 }; 545 546 syscon: syscon@3000000 { 547 compatible = "allwinner,sun55i-a523-system-control", 548 "allwinner,sun50i-a64-system-control"; 549 reg = <0x03000000 0x1000>; 550 #address-cells = <1>; 551 #size-cells = <1>; 552 ranges; 553 }; 554 555 dma: dma-controller@3002000 { 556 compatible = "allwinner,sun55i-a523-dma", 557 "allwinner,sun50i-a100-dma"; 558 reg = <0x03002000 0x1000>; 559 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 560 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 561 clock-names = "bus", "mbus"; 562 dma-channels = <16>; 563 dma-requests = <54>; 564 resets = <&ccu RST_BUS_DMA>; 565 #dma-cells = <1>; 566 }; 567 568 sid: efuse@3006000 { 569 compatible = "allwinner,sun55i-a523-sid", 570 "allwinner,sun50i-a64-sid"; 571 reg = <0x03006000 0x1000>; 572 #address-cells = <1>; 573 #size-cells = <1>; 574 }; 575 576 gic: interrupt-controller@3400000 { 577 compatible = "arm,gic-v3"; 578 #address-cells = <1>; 579 #interrupt-cells = <3>; 580 #size-cells = <1>; 581 ranges; 582 interrupt-controller; 583 reg = <0x3400000 0x10000>, 584 <0x3460000 0x100000>; 585 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 586 dma-noncoherent; 587 588 its: msi-controller@3440000 { 589 compatible = "arm,gic-v3-its"; 590 reg = <0x3440000 0x20000>; 591 msi-controller; 592 #msi-cells = <1>; 593 dma-noncoherent; 594 }; 595 }; 596 597 mmc0: mmc@4020000 { 598 compatible = "allwinner,sun55i-a523-mmc", 599 "allwinner,sun20i-d1-mmc"; 600 reg = <0x04020000 0x1000>; 601 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 602 clock-names = "ahb", "mmc"; 603 resets = <&ccu RST_BUS_MMC0>; 604 reset-names = "ahb"; 605 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 606 pinctrl-names = "default"; 607 pinctrl-0 = <&mmc0_pins>; 608 status = "disabled"; 609 610 max-frequency = <150000000>; 611 cap-sd-highspeed; 612 cap-mmc-highspeed; 613 cap-sdio-irq; 614 #address-cells = <1>; 615 #size-cells = <0>; 616 }; 617 618 mmc1: mmc@4021000 { 619 compatible = "allwinner,sun55i-a523-mmc", 620 "allwinner,sun20i-d1-mmc"; 621 reg = <0x04021000 0x1000>; 622 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 623 clock-names = "ahb", "mmc"; 624 resets = <&ccu RST_BUS_MMC1>; 625 reset-names = "ahb"; 626 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&mmc1_pins>; 629 status = "disabled"; 630 631 max-frequency = <150000000>; 632 cap-sd-highspeed; 633 cap-mmc-highspeed; 634 cap-sdio-irq; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 }; 638 639 mmc2: mmc@4022000 { 640 compatible = "allwinner,sun55i-a523-mmc", 641 "allwinner,sun20i-d1-mmc"; 642 reg = <0x04022000 0x1000>; 643 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 644 clock-names = "ahb", "mmc"; 645 resets = <&ccu RST_BUS_MMC2>; 646 reset-names = "ahb"; 647 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&mmc2_pins>; 650 status = "disabled"; 651 652 max-frequency = <150000000>; 653 cap-sd-highspeed; 654 cap-mmc-highspeed; 655 cap-sdio-irq; 656 #address-cells = <1>; 657 #size-cells = <0>; 658 }; 659 660 spi0: spi@4025000 { 661 compatible = "allwinner,sun55i-a523-spi"; 662 reg = <0x04025000 0x1000>; 663 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 665 clock-names = "ahb", "mod"; 666 dmas = <&dma 22>, <&dma 22>; 667 dma-names = "rx", "tx"; 668 resets = <&ccu RST_BUS_SPI0>; 669 status = "disabled"; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 }; 673 674 spi1: spi@4026000 { 675 compatible = "allwinner,sun55i-a523-spi-dbi", 676 "allwinner,sun55i-a523-spi"; 677 reg = <0x04026000 0x1000>; 678 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 680 clock-names = "ahb", "mod"; 681 dmas = <&dma 23>, <&dma 23>; 682 dma-names = "rx", "tx"; 683 resets = <&ccu RST_BUS_SPI1>; 684 status = "disabled"; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 }; 688 689 spi2: spi@4027000 { 690 compatible = "allwinner,sun55i-a523-spi"; 691 reg = <0x04027000 0x1000>; 692 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 693 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 694 clock-names = "ahb", "mod"; 695 dmas = <&dma 24>, <&dma 24>; 696 dma-names = "rx", "tx"; 697 resets = <&ccu RST_BUS_SPI2>; 698 status = "disabled"; 699 #address-cells = <1>; 700 #size-cells = <0>; 701 }; 702 703 usb_otg: usb@4100000 { 704 compatible = "allwinner,sun55i-a523-musb", 705 "allwinner,sun8i-a33-musb"; 706 reg = <0x4100000 0x400>; 707 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 708 interrupt-names = "mc"; 709 clocks = <&ccu CLK_BUS_OTG>; 710 resets = <&ccu RST_BUS_OTG>; 711 extcon = <&usbphy 0>; 712 phys = <&usbphy 0>; 713 phy-names = "usb"; 714 status = "disabled"; 715 }; 716 717 usbphy: phy@4100400 { 718 compatible = "allwinner,sun55i-a523-usb-phy", 719 "allwinner,sun20i-d1-usb-phy"; 720 reg = <0x4100400 0x100>, 721 <0x4101800 0x100>, 722 <0x4200800 0x100>; 723 reg-names = "phy_ctrl", 724 "pmu0", 725 "pmu1"; 726 clocks = <&osc24M>, 727 <&osc24M>; 728 clock-names = "usb0_phy", 729 "usb1_phy"; 730 resets = <&ccu RST_USB_PHY0>, 731 <&ccu RST_USB_PHY1>; 732 reset-names = "usb0_reset", 733 "usb1_reset"; 734 status = "disabled"; 735 #phy-cells = <1>; 736 }; 737 738 ehci0: usb@4101000 { 739 compatible = "allwinner,sun55i-a523-ehci", 740 "generic-ehci"; 741 reg = <0x4101000 0x100>; 742 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&ccu CLK_BUS_OHCI0>, 744 <&ccu CLK_BUS_EHCI0>, 745 <&ccu CLK_USB_OHCI0>; 746 resets = <&ccu RST_BUS_OHCI0>, 747 <&ccu RST_BUS_EHCI0>; 748 phys = <&usbphy 0>; 749 phy-names = "usb"; 750 status = "disabled"; 751 }; 752 753 ohci0: usb@4101400 { 754 compatible = "allwinner,sun55i-a523-ohci", 755 "generic-ohci"; 756 reg = <0x4101400 0x100>; 757 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 758 clocks = <&ccu CLK_BUS_OHCI0>, 759 <&ccu CLK_USB_OHCI0>; 760 resets = <&ccu RST_BUS_OHCI0>; 761 phys = <&usbphy 0>; 762 phy-names = "usb"; 763 status = "disabled"; 764 }; 765 766 ehci1: usb@4200000 { 767 compatible = "allwinner,sun55i-a523-ehci", 768 "generic-ehci"; 769 reg = <0x4200000 0x100>; 770 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&ccu CLK_BUS_OHCI1>, 772 <&ccu CLK_BUS_EHCI1>, 773 <&ccu CLK_USB_OHCI1>; 774 resets = <&ccu RST_BUS_OHCI1>, 775 <&ccu RST_BUS_EHCI1>; 776 phys = <&usbphy 1>; 777 phy-names = "usb"; 778 status = "disabled"; 779 }; 780 781 ohci1: usb@4200400 { 782 compatible = "allwinner,sun55i-a523-ohci", 783 "generic-ohci"; 784 reg = <0x4200400 0x100>; 785 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_OHCI1>, 787 <&ccu CLK_USB_OHCI1>; 788 resets = <&ccu RST_BUS_OHCI1>; 789 phys = <&usbphy 1>; 790 phy-names = "usb"; 791 status = "disabled"; 792 }; 793 794 gmac0: ethernet@4500000 { 795 compatible = "allwinner,sun55i-a523-gmac0", 796 "allwinner,sun50i-a64-emac"; 797 reg = <0x04500000 0x10000>; 798 clocks = <&ccu CLK_BUS_EMAC0>; 799 clock-names = "stmmaceth"; 800 resets = <&ccu RST_BUS_EMAC0>; 801 reset-names = "stmmaceth"; 802 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 803 interrupt-names = "macirq"; 804 pinctrl-names = "default"; 805 pinctrl-0 = <&rgmii0_pins>; 806 syscon = <&syscon>; 807 status = "disabled"; 808 809 mdio0: mdio { 810 compatible = "snps,dwmac-mdio"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 }; 814 }; 815 816 gmac1: ethernet@4510000 { 817 compatible = "allwinner,sun55i-a523-gmac200", 818 "snps,dwmac-4.20a"; 819 reg = <0x04510000 0x10000>; 820 clocks = <&ccu CLK_BUS_EMAC1>, <&ccu CLK_MBUS_EMAC1>; 821 clock-names = "stmmaceth", "mbus"; 822 resets = <&ccu RST_BUS_EMAC1>; 823 reset-names = "stmmaceth"; 824 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 825 interrupt-names = "macirq"; 826 pinctrl-names = "default"; 827 pinctrl-0 = <&rgmii1_pins>; 828 power-domains = <&pck600 PD_VO1>; 829 syscon = <&syscon>; 830 snps,fixed-burst; 831 snps,axi-config = <&gmac1_stmmac_axi_setup>; 832 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 833 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 834 status = "disabled"; 835 836 mdio1: mdio { 837 compatible = "snps,dwmac-mdio"; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 }; 841 842 gmac1_mtl_rx_setup: rx-queues-config { 843 snps,rx-queues-to-use = <1>; 844 845 queue0 {}; 846 }; 847 848 gmac1_stmmac_axi_setup: stmmac-axi-config { 849 snps,wr_osr_lmt = <0xf>; 850 snps,rd_osr_lmt = <0xf>; 851 snps,blen = <256 128 64 32 16 8 4>; 852 }; 853 854 gmac1_mtl_tx_setup: tx-queues-config { 855 snps,tx-queues-to-use = <1>; 856 857 queue0 {}; 858 }; 859 }; 860 861 ppu: power-controller@7001400 { 862 compatible = "allwinner,sun55i-a523-ppu"; 863 reg = <0x07001400 0x400>; 864 clocks = <&r_ccu CLK_BUS_R_PPU1>; 865 resets = <&r_ccu RST_BUS_R_PPU1>; 866 #power-domain-cells = <1>; 867 }; 868 869 r_ccu: clock-controller@7010000 { 870 compatible = "allwinner,sun55i-a523-r-ccu"; 871 reg = <0x7010000 0x250>; 872 clocks = <&osc24M>, 873 <&rtc CLK_OSC32K>, 874 <&rtc CLK_IOSC>, 875 <&ccu CLK_PLL_PERIPH0_200M>, 876 <&ccu CLK_PLL_AUDIO0_4X>; 877 clock-names = "hosc", 878 "losc", 879 "iosc", 880 "pll-periph", 881 "pll-audio"; 882 #clock-cells = <1>; 883 #reset-cells = <1>; 884 assigned-clocks = <&r_ccu CLK_R_AHB>, <&r_ccu CLK_R_APB0>; 885 assigned-clock-rates = <200000000>, <100000000>; 886 }; 887 888 nmi_intc: interrupt-controller@7010320 { 889 compatible = "allwinner,sun55i-a523-nmi"; 890 reg = <0x07010320 0xc>; 891 interrupt-controller; 892 #interrupt-cells = <2>; 893 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 894 }; 895 896 r_pio: pinctrl@7022000 { 897 compatible = "allwinner,sun55i-a523-r-pinctrl"; 898 reg = <0x7022000 0x800>; 899 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&r_ccu CLK_R_APB0>, 902 <&osc24M>, 903 <&rtc CLK_OSC32K>; 904 clock-names = "apb", "hosc", "losc"; 905 gpio-controller; 906 #gpio-cells = <3>; 907 interrupt-controller; 908 #interrupt-cells = <3>; 909 910 r_i2c_pins: r-i2c-pins { 911 pins = "PL0" ,"PL1"; 912 allwinner,pinmux = <2>; 913 function = "r_i2c0"; 914 }; 915 }; 916 917 pck600: power-controller@7060000 { 918 compatible = "allwinner,sun55i-a523-pck-600"; 919 reg = <0x07060000 0x8000>; 920 clocks = <&r_ccu CLK_BUS_R_PPU0>; 921 resets = <&r_ccu RST_BUS_R_PPU0>; 922 #power-domain-cells = <1>; 923 }; 924 925 r_i2c0: i2c@7081400 { 926 compatible = "allwinner,sun55i-a523-i2c", 927 "allwinner,sun8i-v536-i2c", 928 "allwinner,sun6i-a31-i2c"; 929 reg = <0x07081400 0x400>; 930 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&r_ccu CLK_BUS_R_I2C0>; 932 dmas = <&dma 49>, <&dma 49>; 933 dma-names = "rx", "tx"; 934 resets = <&r_ccu RST_BUS_R_I2C0>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&r_i2c_pins>; 937 status = "disabled"; 938 939 #address-cells = <1>; 940 #size-cells = <0>; 941 }; 942 943 rtc: rtc@7090000 { 944 compatible = "allwinner,sun55i-a523-rtc", 945 "allwinner,sun50i-r329-rtc"; 946 reg = <0x7090000 0x400>; 947 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&r_ccu CLK_BUS_R_RTC>, 949 <&osc24M>, 950 <&r_ccu CLK_R_AHB>; 951 clock-names = "bus", "hosc", "ahb"; 952 #clock-cells = <1>; 953 }; 954 955 r_spi0: spi@7092000 { 956 compatible = "allwinner,sun55i-a523-spi"; 957 reg = <0x07092000 0x1000>; 958 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>; 960 clock-names = "ahb", "mod"; 961 dmas = <&mcu_dma 13>, <&mcu_dma 13>; 962 dma-names = "rx", "tx"; 963 resets = <&r_ccu RST_BUS_R_SPI>; 964 status = "disabled"; 965 #address-cells = <1>; 966 #size-cells = <0>; 967 }; 968 969 mcu_ccu: clock-controller@7102000 { 970 compatible = "allwinner,sun55i-a523-mcu-ccu"; 971 reg = <0x7102000 0x200>; 972 clocks = <&osc24M>, 973 <&rtc CLK_OSC32K>, 974 <&rtc CLK_IOSC>, 975 <&ccu CLK_PLL_AUDIO0_4X>, 976 <&ccu CLK_PLL_PERIPH0_300M>, 977 <&ccu CLK_DSP>, 978 <&ccu CLK_MBUS>, 979 <&r_ccu CLK_R_AHB>, 980 <&r_ccu CLK_R_APB0>; 981 clock-names = "hosc", 982 "losc", 983 "iosc", 984 "pll-audio0-4x", 985 "pll-periph0-300m", 986 "dsp", 987 "mbus", 988 "r-ahb", 989 "r-apb0"; 990 #clock-cells = <1>; 991 #reset-cells = <1>; 992 }; 993 994 i2s0: i2s@7112000 { 995 compatible = "allwinner,sun55i-a523-i2s", 996 "allwinner,sun50i-r329-i2s"; 997 reg = <0x07112000 0x1000>; 998 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&mcu_ccu CLK_BUS_MCU_I2S0>, <&mcu_ccu CLK_MCU_I2S0>; 1000 clock-names = "apb", "mod"; 1001 resets = <&mcu_ccu RST_BUS_MCU_I2S0>; 1002 dmas = <&mcu_dma 3>, <&mcu_dma 3>; 1003 dma-names = "rx", "tx"; 1004 #sound-dai-cells = <0>; 1005 status = "disabled"; 1006 }; 1007 1008 i2s1: i2s@7113000 { 1009 compatible = "allwinner,sun55i-a523-i2s", 1010 "allwinner,sun50i-r329-i2s"; 1011 reg = <0x07113000 0x1000>; 1012 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&mcu_ccu CLK_BUS_MCU_I2S1>, <&mcu_ccu CLK_MCU_I2S1>; 1014 clock-names = "apb", "mod"; 1015 resets = <&mcu_ccu RST_BUS_MCU_I2S1>; 1016 dmas = <&mcu_dma 4>, <&mcu_dma 4>; 1017 dma-names = "rx", "tx"; 1018 #sound-dai-cells = <0>; 1019 status = "disabled"; 1020 }; 1021 1022 i2s2: i2s@7114000 { 1023 compatible = "allwinner,sun55i-a523-i2s", 1024 "allwinner,sun50i-r329-i2s"; 1025 reg = <0x07114000 0x1000>; 1026 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&mcu_ccu CLK_BUS_MCU_I2S2>, <&mcu_ccu CLK_MCU_I2S2>; 1028 clock-names = "apb", "mod"; 1029 resets = <&mcu_ccu RST_BUS_MCU_I2S2>; 1030 dmas = <&mcu_dma 5>, <&mcu_dma 5>; 1031 dma-names = "rx", "tx"; 1032 #sound-dai-cells = <0>; 1033 status = "disabled"; 1034 }; 1035 1036 i2s3: i2s@7115000 { 1037 compatible = "allwinner,sun55i-a523-i2s", 1038 "allwinner,sun50i-r329-i2s"; 1039 reg = <0x07115000 0x1000>; 1040 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 1041 clocks = <&mcu_ccu CLK_BUS_MCU_I2S3>, <&mcu_ccu CLK_MCU_I2S3>; 1042 clock-names = "apb", "mod"; 1043 resets = <&mcu_ccu RST_BUS_MCU_I2S3>; 1044 dmas = <&mcu_dma 6>, <&mcu_dma 6>; 1045 dma-names = "rx", "tx"; 1046 #sound-dai-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 spdif: spdif@7116000 { 1051 compatible = "allwinner,sun55i-a523-spdif"; 1052 reg = <0x07116000 0x400>; 1053 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&mcu_ccu CLK_BUS_MCU_SPDIF>, 1055 <&mcu_ccu CLK_MCU_SPDIF_TX>, 1056 <&mcu_ccu CLK_MCU_SPDIF_RX>; 1057 clock-names = "apb", "tx", "rx"; 1058 resets = <&mcu_ccu RST_BUS_MCU_SPDIF>; 1059 dmas = <&mcu_dma 2>, <&mcu_dma 2>; 1060 dma-names = "rx", "tx"; 1061 #sound-dai-cells = <0>; 1062 status = "disabled"; 1063 }; 1064 1065 mcu_dma: dma-controller@7121000 { 1066 compatible = "allwinner,sun55i-a523-mcu-dma", 1067 "allwinner,sun50i-a100-dma"; 1068 reg = <0x07121000 0x1000>; 1069 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&mcu_ccu CLK_BUS_MCU_DMA>, <&mcu_ccu CLK_MCU_MBUS_DMA>; 1071 clock-names = "bus", "mbus"; 1072 dma-channels = <16>; 1073 dma-requests = <15>; 1074 resets = <&mcu_ccu RST_BUS_MCU_DMA>; 1075 #dma-cells = <1>; 1076 }; 1077 1078 npu: npu@7122000 { 1079 compatible = "vivante,gc"; 1080 reg = <0x07122000 0x1000>; 1081 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&mcu_ccu CLK_BUS_MCU_NPU_ACLK>, 1083 <&ccu CLK_NPU>, 1084 <&mcu_ccu CLK_BUS_MCU_NPU_HCLK>; 1085 clock-names = "bus", "core", "reg"; 1086 resets = <&mcu_ccu RST_BUS_MCU_NPU>; 1087 power-domains = <&ppu PD_NPU>; 1088 }; 1089 }; 1090}; 1091