1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #include "dm_services.h" 6 #include "dm_helpers.h" 7 #include "dc.h" 8 9 #include "dcn32/dcn32_init.h" 10 #include "dcn401/dcn401_init.h" 11 #include "dcn60/dcn60_init.h" 12 13 #include "resource.h" 14 #include "include/irq_service_interface.h" 15 #include "basics/conversion.h" 16 17 #include "dcn20/dcn20_resource.h" 18 #include "dcn30/dcn30_resource.h" 19 #include "dcn32/dcn32_resource.h" 20 #include "dcn321/dcn321_resource.h" 21 #include "dcn401/dcn401_resource.h" 22 #include "dcn42/dcn42_resource.h" 23 #include "dcn60/dcn60_rmcm.h" 24 #include "dcn60_resource.h" 25 26 #include "dcn10/dcn10_ipp.h" 27 #include "dcn60/dcn60_hubbub.h" 28 #include "dcn60/dcn60_mpc.h" 29 #include "dcn60/dcn60_hubp.h" 30 #include "irq/dcn60/irq_service_dcn60.h" 31 #include "dcn60/dcn60_dpp.h" 32 #include "dcn60/dcn60_optc.h" 33 #include "dcn20/dcn20_hwseq.h" 34 #include "dcn30/dcn30_hwseq.h" 35 #include "dcn10/dcn10_hwseq.h" 36 #include "dcn60/dcn60_opp.h" 37 #include "dcn60/dcn60_dsc.h" 38 #include "dcn30/dcn30_vpg.h" 39 #include "dcn31/dcn31_vpg.h" 40 #include "dcn30/dcn30_dio_stream_encoder.h" 41 #include "dcn401/dcn401_dio_stream_encoder.h" 42 #include "dcn60/dcn60_dio_stream_encoder.h" 43 #include "dcn401/dcn401_hpo_frl_stream_encoder.h" 44 #include "dcn30/dcn30_hpo_frl_link_encoder.h" 45 #include "dcn60/dcn60_hpo_frl_link_encoder.h" 46 #include "dcn60/dcn60_hpo_frl_stream_encoder.h" 47 #include "dcn31/dcn31_hpo_dp_stream_encoder.h" 48 #include "dcn31/dcn31_hpo_dp_link_encoder.h" 49 #include "dcn32/dcn32_hpo_dp_link_encoder.h" 50 #include "dcn31/dcn31_dio_link_encoder.h" 51 #include "dcn401/dcn401_dio_link_encoder.h" 52 #include "dcn60/dcn60_dio_link_encoder.h" 53 #include "dcn10/dcn10_link_encoder.h" 54 #include "dcn321/dcn321_dio_link_encoder.h" 55 #include "dce/dce_clock_source.h" 56 #include "dce/dce_audio.h" 57 #include "dce/dce_hwseq.h" 58 #include "clk_mgr.h" 59 #include "dio/virtual/virtual_stream_encoder.h" 60 #include "dml/display_mode_vba.h" 61 #include "dcn60/dcn60_dccg.h" 62 #include "dcn10/dcn10_resource.h" 63 #include "link_service.h" 64 #include "link_enc_cfg.h" 65 #include "dcn31/dcn31_panel_cntl.h" 66 67 #include "dcn30/dcn30_dwb.h" 68 #include "dcn32/dcn32_mmhubbub.h" 69 70 #include "dcn/dcn_6_0_0_offset.h" 71 #include "dcn/dcn_6_0_0_sh_mask.h" 72 #include "dpcs/dpcs_6_0_0_offset.h" 73 #include "dpcs/dpcs_6_0_0_sh_mask.h" 74 75 #include "reg_helper.h" 76 #include "dce/dmub_abm.h" 77 #include "dce/dmub_psr.h" 78 #include "dce/dce_aux.h" 79 #include "dce/dce_i2c.h" 80 81 #include "dml/dcn30/display_mode_vba_30.h" 82 #include "vm_helper.h" 83 #include "dcn20/dcn20_vmid.h" 84 85 #include "dc_state_priv.h" 86 87 #include "dml2_wrapper/dml2_wrapper.h" 88 #include "dml2_wrapper/dml21_wrapper/dml21_wrapper.h" 89 90 #define LSDMA_CONTENTION_BUFFER_SIZE (64 * 1024 * 1024) 91 92 #define DC_LOGGER_INIT(logger) 93 94 /* begin ********************* 95 * macros to expend register list macro defined in HW object header file 96 */ 97 98 enum dcn60_clk_src_array_id { 99 DCN60_CLK_SRC_PLL0, 100 DCN60_CLK_SRC_PLL1, 101 DCN60_CLK_SRC_PLL2, 102 DCN60_CLK_SRC_PLL3, 103 //DCN60_CLK_SRC_PLL4, 104 DCN60_CLK_SRC_TOTAL 105 }; 106 107 static const uint32_t MCACHE_ID_UNASSIGNED = 0xF; 108 static const uint32_t SPLIT_LOCATION_UNDEFINED = 0xFFFF; 109 110 /* DCN */ 111 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg] 112 113 #define BASE(seg) BASE_INNER(seg) 114 115 #define SR(reg_name)\ 116 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 117 reg ## reg_name 118 #define SR_ARR(reg_name, id)\ 119 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 120 reg ## reg_name 121 #define SR_ARR_INIT(reg_name, id, value)\ 122 REG_STRUCT[id].reg_name = value 123 124 #define SRI(reg_name, block, id)\ 125 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 126 reg ## block ## id ## _ ## reg_name 127 128 #define SRI_ARR(reg_name, block, id)\ 129 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 130 reg ## block ## id ## _ ## reg_name 131 132 #define SRI_ARR_DDC(reg_name, block, id)\ 133 REG_STRUCT[id-1].reg_name = BASE(reg ## reg_name ## id ## _ ## block ## _BASE_IDX) + \ 134 reg ## reg_name ## id ## _ ## block 135 136 /* 137 * Used when a reg_name would otherwise begin with an integer 138 */ 139 #define SRI_ARR_US(reg_name, block, id)\ 140 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \ 141 reg ## block ## id ## reg_name 142 #define SR_ARR_I2C(reg_name, id) \ 143 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name 144 145 #define SRI_ARR_I2C(reg_name, block, id)\ 146 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 147 reg ## block ## id ## _ ## reg_name 148 149 #define SRI_ARR_DME(reg_name, block, id, offset)\ 150 REG_STRUCT[id - offset].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 151 reg ## block ## id ## _ ## reg_name 152 153 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\ 154 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 155 reg ## block ## id ## _ ## reg_name 156 157 #define SRI2(reg_name, block, id)\ 158 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 159 reg ## reg_name 160 #define SRI2_ARR(reg_name, block, id)\ 161 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \ 162 reg ## reg_name 163 164 #define SRIR(var_name, reg_name, block, id)\ 165 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 166 reg ## block ## id ## _ ## reg_name 167 168 #define SRII(reg_name, block, id)\ 169 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 170 reg ## block ## id ## _ ## reg_name 171 172 #define SRII_ARR_2(reg_name, block, id, inst)\ 173 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 174 reg ## block ## id ## _ ## reg_name 175 176 #define SRII_MPC_RMU(reg_name, block, id)\ 177 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 178 reg ## block ## id ## _ ## reg_name 179 180 #define SRII_DWB(reg_name, temp_name, block, id)\ 181 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \ 182 reg ## block ## id ## _ ## temp_name 183 184 #define DCCG_SRII(reg_name, block, id)\ 185 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 186 reg ## block ## id ## _ ## reg_name 187 188 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \ 189 .field_name = reg_name ## __ ## field_name ## post_fix 190 191 #define VUPDATE_SRII(reg_name, block, id)\ 192 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \ 193 reg ## reg_name ## _ ## block ## id 194 195 /* bringup_nbif_7_10_0_offset registers */ 196 #define regBIF_BX0_BIOS_SCRATCH_3 0x003b 197 #define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX 1 198 #define regBIF_BX0_BIOS_SCRATCH_6 0x003e 199 #define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX 1 200 201 /* NBIO */ 202 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg] 203 204 #define NBIO_BASE(seg) \ 205 NBIO_BASE_INNER(seg) 206 207 #define NBIO_SR(reg_name)\ 208 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 209 regBIF_BX0_ ## reg_name 210 #define NBIO_SR_ARR(reg_name, id)\ 211 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \ 212 regBIF_BX0_ ## reg_name 213 214 #define CTX ctx 215 #define REG(reg_name) \ 216 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name) 217 218 static struct bios_registers bios_regs; 219 220 #define bios_regs_init() \ 221 NBIO_SR(BIOS_SCRATCH_3),\ 222 NBIO_SR(BIOS_SCRATCH_6) 223 224 #define clk_src_regs_init(index, pllid)\ 225 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid) 226 227 static struct dce110_clk_src_regs clk_src_regs[5]; 228 229 static const struct dce110_clk_src_shift cs_shift = { 230 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT) 231 }; 232 233 static const struct dce110_clk_src_mask cs_mask = { 234 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK) 235 }; 236 237 #define abm_regs_init(id)\ 238 ABM_DCN42_REG_LIST_RI(id) 239 240 static struct dce_abm_registers abm_regs[4]; 241 242 static const struct dce_abm_shift abm_shift = { 243 ABM_MASK_SH_LIST_DCN42(__SHIFT) 244 }; 245 246 static const struct dce_abm_mask abm_mask = { 247 ABM_MASK_SH_LIST_DCN42(_MASK) 248 }; 249 250 #define audio_regs_init(id)\ 251 AUD_COMMON_REG_LIST_RI(id) 252 253 static struct dce_audio_registers audio_regs[5]; 254 255 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\ 256 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\ 257 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\ 258 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\ 259 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\ 260 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\ 261 SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\ 262 SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\ 263 SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\ 264 SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\ 265 SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\ 266 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\ 267 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\ 268 SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh) 269 270 static const struct dce_audio_shift audio_shift = { 271 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) 272 }; 273 274 static const struct dce_audio_mask audio_mask = { 275 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) 276 }; 277 278 #define vpg_regs_init(id)\ 279 VPG_DCN401_REG_LIST_RI(id) 280 281 static struct dcn31_vpg_registers vpg_regs[9]; 282 283 static const struct dcn31_vpg_shift vpg_shift = { 284 DCN31_VPG_MASK_SH_LIST(__SHIFT) 285 }; 286 287 static const struct dcn31_vpg_mask vpg_mask = { 288 DCN31_VPG_MASK_SH_LIST(_MASK) 289 }; 290 291 #define apg_regs_init(id)\ 292 APG_DCN31_REG_LIST_RI(id) 293 294 static struct dcn31_apg_registers apg_regs[5]; 295 296 static const struct dcn31_apg_shift apg_shift = { 297 DCN31_APG_MASK_SH_LIST(__SHIFT) 298 }; 299 300 static const struct dcn31_apg_mask apg_mask = { 301 DCN31_APG_MASK_SH_LIST(_MASK) 302 }; 303 304 #define stream_enc_regs_init(id)\ 305 SE_REG_LIST_DCN60_RI(id) 306 307 static struct dcn10_stream_enc_registers stream_enc_regs[4]; 308 309 static const struct dcn10_stream_encoder_shift se_shift = { 310 SE_COMMON_MASK_SH_LIST_DCN60(__SHIFT) 311 }; 312 313 static const struct dcn10_stream_encoder_mask se_mask = { 314 SE_COMMON_MASK_SH_LIST_DCN60(_MASK) 315 }; 316 317 #define aux_regs_init(id, ddc_id)\ 318 DCN60_AUX_REG_LIST_RI(id, ddc_id) 319 320 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5]; 321 322 #define hpd_regs_init(id)\ 323 HPD_REG_LIST_DCN60_RI(id) 324 325 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5]; 326 327 #define link_regs_init(id, phyid)\ 328 LE_DCN401_REG_LIST_RI(id), \ 329 LE_DCN60_REG_LIST_RI(id) 330 331 static struct dcn10_link_enc_registers link_enc_regs[4]; 332 333 static const struct dcn10_link_enc_shift le_shift = { 334 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT), \ 335 LINK_ENCODER_MASK_SH_LIST_DCN60(__SHIFT) 336 }; 337 338 static const struct dcn10_link_enc_mask le_mask = { 339 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK), \ 340 LINK_ENCODER_MASK_SH_LIST_DCN60(_MASK) 341 }; 342 343 #define hpo_frl_stream_encoder_reg_list(id)\ 344 DCN60_HPO_FRL_STREAM_ENC_REG_LIST_RI(id) 345 346 #define hpo_frl_stream_encoder_dme_reg_list(id)\ 347 DCN3_0_HPO_STREAM_ENC_DME_REG_LIST_RI(id, 4) 348 349 static struct dcn30_hpo_frl_stream_enc_registers hpo_frl_stream_enc_regs[2]; 350 351 static const struct dcn401_hpo_frl_stream_encoder_shift hpo_se_shift = { 352 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(__SHIFT), 353 DCN60_HDMI_STREAM_ENC_MASK_SH_LIST(__SHIFT) 354 }; 355 356 static const struct dcn401_hpo_frl_stream_encoder_mask hpo_se_mask = { 357 DCN401_HPO_STREAM_ENC_MASK_SH_LIST(_MASK), 358 DCN60_HDMI_STREAM_ENC_MASK_SH_LIST(_MASK) 359 }; 360 361 #define hpo_frl_link_encoder_reg_list(id)\ 362 DCN3_0_HPO_FRL_LINK_ENC_REG_LIST_RI(id) 363 364 static struct dcn30_hpo_frl_link_encoder_registers hpo_frl_link_enc_regs[1]; 365 366 static const struct dcn30_hpo_frl_link_encoder_shift hpo_le_shift = { 367 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(__SHIFT) 368 }; 369 370 static const struct dcn30_hpo_frl_link_encoder_mask hpo_le_mask = { 371 DCN3_0_HPO_FRL_LINK_ENC_MASK_SH_LIST(_MASK) 372 }; 373 374 #define hpo_dp_stream_encoder_reg_init(id)\ 375 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id) 376 377 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4]; 378 379 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = { 380 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT) 381 }; 382 383 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = { 384 DCN4_2_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK) 385 }; 386 387 #define hpo_dp_link_encoder_reg_init(id)\ 388 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id) 389 /*DCN3_1_RDPCSTX_REG_LIST(0),*/ 390 /*DCN3_1_RDPCSTX_REG_LIST(1),*/ 391 /*DCN3_1_RDPCSTX_REG_LIST(2),*/ 392 /*DCN3_1_RDPCSTX_REG_LIST(3),*/ 393 394 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4]; 395 396 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = { 397 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT) 398 }; 399 400 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = { 401 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK) 402 }; 403 404 #define dpp_regs_init(id)\ 405 DPP_REG_LIST_DCN60_RI(id) 406 407 static struct dcn60_dpp_registers dpp_regs[4]; 408 409 static const struct dcn60_dpp_shift tf_shift = { 410 DPP_REG_LIST_SH_MASK_DCN60(__SHIFT) 411 }; 412 413 static const struct dcn60_dpp_mask tf_mask = { 414 DPP_REG_LIST_SH_MASK_DCN60(_MASK) 415 }; 416 417 #define opp_regs_init(id)\ 418 OPP_REG_LIST_DCN401_RI(id) 419 420 static struct dcn60_opp_registers opp_regs[4]; 421 422 static const struct dcn60_opp_shift opp_shift = { 423 OPP_MASK_SH_LIST_DCN60(__SHIFT) 424 }; 425 426 static const struct dcn60_opp_mask opp_mask = { 427 OPP_MASK_SH_LIST_DCN60(_MASK) 428 }; 429 430 #define aux_engine_regs_init(id) \ 431 AUX_COMMON_REG_LIST0_RI(id), \ 432 SR_ARR_INIT(AUXN_IMPCAL, id, 0), \ 433 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \ 434 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK) 435 436 static struct dce110_aux_registers aux_engine_regs[4]; 437 438 static const struct dce110_aux_registers_shift aux_shift = { 439 DCN_AUX_MASK_SH_LIST(__SHIFT) 440 }; 441 442 static const struct dce110_aux_registers_mask aux_mask = { 443 DCN_AUX_MASK_SH_LIST(_MASK) 444 }; 445 446 #define dsc_regs_init(id)\ 447 DSC_REG_LIST_DCN60_RI(id) 448 449 static struct dcn401_dsc_registers dsc_regs[4]; 450 451 static const struct dcn60_dsc_shift dsc_shift = { 452 DSC_REG_LIST_SH_MASK_DCN60(__SHIFT) 453 }; 454 455 static const struct dcn60_dsc_mask dsc_mask = { 456 DSC_REG_LIST_SH_MASK_DCN60(_MASK) 457 }; 458 459 static struct dcn60_mpc_registers mpc_regs; 460 461 #define dcn_mpc_regs_init()\ 462 MPC_REG_LIST_DCN6_0_RI(0),\ 463 MPC_REG_LIST_DCN6_0_RI(1),\ 464 MPC_REG_LIST_DCN6_0_RI(2),\ 465 MPC_REG_LIST_DCN6_0_RI(3),\ 466 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\ 467 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\ 468 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\ 469 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3) 470 471 static const struct dcn60_mpc_shift mpc_shift = { 472 MPC_COMMON_MASK_SH_LIST_DCN6_0(__SHIFT) 473 }; 474 475 static const struct dcn60_mpc_mask mpc_mask = { 476 MPC_COMMON_MASK_SH_LIST_DCN6_0(_MASK) 477 }; 478 479 #define optc_regs_init(id)\ 480 OPTC_COMMON_REG_LIST_DCN60_RI(id) 481 482 static struct dcn_optc_registers optc_regs[4]; 483 484 static const struct dcn_optc_shift optc_shift = { 485 OPTC_COMMON_MASK_SH_LIST_DCN60(__SHIFT) 486 }; 487 488 static const struct dcn_optc_mask optc_mask = { 489 OPTC_COMMON_MASK_SH_LIST_DCN60(_MASK) 490 }; 491 492 static struct dcn_hubp2_registers hubp_regs[4]; 493 494 #define hubp_regs_init(id)\ 495 HUBP_REG_LIST_DCN60_RI(id) 496 497 static const struct dcn_hubp2_shift hubp_shift = { 498 HUBP_MASK_SH_LIST_DCN60(__SHIFT) 499 }; 500 501 static const struct dcn_hubp2_mask hubp_mask = { 502 HUBP_MASK_SH_LIST_DCN60(_MASK) 503 }; 504 505 static struct dcn_hubbub_registers hubbub_reg; 506 #define hubbub_reg_init()\ 507 HUBBUB_REG_LIST_DCN60_RI(0) 508 509 static const struct dcn_hubbub_shift hubbub_shift = { 510 HUBBUB_MASK_SH_LIST_DCN6_0(__SHIFT) 511 }; 512 513 static const struct dcn_hubbub_mask hubbub_mask = { 514 HUBBUB_MASK_SH_LIST_DCN6_0(_MASK) 515 }; 516 517 static struct dccg_registers dccg_regs; 518 519 #define dccg_regs_init()\ 520 DCCG_REG_LIST_DCN60_RI() 521 522 static const struct dccg_shift dccg_shift = { 523 DCCG_MASK_SH_LIST_DCN60(__SHIFT) 524 }; 525 526 static const struct dccg_mask dccg_mask = { 527 DCCG_MASK_SH_LIST_DCN60(_MASK) 528 }; 529 530 #define SRII2(reg_name_pre, reg_name_post, id)\ 531 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \ 532 ## id ## _ ## reg_name_post ## _BASE_IDX) + \ 533 reg ## reg_name_pre ## id ## _ ## reg_name_post 534 535 static struct dce_hwseq_registers hwseq_reg; 536 537 #define hwseq_reg_init()\ 538 HWSEQ_DCN60_REG_LIST() 539 540 #define HWSEQ_DCN60_MASK_SH_LIST(mask_sh)\ 541 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \ 542 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \ 543 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \ 544 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \ 545 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \ 546 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \ 547 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \ 548 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP0_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \ 549 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP1_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \ 550 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP2_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), \ 551 HWS_SF(, HDCP_INTERRUPT_DEST, DOUT_IHC_HDCP3_I2C_XFER_REQ_INTERRUPT_DEST, mask_sh), 552 553 static const struct dce_hwseq_shift hwseq_shift = { 554 HWSEQ_DCN60_MASK_SH_LIST(__SHIFT) 555 }; 556 557 static const struct dce_hwseq_mask hwseq_mask = { 558 HWSEQ_DCN60_MASK_SH_LIST(_MASK) 559 }; 560 561 #define vmid_regs_init(id)\ 562 DCN20_VMID_REG_LIST_RI(id) 563 564 static struct dcn_vmid_registers vmid_regs[16]; 565 566 static const struct dcn20_vmid_shift vmid_shifts = { 567 DCN20_VMID_MASK_SH_LIST(__SHIFT) 568 }; 569 570 static const struct dcn20_vmid_mask vmid_masks = { 571 DCN20_VMID_MASK_SH_LIST(_MASK) 572 }; 573 574 static const struct resource_caps res_cap_dcn6_0 = { 575 .num_timing_generator = 4, 576 .num_opp = 4, 577 .num_video_plane = 4, 578 .num_audio = 4, 579 .num_stream_encoder = 4, 580 .num_hpo_frl = 1, 581 .num_hpo_dp_stream_encoder = 4, 582 .num_hpo_dp_link_encoder = 4, 583 .num_pll = 4, 584 .num_dwb = 0, 585 .num_ddc = 2, 586 .num_vmid = 16, 587 .num_mpc_3dlut = 4, 588 .num_dsc = 4, 589 .num_aux = 4, 590 .num_rmcm = 2, 591 }; 592 593 static const struct dc_plane_cap plane_cap = { 594 .type = DC_PLANE_TYPE_DCN_UNIVERSAL, 595 .per_pixel_alpha = true, 596 597 .pixel_format_support = { 598 .argb8888 = true, 599 .nv12 = true, 600 .fp16 = true, 601 .p010 = true, 602 .ayuv = false, 603 }, 604 605 .max_upscale_factor = { 606 .argb8888 = 16000, 607 .nv12 = 16000, 608 .fp16 = 16000 609 }, 610 611 // 6:1 downscaling ratio: 1000/6 = 166.666 612 .max_downscale_factor = { 613 .argb8888 = 167, 614 .nv12 = 167, 615 .fp16 = 167 616 }, 617 64, 618 64 619 }; 620 621 static const struct dc_debug_options debug_defaults_drv = { 622 .limit_ffe = 7, 623 .disable_dmcu = true, 624 .force_abm_enable = false, 625 .clock_trace = true, 626 .disable_pplib_clock_request = false, 627 .pipe_split_policy = MPC_SPLIT_AVOID, 628 .force_single_disp_pipe_split = false, 629 .disable_dcc = DCC_ENABLE, 630 .vsr_support = true, 631 .performance_trace = false, 632 .max_downscale_src_width = 7680,/*upto 8K*/ 633 .disable_pplib_wm_range = false, 634 .scl_reset_length10 = true, 635 .sanity_checks = false, 636 .underflow_assert_delay_us = 0xFFFFFFFF, 637 .dwb_fi_phase = -1, // -1 = disable, 638 .dmub_command_table = true, 639 .enable_mem_low_power = { 640 .bits = { 641 .vga = false, 642 .i2c = false, 643 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled 644 .dscl = false, 645 .cm = false, 646 .mpc = false, 647 .optc = true, 648 } 649 }, 650 .use_max_lb = true, 651 .exit_idle_opt_for_cursor_updates = true, 652 .using_dml2 = true, 653 .using_dml21 = true, 654 .enable_single_display_2to1_odm_policy = true, 655 656 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions 657 .enable_double_buffered_dsc_pg_support = true, 658 .enable_dp_dig_pixel_rate_div_policy = 1, 659 .allow_sw_cursor_fallback = false, 660 .alloc_extra_way_for_cursor = true, 661 .min_prefetch_in_strobe_ns = 60000, // 60us 662 .disable_unbounded_requesting = false, 663 .dcc_meta_propagation_delay_us = 10, 664 .fams_version = { 665 .minor = 0, 666 .major = 3, 667 }, // v3.0 668 .fams2_config = { 669 .bits = { 670 .enable = true, 671 .enable_ppt_check = true, 672 .enable_offload_flip = true, 673 .enable_stall_recovery = true, 674 .alternate_channel_workaround = true, 675 } 676 }, 677 .force_cositing = CHROMA_COSITING_NONE + 1, 678 }; 679 680 static const struct dc_check_config config_defaults = { 681 .enable_legacy_fast_update = false, 682 }; 683 684 static bool is_plane1_enabled(enum surface_pixel_format format) 685 { 686 return (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA || 687 format == SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb || 688 format == SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb); 689 } 690 691 static void reset_mcache_allocations(struct dml2_hubp_pipe_mcache_regs *pipe_mcache_regs) 692 { 693 // Initialize all entries to special valid MCache ID and special valid split coordinate 694 pipe_mcache_regs->main.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; 695 pipe_mcache_regs->main.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; 696 pipe_mcache_regs->main.p0.split_location = SPLIT_LOCATION_UNDEFINED; 697 698 pipe_mcache_regs->mall.p0.mcache_id_first = MCACHE_ID_UNASSIGNED; 699 pipe_mcache_regs->mall.p0.mcache_id_second = MCACHE_ID_UNASSIGNED; 700 pipe_mcache_regs->mall.p0.split_location = SPLIT_LOCATION_UNDEFINED; 701 702 pipe_mcache_regs->main.p1.mcache_id_first = MCACHE_ID_UNASSIGNED; 703 pipe_mcache_regs->main.p1.mcache_id_second = MCACHE_ID_UNASSIGNED; 704 pipe_mcache_regs->main.p1.split_location = SPLIT_LOCATION_UNDEFINED; 705 706 pipe_mcache_regs->mall.p1.mcache_id_first = MCACHE_ID_UNASSIGNED; 707 pipe_mcache_regs->mall.p1.mcache_id_second = MCACHE_ID_UNASSIGNED; 708 pipe_mcache_regs->mall.p1.split_location = SPLIT_LOCATION_UNDEFINED; 709 } 710 711 static void get_plane_count(struct dc_state *context, unsigned int *plane_count) 712 { 713 int i; 714 *plane_count = 0; 715 for (i = 0; i < context->stream_count; i++) { 716 *plane_count += context->stream_status[i].plane_count; 717 } 718 } 719 720 static bool get_plane_index(struct dc_state *context, struct dc_plane_state *plane_state, unsigned int *plane_idx) 721 { 722 int i, j; 723 *plane_idx = 0; 724 for (i = 0; i < context->stream_count; i++) { 725 for (j = 0; j < context->stream_status[i].plane_count; j++) { 726 if (plane_state == context->stream_status[i].plane_states[j]) { 727 return true; 728 } 729 (*plane_idx)++; 730 } 731 } 732 // No planes have been mapped to this pipe, so just return false 733 return false; 734 } 735 736 static void assign_global_mcache_ids(struct dc_state *context, const struct dc_mcache_params *mcache_params, struct dc_mcache_allocations *mcache_allocations) 737 { 738 unsigned int plane_count = 0; 739 unsigned int i; 740 unsigned int plane_idx; 741 uint32_t next_unused_cache_id = 0; 742 743 //Get plane count 744 get_plane_count(context, &plane_count); 745 746 //Assign global_mcache id 747 for (plane_idx = 0; plane_idx < plane_count; plane_idx++) { 748 if (!mcache_params[plane_idx].valid) 749 continue; 750 751 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane0; i++) { 752 mcache_allocations[plane_idx].global_mcache_ids_plane0[i] = next_unused_cache_id++; 753 } 754 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane1; i++) { 755 mcache_allocations[plane_idx].global_mcache_ids_plane1[i] = next_unused_cache_id++; 756 } 757 758 // The "psuedo-last" slice is always wrapped around 759 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0] = 760 mcache_allocations[plane_idx].global_mcache_ids_plane0[0]; 761 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1] = 762 mcache_allocations[plane_idx].global_mcache_ids_plane1[0]; 763 764 // If we need dedicated caches for mall requesting, then we assign them here. 765 if (mcache_params[plane_idx].requires_dedicated_mall_mcache) { 766 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane0; i++) { 767 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[i] = next_unused_cache_id++; 768 } 769 for (i = 0; i < mcache_params[plane_idx].num_mcaches_plane1; i++) { 770 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[i] = next_unused_cache_id++; 771 } 772 773 // The "psuedo-last" slice is always wrapped around 774 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0] = 775 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[0]; 776 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1] = 777 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[0]; 778 } 779 780 // If P0 and P1 are sharing caches, then it means the largest mcache IDs for p0 and p1 can be the same 781 // since mcache IDs are always ascending, then it means the largest mcacheID of p1 should be the 782 // largest mcacheID of P0 783 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].num_mcaches_plane1 > 0 && 784 mcache_params[plane_idx].last_slice_sharing.plane0_plane1) { 785 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] = 786 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1]; 787 } 788 789 // If we need dedicated caches handle last slice sharing 790 if (mcache_params[plane_idx].requires_dedicated_mall_mcache) { 791 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].num_mcaches_plane1 > 0 && 792 mcache_params[plane_idx].last_slice_sharing.plane0_plane1) { 793 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] = 794 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1]; 795 } 796 // If mall_comb_mcache_l is set then it means that largest mcache ID for MALL p0 can be same as regular read p0 797 if (mcache_params[plane_idx].num_mcaches_plane0 > 0 && mcache_params[plane_idx].last_slice_sharing.mall_comb_mcache_p0) { 798 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1] = 799 mcache_allocations[plane_idx].global_mcache_ids_plane0[mcache_params[plane_idx].num_mcaches_plane0 - 1]; 800 } 801 // If mall_comb_mcache_c is set then it means that largest mcache ID for MALL p1 can be same as regular 802 // read p1 (which can be same as regular read p0 if plane0_plane1 is also set) 803 if (mcache_params[plane_idx].num_mcaches_plane1 > 0 && mcache_params[plane_idx].last_slice_sharing.mall_comb_mcache_p1) { 804 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1] = 805 mcache_allocations[plane_idx].global_mcache_ids_plane1[mcache_params[plane_idx].num_mcaches_plane1 - 1]; 806 } 807 } 808 809 // If you don't need dedicated mall mcaches, the mall mcache assignments are identical to the normal requesting 810 if (!mcache_params[plane_idx].requires_dedicated_mall_mcache) { 811 memcpy(mcache_allocations[plane_idx].global_mcache_ids_mall_plane0, mcache_allocations[plane_idx].global_mcache_ids_plane0, 812 sizeof(mcache_allocations[plane_idx].global_mcache_ids_mall_plane0)); 813 memcpy(mcache_allocations[plane_idx].global_mcache_ids_mall_plane1, mcache_allocations[plane_idx].global_mcache_ids_plane1, 814 sizeof(mcache_allocations[plane_idx].global_mcache_ids_mall_plane1)); 815 } 816 } 817 } 818 819 static bool dc_calculate_first_second_splitting(const int *mcache_boundaries, int num_boundaries, int shift, 820 int pipe_h_vp_start, int pipe_h_vp_end, int *first_offset, int *second_offset) 821 { 822 const int MAX_VP = 0xFFFFFF; 823 int left_cache_id; 824 int right_cache_id; 825 int range_start; 826 int range_end; 827 bool success = false; 828 829 if (num_boundaries <= 1) { 830 if (first_offset && second_offset) { 831 *first_offset = 0; 832 *second_offset = -1; 833 } 834 success = true; 835 return success; 836 } else { 837 range_start = 0; 838 for (left_cache_id = 0; left_cache_id < num_boundaries; left_cache_id++) { 839 range_end = mcache_boundaries[left_cache_id] - shift - 1; 840 841 if (range_start <= pipe_h_vp_start && pipe_h_vp_start <= range_end) 842 break; 843 844 range_start = range_end + 1; 845 } 846 847 range_end = MAX_VP; 848 for (right_cache_id = num_boundaries - 1; right_cache_id >= -1; right_cache_id--) { 849 if (right_cache_id >= 0) 850 range_start = mcache_boundaries[right_cache_id] - shift; 851 else 852 range_start = 0; 853 854 if (range_start <= pipe_h_vp_end && pipe_h_vp_end <= range_end) { 855 break; 856 } 857 range_end = range_start - 1; 858 } 859 right_cache_id = (right_cache_id + 1) % num_boundaries; 860 861 if (right_cache_id == left_cache_id) { 862 if (first_offset && second_offset) { 863 *first_offset = left_cache_id; 864 *second_offset = -1; 865 } 866 success = true; 867 } else if (right_cache_id == (left_cache_id + 1) % num_boundaries) { 868 if (first_offset && second_offset) { 869 *first_offset = left_cache_id; 870 *second_offset = right_cache_id; 871 } 872 success = true; 873 } 874 } 875 876 return success; 877 } 878 879 static bool build_mcache_pipe_regs_config(struct dc_state *context, const struct dc_mcache_params *mcache_params, struct dc_mcache_allocations *mcache_allocations) 880 { 881 bool success = true; 882 int first_offset, second_offset; 883 unsigned int plane_idx; 884 int pipe_idx; 885 886 for (pipe_idx = 0; pipe_idx < MAX_PIPES; pipe_idx++) { 887 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 888 if (get_plane_index(context, pipe_ctx->plane_state, &plane_idx) && pipe_ctx->plane_res.hubp) { 889 reset_mcache_allocations(&pipe_ctx->mcache_regs); 890 if (pipe_ctx->plane_state->dcc.enable) { 891 // P0 always enabled 892 if (!dc_calculate_first_second_splitting(mcache_params[plane_idx].mcache_x_offsets_plane0, 893 mcache_params[plane_idx].num_mcaches_plane0, 894 0, 895 pipe_ctx->plane_res.scl_data.viewport.x, 896 pipe_ctx->plane_res.scl_data.viewport.x + 897 pipe_ctx->plane_res.scl_data.viewport.width - 1, 898 &first_offset, &second_offset)) { 899 success = false; 900 break; 901 } 902 903 pipe_ctx->mcache_regs.main.p0.mcache_id_first = 904 mcache_allocations[plane_idx].global_mcache_ids_plane0[first_offset]; 905 906 pipe_ctx->mcache_regs.mall.p0.mcache_id_first = 907 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[first_offset]; 908 909 if (second_offset >= 0) { 910 pipe_ctx->mcache_regs.main.p0.mcache_id_second = 911 mcache_allocations[plane_idx].global_mcache_ids_plane0[second_offset]; 912 pipe_ctx->mcache_regs.main.p0.split_location = 913 mcache_params[plane_idx].mcache_x_offsets_plane0[first_offset] - 1; 914 915 pipe_ctx->mcache_regs.mall.p0.mcache_id_second = 916 mcache_allocations[plane_idx].global_mcache_ids_mall_plane0[second_offset]; 917 pipe_ctx->mcache_regs.mall.p0.split_location = 918 mcache_params[plane_idx].mcache_x_offsets_plane0[first_offset] - 1; 919 } 920 921 // Populate P1 if enabled 922 if (is_plane1_enabled(pipe_ctx->plane_state->format)) { 923 if (!dc_calculate_first_second_splitting(mcache_params[plane_idx].mcache_x_offsets_plane1, 924 mcache_params[plane_idx].num_mcaches_plane1, 925 0, 926 pipe_ctx->plane_res.scl_data.viewport_c.x, 927 pipe_ctx->plane_res.scl_data.viewport_c.x + 928 pipe_ctx->plane_res.scl_data.viewport_c.width - 1, 929 &first_offset, &second_offset)) { 930 success = false; 931 break; 932 } 933 934 pipe_ctx->mcache_regs.main.p1.mcache_id_first = 935 mcache_allocations[plane_idx].global_mcache_ids_plane1[first_offset]; 936 937 pipe_ctx->mcache_regs.mall.p1.mcache_id_first = 938 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[first_offset]; 939 940 if (second_offset >= 0) { 941 pipe_ctx->mcache_regs.main.p1.mcache_id_second = 942 mcache_allocations[plane_idx].global_mcache_ids_plane1[second_offset]; 943 pipe_ctx->mcache_regs.main.p1.split_location = 944 mcache_params[plane_idx].mcache_x_offsets_plane1[first_offset] - 1; 945 946 pipe_ctx->mcache_regs.mall.p1.mcache_id_second = 947 mcache_allocations[plane_idx].global_mcache_ids_mall_plane1[second_offset]; 948 pipe_ctx->mcache_regs.mall.p1.split_location = 949 mcache_params[plane_idx].mcache_x_offsets_plane1[first_offset] - 1; 950 } 951 } 952 } 953 } 954 } 955 return success; 956 } 957 958 bool dcn60_program_mcache_pipe_config(struct dc_state *context, const struct dc_mcache_params *mcache_params) 959 { 960 struct dc_mcache_allocations mcache_allocations[MAX_PLANES] = {0}; 961 if (!mcache_params) { 962 return false; 963 } 964 965 // Step 1: Assign global mcache IDs for each plane 966 assign_global_mcache_ids(context, mcache_params, mcache_allocations); 967 968 // Step 2: Build the mcache pipe configuration 969 if (!build_mcache_pipe_regs_config(context, mcache_params, mcache_allocations)) { 970 return false; 971 } 972 973 return true; 974 } 975 976 bool dcn50_program_mcache_pipe_config(struct dc_state *context, const struct dc_mcache_params *mcache_params) 977 { 978 int pipe_idx; 979 980 if (!mcache_params) { 981 return false; 982 } 983 984 for (pipe_idx = 0; pipe_idx < MAX_PIPES; pipe_idx++) { 985 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 986 reset_mcache_allocations(&pipe_ctx->mcache_regs); 987 if (pipe_ctx->plane_state && pipe_ctx->plane_state->dcc.enable) { 988 pipe_ctx->mcache_regs.main.p0.mcache_id_first = pipe_ctx->pipe_idx; 989 pipe_ctx->mcache_regs.mall.p0.mcache_id_first = pipe_ctx->pipe_idx; 990 // Populate P1 if enabled 991 if (is_plane1_enabled(pipe_ctx->plane_state->format)) { 992 pipe_ctx->mcache_regs.main.p1.mcache_id_first = pipe_ctx->pipe_idx; 993 pipe_ctx->mcache_regs.mall.p1.mcache_id_first = pipe_ctx->pipe_idx; 994 } 995 } 996 } 997 return true; 998 } 999 1000 static struct dce_aux *dcn60_aux_engine_create( 1001 struct dc_context *ctx, 1002 uint32_t inst) 1003 { 1004 struct aux_engine_dce110 *aux_engine = 1005 kzalloc_obj(struct aux_engine_dce110); 1006 1007 if (!aux_engine) 1008 return NULL; 1009 1010 #undef REG_STRUCT 1011 #define REG_STRUCT aux_engine_regs 1012 aux_engine_regs_init(0), 1013 aux_engine_regs_init(1), 1014 aux_engine_regs_init(2), 1015 aux_engine_regs_init(3); 1016 1017 dce110_aux_engine_construct(aux_engine, ctx, inst, 1018 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 1019 &aux_engine_regs[inst], 1020 &aux_mask, 1021 &aux_shift, 1022 ctx->dc->caps.extended_aux_timeout_support); 1023 1024 return &aux_engine->base; 1025 } 1026 #define i2c_inst_regs_init(id)\ 1027 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id) 1028 1029 static struct dce_i2c_registers i2c_hw_regs[2]; 1030 1031 static const struct dce_i2c_shift i2c_shifts = { 1032 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT) 1033 }; 1034 1035 static const struct dce_i2c_mask i2c_masks = { 1036 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK) 1037 }; 1038 1039 static struct dce_i2c_hw *dcn60_i2c_hw_create( 1040 struct dc_context *ctx, 1041 uint32_t inst) 1042 { 1043 struct dce_i2c_hw *dce_i2c_hw = 1044 kzalloc_obj(struct dce_i2c_hw); 1045 1046 if (!dce_i2c_hw) 1047 return NULL; 1048 1049 #undef REG_STRUCT 1050 #define REG_STRUCT i2c_hw_regs 1051 i2c_inst_regs_init(1), 1052 i2c_inst_regs_init(2); 1053 1054 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, 1055 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 1056 1057 return dce_i2c_hw; 1058 } 1059 1060 static struct clock_source *dcn60_clock_source_create( 1061 struct dc_context *ctx, 1062 struct dc_bios *bios, 1063 enum clock_source_id id, 1064 const struct dce110_clk_src_regs *regs, 1065 bool dp_clk_src) 1066 { 1067 struct dce110_clk_src *clk_src = 1068 kzalloc_obj(struct dce110_clk_src); 1069 1070 if (!clk_src) 1071 return NULL; 1072 1073 if (dcn50_clk_src_construct(clk_src, ctx, bios, id, 1074 regs, &cs_shift, &cs_mask)) { 1075 clk_src->base.dp_clk_src = dp_clk_src; 1076 return &clk_src->base; 1077 } 1078 1079 kfree(clk_src); 1080 BREAK_TO_DEBUGGER(); 1081 return NULL; 1082 } 1083 1084 static struct hubbub *dcn60_hubbub_create(struct dc_context *ctx) 1085 { 1086 int i; 1087 1088 struct dcn20_hubbub *hubbub2 = kzalloc_obj(struct dcn20_hubbub); 1089 1090 if (!hubbub2) 1091 return NULL; 1092 1093 #undef REG_STRUCT 1094 #define REG_STRUCT hubbub_reg 1095 hubbub_reg_init(); 1096 1097 #undef REG_STRUCT 1098 #define REG_STRUCT vmid_regs 1099 vmid_regs_init(0), 1100 vmid_regs_init(1), 1101 vmid_regs_init(2), 1102 vmid_regs_init(3), 1103 vmid_regs_init(4), 1104 vmid_regs_init(5), 1105 vmid_regs_init(6), 1106 vmid_regs_init(7), 1107 vmid_regs_init(8), 1108 vmid_regs_init(9), 1109 vmid_regs_init(10), 1110 vmid_regs_init(11), 1111 vmid_regs_init(12), 1112 vmid_regs_init(13), 1113 vmid_regs_init(14), 1114 vmid_regs_init(15); 1115 1116 hubbub60_construct(hubbub2, ctx, 1117 &hubbub_reg, 1118 &hubbub_shift, 1119 &hubbub_mask, 1120 DCN6_0_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes, 1121 8, //dml2 ip_params_st.pixel_chunk_size_kbytes 1122 DCN6_0_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes 1123 1124 for (i = 0; i < res_cap_dcn6_0.num_vmid; i++) { 1125 struct dcn20_vmid *vmid = &hubbub2->vmid[i]; 1126 1127 vmid->ctx = ctx; 1128 1129 vmid->regs = &vmid_regs[i]; 1130 vmid->shifts = &vmid_shifts; 1131 vmid->masks = &vmid_masks; 1132 } 1133 1134 return &hubbub2->base; 1135 } 1136 1137 static struct hubp *dcn60_hubp_create( 1138 struct dc_context *ctx, 1139 uint32_t inst) 1140 { 1141 struct dcn20_hubp *hubp2 = 1142 kzalloc_obj(struct dcn20_hubp); 1143 1144 if (!hubp2) 1145 return NULL; 1146 1147 #undef REG_STRUCT 1148 #define REG_STRUCT hubp_regs 1149 hubp_regs_init(0), 1150 hubp_regs_init(1), 1151 hubp_regs_init(2), 1152 hubp_regs_init(3); 1153 1154 if (hubp60_construct(hubp2, ctx, inst, 1155 &hubp_regs[inst], &hubp_shift, &hubp_mask)) 1156 return &hubp2->base; 1157 1158 BREAK_TO_DEBUGGER(); 1159 kfree(hubp2); 1160 return NULL; 1161 } 1162 1163 static void dcn60_dpp_destroy(struct dpp **dpp) 1164 { 1165 kfree(TO_DCN60_DPP(*dpp)); 1166 *dpp = NULL; 1167 } 1168 1169 static struct dpp *dcn60_dpp_create( 1170 struct dc_context *ctx, 1171 uint32_t inst) 1172 { 1173 struct dcn60_dpp *dpp60 = 1174 kzalloc_obj(struct dcn60_dpp); 1175 1176 if (!dpp60) 1177 return NULL; 1178 1179 #undef REG_STRUCT 1180 #define REG_STRUCT dpp_regs 1181 dpp_regs_init(0), 1182 dpp_regs_init(1), 1183 dpp_regs_init(2), 1184 dpp_regs_init(3); 1185 1186 if (dpp60_construct(dpp60, ctx, inst, 1187 &dpp_regs[inst], &tf_shift, &tf_mask)) 1188 return &dpp60->base; 1189 1190 BREAK_TO_DEBUGGER(); 1191 kfree(dpp60); 1192 return NULL; 1193 } 1194 1195 static struct mpc *dcn60_mpc_create( 1196 struct dc_context *ctx, 1197 int num_mpcc, 1198 int num_rmu) 1199 { 1200 struct dcn60_mpc *mpc60 = kzalloc_obj(struct dcn60_mpc); 1201 1202 if (!mpc60) 1203 return NULL; 1204 1205 #undef REG_STRUCT 1206 #define REG_STRUCT mpc_regs 1207 dcn_mpc_regs_init(); 1208 1209 dcn60_mpc_construct(mpc60, ctx, 1210 &mpc_regs, 1211 &mpc_shift, 1212 &mpc_mask, 1213 num_mpcc, 1214 num_rmu); 1215 1216 return &mpc60->base; 1217 } 1218 1219 static struct output_pixel_processor *dcn60_opp_create( 1220 struct dc_context *ctx, uint32_t inst) 1221 { 1222 struct dcn20_opp *opp2 = 1223 kzalloc_obj(struct dcn20_opp); 1224 1225 if (!opp2) { 1226 BREAK_TO_DEBUGGER(); 1227 return NULL; 1228 } 1229 1230 #undef REG_STRUCT 1231 #define REG_STRUCT opp_regs 1232 opp_regs_init(0), 1233 opp_regs_init(1), 1234 opp_regs_init(2), 1235 opp_regs_init(3); 1236 1237 dcn60_opp_construct(opp2, ctx, inst, 1238 &opp_regs[inst], &opp_shift, &opp_mask); 1239 return &opp2->base; 1240 } 1241 1242 static struct timing_generator *dcn60_timing_generator_create( 1243 struct dc_context *ctx, 1244 uint32_t instance) 1245 { 1246 struct optc *tgn10 = 1247 kzalloc_obj(struct optc); 1248 1249 if (!tgn10) 1250 return NULL; 1251 #undef REG_STRUCT 1252 #define REG_STRUCT optc_regs 1253 optc_regs_init(0), 1254 optc_regs_init(1), 1255 optc_regs_init(2), 1256 optc_regs_init(3); 1257 1258 tgn10->base.inst = instance; 1259 tgn10->base.ctx = ctx; 1260 1261 tgn10->tg_regs = &optc_regs[instance]; 1262 tgn10->tg_shift = &optc_shift; 1263 tgn10->tg_mask = &optc_mask; 1264 1265 dcn60_timing_generator_init(tgn10); 1266 1267 return &tgn10->base; 1268 } 1269 1270 static const struct encoder_feature_support link_enc_feature = { 1271 .max_hdmi_deep_color = COLOR_DEPTH_121212, 1272 .max_hdmi_pixel_clock = 600000, 1273 .hdmi_ycbcr420_supported = true, 1274 .dp_ycbcr420_supported = true, 1275 .fec_supported = true, 1276 .flags.bits.IS_HBR2_CAPABLE = true, 1277 .flags.bits.IS_HBR3_CAPABLE = true, 1278 .flags.bits.IS_TPS3_CAPABLE = true, 1279 .flags.bits.IS_TPS4_CAPABLE = true 1280 }; 1281 1282 static struct link_encoder *dcn60_link_encoder_create( 1283 struct dc_context *ctx, 1284 const struct encoder_init_data *enc_init_data) 1285 { 1286 struct dcn20_link_encoder *enc20 = 1287 kzalloc_obj(struct dcn20_link_encoder); 1288 1289 if (!enc20 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) { 1290 kfree(enc20); 1291 return NULL; 1292 } 1293 1294 #undef REG_STRUCT 1295 #define REG_STRUCT link_enc_aux_regs 1296 aux_regs_init(0, 1), 1297 aux_regs_init(1, 2), 1298 aux_regs_init(2, 3), 1299 aux_regs_init(3, 4); 1300 1301 #undef REG_STRUCT 1302 #define REG_STRUCT link_enc_hpd_regs 1303 hpd_regs_init(0), 1304 hpd_regs_init(1), 1305 hpd_regs_init(2), 1306 hpd_regs_init(3); 1307 #undef REG_STRUCT 1308 #define REG_STRUCT link_enc_regs 1309 link_regs_init(0, A), 1310 link_regs_init(1, B), 1311 link_regs_init(2, C), 1312 link_regs_init(3, D); 1313 1314 dcn60_link_encoder_construct(enc20, 1315 enc_init_data, 1316 &link_enc_feature, 1317 &link_enc_regs[enc_init_data->transmitter], 1318 &link_enc_aux_regs[enc_init_data->channel - 1], 1319 &link_enc_hpd_regs[enc_init_data->hpd_source], 1320 &le_shift, 1321 &le_mask); 1322 return &enc20->enc10.base; 1323 } 1324 1325 static void read_dce_straps( 1326 struct dc_context *ctx, 1327 struct resource_straps *straps) 1328 { 1329 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX), 1330 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio); 1331 1332 } 1333 1334 static struct audio *dcn60_create_audio( 1335 struct dc_context *ctx, unsigned int inst) 1336 { 1337 1338 #undef REG_STRUCT 1339 #define REG_STRUCT audio_regs 1340 audio_regs_init(0), 1341 audio_regs_init(1), 1342 audio_regs_init(2), 1343 audio_regs_init(3), 1344 audio_regs_init(4); 1345 1346 return dce_audio_create(ctx, inst, 1347 &audio_regs[inst], &audio_shift, &audio_mask); 1348 } 1349 1350 static struct vpg *dcn60_vpg_create( 1351 struct dc_context *ctx, 1352 uint32_t inst) 1353 { 1354 struct dcn31_vpg *vpg6 = kzalloc_obj(struct dcn31_vpg); 1355 1356 if (!vpg6) 1357 return NULL; 1358 1359 #undef REG_STRUCT 1360 #define REG_STRUCT vpg_regs 1361 vpg_regs_init(0), 1362 vpg_regs_init(1), 1363 vpg_regs_init(2), 1364 vpg_regs_init(3), 1365 vpg_regs_init(4), 1366 vpg_regs_init(5), 1367 vpg_regs_init(6), 1368 vpg_regs_init(7), 1369 vpg_regs_init(8); 1370 1371 vpg31_construct(vpg6, ctx, inst, 1372 &vpg_regs[inst], 1373 &vpg_shift, 1374 &vpg_mask); 1375 1376 return &vpg6->base; 1377 } 1378 1379 static struct apg *dcn60_apg_create( 1380 struct dc_context *ctx, 1381 uint32_t inst) 1382 { 1383 struct dcn31_apg *apg60 = kzalloc_obj(struct dcn31_apg); 1384 1385 if (!apg60) 1386 return NULL; 1387 1388 #undef REG_STRUCT 1389 #define REG_STRUCT apg_regs 1390 apg_regs_init(0), 1391 apg_regs_init(1), 1392 apg_regs_init(2), 1393 apg_regs_init(3), 1394 apg_regs_init(4); 1395 1396 apg31_construct(apg60, ctx, inst, 1397 &apg_regs[inst], 1398 &apg_shift, 1399 &apg_mask); 1400 1401 return &apg60->base; 1402 } 1403 1404 static struct stream_encoder *dcn60_stream_encoder_create( 1405 enum engine_id eng_id, 1406 struct dc_context *ctx) 1407 { 1408 struct dcn10_stream_encoder *enc1; 1409 struct vpg *vpg; 1410 struct apg *apg; 1411 int vpg_inst; 1412 uint32_t apg_inst; 1413 1414 /* Mapping of VPG, APG, DME register blocks to DIO block instance */ 1415 if (eng_id <= ENGINE_ID_DIGF) { 1416 vpg_inst = eng_id; 1417 apg_inst = eng_id; 1418 } else 1419 return NULL; 1420 1421 enc1 = kzalloc_obj(struct dcn10_stream_encoder); 1422 vpg = dcn60_vpg_create(ctx, vpg_inst); 1423 apg = dcn60_apg_create(ctx, apg_inst); 1424 1425 if (!enc1 || !vpg || !apg || eng_id >= ARRAY_SIZE(stream_enc_regs)) { 1426 kfree(enc1); 1427 kfree(vpg); 1428 kfree(apg); 1429 return NULL; 1430 } 1431 #undef REG_STRUCT 1432 #define REG_STRUCT stream_enc_regs 1433 stream_enc_regs_init(0), 1434 stream_enc_regs_init(1), 1435 stream_enc_regs_init(2), 1436 stream_enc_regs_init(3); 1437 1438 dcn60_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, 1439 eng_id, vpg, apg, 1440 &stream_enc_regs[eng_id], 1441 &se_shift, &se_mask); 1442 return &enc1->base; 1443 } 1444 1445 static struct hpo_frl_stream_encoder *dcn60_hpo_frl_stream_encoder_create( 1446 enum engine_id eng_id, 1447 struct dc_context *ctx) 1448 { 1449 struct dcn401_hpo_frl_stream_encoder *hpo_enc60; 1450 struct vpg *vpg; 1451 struct apg *apg; 1452 int vpg_inst; 1453 int apg_inst; 1454 1455 #undef REG_STRUCT 1456 #define REG_STRUCT hpo_frl_stream_enc_regs 1457 hpo_frl_stream_encoder_reg_list(0), 1458 hpo_frl_stream_encoder_dme_reg_list(4); 1459 1460 /* Mapping of VPG, APG, DME register blocks to HPO block instance */ 1461 if (eng_id == ENGINE_ID_HPO_0) { 1462 vpg_inst = 4; 1463 apg_inst = 4; 1464 } else 1465 return NULL; 1466 1467 /* allocate HPO stream encoder and create VPG, APG sub-blocks */ 1468 hpo_enc60 = kzalloc_obj(struct dcn401_hpo_frl_stream_encoder); 1469 vpg = dcn60_vpg_create(ctx, vpg_inst); 1470 apg = dcn60_apg_create(ctx, apg_inst); 1471 1472 if (!hpo_enc60 || !vpg || !apg) { 1473 kfree(hpo_enc60); 1474 kfree(vpg); 1475 kfree(apg); 1476 return NULL; 1477 } 1478 1479 dcn60_hpo_frl_stream_encoder_construct(hpo_enc60, ctx, ctx->dc_bios, 1480 eng_id, vpg, apg, 1481 &hpo_frl_stream_enc_regs[eng_id-ENGINE_ID_HPO_0], 1482 &hpo_se_shift, &hpo_se_mask); 1483 1484 return &hpo_enc60->base; 1485 } 1486 1487 static struct hpo_frl_link_encoder *dcn60_hpo_frl_link_encoder_create( 1488 enum engine_id eng_id, 1489 struct dc_context *ctx) 1490 { 1491 struct dcn30_hpo_frl_link_encoder *hpo_link_enc; 1492 ASSERT((eng_id == ENGINE_ID_HPO_0) || (eng_id == ENGINE_ID_HPO_1)); 1493 1494 #undef REG_STRUCT 1495 #define REG_STRUCT hpo_frl_link_enc_regs 1496 hpo_frl_link_encoder_reg_list(0); 1497 1498 /* allocate HPO link encoder */ 1499 hpo_link_enc = kzalloc_obj(struct dcn30_hpo_frl_link_encoder); 1500 if (!hpo_link_enc) 1501 return NULL; /* out of memory */ 1502 1503 hpo_frl_link_encoder60_construct(hpo_link_enc, ctx, eng_id-ENGINE_ID_HPO_0, 1504 &hpo_frl_link_enc_regs[eng_id-ENGINE_ID_HPO_0], 1505 &hpo_le_shift, &hpo_le_mask); 1506 1507 return &hpo_link_enc->base; 1508 } 1509 1510 static struct hpo_dp_stream_encoder *dcn60_hpo_dp_stream_encoder_create( 1511 enum engine_id eng_id, 1512 struct dc_context *ctx) 1513 { 1514 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc60; 1515 struct vpg *vpg; 1516 struct apg *apg; 1517 uint32_t hpo_dp_inst; 1518 uint32_t vpg_inst; 1519 uint32_t apg_inst; 1520 1521 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3)); 1522 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0; 1523 1524 /* Mapping of VPG register blocks to HPO DP block instance: 1525 * VPG[6] -> HPO_DP[0] 1526 * VPG[7] -> HPO_DP[1] 1527 * VPG[8] -> HPO_DP[2] 1528 * VPG[9] -> HPO_DP[3] 1529 */ 1530 vpg_inst = hpo_dp_inst + 5; 1531 1532 /* Mapping of APG register blocks to HPO DP block instance: 1533 * APG[0] -> HPO_DP[0] 1534 * APG[1] -> HPO_DP[1] 1535 * APG[2] -> HPO_DP[2] 1536 * APG[3] -> HPO_DP[3] 1537 */ 1538 apg_inst = hpo_dp_inst; 1539 1540 /* allocate HPO stream encoder and create VPG sub-block */ 1541 hpo_dp_enc60 = kzalloc_obj(struct dcn31_hpo_dp_stream_encoder); 1542 vpg = dcn60_vpg_create(ctx, vpg_inst); 1543 apg = dcn60_apg_create(ctx, apg_inst); 1544 1545 if (!hpo_dp_enc60 || !vpg || !apg) { 1546 kfree(hpo_dp_enc60); 1547 kfree(vpg); 1548 kfree(apg); 1549 return NULL; 1550 } 1551 1552 #undef REG_STRUCT 1553 #define REG_STRUCT hpo_dp_stream_enc_regs 1554 hpo_dp_stream_encoder_reg_init(0), 1555 hpo_dp_stream_encoder_reg_init(1), 1556 hpo_dp_stream_encoder_reg_init(2), 1557 hpo_dp_stream_encoder_reg_init(3); 1558 1559 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc60, ctx, ctx->dc_bios, 1560 hpo_dp_inst, eng_id, vpg, apg, 1561 &hpo_dp_stream_enc_regs[hpo_dp_inst], 1562 &hpo_dp_se_shift, &hpo_dp_se_mask); 1563 1564 return &hpo_dp_enc60->base; 1565 } 1566 1567 static struct hpo_dp_link_encoder *dcn60_hpo_dp_link_encoder_create( 1568 uint8_t inst, 1569 struct dc_context *ctx) 1570 { 1571 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc60; 1572 1573 /* allocate HPO link encoder */ 1574 hpo_dp_enc60 = kzalloc_obj(struct dcn31_hpo_dp_link_encoder); 1575 if (!hpo_dp_enc60) 1576 return NULL; /* out of memory */ 1577 1578 #undef REG_STRUCT 1579 #define REG_STRUCT hpo_dp_link_enc_regs 1580 hpo_dp_link_encoder_reg_init(0), 1581 hpo_dp_link_encoder_reg_init(1), 1582 hpo_dp_link_encoder_reg_init(2), 1583 hpo_dp_link_encoder_reg_init(3); 1584 1585 hpo_dp_link_encoder32_construct(hpo_dp_enc60, ctx, inst, 1586 &hpo_dp_link_enc_regs[inst], 1587 &hpo_dp_le_shift, &hpo_dp_le_mask); 1588 1589 return &hpo_dp_enc60->base; 1590 } 1591 1592 static struct dce_hwseq *dcn60_hwseq_create( 1593 struct dc_context *ctx) 1594 { 1595 struct dce_hwseq *hws = kzalloc_obj(struct dce_hwseq); 1596 1597 #undef REG_STRUCT 1598 #define REG_STRUCT hwseq_reg 1599 hwseq_reg_init(); 1600 1601 if (hws) { 1602 hws->ctx = ctx; 1603 hws->regs = &hwseq_reg; 1604 hws->shifts = &hwseq_shift; 1605 hws->masks = &hwseq_mask; 1606 } 1607 1608 return hws; 1609 } 1610 static const struct resource_create_funcs res_create_funcs = { 1611 .read_dce_straps = read_dce_straps, 1612 .create_audio = dcn60_create_audio, 1613 .create_stream_encoder = dcn60_stream_encoder_create, 1614 .create_hpo_frl_stream_encoder = dcn60_hpo_frl_stream_encoder_create, 1615 .create_hpo_dp_stream_encoder = dcn60_hpo_dp_stream_encoder_create, 1616 .create_hpo_dp_link_encoder = dcn60_hpo_dp_link_encoder_create, 1617 .create_hwseq = dcn60_hwseq_create, 1618 }; 1619 1620 static void dcn60_dsc_destroy(struct display_stream_compressor **dsc) 1621 { 1622 kfree(container_of(*dsc, struct dcn60_dsc, base)); 1623 *dsc = NULL; 1624 } 1625 1626 static void dcn60_resource_destruct(struct dcn60_resource_pool *pool) 1627 { 1628 unsigned int i; 1629 1630 if (pool->base.lsdma_scratch.buffer) { 1631 dm_helpers_free_gpu_mem(pool->base.ctx, 1632 DC_MEM_ALLOC_TYPE_GART, pool->base.lsdma_scratch.buffer); 1633 pool->base.lsdma_scratch.buffer = NULL; 1634 } 1635 1636 for (i = 0; i < pool->base.stream_enc_count; i++) { 1637 if (pool->base.stream_enc[i] != NULL) { 1638 if (pool->base.stream_enc[i]->vpg != NULL) { 1639 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg)); 1640 pool->base.stream_enc[i]->vpg = NULL; 1641 } 1642 if (pool->base.stream_enc[i]->apg != NULL) { 1643 kfree(DCN31_APG_FROM_APG(pool->base.stream_enc[i]->apg)); 1644 pool->base.stream_enc[i]->apg = NULL; 1645 } 1646 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i])); 1647 pool->base.stream_enc[i] = NULL; 1648 } 1649 } 1650 1651 for (i = 0; i < pool->base.hpo_frl_stream_enc_count; i++) { 1652 if (pool->base.hpo_frl_stream_enc[i] != NULL) { 1653 if (pool->base.hpo_frl_stream_enc[i]->vpg != NULL) { 1654 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_frl_stream_enc[i]->vpg)); 1655 pool->base.hpo_frl_stream_enc[i]->vpg = NULL; 1656 } 1657 if (pool->base.hpo_frl_stream_enc[i]->apg != NULL) { 1658 kfree(DCN31_APG_FROM_APG(pool->base.hpo_frl_stream_enc[i]->apg)); 1659 pool->base.hpo_frl_stream_enc[i]->apg = NULL; 1660 } 1661 kfree(DCN401_HPO_FRL_STRENC_FROM_HPO_FRL_STRENC(pool->base.hpo_frl_stream_enc[i])); 1662 pool->base.hpo_frl_stream_enc[i] = NULL; 1663 } 1664 } 1665 1666 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) { 1667 if (pool->base.hpo_dp_stream_enc[i] != NULL) { 1668 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) { 1669 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg)); 1670 pool->base.hpo_dp_stream_enc[i]->vpg = NULL; 1671 } 1672 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) { 1673 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg)); 1674 pool->base.hpo_dp_stream_enc[i]->apg = NULL; 1675 } 1676 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i])); 1677 pool->base.hpo_dp_stream_enc[i] = NULL; 1678 } 1679 } 1680 1681 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) { 1682 if (pool->base.hpo_dp_link_enc[i] != NULL) { 1683 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i])); 1684 pool->base.hpo_dp_link_enc[i] = NULL; 1685 } 1686 } 1687 1688 for (i = 0; i < (unsigned int)pool->base.res_cap->num_dsc; i++) { 1689 if (pool->base.dscs[i] != NULL) 1690 dcn60_dsc_destroy(&pool->base.dscs[i]); 1691 } 1692 1693 if (pool->base.mpc != NULL) { 1694 kfree(TO_DCN20_MPC(pool->base.mpc)); 1695 pool->base.mpc = NULL; 1696 } 1697 for (i = 0; i < MAX_RMCM_INST; i++) 1698 dcn60_rmcm_destroy(&pool->base.rmcm[i]); 1699 if (pool->base.hubbub != NULL) { 1700 kfree(TO_DCN20_HUBBUB(pool->base.hubbub)); 1701 pool->base.hubbub = NULL; 1702 } 1703 for (i = 0; i < pool->base.pipe_count; i++) { 1704 if (pool->base.dpps[i] != NULL) 1705 dcn60_dpp_destroy(&pool->base.dpps[i]); 1706 1707 if (pool->base.ipps[i] != NULL) 1708 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); 1709 1710 if (pool->base.hubps[i] != NULL) { 1711 kfree(TO_DCN20_HUBP(pool->base.hubps[i])); 1712 pool->base.hubps[i] = NULL; 1713 } 1714 1715 if (pool->base.irqs != NULL) { 1716 dal_irq_service_destroy(&pool->base.irqs); 1717 } 1718 } 1719 1720 for (i = 0; i < (unsigned int)pool->base.res_cap->num_aux; i++) { 1721 if (pool->base.engines[i] != NULL) 1722 dce110_engine_destroy(&pool->base.engines[i]); 1723 } 1724 1725 for (i = 0; i < (unsigned int)pool->base.res_cap->num_ddc; i++) { 1726 if (pool->base.hw_i2cs[i] != NULL) { 1727 kfree(pool->base.hw_i2cs[i]); 1728 pool->base.hw_i2cs[i] = NULL; 1729 } 1730 if (pool->base.sw_i2cs[i] != NULL) { 1731 kfree(pool->base.sw_i2cs[i]); 1732 pool->base.sw_i2cs[i] = NULL; 1733 } 1734 } 1735 1736 for (i = 0; i < (unsigned int)pool->base.res_cap->num_opp; i++) { 1737 if (pool->base.opps[i] != NULL) 1738 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]); 1739 } 1740 1741 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1742 if (pool->base.timing_generators[i] != NULL) { 1743 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); 1744 pool->base.timing_generators[i] = NULL; 1745 } 1746 } 1747 1748 for (i = 0; i < pool->base.audio_count; i++) { 1749 if (pool->base.audios[i]) 1750 dce_aud_destroy(&pool->base.audios[i]); 1751 } 1752 1753 for (i = 0; i < pool->base.clk_src_count; i++) { 1754 if (pool->base.clock_sources[i] != NULL) { 1755 dcn20_clock_source_destroy(&pool->base.clock_sources[i]); 1756 pool->base.clock_sources[i] = NULL; 1757 } 1758 } 1759 1760 for (i = 0; i < (unsigned int)pool->base.res_cap->num_mpc_3dlut; i++) { 1761 if (pool->base.mpc_lut[i] != NULL) { 1762 dc_3dlut_func_release(pool->base.mpc_lut[i]); 1763 pool->base.mpc_lut[i] = NULL; 1764 } 1765 if (pool->base.mpc_shaper[i] != NULL) { 1766 dc_transfer_func_release(pool->base.mpc_shaper[i]); 1767 pool->base.mpc_shaper[i] = NULL; 1768 } 1769 } 1770 1771 if (pool->base.dp_clock_source != NULL) { 1772 dcn20_clock_source_destroy(&pool->base.dp_clock_source); 1773 pool->base.dp_clock_source = NULL; 1774 } 1775 1776 for (i = 0; i < (unsigned int)pool->base.res_cap->num_timing_generator; i++) { 1777 if (pool->base.multiple_abms[i] != NULL) 1778 dce_abm_destroy(&pool->base.multiple_abms[i]); 1779 } 1780 1781 if (pool->base.psr != NULL) 1782 dmub_psr_destroy(&pool->base.psr); 1783 1784 if (pool->base.dccg != NULL) 1785 dcn_dccg_destroy(&pool->base.dccg); 1786 1787 if (pool->base.oem_device != NULL) { 1788 struct dc *dc = pool->base.oem_device->ctx->dc; 1789 1790 dc->link_srv->destroy_ddc_service(&pool->base.oem_device); 1791 } 1792 } 1793 1794 static struct display_stream_compressor *dcn60_dsc_create( 1795 struct dc_context *ctx, uint32_t inst) 1796 { 1797 struct dcn60_dsc *dsc = 1798 kzalloc_obj(struct dcn60_dsc); 1799 1800 if (!dsc) { 1801 BREAK_TO_DEBUGGER(); 1802 return NULL; 1803 } 1804 1805 #undef REG_STRUCT 1806 #define REG_STRUCT dsc_regs 1807 dsc_regs_init(0), 1808 dsc_regs_init(1), 1809 dsc_regs_init(2), 1810 dsc_regs_init(3); 1811 1812 dsc60_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); 1813 1814 //dsc->max_image_width = 6016; 1815 dsc->max_image_width = 5760; 1816 1817 return &dsc->base; 1818 } 1819 1820 static void dcn60_destroy_resource_pool(struct resource_pool **pool) 1821 { 1822 struct dcn60_resource_pool *dcn60_pool = TO_DCN60_RES_POOL(*pool); 1823 1824 dcn60_resource_destruct(dcn60_pool); 1825 kfree(dcn60_pool); 1826 *pool = NULL; 1827 } 1828 1829 static struct dc_cap_funcs cap_funcs = { 1830 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap, 1831 }; 1832 1833 static void dcn60_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params) 1834 { 1835 (void)bw_params; 1836 dc_assert_fp_enabled(); 1837 1838 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2) 1839 dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2); 1840 1841 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source) 1842 dml2_reinit(dc, &dc->dml2_dc_power_options, &dc->current_state->bw_ctx.dml2_dc_power_source); 1843 } 1844 1845 static void dcn60_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) 1846 { 1847 DC_FP_START(); 1848 dcn60_update_bw_bounding_box_fpu(dc, bw_params); 1849 DC_FP_END(); 1850 } 1851 1852 static void dcn60_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) 1853 { 1854 const struct dc_stream_state *stream = pipe_ctx->stream; 1855 struct dc_link *link = stream->link; 1856 struct link_encoder *link_enc = NULL; 1857 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params; 1858 1859 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz; 1860 1861 link_enc = link_enc_cfg_get_link_enc(link); 1862 if (link_enc) 1863 pixel_clk_params->encoder_object_id = link_enc->id; 1864 1865 pixel_clk_params->signal_type = pipe_ctx->stream->signal; 1866 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; 1867 /* TODO: un-hardcode*/ 1868 1869 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */ 1870 1871 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW * 1872 LINK_RATE_REF_FREQ_IN_KHZ; 1873 pixel_clk_params->flags.ENABLE_SS = 0; 1874 pixel_clk_params->color_depth = 1875 stream->timing.display_color_depth; 1876 pixel_clk_params->flags.DISPLAY_BLANKED = 1; 1877 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; 1878 1879 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 1880 pixel_clk_params->color_depth = COLOR_DEPTH_888; 1881 1882 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) 1883 pixel_clk_params->requested_pix_clk_100hz *= 2; 1884 if (dc_is_tmds_signal(stream->signal) && 1885 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1886 pixel_clk_params->requested_pix_clk_100hz /= 2; 1887 1888 pipe_ctx->clock_source->funcs->get_pix_clk_dividers( 1889 pipe_ctx->clock_source, 1890 &pipe_ctx->stream_res.pix_clk_params, 1891 &pipe_ctx->pll_settings); 1892 1893 pixel_clk_params->dio_se_pix_per_cycle = 1; 1894 if (dc_is_tmds_signal(stream->signal) && 1895 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1896 pixel_clk_params->dio_se_pix_per_cycle = 2; 1897 } else if (dc_is_dp_signal(stream->signal)) { 1898 /* round up to nearest power of 2, or max at 8 pixels per cycle */ 1899 if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1900 pixel_clk_params->dio_se_pix_per_cycle = 8; 1901 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1902 pixel_clk_params->dio_se_pix_per_cycle = 4; 1903 } else if (pixel_clk_params->requested_pix_clk_100hz > (uint32_t)(stream->ctx->dc->clk_mgr->dprefclk_khz * 10)) { 1904 pixel_clk_params->dio_se_pix_per_cycle = 2; 1905 } else { 1906 pixel_clk_params->dio_se_pix_per_cycle = 1; 1907 } 1908 } 1909 } 1910 1911 static int dcn60_get_power_profile(const struct dc_state *context) 1912 { 1913 unsigned int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; 1914 int dpm_level = 0; 1915 1916 for (unsigned int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { 1917 if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || 1918 uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) 1919 break; 1920 if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) 1921 dpm_level++; 1922 } 1923 1924 return dpm_level; 1925 } 1926 1927 static struct resource_funcs dcn60_res_pool_funcs = { 1928 .destroy = dcn60_destroy_resource_pool, 1929 .link_enc_create = dcn60_link_encoder_create, 1930 .link_enc_create_minimal = NULL, 1931 .hpo_frl_link_enc_create = dcn60_hpo_frl_link_encoder_create, 1932 .panel_cntl_create = dcn32_panel_cntl_create, 1933 .validate_bandwidth = dcn401_validate_bandwidth, 1934 .calculate_wm_and_dlg = NULL, 1935 .populate_dml_pipes = NULL, 1936 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe, 1937 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, 1938 .release_pipe = dcn20_release_pipe, 1939 .add_stream_to_ctx = dcn30_add_stream_to_ctx, 1940 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, 1941 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, 1942 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, 1943 .set_mcif_arb_params = dcn30_set_mcif_arb_params, 1944 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link, 1945 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut, 1946 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut, 1947 .update_bw_bounding_box = dcn60_update_bw_bounding_box, 1948 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state, 1949 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, 1950 .add_phantom_pipes = dcn32_add_phantom_pipes, 1951 .build_pipe_pix_clk_params = dcn60_build_pipe_pix_clk_params, 1952 .get_power_profile = dcn60_get_power_profile, 1953 .program_mcache_pipe_config = dcn60_program_mcache_pipe_config, 1954 .get_default_tiling_info = dcn401_get_default_tiling_info 1955 }; 1956 1957 static uint32_t read_pipe_fuses(struct dc_context *ctx) 1958 { 1959 (void)ctx; 1960 uint32_t value = 0; // CC_DC_PIPE_DIS in DCN6 only indicates DCN IP full fuse, not per pipe fuse 1961 return value; 1962 } 1963 1964 static bool dcn60_resource_construct( 1965 uint8_t num_virtual_links, 1966 struct dc *dc, 1967 struct dcn60_resource_pool *pool) 1968 { 1969 int i; 1970 unsigned int j; 1971 struct dc_context *ctx = dc->ctx; 1972 struct irq_service_init_data init_data; 1973 struct ddc_service_init_data ddc_init_data = {0}; 1974 uint32_t pipe_fuses = 0; 1975 uint32_t num_pipes = 4; 1976 bool is_lite3 = 1977 ASICREV_IS_DCN6_VARIANT_LITE3(ctx->asic_id.hw_internal_rev); 1978 1979 #undef REG_STRUCT 1980 #define REG_STRUCT bios_regs 1981 bios_regs_init(); 1982 1983 #undef REG_STRUCT 1984 #define REG_STRUCT clk_src_regs 1985 clk_src_regs_init(0, A), 1986 clk_src_regs_init(1, B), 1987 clk_src_regs_init(2, C), 1988 clk_src_regs_init(3, D); 1989 1990 #undef REG_STRUCT 1991 #define REG_STRUCT abm_regs 1992 abm_regs_init(0), 1993 abm_regs_init(1), 1994 abm_regs_init(2), 1995 abm_regs_init(3); 1996 1997 #undef REG_STRUCT 1998 #define REG_STRUCT dccg_regs 1999 dccg_regs_init(); 2000 2001 ctx->dc_bios->regs = &bios_regs; 2002 2003 pool->base.res_cap = &res_cap_dcn6_0; 2004 2005 /* max number of pipes for ASIC before checking for pipe fuses */ 2006 num_pipes = pool->base.res_cap->num_timing_generator; 2007 pipe_fuses = read_pipe_fuses(ctx); 2008 2009 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) 2010 if (pipe_fuses & 1 << i) 2011 num_pipes--; 2012 2013 if (pipe_fuses & 1) 2014 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional! 2015 2016 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK) 2017 ASSERT(0); //Entire DCN is harvested! 2018 2019 pool->base.funcs = &dcn60_res_pool_funcs; 2020 2021 /************************************************* 2022 * Resource + asic cap harcoding * 2023 *************************************************/ 2024 pool->base.underlay_pipe_index = (unsigned int)NO_UNDERLAY_PIPE; 2025 pool->base.timing_generator_count = num_pipes; 2026 pool->base.pipe_count = num_pipes; 2027 pool->base.mpcc_count = num_pipes; 2028 dc->caps.max_downscale_ratio = 600; 2029 dc->caps.i2c_speed_in_khz = 95; 2030 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/ 2031 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/ 2032 dc->caps.max_cursor_size = 64; 2033 dc->caps.cursor_not_scaled = true; 2034 dc->caps.min_horizontal_blanking_period = 80; 2035 dc->caps.dmdata_alloc_size = 2048; 2036 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; 2037 dc->caps.cache_line_size = 64; 2038 dc->caps.cache_num_ways = 16; 2039 2040 dc->caps.max_slave_planes = 3; 2041 dc->caps.max_slave_yuv_planes = 3; 2042 dc->caps.max_slave_rgb_planes = 3; 2043 dc->caps.post_blend_color_processing = true; 2044 dc->caps.force_dp_tps4_for_cp2520 = true; 2045 dc->caps.hdmi_hpo = true; 2046 dc->caps.dp_hpo = true; 2047 dc->caps.dp_hdmi21_pcon_support = true; 2048 dc->caps.edp_dsc_support = true; 2049 dc->caps.extended_aux_timeout_support = true; 2050 dc->caps.dmcub_support = true; 2051 dc->caps.utm_support = true; 2052 dc->caps.max_v_total = (1 << 15) - 1; 2053 2054 pool->base.ctx = ctx; 2055 2056 if (dc->config.lsdma_peak_bw_contention_support) { 2057 pool->base.lsdma_scratch.buffer = dm_helpers_allocate_gpu_mem(ctx, 2058 DC_MEM_ALLOC_TYPE_GART, LSDMA_CONTENTION_BUFFER_SIZE, 2059 &pool->base.lsdma_scratch.pa); 2060 if (pool->base.lsdma_scratch.buffer) 2061 pool->base.lsdma_scratch.size = LSDMA_CONTENTION_BUFFER_SIZE; 2062 } 2063 2064 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) 2065 dc->caps.dcc_plane_width_limit = 7680; 2066 2067 /* Color pipeline capabilities */ 2068 dc->caps.color.dpp.dcn_arch = 1; 2069 dc->caps.color.dpp.input_lut_shared = 0; 2070 dc->caps.color.dpp.icsc = 1; 2071 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr 2072 dc->caps.color.dpp.dgam_rom_caps.srgb = 1; 2073 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1; 2074 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1; 2075 dc->caps.color.dpp.dgam_rom_caps.pq = 1; 2076 dc->caps.color.dpp.dgam_rom_caps.hlg = 1; 2077 dc->caps.color.dpp.post_csc = 1; 2078 dc->caps.color.dpp.gamma_corr = 1; 2079 dc->caps.color.dpp.dgam_rom_for_yuv = 0; 2080 dc->caps.color.dpp.upsp_pre_scaler = 1; 2081 2082 dc->caps.color.dpp.hw_3d_lut = 0; 2083 dc->caps.color.dpp.ogam_ram = 0; 2084 // no OGAM ROM on DCN2 and later ASICs 2085 dc->caps.color.dpp.ogam_rom_caps.srgb = 0; 2086 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0; 2087 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0; 2088 dc->caps.color.dpp.ogam_rom_caps.pq = 0; 2089 dc->caps.color.dpp.ogam_rom_caps.hlg = 0; 2090 dc->caps.color.dpp.ocsc = 0; 2091 2092 dc->caps.color.mpc.gamut_remap = 1; 2093 dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC 2094 dc->caps.color.mpc.ogam_ram = 1; 2095 dc->caps.color.mpc.ogam_rom_caps.srgb = 0; 2096 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0; 2097 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0; 2098 dc->caps.color.mpc.ogam_rom_caps.pq = 0; 2099 dc->caps.color.mpc.ogam_rom_caps.hlg = 0; 2100 dc->caps.color.mpc.ocsc = 1; 2101 dc->caps.color.mpc.preblend = true; 2102 dc->caps.color.mpc.max_gamut_remap_coeff = dc_fixpt_from_fraction(S3D12_MAX, DIVIDER); 2103 /* HACK: Force FRL support until BIOS is ready. */ 2104 dc->config.force_hdmi21_frl_enc_enable = true; 2105 dc->config.use_spl = true; 2106 dc->config.prefer_easf = true; 2107 2108 dc->config.dcn_sharpness_range.sdr_rgb_min = 0; 2109 dc->config.dcn_sharpness_range.sdr_rgb_max = 1750; 2110 dc->config.dcn_sharpness_range.sdr_rgb_mid = 750; 2111 dc->config.dcn_sharpness_range.sdr_yuv_min = 0; 2112 dc->config.dcn_sharpness_range.sdr_yuv_max = 3500; 2113 dc->config.dcn_sharpness_range.sdr_yuv_mid = 1500; 2114 dc->config.dcn_sharpness_range.hdr_rgb_min = 0; 2115 dc->config.dcn_sharpness_range.hdr_rgb_max = 2750; 2116 dc->config.dcn_sharpness_range.hdr_rgb_mid = 1500; 2117 2118 dc->config.dcn_override_sharpness_range.sdr_rgb_min = 0; 2119 dc->config.dcn_override_sharpness_range.sdr_rgb_max = 3250; 2120 dc->config.dcn_override_sharpness_range.sdr_rgb_mid = 1250; 2121 dc->config.dcn_override_sharpness_range.sdr_yuv_min = 0; 2122 dc->config.dcn_override_sharpness_range.sdr_yuv_max = 3500; 2123 dc->config.dcn_override_sharpness_range.sdr_yuv_mid = 1500; 2124 dc->config.dcn_override_sharpness_range.hdr_rgb_min = 0; 2125 dc->config.dcn_override_sharpness_range.hdr_rgb_max = 2750; 2126 dc->config.dcn_override_sharpness_range.hdr_rgb_mid = 1500; 2127 2128 dc->config.enable_cursor_offload = true; 2129 dc->config.dc_mode_clk_limit_support = true; 2130 dc->config.enable_windowed_mpo_odm = true; 2131 dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */ 2132 dc->config.dp_connector_no_native_i2c = true; 2133 dc->caps.fused_io_supported = true; 2134 /* read VBIOS LTTPR caps */ 2135 { 2136 if (ctx->dc_bios->funcs->get_lttpr_caps) { 2137 enum bp_result bp_query_result; 2138 uint8_t is_vbios_lttpr_enable = 0; 2139 2140 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable); 2141 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable; 2142 } 2143 2144 /* interop bit is implicit */ 2145 { 2146 dc->caps.vbios_lttpr_aware = true; 2147 } 2148 } 2149 dc->check_config = config_defaults; 2150 2151 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) 2152 dc->debug = debug_defaults_drv; 2153 2154 // Init the vm_helper 2155 if (dc->vm_helper) 2156 vm_helper_init(dc->vm_helper, 16); 2157 2158 /************************************************* 2159 * Create resources * 2160 *************************************************/ 2161 2162 /* Clock Sources for Pixel Clock*/ 2163 pool->base.clock_sources[DCN60_CLK_SRC_PLL0] = 2164 dcn60_clock_source_create(ctx, ctx->dc_bios, 2165 CLOCK_SOURCE_COMBO_PHY_PLL0, 2166 &clk_src_regs[0], false); 2167 pool->base.clock_sources[DCN60_CLK_SRC_PLL1] = 2168 dcn60_clock_source_create(ctx, ctx->dc_bios, 2169 CLOCK_SOURCE_COMBO_PHY_PLL1, 2170 &clk_src_regs[1], false); 2171 pool->base.clock_sources[DCN60_CLK_SRC_PLL2] = 2172 dcn60_clock_source_create(ctx, ctx->dc_bios, 2173 CLOCK_SOURCE_COMBO_PHY_PLL2, 2174 &clk_src_regs[2], false); 2175 pool->base.clock_sources[DCN60_CLK_SRC_PLL3] = 2176 dcn60_clock_source_create(ctx, ctx->dc_bios, 2177 CLOCK_SOURCE_COMBO_PHY_PLL3, 2178 &clk_src_regs[3], false); 2179 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] = 2180 // dcn60_clock_source_create(ctx, ctx->dc_bios, 2181 // CLOCK_SOURCE_COMBO_PHY_PLL4, 2182 // &clk_src_regs[4], false); 2183 2184 pool->base.clk_src_count = DCN60_CLK_SRC_TOTAL; 2185 2186 /* todo: not reuse phy_pll registers */ 2187 pool->base.dp_clock_source = 2188 dcn60_clock_source_create(ctx, ctx->dc_bios, 2189 CLOCK_SOURCE_ID_DP_DTO, 2190 &clk_src_regs[0], true); 2191 2192 for (i = 0; i < (int)pool->base.clk_src_count; i++) { 2193 if (pool->base.clock_sources[i] == NULL) { 2194 dm_error("DC: failed to create clock sources!\n"); 2195 BREAK_TO_DEBUGGER(); 2196 goto create_fail; 2197 } 2198 } 2199 2200 /* DCCG */ 2201 pool->base.dccg = dccg60_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask); 2202 if (pool->base.dccg == NULL) { 2203 dm_error("DC: failed to create dccg!\n"); 2204 BREAK_TO_DEBUGGER(); 2205 goto create_fail; 2206 } 2207 2208 /* IRQ Service */ 2209 init_data.ctx = dc->ctx; 2210 pool->base.irqs = dal_irq_service_dcn60_create(&init_data); 2211 if (!pool->base.irqs) 2212 goto create_fail; 2213 2214 /* HUBBUB */ 2215 pool->base.hubbub = dcn60_hubbub_create(ctx); 2216 if (pool->base.hubbub == NULL) { 2217 BREAK_TO_DEBUGGER(); 2218 dm_error("DC: failed to create hubbub!\n"); 2219 goto create_fail; 2220 } 2221 2222 /* HUBPs, DPPs, OPPs, TGs, ABMs */ 2223 for (i = 0, j = 0; i < (int)pool->base.res_cap->num_timing_generator; i++) { 2224 2225 /* if pipe is disabled, skip instance of HW pipe, 2226 * i.e, skip ASIC register instance 2227 */ 2228 if (pipe_fuses & 1 << i) 2229 continue; 2230 pool->base.hubps[j] = dcn60_hubp_create(ctx, i); 2231 if (pool->base.hubps[j] == NULL) { 2232 BREAK_TO_DEBUGGER(); 2233 dm_error( 2234 "DC: failed to create hubps!\n"); 2235 goto create_fail; 2236 } 2237 2238 pool->base.dpps[j] = dcn60_dpp_create(ctx, i); 2239 if (pool->base.dpps[j] == NULL) { 2240 BREAK_TO_DEBUGGER(); 2241 dm_error( 2242 "DC: failed to create dpps!\n"); 2243 goto create_fail; 2244 } 2245 2246 pool->base.opps[j] = dcn60_opp_create(ctx, i); 2247 if (pool->base.opps[j] == NULL) { 2248 BREAK_TO_DEBUGGER(); 2249 dm_error( 2250 "DC: failed to create output pixel processor!\n"); 2251 goto create_fail; 2252 } 2253 2254 pool->base.timing_generators[j] = dcn60_timing_generator_create( 2255 ctx, i); 2256 if (pool->base.timing_generators[j] == NULL) { 2257 BREAK_TO_DEBUGGER(); 2258 dm_error("DC: failed to create tg!\n"); 2259 goto create_fail; 2260 } 2261 2262 pool->base.multiple_abms[j] = dmub_abm_create(ctx, 2263 &abm_regs[i], 2264 &abm_shift, 2265 &abm_mask); 2266 if (pool->base.multiple_abms[j] == NULL) { 2267 dm_error("DC: failed to create abm for pipe %d!\n", i); 2268 BREAK_TO_DEBUGGER(); 2269 goto create_fail; 2270 } 2271 2272 /* index for resource pool arrays for next valid pipe */ 2273 j++; 2274 } 2275 2276 /* PSR */ 2277 pool->base.psr = dmub_psr_create(ctx); 2278 if (pool->base.psr == NULL) { 2279 dm_error("DC: failed to create psr obj!\n"); 2280 BREAK_TO_DEBUGGER(); 2281 goto create_fail; 2282 } 2283 2284 /* MPCCs */ 2285 pool->base.mpc = dcn60_mpc_create(ctx, pool->base.res_cap->num_timing_generator, 2286 pool->base.res_cap->num_mpc_3dlut); 2287 if (pool->base.mpc == NULL) { 2288 BREAK_TO_DEBUGGER(); 2289 dm_error("DC: failed to create mpc!\n"); 2290 goto create_fail; 2291 } 2292 2293 /* RMCMs */ 2294 for (i = 0; i < pool->base.res_cap->num_rmcm && i < MAX_RMCM_INST; i++) { 2295 pool->base.rmcm[i] = dcn60_rmcm_create(ctx, i); 2296 if (pool->base.rmcm[i] == NULL) { 2297 BREAK_TO_DEBUGGER(); 2298 dm_error("DC: failed to create rmcm%d!\n", i); 2299 goto create_fail; 2300 } 2301 } 2302 2303 /* DSCs */ 2304 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { 2305 pool->base.dscs[i] = dcn60_dsc_create(ctx, i); 2306 if (pool->base.dscs[i] == NULL) { 2307 BREAK_TO_DEBUGGER(); 2308 dm_error("DC: failed to create display stream compressor %d!\n", i); 2309 goto create_fail; 2310 } 2311 } 2312 2313 /* AUX */ 2314 for (i = 0; i < pool->base.res_cap->num_aux; i++) { 2315 pool->base.engines[i] = dcn60_aux_engine_create(ctx, i); 2316 if (pool->base.engines[i] == NULL) { 2317 BREAK_TO_DEBUGGER(); 2318 dm_error( 2319 "DC:failed to create aux engine!!\n"); 2320 goto create_fail; 2321 } 2322 } 2323 2324 /* I2C */ 2325 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 2326 pool->base.hw_i2cs[i] = dcn60_i2c_hw_create(ctx, i); 2327 if (pool->base.hw_i2cs[i] == NULL) { 2328 BREAK_TO_DEBUGGER(); 2329 dm_error( 2330 "DC:failed to create hw i2c!!\n"); 2331 goto create_fail; 2332 } 2333 pool->base.sw_i2cs[i] = NULL; 2334 } 2335 2336 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */ 2337 if (!resource_construct(num_virtual_links, dc, &pool->base, 2338 &res_create_funcs)) 2339 goto create_fail; 2340 2341 /* HW Sequencer init functions and Plane caps */ 2342 dcn60_hw_sequencer_init_functions(dc); 2343 2344 dc->caps.max_planes = pool->base.pipe_count; 2345 2346 for (i = 0; i < (int)dc->caps.max_planes; ++i) 2347 dc->caps.planes[i] = plane_cap; 2348 2349 dc->caps.max_odm_combine_factor = 4; 2350 2351 dc->cap_funcs = cap_funcs; 2352 2353 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) { 2354 ddc_init_data.ctx = dc->ctx; 2355 ddc_init_data.link = NULL; 2356 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id; 2357 ddc_init_data.id.enum_id = 0; 2358 ddc_init_data.id.type = OBJECT_TYPE_GENERIC; 2359 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data); 2360 } else { 2361 pool->base.oem_device = NULL; 2362 } 2363 2364 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided 2365 if (dc->config.sdpif_request_limit_words_per_umc == 0) 2366 dc->config.sdpif_request_limit_words_per_umc = 16; 2367 2368 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count; 2369 dc->dml2_options.use_native_soc_bb_construction = true; 2370 dc->dml2_options.minimize_dispclk_using_odm = true; 2371 dc->dml2_options.map_dc_pipes_with_callbacks = true; 2372 dc->dml2_options.force_tdlut_enable = true; 2373 2374 resource_init_common_dml2_callbacks(dc, &dc->dml2_options); 2375 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = 2376 &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch; 2377 2378 dc->dml2_options.max_segments_per_hubp = 20; 2379 dc->dml2_options.det_segment_size = DCN6_0_CRB_SEGMENT_SIZE_KB; 2380 if (is_lite3) { 2381 dc->dml2_options.gpuvm_enable = true; 2382 dc->dml2_options.hostvm_enable = true; 2383 } 2384 2385 /* SPL */ 2386 dc->caps.scl_caps.sharpener_support = true; 2387 2388 /* init DC limited DML2 options */ 2389 memcpy(&dc->dml2_dc_power_options, &dc->dml2_options, sizeof(struct dml2_configuration_options)); 2390 dc->dml2_dc_power_options.use_clock_dc_limits = true; 2391 2392 return true; 2393 2394 create_fail: 2395 2396 dcn60_resource_destruct(pool); 2397 2398 return false; 2399 } 2400 2401 struct resource_pool *dcn60_create_resource_pool( 2402 const struct dc_init_data *init_data, 2403 struct dc *dc) 2404 { 2405 struct dcn60_resource_pool *pool = 2406 kzalloc_obj(struct dcn60_resource_pool); 2407 2408 if (!pool) 2409 return NULL; 2410 2411 if (dcn60_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool)) 2412 return &pool->base; 2413 2414 BREAK_TO_DEBUGGER(); 2415 kfree(pool); 2416 return NULL; 2417 } 2418