1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Device Tree Source for AM4372 SoC 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/bus/ti-sysc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/am4.h> 12 13/ { 14 compatible = "ti,am4372", "ti,am43"; 15 interrupt-parent = <&wakeupgen>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 chosen { }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0 0>; 23 }; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 serial0 = &uart0; 30 serial1 = &uart1; 31 serial2 = &uart2; 32 serial3 = &uart3; 33 serial4 = &uart4; 34 serial5 = &uart5; 35 ethernet0 = &cpsw_port1; 36 ethernet1 = &cpsw_port2; 37 spi0 = &qspi; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 cpu: cpu@0 { 44 compatible = "arm,cortex-a9"; 45 enable-method = "ti,am4372"; 46 device_type = "cpu"; 47 reg = <0>; 48 49 clocks = <&dpll_mpu_ck>; 50 clock-names = "cpu"; 51 52 operating-points-v2 = <&cpu0_opp_table>; 53 54 clock-latency = <300000>; /* From omap-cpufreq driver */ 55 cpu-idle-states = <&mpu_gate>; 56 }; 57 58 idle-states { 59 mpu_gate: mpu_gate { 60 compatible = "arm,idle-state"; 61 entry-latency-us = <40>; 62 exit-latency-us = <100>; 63 min-residency-us = <300>; 64 local-timer-stop; 65 }; 66 }; 67 }; 68 69 cpu0_opp_table: opp-table { 70 compatible = "operating-points-v2-ti-cpu"; 71 syscon = <&scm_conf>; 72 73 opp-50-300000000 { 74 /* OPP50 */ 75 opp-hz = /bits/ 64 <300000000>; 76 opp-microvolt = <950000 931000 969000>; 77 opp-supported-hw = <0xFF 0x01>; 78 opp-suspend; 79 }; 80 81 opp-100-600000000 { 82 /* OPP100 */ 83 opp-hz = /bits/ 64 <600000000>; 84 opp-microvolt = <1100000 1078000 1122000>; 85 opp-supported-hw = <0xFF 0x04>; 86 }; 87 88 opp-120-720000000 { 89 /* OPP120 */ 90 opp-hz = /bits/ 64 <720000000>; 91 opp-microvolt = <1200000 1176000 1224000>; 92 opp-supported-hw = <0xFF 0x08>; 93 }; 94 95 opp-800000000 { 96 /* OPP Turbo */ 97 opp-hz = /bits/ 64 <800000000>; 98 opp-microvolt = <1260000 1234800 1285200>; 99 opp-supported-hw = <0xFF 0x10>; 100 }; 101 102 opp-1000000000 { 103 /* OPP Nitro */ 104 opp-hz = /bits/ 64 <1000000000>; 105 opp-microvolt = <1325000 1298500 1351500>; 106 opp-supported-hw = <0xFF 0x20>; 107 }; 108 }; 109 110 soc { 111 compatible = "ti,omap-infra"; 112 }; 113 114 gic: interrupt-controller@48241000 { 115 compatible = "arm,cortex-a9-gic"; 116 interrupt-controller; 117 #interrupt-cells = <3>; 118 reg = <0x48241000 0x1000>, 119 <0x48240100 0x0100>; 120 interrupt-parent = <&gic>; 121 }; 122 123 wakeupgen: interrupt-controller@48281000 { 124 compatible = "ti,omap4-wugen-mpu"; 125 interrupt-controller; 126 #interrupt-cells = <3>; 127 reg = <0x48281000 0x1000>; 128 interrupt-parent = <&gic>; 129 }; 130 131 scu: scu@48240000 { 132 compatible = "arm,cortex-a9-scu"; 133 reg = <0x48240000 0x100>; 134 }; 135 136 global_timer: timer@48240200 { 137 compatible = "arm,cortex-a9-global-timer"; 138 reg = <0x48240200 0x100>; 139 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 140 interrupt-parent = <&gic>; 141 clocks = <&mpu_periphclk>; 142 }; 143 144 local_timer: timer@48240600 { 145 compatible = "arm,cortex-a9-twd-timer"; 146 reg = <0x48240600 0x100>; 147 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 148 interrupt-parent = <&gic>; 149 clocks = <&mpu_periphclk>; 150 }; 151 152 cache-controller@48242000 { 153 compatible = "arm,pl310-cache"; 154 reg = <0x48242000 0x1000>; 155 cache-unified; 156 cache-level = <2>; 157 }; 158 159 ocp@44000000 { 160 compatible = "simple-pm-bus"; 161 power-domains = <&prm_per>; 162 clocks = <&l3_clkctrl AM4_L3_L3_MAIN_CLKCTRL 0>; 163 clock-names = "fck"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges; 167 ti,no-idle; 168 169 l3-noc@44000000 { 170 compatible = "ti,am4372-l3-noc"; 171 reg = <0x44000000 0x400000>, 172 <0x44800000 0x400000>; 173 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 l4_wkup: interconnect@44c00000 { 178 }; 179 l4_per: interconnect@48000000 { 180 }; 181 l4_fast: interconnect@4a000000 { 182 }; 183 184 target-module@4c000000 { 185 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 186 reg = <0x4c000000 0x4>; 187 reg-names = "rev"; 188 clocks = <&emif_clkctrl AM4_EMIF_EMIF_CLKCTRL 0>; 189 clock-names = "fck"; 190 ti,no-idle; 191 #address-cells = <1>; 192 #size-cells = <1>; 193 ranges = <0x0 0x4c000000 0x1000000>; 194 195 emif: emif@0 { 196 compatible = "ti,emif-am4372"; 197 reg = <0 0x1000000>; 198 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 199 sram = <&pm_sram_code 200 &pm_sram_data>; 201 }; 202 }; 203 204 target-module@49000000 { 205 compatible = "ti,sysc-omap4", "ti,sysc"; 206 reg = <0x49000000 0x4>; 207 reg-names = "rev"; 208 clocks = <&l3_clkctrl AM4_L3_TPCC_CLKCTRL 0>; 209 clock-names = "fck"; 210 #address-cells = <1>; 211 #size-cells = <1>; 212 ranges = <0x0 0x49000000 0x10000>; 213 214 edma: dma@0 { 215 compatible = "ti,edma3-tpcc"; 216 reg = <0 0x10000>; 217 reg-names = "edma3_cc"; 218 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "edma3_ccint", "edma3_mperr", 222 "edma3_ccerrint"; 223 dma-requests = <64>; 224 #dma-cells = <2>; 225 226 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 227 <&edma_tptc2 0>; 228 229 ti,edma-memcpy-channels = <58 59>; 230 }; 231 }; 232 233 target-module@49800000 { 234 compatible = "ti,sysc-omap4", "ti,sysc"; 235 reg = <0x49800000 0x4>, 236 <0x49800010 0x4>; 237 reg-names = "rev", "sysc"; 238 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 239 ti,sysc-midle = <SYSC_IDLE_FORCE>; 240 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 241 <SYSC_IDLE_SMART>; 242 clocks = <&l3_clkctrl AM4_L3_TPTC0_CLKCTRL 0>; 243 clock-names = "fck"; 244 #address-cells = <1>; 245 #size-cells = <1>; 246 ranges = <0x0 0x49800000 0x100000>; 247 248 edma_tptc0: dma@0 { 249 compatible = "ti,edma3-tptc"; 250 reg = <0 0x100000>; 251 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "edma3_tcerrint"; 253 }; 254 }; 255 256 target-module@49900000 { 257 compatible = "ti,sysc-omap4", "ti,sysc"; 258 reg = <0x49900000 0x4>, 259 <0x49900010 0x4>; 260 reg-names = "rev", "sysc"; 261 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 262 ti,sysc-midle = <SYSC_IDLE_FORCE>; 263 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 264 <SYSC_IDLE_SMART>; 265 clocks = <&l3_clkctrl AM4_L3_TPTC1_CLKCTRL 0>; 266 clock-names = "fck"; 267 #address-cells = <1>; 268 #size-cells = <1>; 269 ranges = <0x0 0x49900000 0x100000>; 270 271 edma_tptc1: dma@0 { 272 compatible = "ti,edma3-tptc"; 273 reg = <0 0x100000>; 274 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 275 interrupt-names = "edma3_tcerrint"; 276 }; 277 }; 278 279 target-module@49a00000 { 280 compatible = "ti,sysc-omap4", "ti,sysc"; 281 reg = <0x49a00000 0x4>, 282 <0x49a00010 0x4>; 283 reg-names = "rev", "sysc"; 284 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>; 285 ti,sysc-midle = <SYSC_IDLE_FORCE>; 286 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 287 <SYSC_IDLE_SMART>; 288 clocks = <&l3_clkctrl AM4_L3_TPTC2_CLKCTRL 0>; 289 clock-names = "fck"; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0x0 0x49a00000 0x100000>; 293 294 edma_tptc2: dma@0 { 295 compatible = "ti,edma3-tptc"; 296 reg = <0 0x100000>; 297 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 298 interrupt-names = "edma3_tcerrint"; 299 }; 300 }; 301 302 target-module@47810000 { 303 compatible = "ti,sysc-omap2", "ti,sysc"; 304 reg = <0x478102fc 0x4>, 305 <0x47810110 0x4>, 306 <0x47810114 0x4>; 307 reg-names = "rev", "sysc", "syss"; 308 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | 309 SYSC_OMAP2_ENAWAKEUP | 310 SYSC_OMAP2_SOFTRESET | 311 SYSC_OMAP2_AUTOIDLE)>; 312 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 313 <SYSC_IDLE_NO>, 314 <SYSC_IDLE_SMART>; 315 ti,syss-mask = <1>; 316 clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>; 317 clock-names = "fck"; 318 #address-cells = <1>; 319 #size-cells = <1>; 320 ranges = <0x0 0x47810000 0x1000>; 321 322 mmc3: mmc@0 { 323 compatible = "ti,am437-sdhci"; 324 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 325 reg = <0x0 0x1000>; 326 status = "disabled"; 327 }; 328 }; 329 330 sham_target: target-module@53100000 { 331 compatible = "ti,sysc-omap3-sham", "ti,sysc"; 332 reg = <0x53100100 0x4>, 333 <0x53100110 0x4>, 334 <0x53100114 0x4>; 335 reg-names = "rev", "sysc", "syss"; 336 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 337 SYSC_OMAP2_AUTOIDLE)>; 338 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 339 <SYSC_IDLE_NO>, 340 <SYSC_IDLE_SMART>; 341 ti,syss-mask = <1>; 342 /* Domains (P, C): per_pwrdm, l3_clkdm */ 343 clocks = <&l3_clkctrl AM4_L3_SHAM_CLKCTRL 0>; 344 clock-names = "fck"; 345 #address-cells = <1>; 346 #size-cells = <1>; 347 ranges = <0x0 0x53100000 0x1000>; 348 349 sham: sham@0 { 350 compatible = "ti,omap5-sham"; 351 reg = <0 0x300>; 352 dmas = <&edma 36 0>; 353 dma-names = "rx"; 354 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 355 }; 356 }; 357 358 aes_target: target-module@53501000 { 359 compatible = "ti,sysc-omap2", "ti,sysc"; 360 reg = <0x53501080 0x4>, 361 <0x53501084 0x4>, 362 <0x53501088 0x4>; 363 reg-names = "rev", "sysc", "syss"; 364 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 365 SYSC_OMAP2_AUTOIDLE)>; 366 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 367 <SYSC_IDLE_NO>, 368 <SYSC_IDLE_SMART>, 369 <SYSC_IDLE_SMART_WKUP>; 370 ti,syss-mask = <1>; 371 /* Domains (P, C): per_pwrdm, l3_clkdm */ 372 clocks = <&l3_clkctrl AM4_L3_AES_CLKCTRL 0>; 373 clock-names = "fck"; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x0 0x53501000 0x1000>; 377 378 aes: aes@0 { 379 compatible = "ti,omap4-aes"; 380 reg = <0 0xa0>; 381 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 382 dmas = <&edma 6 0>, 383 <&edma 5 0>; 384 dma-names = "tx", "rx"; 385 }; 386 }; 387 388 des_target: target-module@53701000 { 389 compatible = "ti,sysc-omap2", "ti,sysc"; 390 reg = <0x53701030 0x4>, 391 <0x53701034 0x4>, 392 <0x53701038 0x4>; 393 reg-names = "rev", "sysc", "syss"; 394 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | 395 SYSC_OMAP2_AUTOIDLE)>; 396 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 397 <SYSC_IDLE_NO>, 398 <SYSC_IDLE_SMART>, 399 <SYSC_IDLE_SMART_WKUP>; 400 ti,syss-mask = <1>; 401 /* Domains (P, C): per_pwrdm, l3_clkdm */ 402 clocks = <&l3_clkctrl AM4_L3_DES_CLKCTRL 0>; 403 clock-names = "fck"; 404 #address-cells = <1>; 405 #size-cells = <1>; 406 ranges = <0 0x53701000 0x1000>; 407 408 des: des@0 { 409 compatible = "ti,omap4-des"; 410 reg = <0 0xa0>; 411 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 412 dmas = <&edma 34 0>, 413 <&edma 33 0>; 414 dma-names = "tx", "rx"; 415 }; 416 }; 417 418 pruss_tm: target-module@54400000 { 419 compatible = "ti,sysc-pruss", "ti,sysc"; 420 reg = <0x54426000 0x4>, 421 <0x54426004 0x4>; 422 reg-names = "rev", "sysc"; 423 ti,sysc-mask = <(SYSC_PRUSS_STANDBY_INIT | 424 SYSC_PRUSS_SUB_MWAIT)>; 425 ti,sysc-midle = <SYSC_IDLE_FORCE>, 426 <SYSC_IDLE_NO>, 427 <SYSC_IDLE_SMART>; 428 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 429 <SYSC_IDLE_NO>, 430 <SYSC_IDLE_SMART>; 431 clocks = <&pruss_ocp_clkctrl AM4_PRUSS_OCP_PRUSS_CLKCTRL 0>; 432 clock-names = "fck"; 433 resets = <&prm_per 1>; 434 reset-names = "rstctrl"; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 ranges = <0x0 0x54400000 0x80000>; 438 439 pruss1: pruss@0 { 440 compatible = "ti,am4376-pruss1"; 441 reg = <0x0 0x40000>; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges; 445 446 pruss1_mem: memories@0 { 447 reg = <0x0 0x2000>, 448 <0x2000 0x2000>, 449 <0x10000 0x8000>; 450 reg-names = "dram0", "dram1", 451 "shrdram2"; 452 }; 453 454 pruss1_cfg: cfg@26000 { 455 compatible = "ti,pruss-cfg", "syscon"; 456 reg = <0x26000 0x2000>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 ranges = <0x0 0x26000 0x2000>; 460 461 clocks { 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 pruss1_iepclk_mux: iepclk-mux@30 { 466 reg = <0x30>; 467 #clock-cells = <0>; 468 clocks = <&sysclk_div>, /* icss_iep_gclk */ 469 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 470 }; 471 }; 472 }; 473 474 pruss1_mii_rt: mii-rt@32000 { 475 compatible = "ti,pruss-mii", "syscon"; 476 reg = <0x32000 0x58>; 477 }; 478 479 pruss1_intc: interrupt-controller@20000 { 480 compatible = "ti,pruss-intc"; 481 reg = <0x20000 0x2000>; 482 interrupt-controller; 483 #interrupt-cells = <3>; 484 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-names = "host_intr0", "host_intr1", 492 "host_intr2", "host_intr3", 493 "host_intr4", 494 "host_intr6", "host_intr7"; 495 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 496 }; 497 498 pru1_0: pru@34000 { 499 compatible = "ti,am4376-pru"; 500 reg = <0x34000 0x3000>, 501 <0x22000 0x400>, 502 <0x22400 0x100>; 503 reg-names = "iram", "control", "debug"; 504 firmware-name = "am437x-pru1_0-fw"; 505 }; 506 507 pru1_1: pru@38000 { 508 compatible = "ti,am4376-pru"; 509 reg = <0x38000 0x3000>, 510 <0x24000 0x400>, 511 <0x24400 0x100>; 512 reg-names = "iram", "control", "debug"; 513 firmware-name = "am437x-pru1_1-fw"; 514 }; 515 516 pruss1_mdio: mdio@32400 { 517 compatible = "ti,davinci_mdio"; 518 reg = <0x32400 0x90>; 519 clocks = <&dpll_core_m4_ck>; 520 clock-names = "fck"; 521 bus_freq = <1000000>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 }; 525 }; 526 527 pruss0: pruss@40000 { 528 compatible = "ti,am4376-pruss0"; 529 reg = <0x40000 0x40000>; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 534 pruss0_mem: memories@40000 { 535 reg = <0x40000 0x1000>, 536 <0x42000 0x1000>; 537 reg-names = "dram0", "dram1"; 538 }; 539 540 pruss0_cfg: cfg@66000 { 541 compatible = "ti,pruss-cfg", "syscon"; 542 reg = <0x66000 0x2000>; 543 #address-cells = <1>; 544 #size-cells = <1>; 545 ranges = <0x0 0x66000 0x2000>; 546 547 clocks { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 pruss0_iepclk_mux: iepclk-mux@30 { 552 reg = <0x30>; 553 #clock-cells = <0>; 554 clocks = <&sysclk_div>, /* icss_iep_gclk */ 555 <&pruss_ocp_gclk>; /* icss_ocp_gclk */ 556 }; 557 }; 558 }; 559 560 pruss0_mii_rt: mii-rt@72000 { 561 compatible = "ti,pruss-mii", "syscon"; 562 reg = <0x72000 0x58>; 563 status = "disabled"; 564 }; 565 566 pruss0_intc: interrupt-controller@60000 { 567 compatible = "ti,pruss-intc"; 568 reg = <0x60000 0x2000>; 569 interrupt-controller; 570 #interrupt-cells = <3>; 571 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 575 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 576 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 577 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 578 interrupt-names = "host_intr0", "host_intr1", 579 "host_intr2", "host_intr3", 580 "host_intr4", 581 "host_intr6", "host_intr7"; 582 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */ 583 }; 584 585 pru0_0: pru@74000 { 586 compatible = "ti,am4376-pru"; 587 reg = <0x74000 0x1000>, 588 <0x62000 0x400>, 589 <0x62400 0x100>; 590 reg-names = "iram", "control", "debug"; 591 firmware-name = "am437x-pru0_0-fw"; 592 }; 593 594 pru0_1: pru@78000 { 595 compatible = "ti,am4376-pru"; 596 reg = <0x78000 0x1000>, 597 <0x64000 0x400>, 598 <0x64400 0x100>; 599 reg-names = "iram", "control", "debug"; 600 firmware-name = "am437x-pru0_1-fw"; 601 }; 602 }; 603 }; 604 605 target-module@50000000 { 606 compatible = "ti,sysc-omap2", "ti,sysc"; 607 reg = <0x50000000 4>, 608 <0x50000010 4>, 609 <0x50000014 4>; 610 reg-names = "rev", "sysc", "syss"; 611 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 612 <SYSC_IDLE_NO>, 613 <SYSC_IDLE_SMART>; 614 ti,syss-mask = <1>; 615 clocks = <&l3s_clkctrl AM4_L3S_GPMC_CLKCTRL 0>; 616 clock-names = "fck"; 617 #address-cells = <1>; 618 #size-cells = <1>; 619 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */ 620 <0x00000000 0x00000000 0x40000000>; /* data */ 621 622 gpmc: gpmc@50000000 { 623 compatible = "ti,am3352-gpmc"; 624 dmas = <&edma 52 0>; 625 dma-names = "rxtx"; 626 clocks = <&l3s_gclk>; 627 clock-names = "fck"; 628 reg = <0x50000000 0x2000>; 629 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 630 gpmc,num-cs = <7>; 631 gpmc,num-waitpins = <2>; 632 #address-cells = <2>; 633 #size-cells = <1>; 634 interrupt-controller; 635 #interrupt-cells = <2>; 636 gpio-controller; 637 #gpio-cells = <2>; 638 status = "disabled"; 639 }; 640 }; 641 642 target-module@47900000 { 643 compatible = "ti,sysc-omap4", "ti,sysc"; 644 reg = <0x47900000 0x4>, 645 <0x47900010 0x4>; 646 reg-names = "rev", "sysc"; 647 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 648 <SYSC_IDLE_NO>, 649 <SYSC_IDLE_SMART>, 650 <SYSC_IDLE_SMART_WKUP>; 651 clocks = <&l3s_clkctrl AM4_L3S_QSPI_CLKCTRL 0>; 652 clock-names = "fck"; 653 #address-cells = <1>; 654 #size-cells = <1>; 655 ranges = <0x0 0x47900000 0x1000>, 656 <0x30000000 0x30000000 0x4000000>; 657 658 qspi: spi@0 { 659 compatible = "ti,am4372-qspi"; 660 reg = <0 0x100>, 661 <0x30000000 0x4000000>; 662 reg-names = "qspi_base", "qspi_mmap"; 663 clocks = <&dpll_per_m2_div4_ck>; 664 clock-names = "fck"; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 interrupts = <0 138 0x4>; 668 num-cs = <4>; 669 }; 670 }; 671 672 target-module@40300000 { 673 compatible = "ti,sysc-omap4-simple", "ti,sysc"; 674 clocks = <&l3_clkctrl AM4_L3_OCMCRAM_CLKCTRL 0>; 675 clock-names = "fck"; 676 ti,no-idle; 677 #address-cells = <1>; 678 #size-cells = <1>; 679 ranges = <0 0x40300000 0x40000>; 680 681 ocmcram: sram@0 { 682 compatible = "mmio-sram"; 683 reg = <0 0x40000>; /* 256k */ 684 ranges = <0 0 0x40000>; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 688 pm_sram_code: pm-code-sram@0 { 689 compatible = "ti,sram"; 690 reg = <0x0 0x1000>; 691 protect-exec; 692 }; 693 694 pm_sram_data: pm-data-sram@1000 { 695 compatible = "ti,sram"; 696 reg = <0x1000 0x1000>; 697 pool; 698 }; 699 }; 700 }; 701 702 target-module@56000000 { 703 compatible = "ti,sysc-omap4", "ti,sysc"; 704 reg = <0x5600fe00 0x4>, 705 <0x5600fe10 0x4>; 706 reg-names = "rev", "sysc"; 707 ti,sysc-midle = <SYSC_IDLE_FORCE>, 708 <SYSC_IDLE_NO>, 709 <SYSC_IDLE_SMART>; 710 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 711 <SYSC_IDLE_NO>, 712 <SYSC_IDLE_SMART>; 713 clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>; 714 clock-names = "fck"; 715 power-domains = <&prm_gfx>; 716 resets = <&prm_gfx 0>; 717 reset-names = "rstctrl"; 718 #address-cells = <1>; 719 #size-cells = <1>; 720 ranges = <0 0x56000000 0x1000000>; 721 722 gpu@0 { 723 compatible = "ti,omap3630-gpu", "img,powervr-sgx530"; 724 reg = <0x0 0x10000>; /* 64kB */ 725 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 726 }; 727 }; 728 }; 729}; 730 731#include "am437x-l4.dtsi" 732#include "am43xx-clocks.dtsi" 733 734&prcm { 735 prm_mpu: prm@300 { 736 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 737 reg = <0x300 0x100>; 738 #power-domain-cells = <0>; 739 }; 740 741 prm_gfx: prm@400 { 742 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 743 reg = <0x400 0x100>; 744 #power-domain-cells = <0>; 745 #reset-cells = <1>; 746 }; 747 748 prm_rtc: prm@500 { 749 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 750 reg = <0x500 0x100>; 751 #power-domain-cells = <0>; 752 }; 753 754 prm_tamper: prm@600 { 755 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 756 reg = <0x600 0x100>; 757 #power-domain-cells = <0>; 758 }; 759 760 prm_cefuse: prm@700 { 761 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 762 reg = <0x700 0x100>; 763 #power-domain-cells = <0>; 764 }; 765 766 prm_per: prm@800 { 767 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 768 reg = <0x800 0x100>; 769 #reset-cells = <1>; 770 #power-domain-cells = <0>; 771 }; 772 773 prm_wkup: prm@2000 { 774 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 775 reg = <0x2000 0x100>; 776 #reset-cells = <1>; 777 #power-domain-cells = <0>; 778 }; 779 780 prm_device: prm@4000 { 781 compatible = "ti,am4-prm-inst", "ti,omap-prm-inst"; 782 reg = <0x4000 0x100>; 783 #reset-cells = <1>; 784 }; 785}; 786 787/* Preferred always-on timer for clocksource */ 788&timer1_target { 789 ti,no-reset-on-init; 790 ti,no-idle; 791 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_TIMER1_CLKCTRL 0>, 792 <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>; 793 clock-names = "fck", "ick"; 794 timer@0 { 795 assigned-clocks = <&timer1_fck>; 796 assigned-clock-parents = <&sys_clkin_ck>; 797 }; 798}; 799 800/* Preferred timer for clockevent */ 801&timer2_target { 802 ti,no-reset-on-init; 803 ti,no-idle; 804 clocks = <&l4ls_clkctrl AM4_L4LS_TIMER2_CLKCTRL 0>, 805 <&l4ls_clkctrl AM4_L4LS_L4_LS_CLKCTRL 0>; 806 clock-names = "fck", "ick"; 807 timer@0 { 808 assigned-clocks = <&timer2_fck>; 809 assigned-clock-parents = <&sys_clkin_ck>; 810 }; 811}; 812