1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 12#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a78c"; 53 reg = <0x0 0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 capacity-dmips-mhz = <1946>; 59 dynamic-power-coefficient = <472>; 60 #cooling-cells = <2>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 64 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 65 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 66 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 67 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78c"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_1>; 82 power-domains = <&cpu_pd1>; 83 power-domain-names = "psci"; 84 capacity-dmips-mhz = <1946>; 85 #cooling-cells = <2>; 86 dynamic-power-coefficient = <472>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 90 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 91 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 92 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 93 94 l2_1: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_0>; 99 }; 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a78c"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 next-level-cache = <&l2_2>; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 capacity-dmips-mhz = <1946>; 111 #cooling-cells = <2>; 112 dynamic-power-coefficient = <507>; 113 qcom,freq-domain = <&cpufreq_hw 2>; 114 operating-points-v2 = <&cpu2_opp_table>; 115 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 116 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 117 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 118 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 119 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78c"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 next-level-cache = <&l2_3>; 134 power-domains = <&cpu_pd3>; 135 power-domain-names = "psci"; 136 capacity-dmips-mhz = <1946>; 137 #cooling-cells = <2>; 138 dynamic-power-coefficient = <507>; 139 qcom,freq-domain = <&cpufreq_hw 2>; 140 operating-points-v2 = <&cpu2_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 146 l2_3: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu4: cpu@10000 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a55"; 157 reg = <0x0 0x10000>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_4>; 160 power-domains = <&cpu_pd4>; 161 power-domain-names = "psci"; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 operating-points-v2 = <&cpu4_opp_table>; 167 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 168 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 170 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 171 172 l2_4: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_1>; 177 }; 178 }; 179 180 cpu5: cpu@10100 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a55"; 183 reg = <0x0 0x10100>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_5>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 capacity-dmips-mhz = <1024>; 189 #cooling-cells = <2>; 190 dynamic-power-coefficient = <100>; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 operating-points-v2 = <&cpu4_opp_table>; 193 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 195 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 196 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 197 198 l2_5: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_1>; 203 }; 204 }; 205 206 cpu6: cpu@10200 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a55"; 209 reg = <0x0 0x10200>; 210 enable-method = "psci"; 211 next-level-cache = <&l2_6>; 212 power-domains = <&cpu_pd6>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <1024>; 215 #cooling-cells = <2>; 216 dynamic-power-coefficient = <100>; 217 qcom,freq-domain = <&cpufreq_hw 1>; 218 operating-points-v2 = <&cpu4_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 221 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 222 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 223 224 l2_6: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_1>; 229 }; 230 }; 231 232 cpu7: cpu@10300 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a55"; 235 reg = <0x0 0x10300>; 236 enable-method = "psci"; 237 next-level-cache = <&l2_7>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 capacity-dmips-mhz = <1024>; 241 #cooling-cells = <2>; 242 dynamic-power-coefficient = <100>; 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 operating-points-v2 = <&cpu4_opp_table>; 245 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 247 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 248 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 249 250 l2_7: l2-cache { 251 compatible = "cache"; 252 cache-level = <2>; 253 cache-unified; 254 next-level-cache = <&l3_1>; 255 }; 256 }; 257 258 cpu-map { 259 cluster0 { 260 core0 { 261 cpu = <&cpu0>; 262 }; 263 264 core1 { 265 cpu = <&cpu1>; 266 }; 267 268 core2 { 269 cpu = <&cpu2>; 270 }; 271 272 core3 { 273 cpu = <&cpu3>; 274 }; 275 }; 276 277 cluster1 { 278 core0 { 279 cpu = <&cpu4>; 280 }; 281 282 core1 { 283 cpu = <&cpu5>; 284 }; 285 286 core2 { 287 cpu = <&cpu6>; 288 }; 289 290 core3 { 291 cpu = <&cpu7>; 292 }; 293 }; 294 }; 295 296 l3_0: l3-cache-0 { 297 compatible = "cache"; 298 cache-level = <3>; 299 cache-unified; 300 }; 301 302 l3_1: l3-cache-1 { 303 compatible = "cache"; 304 cache-level = <3>; 305 cache-unified; 306 }; 307 308 idle-states { 309 entry-method = "psci"; 310 311 little_cpu_sleep_0: cpu-sleep-0-0 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "silver-power-collapse"; 314 arm,psci-suspend-param = <0x40000003>; 315 entry-latency-us = <449>; 316 exit-latency-us = <801>; 317 min-residency-us = <1574>; 318 local-timer-stop; 319 }; 320 321 little_cpu_sleep_1: cpu-sleep-0-1 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "silver-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <602>; 326 exit-latency-us = <961>; 327 min-residency-us = <4288>; 328 local-timer-stop; 329 }; 330 331 big_cpu_sleep_0: cpu-sleep-1-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-power-collapse"; 334 arm,psci-suspend-param = <0x40000003>; 335 entry-latency-us = <549>; 336 exit-latency-us = <901>; 337 min-residency-us = <1774>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_1: cpu-sleep-1-1 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "gold-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <702>; 346 exit-latency-us = <1061>; 347 min-residency-us = <4488>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 silver_cluster_sleep: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x41000044>; 356 entry-latency-us = <2552>; 357 exit-latency-us = <2848>; 358 min-residency-us = <5908>; 359 }; 360 361 gold_cluster_sleep: cluster-sleep-1 { 362 compatible = "domain-idle-state"; 363 arm,psci-suspend-param = <0x41000044>; 364 entry-latency-us = <2752>; 365 exit-latency-us = <3048>; 366 min-residency-us = <6118>; 367 }; 368 369 system_sleep: domain-sleep { 370 compatible = "domain-idle-state"; 371 arm,psci-suspend-param = <0x42000144>; 372 entry-latency-us = <3263>; 373 exit-latency-us = <6562>; 374 min-residency-us = <9987>; 375 }; 376 }; 377 }; 378 379 cpu0_opp_table: opp-table-cpu0 { 380 compatible = "operating-points-v2"; 381 opp-shared; 382 383 opp-902400000 { 384 opp-hz = /bits/ 64 <902400000>; 385 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 386 }; 387 388 opp-1017600000 { 389 opp-hz = /bits/ 64 <1017600000>; 390 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 391 }; 392 393 opp-1190400000 { 394 opp-hz = /bits/ 64 <1190400000>; 395 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 396 }; 397 398 opp-1267200000 { 399 opp-hz = /bits/ 64 <1267200000>; 400 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 401 }; 402 403 opp-1344000000 { 404 opp-hz = /bits/ 64 <1344000000>; 405 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 406 }; 407 408 opp-1420800000 { 409 opp-hz = /bits/ 64 <1420800000>; 410 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 411 }; 412 413 opp-1497600000 { 414 opp-hz = /bits/ 64 <1497600000>; 415 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 416 }; 417 418 opp-1574400000 { 419 opp-hz = /bits/ 64 <1574400000>; 420 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 421 }; 422 423 opp-1670400000 { 424 opp-hz = /bits/ 64 <1670400000>; 425 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 426 }; 427 428 opp-1747200000 { 429 opp-hz = /bits/ 64 <1747200000>; 430 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 431 }; 432 433 opp-1824000000 { 434 opp-hz = /bits/ 64 <1824000000>; 435 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 436 }; 437 438 opp-1900800000 { 439 opp-hz = /bits/ 64 <1900800000>; 440 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 441 }; 442 443 opp-1977600000 { 444 opp-hz = /bits/ 64 <1977600000>; 445 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 446 }; 447 448 opp-2054400000 { 449 opp-hz = /bits/ 64 <2054400000>; 450 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 451 }; 452 453 opp-2112000000 { 454 opp-hz = /bits/ 64 <2112000000>; 455 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 456 }; 457 458 }; 459 460 cpu2_opp_table: opp-table-cpu2 { 461 compatible = "operating-points-v2"; 462 opp-shared; 463 464 opp-940800000 { 465 opp-hz = /bits/ 64 <940800000>; 466 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 467 }; 468 469 opp-1094400000 { 470 opp-hz = /bits/ 64 <1094400000>; 471 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 472 }; 473 474 opp-1267200000 { 475 opp-hz = /bits/ 64 <1267200000>; 476 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 477 }; 478 479 opp-1344000000 { 480 opp-hz = /bits/ 64 <1344000000>; 481 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 482 }; 483 484 opp-1420800000 { 485 opp-hz = /bits/ 64 <1420800000>; 486 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 487 }; 488 489 opp-1497600000 { 490 opp-hz = /bits/ 64 <1497600000>; 491 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 492 }; 493 494 opp-1574400000 { 495 opp-hz = /bits/ 64 <1574400000>; 496 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 497 }; 498 499 opp-1632000000 { 500 opp-hz = /bits/ 64 <1632000000>; 501 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 502 }; 503 504 opp-1708800000 { 505 opp-hz = /bits/ 64 <1708800000>; 506 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 507 }; 508 509 opp-1804800000 { 510 opp-hz = /bits/ 64 <1804800000>; 511 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 512 }; 513 514 opp-1900800000 { 515 opp-hz = /bits/ 64 <1900800000>; 516 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 517 }; 518 519 opp-1977600000 { 520 opp-hz = /bits/ 64 <1977600000>; 521 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 522 }; 523 524 opp-2054400000 { 525 opp-hz = /bits/ 64 <2054400000>; 526 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 527 }; 528 529 opp-2131200000 { 530 opp-hz = /bits/ 64 <2131200000>; 531 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 532 }; 533 534 opp-2208000000 { 535 opp-hz = /bits/ 64 <2208000000>; 536 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 537 }; 538 539 opp-2284800000 { 540 opp-hz = /bits/ 64 <2284800000>; 541 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 542 }; 543 544 opp-2361600000 { 545 opp-hz = /bits/ 64 <2361600000>; 546 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 547 }; 548 549 }; 550 551 cpu4_opp_table: opp-table-cpu4 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 opp-844800000 { 556 opp-hz = /bits/ 64 <844800000>; 557 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 558 }; 559 560 opp-1113600000 { 561 opp-hz = /bits/ 64 <1113600000>; 562 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 563 }; 564 565 opp-1209600000 { 566 opp-hz = /bits/ 64 <1209600000>; 567 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 568 }; 569 570 opp-1305600000 { 571 opp-hz = /bits/ 64 <1305600000>; 572 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 573 }; 574 575 opp-1382400000 { 576 opp-hz = /bits/ 64 <1382400000>; 577 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 578 }; 579 580 opp-1459200000 { 581 opp-hz = /bits/ 64 <1459200000>; 582 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 583 }; 584 585 opp-1497600000 { 586 opp-hz = /bits/ 64 <1497600000>; 587 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 588 }; 589 590 opp-1574400000 { 591 opp-hz = /bits/ 64 <1574400000>; 592 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 593 }; 594 595 opp-1651200000 { 596 opp-hz = /bits/ 64 <1651200000>; 597 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 598 }; 599 600 opp-1728000000 { 601 opp-hz = /bits/ 64 <1728000000>; 602 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 603 }; 604 605 opp-1804800000 { 606 opp-hz = /bits/ 64 <1804800000>; 607 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 608 }; 609 610 opp-1881600000 { 611 opp-hz = /bits/ 64 <1881600000>; 612 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 613 }; 614 615 opp-1958400000 { 616 opp-hz = /bits/ 64 <1958400000>; 617 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 618 }; 619 }; 620 621 dummy_eud: dummy-sink { 622 compatible = "arm,coresight-dummy-sink"; 623 624 in-ports { 625 port { 626 eud_in: endpoint { 627 remote-endpoint = <&swao_rep_out1>; 628 }; 629 }; 630 }; 631 }; 632 633 firmware { 634 scm: scm { 635 compatible = "qcom,scm-qcs8300", "qcom,scm"; 636 qcom,dload-mode = <&tcsr 0x13000>; 637 }; 638 }; 639 640 memory@80000000 { 641 device_type = "memory"; 642 /* We expect the bootloader to fill in the size */ 643 reg = <0x0 0x80000000 0x0 0x0>; 644 }; 645 646 clk_virt: interconnect-0 { 647 compatible = "qcom,qcs8300-clk-virt"; 648 #interconnect-cells = <2>; 649 qcom,bcm-voters = <&apps_bcm_voter>; 650 }; 651 652 mc_virt: interconnect-1 { 653 compatible = "qcom,qcs8300-mc-virt"; 654 #interconnect-cells = <2>; 655 qcom,bcm-voters = <&apps_bcm_voter>; 656 }; 657 658 qup_opp_table: opp-table-qup { 659 compatible = "operating-points-v2"; 660 661 opp-120000000 { 662 opp-hz = /bits/ 64 <120000000>; 663 required-opps = <&rpmhpd_opp_svs_l1>; 664 }; 665 }; 666 667 pmu-a55 { 668 compatible = "arm,cortex-a55-pmu"; 669 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 670 }; 671 672 pmu-a78 { 673 compatible = "arm,cortex-a78-pmu"; 674 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 675 }; 676 677 psci { 678 compatible = "arm,psci-1.0"; 679 method = "smc"; 680 681 cpu_pd0: power-domain-cpu0 { 682 #power-domain-cells = <0>; 683 power-domains = <&cluster_pd0>; 684 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 685 }; 686 687 cpu_pd1: power-domain-cpu1 { 688 #power-domain-cells = <0>; 689 power-domains = <&cluster_pd0>; 690 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 691 }; 692 693 cpu_pd2: power-domain-cpu2 { 694 #power-domain-cells = <0>; 695 power-domains = <&cluster_pd0>; 696 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 697 }; 698 699 cpu_pd3: power-domain-cpu3 { 700 #power-domain-cells = <0>; 701 power-domains = <&cluster_pd0>; 702 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 703 }; 704 705 cpu_pd4: power-domain-cpu4 { 706 #power-domain-cells = <0>; 707 power-domains = <&cluster_pd1>; 708 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 709 }; 710 711 cpu_pd5: power-domain-cpu5 { 712 #power-domain-cells = <0>; 713 power-domains = <&cluster_pd1>; 714 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 715 }; 716 717 cpu_pd6: power-domain-cpu6 { 718 #power-domain-cells = <0>; 719 power-domains = <&cluster_pd1>; 720 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 721 }; 722 723 cpu_pd7: power-domain-cpu7 { 724 #power-domain-cells = <0>; 725 power-domains = <&cluster_pd1>; 726 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 727 }; 728 729 cluster_pd0: power-domain-cluster0 { 730 #power-domain-cells = <0>; 731 power-domains = <&system_pd>; 732 domain-idle-states = <&gold_cluster_sleep>; 733 }; 734 735 cluster_pd1: power-domain-cluster1 { 736 #power-domain-cells = <0>; 737 power-domains = <&system_pd>; 738 domain-idle-states = <&silver_cluster_sleep>; 739 }; 740 741 system_pd: power-domain-system { 742 #power-domain-cells = <0>; 743 domain-idle-states = <&system_sleep>; 744 }; 745 }; 746 747 reserved-memory { 748 #address-cells = <2>; 749 #size-cells = <2>; 750 ranges; 751 752 aop_image_mem: aop-image-region@90800000 { 753 reg = <0x0 0x90800000 0x0 0x60000>; 754 no-map; 755 }; 756 757 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 758 compatible = "qcom,cmd-db"; 759 reg = <0x0 0x90860000 0x0 0x20000>; 760 no-map; 761 }; 762 763 smem_mem: smem@90900000 { 764 compatible = "qcom,smem"; 765 reg = <0x0 0x90900000 0x0 0x200000>; 766 no-map; 767 hwlocks = <&tcsr_mutex 3>; 768 }; 769 770 gunyah_md_mem: gunyah-md-region@91a80000 { 771 reg = <0x0 0x91a80000 0x0 0x80000>; 772 no-map; 773 }; 774 775 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 776 reg = <0x0 0x93b00000 0x0 0xf00000>; 777 no-map; 778 }; 779 780 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 781 reg = <0x0 0x94a00000 0x0 0x800000>; 782 no-map; 783 }; 784 785 camera_mem: camera-region@95200000 { 786 reg = <0x0 0x95200000 0x0 0x500000>; 787 no-map; 788 }; 789 790 adsp_mem: adsp-region@95c00000 { 791 no-map; 792 reg = <0x0 0x95c00000 0x0 0x1e00000>; 793 }; 794 795 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 796 reg = <0x0 0x97a00000 0x0 0x80000>; 797 no-map; 798 }; 799 800 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 801 reg = <0x0 0x97a80000 0x0 0x80000>; 802 no-map; 803 }; 804 805 gpdsp_mem: gpdsp-region@97b00000 { 806 reg = <0x0 0x97b00000 0x0 0x1e00000>; 807 no-map; 808 }; 809 810 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 811 reg = <0x0 0x99900000 0x0 0x80000>; 812 no-map; 813 }; 814 815 cdsp_mem: cdsp-region@99980000 { 816 reg = <0x0 0x99980000 0x0 0x1e00000>; 817 no-map; 818 }; 819 820 gpu_microcode_mem: gpu-microcode-region@9b780000 { 821 reg = <0x0 0x9b780000 0x0 0x2000>; 822 no-map; 823 }; 824 825 cvp_mem: cvp-region@9b782000 { 826 reg = <0x0 0x9b782000 0x0 0x700000>; 827 no-map; 828 }; 829 830 video_mem: video-region@9be82000 { 831 reg = <0x0 0x9be82000 0x0 0x700000>; 832 no-map; 833 }; 834 }; 835 836 smp2p-adsp { 837 compatible = "qcom,smp2p"; 838 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 839 IPCC_MPROC_SIGNAL_SMP2P 840 IRQ_TYPE_EDGE_RISING>; 841 mboxes = <&ipcc IPCC_CLIENT_LPASS 842 IPCC_MPROC_SIGNAL_SMP2P>; 843 844 qcom,smem = <443>, <429>; 845 qcom,local-pid = <0>; 846 qcom,remote-pid = <2>; 847 848 smp2p_adsp_in: slave-kernel { 849 qcom,entry-name = "slave-kernel"; 850 interrupt-controller; 851 #interrupt-cells = <2>; 852 }; 853 854 smp2p_adsp_out: master-kernel { 855 qcom,entry-name = "master-kernel"; 856 #qcom,smem-state-cells = <1>; 857 }; 858 }; 859 860 smp2p-cdsp { 861 compatible = "qcom,smp2p"; 862 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 863 IPCC_MPROC_SIGNAL_SMP2P 864 IRQ_TYPE_EDGE_RISING>; 865 mboxes = <&ipcc IPCC_CLIENT_CDSP 866 IPCC_MPROC_SIGNAL_SMP2P>; 867 868 qcom,smem = <94>, <432>; 869 qcom,local-pid = <0>; 870 qcom,remote-pid = <5>; 871 872 smp2p_cdsp_in: slave-kernel { 873 qcom,entry-name = "slave-kernel"; 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 }; 877 878 smp2p_cdsp_out: master-kernel { 879 qcom,entry-name = "master-kernel"; 880 #qcom,smem-state-cells = <1>; 881 }; 882 }; 883 884 smp2p-gpdsp { 885 compatible = "qcom,smp2p"; 886 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 887 IPCC_MPROC_SIGNAL_SMP2P 888 IRQ_TYPE_EDGE_RISING>; 889 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 890 IPCC_MPROC_SIGNAL_SMP2P>; 891 892 qcom,smem = <617>, <616>; 893 qcom,local-pid = <0>; 894 qcom,remote-pid = <17>; 895 896 smp2p_gpdsp_in: slave-kernel { 897 qcom,entry-name = "slave-kernel"; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 }; 901 902 smp2p_gpdsp_out: master-kernel { 903 qcom,entry-name = "master-kernel"; 904 #qcom,smem-state-cells = <1>; 905 }; 906 }; 907 908 soc: soc@0 { 909 compatible = "simple-bus"; 910 ranges = <0 0 0 0 0x10 0>; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 914 gcc: clock-controller@100000 { 915 compatible = "qcom,qcs8300-gcc"; 916 reg = <0x0 0x00100000 0x0 0xc7018>; 917 #clock-cells = <1>; 918 #reset-cells = <1>; 919 #power-domain-cells = <1>; 920 clocks = <&rpmhcc RPMH_CXO_CLK>, 921 <&sleep_clk>, 922 <&pcie0_phy>, 923 <&pcie1_phy>, 924 <0>, 925 <0>, 926 <0>, 927 <0>, 928 <0>, 929 <0>; 930 }; 931 932 ipcc: mailbox@408000 { 933 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 934 reg = <0x0 0x408000 0x0 0x1000>; 935 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-controller; 937 #interrupt-cells = <3>; 938 #mbox-cells = <2>; 939 }; 940 941 qfprom: efuse@784000 { 942 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 943 reg = <0x0 0x00784000 0x0 0x2410>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 947 gpu_speed_bin: gpu-speed-bin@240c { 948 reg = <0x240c 0x1>; 949 bits = <0 8>; 950 }; 951 }; 952 953 gpi_dma0: dma-controller@900000 { 954 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 955 reg = <0x0 0x900000 0x0 0x60000>; 956 #dma-cells = <3>; 957 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 969 iommus = <&apps_smmu 0x416 0x0>; 970 dma-channels = <12>; 971 dma-channel-mask = <0xfff>; 972 dma-coherent; 973 status = "disabled"; 974 }; 975 976 qupv3_id_0: geniqup@9c0000 { 977 compatible = "qcom,geni-se-qup"; 978 reg = <0x0 0x9c0000 0x0 0x2000>; 979 ranges; 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 982 clock-names = "m-ahb", 983 "s-ahb"; 984 #address-cells = <2>; 985 #size-cells = <2>; 986 iommus = <&apps_smmu 0x403 0x0>; 987 dma-coherent; 988 status = "disabled"; 989 990 i2c0: i2c@980000 { 991 compatible = "qcom,geni-i2c"; 992 reg = <0x0 0x980000 0x0 0x4000>; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 994 clock-names = "se"; 995 pinctrl-0 = <&qup_i2c0_data_clk>; 996 pinctrl-names = "default"; 997 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1001 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1003 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1004 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1006 interconnect-names = "qup-core", 1007 "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1013 dma-names = "tx", 1014 "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 spi0: spi@980000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0x0 0x980000 0x0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1022 clock-names = "se"; 1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1024 pinctrl-names = "default"; 1025 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 power-domains = <&rpmhpd RPMHPD_CX>; 1035 operating-points-v2 = <&qup_opp_table>; 1036 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", 1039 "rx"; 1040 status = "disabled"; 1041 }; 1042 1043 uart0: serial@980000 { 1044 compatible = "qcom,geni-uart"; 1045 reg = <0x0 0x980000 0x0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1047 clock-names = "se"; 1048 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1049 <&qup_uart0_tx>, <&qup_uart0_rx>; 1050 pinctrl-names = "default"; 1051 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1055 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1056 interconnect-names = "qup-core", 1057 "qup-config"; 1058 power-domains = <&rpmhpd RPMHPD_CX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c1: i2c@984000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0x0 0x984000 0x0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1067 clock-names = "se"; 1068 pinctrl-0 = <&qup_i2c1_data_clk>; 1069 pinctrl-names = "default"; 1070 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1074 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1075 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1076 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1077 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1079 interconnect-names = "qup-core", 1080 "qup-config", 1081 "qup-memory"; 1082 power-domains = <&rpmhpd RPMHPD_CX>; 1083 required-opps = <&rpmhpd_opp_low_svs>; 1084 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1086 dma-names = "tx", 1087 "rx"; 1088 status = "disabled"; 1089 }; 1090 1091 spi1: spi@984000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0x0 0x984000 0x0 0x4000>; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1095 clock-names = "se"; 1096 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1097 pinctrl-names = "default"; 1098 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1102 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1103 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1104 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1105 interconnect-names = "qup-core", 1106 "qup-config"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table>; 1109 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1110 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1111 dma-names = "tx", 1112 "rx"; 1113 status = "disabled"; 1114 }; 1115 1116 uart1: serial@984000 { 1117 compatible = "qcom,geni-uart"; 1118 reg = <0x0 0x984000 0x0 0x4000>; 1119 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1120 clock-names = "se"; 1121 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1122 <&qup_uart1_tx>, <&qup_uart1_rx>; 1123 pinctrl-names = "default"; 1124 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1126 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1127 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1128 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1129 interconnect-names = "qup-core", 1130 "qup-config"; 1131 power-domains = <&rpmhpd RPMHPD_CX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 status = "disabled"; 1134 }; 1135 1136 i2c2: i2c@988000 { 1137 compatible = "qcom,geni-i2c"; 1138 reg = <0x0 0x988000 0x0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1140 clock-names = "se"; 1141 pinctrl-0 = <&qup_i2c2_data_clk>; 1142 pinctrl-names = "default"; 1143 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1150 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1152 interconnect-names = "qup-core", 1153 "qup-config", 1154 "qup-memory"; 1155 power-domains = <&rpmhpd RPMHPD_CX>; 1156 required-opps = <&rpmhpd_opp_low_svs>; 1157 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1158 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1159 dma-names = "tx", 1160 "rx"; 1161 status = "disabled"; 1162 }; 1163 1164 spi2: spi@988000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0x0 0x988000 0x0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1168 clock-names = "se"; 1169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1170 pinctrl-names = "default"; 1171 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1175 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1176 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1177 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1178 interconnect-names = "qup-core", 1179 "qup-config"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1183 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1184 dma-names = "tx", 1185 "rx"; 1186 status = "disabled"; 1187 }; 1188 1189 uart2: serial@988000 { 1190 compatible = "qcom,geni-uart"; 1191 reg = <0x0 0x988000 0x0 0x4000>; 1192 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1193 clock-names = "se"; 1194 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1195 <&qup_uart2_tx>, <&qup_uart2_rx>; 1196 pinctrl-names = "default"; 1197 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1201 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "qup-core", 1203 "qup-config"; 1204 power-domains = <&rpmhpd RPMHPD_CX>; 1205 operating-points-v2 = <&qup_opp_table>; 1206 status = "disabled"; 1207 }; 1208 1209 i2c3: i2c@98c000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0x0 0x98c000 0x0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1213 clock-names = "se"; 1214 pinctrl-0 = <&qup_i2c3_data_clk>; 1215 pinctrl-names = "default"; 1216 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1220 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1222 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1223 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config", 1227 "qup-memory"; 1228 power-domains = <&rpmhpd RPMHPD_CX>; 1229 required-opps = <&rpmhpd_opp_low_svs>; 1230 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1231 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1232 dma-names = "tx", 1233 "rx"; 1234 status = "disabled"; 1235 }; 1236 1237 spi3: spi@98c000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0x0 0x98c000 0x0 0x4000>; 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1241 clock-names = "se"; 1242 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1243 pinctrl-names = "default"; 1244 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1248 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1250 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1251 interconnect-names = "qup-core", 1252 "qup-config"; 1253 power-domains = <&rpmhpd RPMHPD_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1256 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1257 dma-names = "tx", 1258 "rx"; 1259 status = "disabled"; 1260 }; 1261 1262 uart3: serial@98c000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0x0 0x98c000 0x0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1266 clock-names = "se"; 1267 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1268 <&qup_uart3_tx>, <&qup_uart3_rx>; 1269 pinctrl-names = "default"; 1270 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1274 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config"; 1277 power-domains = <&rpmhpd RPMHPD_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 status = "disabled"; 1280 }; 1281 1282 i2c4: i2c@990000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0x0 0x990000 0x0 0x4000>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1286 clock-names = "se"; 1287 pinctrl-0 = <&qup_i2c4_data_clk>; 1288 pinctrl-names = "default"; 1289 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1293 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1294 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1295 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1296 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1297 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1298 interconnect-names = "qup-core", 1299 "qup-config", 1300 "qup-memory"; 1301 power-domains = <&rpmhpd RPMHPD_CX>; 1302 required-opps = <&rpmhpd_opp_low_svs>; 1303 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1304 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1305 dma-names = "tx", 1306 "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 spi4: spi@990000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0x0 0x990000 0x0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1314 clock-names = "se"; 1315 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1316 pinctrl-names = "default"; 1317 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1321 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1322 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1323 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1324 interconnect-names = "qup-core", 1325 "qup-config"; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1329 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1330 dma-names = "tx", 1331 "rx"; 1332 status = "disabled"; 1333 }; 1334 1335 uart4: serial@990000 { 1336 compatible = "qcom,geni-uart"; 1337 reg = <0x0 0x990000 0x0 0x4000>; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1339 clock-names = "se"; 1340 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1341 <&qup_uart4_tx>, <&qup_uart4_rx>; 1342 pinctrl-names = "default"; 1343 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1344 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1345 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1347 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1348 interconnect-names = "qup-core", 1349 "qup-config"; 1350 power-domains = <&rpmhpd RPMHPD_CX>; 1351 operating-points-v2 = <&qup_opp_table>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c5: i2c@994000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0x0 0x994000 0x0 0x4000>; 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1359 clock-names = "se"; 1360 pinctrl-0 = <&qup_i2c5_data_clk>; 1361 pinctrl-names = "default"; 1362 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1366 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1368 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1369 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1370 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1371 interconnect-names = "qup-core", 1372 "qup-config", 1373 "qup-memory"; 1374 power-domains = <&rpmhpd RPMHPD_CX>; 1375 required-opps = <&rpmhpd_opp_low_svs>; 1376 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1377 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1378 dma-names = "tx", 1379 "rx"; 1380 status = "disabled"; 1381 }; 1382 1383 spi5: spi@994000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0x0 0x994000 0x0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1387 clock-names = "se"; 1388 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1389 pinctrl-names = "default"; 1390 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1394 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1395 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1396 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1397 interconnect-names = "qup-core", 1398 "qup-config"; 1399 power-domains = <&rpmhpd RPMHPD_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1402 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1403 dma-names = "tx", 1404 "rx"; 1405 status = "disabled"; 1406 }; 1407 1408 uart5: serial@994000 { 1409 compatible = "qcom,geni-uart"; 1410 reg = <0x0 0x994000 0x0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1414 <&qup_uart5_tx>, <&qup_uart5_rx>; 1415 pinctrl-names = "default"; 1416 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1418 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1420 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config"; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 operating-points-v2 = <&qup_opp_table>; 1425 status = "disabled"; 1426 }; 1427 1428 i2c6: i2c@998000 { 1429 compatible = "qcom,geni-i2c"; 1430 reg = <0x0 0x998000 0x0 0x4000>; 1431 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1432 clock-names = "se"; 1433 pinctrl-0 = <&qup_i2c6_data_clk>; 1434 pinctrl-names = "default"; 1435 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1439 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1441 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1442 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1444 interconnect-names = "qup-core", 1445 "qup-config", 1446 "qup-memory"; 1447 power-domains = <&rpmhpd RPMHPD_CX>; 1448 required-opps = <&rpmhpd_opp_low_svs>; 1449 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1450 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1451 dma-names = "tx", 1452 "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 spi6: spi@998000 { 1457 compatible = "qcom,geni-spi"; 1458 reg = <0x0 0x998000 0x0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1460 clock-names = "se"; 1461 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1462 pinctrl-names = "default"; 1463 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1469 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1470 interconnect-names = "qup-core", 1471 "qup-config"; 1472 power-domains = <&rpmhpd RPMHPD_CX>; 1473 operating-points-v2 = <&qup_opp_table>; 1474 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1475 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1476 dma-names = "tx", 1477 "rx"; 1478 status = "disabled"; 1479 }; 1480 1481 uart6: serial@998000 { 1482 compatible = "qcom,geni-uart"; 1483 reg = <0x0 0x998000 0x0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1485 clock-names = "se"; 1486 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1487 <&qup_uart6_tx>, <&qup_uart6_rx>; 1488 pinctrl-names = "default"; 1489 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1491 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1493 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1494 interconnect-names = "qup-core", 1495 "qup-config"; 1496 power-domains = <&rpmhpd RPMHPD_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 status = "disabled"; 1499 }; 1500 1501 uart7: serial@99c000 { 1502 compatible = "qcom,geni-debug-uart"; 1503 reg = <0x0 0x0099c000 0x0 0x4000>; 1504 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1505 clock-names = "se"; 1506 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1507 pinctrl-names = "default"; 1508 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1510 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1512 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1513 interconnect-names = "qup-core", 1514 "qup-config"; 1515 power-domains = <&rpmhpd RPMHPD_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 gpi_dma1: dma-controller@a00000 { 1522 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1523 reg = <0x0 0xa00000 0x0 0x60000>; 1524 #dma-cells = <3>; 1525 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1537 iommus = <&apps_smmu 0x456 0x0>; 1538 dma-channels = <12>; 1539 dma-channel-mask = <0xfff>; 1540 dma-coherent; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_1: geniqup@ac0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0x0 0xac0000 0x0 0x2000>; 1547 ranges; 1548 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1549 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1550 clock-names = "m-ahb", 1551 "s-ahb"; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 iommus = <&apps_smmu 0x443 0x0>; 1555 dma-coherent; 1556 status = "disabled"; 1557 1558 i2c8: i2c@a80000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0x0 0xa80000 0x0 0x4000>; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1562 clock-names = "se"; 1563 pinctrl-0 = <&qup_i2c8_data_clk>; 1564 pinctrl-names = "default"; 1565 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1569 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1571 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1572 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1574 interconnect-names = "qup-core", 1575 "qup-config", 1576 "qup-memory"; 1577 power-domains = <&rpmhpd RPMHPD_CX>; 1578 required-opps = <&rpmhpd_opp_low_svs>; 1579 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1580 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1581 dma-names = "tx", 1582 "rx"; 1583 status = "disabled"; 1584 }; 1585 1586 spi8: spi@a80000 { 1587 compatible = "qcom,geni-spi"; 1588 reg = <0x0 0xa80000 0x0 0x4000>; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1590 clock-names = "se"; 1591 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1592 pinctrl-names = "default"; 1593 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1597 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1598 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1599 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1600 interconnect-names = "qup-core", 1601 "qup-config"; 1602 power-domains = <&rpmhpd RPMHPD_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1606 dma-names = "tx", 1607 "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart8: serial@a80000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0x0 0xa80000 0x0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1615 clock-names = "se"; 1616 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1617 <&qup_uart8_tx>, <&qup_uart8_rx>; 1618 pinctrl-names = "default"; 1619 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1621 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1622 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1623 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1624 interconnect-names = "qup-core", 1625 "qup-config"; 1626 power-domains = <&rpmhpd RPMHPD_CX>; 1627 operating-points-v2 = <&qup_opp_table>; 1628 status = "disabled"; 1629 }; 1630 1631 i2c9: i2c@a84000 { 1632 compatible = "qcom,geni-i2c"; 1633 reg = <0x0 0xa84000 0x0 0x4000>; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1635 clock-names = "se"; 1636 pinctrl-0 = <&qup_i2c9_data_clk>; 1637 pinctrl-names = "default"; 1638 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1642 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1643 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1644 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1645 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1646 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1647 interconnect-names = "qup-core", 1648 "qup-config", 1649 "qup-memory"; 1650 power-domains = <&rpmhpd RPMHPD_CX>; 1651 required-opps = <&rpmhpd_opp_low_svs>; 1652 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1653 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1654 dma-names = "tx", 1655 "rx"; 1656 status = "disabled"; 1657 }; 1658 1659 spi9: spi@a84000 { 1660 compatible = "qcom,geni-spi"; 1661 reg = <0x0 0xa84000 0x0 0x4000>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1663 clock-names = "se"; 1664 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1665 pinctrl-names = "default"; 1666 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1670 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1672 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1673 interconnect-names = "qup-core", 1674 "qup-config"; 1675 power-domains = <&rpmhpd RPMHPD_CX>; 1676 operating-points-v2 = <&qup_opp_table>; 1677 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1678 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1679 dma-names = "tx", 1680 "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 uart9: serial@a84000 { 1685 compatible = "qcom,geni-uart"; 1686 reg = <0x0 0xa84000 0x0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1688 clock-names = "se"; 1689 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1690 <&qup_uart9_tx>, <&qup_uart9_rx>; 1691 pinctrl-names = "default"; 1692 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1693 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1694 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1695 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1696 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1697 interconnect-names = "qup-core", 1698 "qup-config"; 1699 power-domains = <&rpmhpd RPMHPD_CX>; 1700 operating-points-v2 = <&qup_opp_table>; 1701 status = "disabled"; 1702 }; 1703 1704 i2c10: i2c@a88000 { 1705 compatible = "qcom,geni-i2c"; 1706 reg = <0x0 0xa88000 0x0 0x4000>; 1707 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1708 clock-names = "se"; 1709 pinctrl-0 = <&qup_i2c10_data_clk>; 1710 pinctrl-names = "default"; 1711 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 power-domains = <&rpmhpd RPMHPD_CX>; 1724 required-opps = <&rpmhpd_opp_low_svs>; 1725 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1726 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1727 dma-names = "tx", 1728 "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 spi10: spi@a88000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0xa88000 0x0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1736 clock-names = "se"; 1737 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1738 pinctrl-names = "default"; 1739 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1743 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1745 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1746 interconnect-names = "qup-core", 1747 "qup-config"; 1748 power-domains = <&rpmhpd RPMHPD_CX>; 1749 operating-points-v2 = <&qup_opp_table>; 1750 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1751 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1752 dma-names = "tx", 1753 "rx"; 1754 status = "disabled"; 1755 }; 1756 1757 uart10: serial@a88000 { 1758 compatible = "qcom,geni-uart"; 1759 reg = <0x0 0xa88000 0x0 0x4000>; 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1761 clock-names = "se"; 1762 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1763 <&qup_uart10_tx>, <&qup_uart10_rx>; 1764 pinctrl-names = "default"; 1765 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1766 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1767 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1768 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1769 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1770 interconnect-names = "qup-core", 1771 "qup-config"; 1772 power-domains = <&rpmhpd RPMHPD_CX>; 1773 operating-points-v2 = <&qup_opp_table>; 1774 status = "disabled"; 1775 }; 1776 1777 i2c11: i2c@a8c000 { 1778 compatible = "qcom,geni-i2c"; 1779 reg = <0x0 0xa8c000 0x0 0x4000>; 1780 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1781 clock-names = "se"; 1782 pinctrl-0 = <&qup_i2c11_data_clk>; 1783 pinctrl-names = "default"; 1784 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1788 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1789 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1790 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1791 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1792 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1793 interconnect-names = "qup-core", 1794 "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd RPMHPD_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1800 dma-names = "tx", 1801 "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart11: serial@a8c000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0x0 0xa8c000 0x0 0x4000>; 1808 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1809 clock-names = "se"; 1810 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1811 pinctrl-names = "default"; 1812 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1817 interconnect-names = "qup-core", 1818 "qup-config"; 1819 power-domains = <&rpmhpd RPMHPD_CX>; 1820 operating-points-v2 = <&qup_opp_table>; 1821 status = "disabled"; 1822 }; 1823 1824 i2c12: i2c@a90000 { 1825 compatible = "qcom,geni-i2c"; 1826 reg = <0x0 0xa90000 0x0 0x4000>; 1827 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1828 clock-names = "se"; 1829 pinctrl-0 = <&qup_i2c12_data_clk>; 1830 pinctrl-names = "default"; 1831 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1835 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1836 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1837 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1838 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1839 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1840 interconnect-names = "qup-core", 1841 "qup-config", 1842 "qup-memory"; 1843 power-domains = <&rpmhpd RPMHPD_CX>; 1844 required-opps = <&rpmhpd_opp_low_svs>; 1845 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1846 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1847 dma-names = "tx", 1848 "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 spi12: spi@a90000 { 1853 compatible = "qcom,geni-spi"; 1854 reg = <0x0 0xa90000 0x0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1856 clock-names = "se"; 1857 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1858 pinctrl-names = "default"; 1859 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1863 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1864 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1865 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1866 interconnect-names = "qup-core", 1867 "qup-config"; 1868 power-domains = <&rpmhpd RPMHPD_CX>; 1869 operating-points-v2 = <&qup_opp_table>; 1870 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1871 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1872 dma-names = "tx", 1873 "rx"; 1874 status = "disabled"; 1875 }; 1876 1877 uart12: serial@a90000 { 1878 compatible = "qcom,geni-uart"; 1879 reg = <0x0 0xa90000 0x0 0x4000>; 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1881 clock-names = "se"; 1882 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1883 <&qup_uart12_tx>, <&qup_uart12_rx>; 1884 pinctrl-names = "default"; 1885 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1888 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1889 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1890 interconnect-names = "qup-core", 1891 "qup-config"; 1892 power-domains = <&rpmhpd RPMHPD_CX>; 1893 operating-points-v2 = <&qup_opp_table>; 1894 status = "disabled"; 1895 }; 1896 1897 i2c13: i2c@a94000 { 1898 compatible = "qcom,geni-i2c"; 1899 reg = <0x0 0xa94000 0x0 0x4000>; 1900 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1901 clock-names = "se"; 1902 pinctrl-0 = <&qup_i2c13_data_clk>; 1903 pinctrl-names = "default"; 1904 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1908 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1910 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1911 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1912 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1913 interconnect-names = "qup-core", 1914 "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd RPMHPD_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1920 dma-names = "tx", 1921 "rx"; 1922 status = "disabled"; 1923 }; 1924 1925 spi13: spi@a94000 { 1926 compatible = "qcom,geni-spi"; 1927 reg = <0x0 0xa94000 0x0 0x4000>; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1929 clock-names = "se"; 1930 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1931 pinctrl-names = "default"; 1932 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1936 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1937 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1938 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1939 interconnect-names = "qup-core", 1940 "qup-config"; 1941 power-domains = <&rpmhpd RPMHPD_CX>; 1942 operating-points-v2 = <&qup_opp_table>; 1943 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1944 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1945 dma-names = "tx", 1946 "rx"; 1947 status = "disabled"; 1948 }; 1949 1950 uart13: serial@a94000 { 1951 compatible = "qcom,geni-uart"; 1952 reg = <0x0 0xa94000 0x0 0x4000>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1954 clock-names = "se"; 1955 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1956 <&qup_uart13_tx>, <&qup_uart13_rx>; 1957 pinctrl-names = "default"; 1958 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1959 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1960 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1961 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1962 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config"; 1965 power-domains = <&rpmhpd RPMHPD_CX>; 1966 operating-points-v2 = <&qup_opp_table>; 1967 status = "disabled"; 1968 }; 1969 1970 i2c14: i2c@a98000 { 1971 compatible = "qcom,geni-i2c"; 1972 reg = <0x0 0xa98000 0x0 0x4000>; 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1974 clock-names = "se"; 1975 pinctrl-0 = <&qup_i2c14_data_clk>; 1976 pinctrl-names = "default"; 1977 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1981 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1983 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1984 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1986 interconnect-names = "qup-core", 1987 "qup-config", 1988 "qup-memory"; 1989 power-domains = <&rpmhpd RPMHPD_CX>; 1990 required-opps = <&rpmhpd_opp_low_svs>; 1991 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1992 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1993 dma-names = "tx", 1994 "rx"; 1995 status = "disabled"; 1996 }; 1997 1998 spi14: spi@a98000 { 1999 compatible = "qcom,geni-spi"; 2000 reg = <0x0 0xa98000 0x0 0x4000>; 2001 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2002 clock-names = "se"; 2003 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2004 pinctrl-names = "default"; 2005 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2009 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2011 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2012 interconnect-names = "qup-core", 2013 "qup-config"; 2014 power-domains = <&rpmhpd RPMHPD_CX>; 2015 operating-points-v2 = <&qup_opp_table>; 2016 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2017 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2018 dma-names = "tx", 2019 "rx"; 2020 status = "disabled"; 2021 }; 2022 2023 uart14: serial@a98000 { 2024 compatible = "qcom,geni-uart"; 2025 reg = <0x0 0xa98000 0x0 0x4000>; 2026 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2027 clock-names = "se"; 2028 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2029 <&qup_uart14_tx>, <&qup_uart14_rx>; 2030 pinctrl-names = "default"; 2031 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2032 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2033 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2035 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2036 interconnect-names = "qup-core", 2037 "qup-config"; 2038 power-domains = <&rpmhpd RPMHPD_CX>; 2039 operating-points-v2 = <&qup_opp_table>; 2040 status = "disabled"; 2041 }; 2042 2043 i2c15: i2c@a9c000 { 2044 compatible = "qcom,geni-i2c"; 2045 reg = <0x0 0xa9c000 0x0 0x4000>; 2046 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2047 clock-names = "se"; 2048 pinctrl-0 = <&qup_i2c15_data_clk>; 2049 pinctrl-names = "default"; 2050 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2054 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2056 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2057 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2059 interconnect-names = "qup-core", 2060 "qup-config", 2061 "qup-memory"; 2062 power-domains = <&rpmhpd RPMHPD_CX>; 2063 required-opps = <&rpmhpd_opp_low_svs>; 2064 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2065 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2066 dma-names = "tx", 2067 "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi15: spi@a9c000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0x0 0xa9c000 0x0 0x4000>; 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2077 pinctrl-names = "default"; 2078 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2082 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2083 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2084 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2085 interconnect-names = "qup-core", 2086 "qup-config"; 2087 power-domains = <&rpmhpd RPMHPD_CX>; 2088 operating-points-v2 = <&qup_opp_table>; 2089 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2090 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2091 dma-names = "tx", 2092 "rx"; 2093 status = "disabled"; 2094 }; 2095 2096 uart15: serial@a9c000 { 2097 compatible = "qcom,geni-uart"; 2098 reg = <0x0 0xa9c000 0x0 0x4000>; 2099 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2100 clock-names = "se"; 2101 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2102 <&qup_uart15_tx>, <&qup_uart15_rx>; 2103 pinctrl-names = "default"; 2104 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2105 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2106 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2108 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2109 interconnect-names = "qup-core", 2110 "qup-config"; 2111 power-domains = <&rpmhpd RPMHPD_CX>; 2112 operating-points-v2 = <&qup_opp_table>; 2113 status = "disabled"; 2114 }; 2115 }; 2116 2117 gpi_dma3: dma-controller@b00000 { 2118 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2119 reg = <0x0 0xb00000 0x0 0x60000>; 2120 #dma-cells = <3>; 2121 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2125 iommus = <&apps_smmu 0x56 0x0>; 2126 dma-channels = <4>; 2127 dma-channel-mask = <0xf>; 2128 dma-coherent; 2129 status = "disabled"; 2130 }; 2131 2132 qupv3_id_3: geniqup@bc0000 { 2133 compatible = "qcom,geni-se-qup"; 2134 reg = <0x0 0xbc0000 0x0 0x2000>; 2135 ranges; 2136 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2137 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2138 clock-names = "m-ahb", 2139 "s-ahb"; 2140 #address-cells = <2>; 2141 #size-cells = <2>; 2142 iommus = <&apps_smmu 0x43 0x0>; 2143 dma-coherent; 2144 status = "disabled"; 2145 2146 i2c16: i2c@b80000 { 2147 compatible = "qcom,geni-i2c"; 2148 reg = <0x0 0xb80000 0x0 0x4000>; 2149 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2150 clock-names = "se"; 2151 pinctrl-0 = <&qup_i2c16_data_clk>; 2152 pinctrl-names = "default"; 2153 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2157 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2158 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2159 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2160 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2162 interconnect-names = "qup-core", 2163 "qup-config", 2164 "qup-memory"; 2165 power-domains = <&rpmhpd RPMHPD_CX>; 2166 required-opps = <&rpmhpd_opp_low_svs>; 2167 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2168 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2169 dma-names = "tx", 2170 "rx"; 2171 status = "disabled"; 2172 }; 2173 2174 spi16: spi@b80000 { 2175 compatible = "qcom,geni-spi"; 2176 reg = <0x0 0xb80000 0x0 0x4000>; 2177 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2178 clock-names = "se"; 2179 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2180 pinctrl-names = "default"; 2181 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2185 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2186 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2187 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2188 interconnect-names = "qup-core", 2189 "qup-config"; 2190 power-domains = <&rpmhpd RPMHPD_CX>; 2191 operating-points-v2 = <&qup_opp_table>; 2192 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2193 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2194 dma-names = "tx", 2195 "rx"; 2196 status = "disabled"; 2197 }; 2198 2199 uart16: serial@b80000 { 2200 compatible = "qcom,geni-uart"; 2201 reg = <0x0 0xb80000 0x0 0x4000>; 2202 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2203 clock-names = "se"; 2204 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2205 <&qup_uart16_tx>, <&qup_uart16_rx>; 2206 pinctrl-names = "default"; 2207 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2208 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2209 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2211 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2212 interconnect-names = "qup-core", 2213 "qup-config"; 2214 power-domains = <&rpmhpd RPMHPD_CX>; 2215 operating-points-v2 = <&qup_opp_table>; 2216 status = "disabled"; 2217 }; 2218 }; 2219 2220 rng: rng@10d2000 { 2221 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2222 reg = <0x0 0x010d2000 0x0 0x1000>; 2223 }; 2224 2225 config_noc: interconnect@14c0000 { 2226 compatible = "qcom,qcs8300-config-noc"; 2227 reg = <0x0 0x014c0000 0x0 0x13080>; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 system_noc: interconnect@1680000 { 2233 compatible = "qcom,qcs8300-system-noc"; 2234 reg = <0x0 0x01680000 0x0 0x15080>; 2235 #interconnect-cells = <2>; 2236 qcom,bcm-voters = <&apps_bcm_voter>; 2237 }; 2238 2239 aggre1_noc: interconnect@16c0000 { 2240 compatible = "qcom,qcs8300-aggre1-noc"; 2241 reg = <0x0 0x016c0000 0x0 0x17080>; 2242 #interconnect-cells = <2>; 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2245 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2246 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2247 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2248 }; 2249 2250 aggre2_noc: interconnect@1700000 { 2251 compatible = "qcom,qcs8300-aggre2-noc"; 2252 reg = <0x0 0x01700000 0x0 0x1a080>; 2253 #interconnect-cells = <2>; 2254 qcom,bcm-voters = <&apps_bcm_voter>; 2255 clocks = <&rpmhcc RPMH_IPA_CLK>; 2256 }; 2257 2258 pcie_anoc: interconnect@1760000 { 2259 compatible = "qcom,qcs8300-pcie-anoc"; 2260 reg = <0x0 0x01760000 0x0 0xc080>; 2261 #interconnect-cells = <2>; 2262 qcom,bcm-voters = <&apps_bcm_voter>; 2263 }; 2264 2265 gpdsp_anoc: interconnect@1780000 { 2266 compatible = "qcom,qcs8300-gpdsp-anoc"; 2267 reg = <0x0 0x01780000 0x0 0xd080>; 2268 #interconnect-cells = <2>; 2269 qcom,bcm-voters = <&apps_bcm_voter>; 2270 }; 2271 2272 mmss_noc: interconnect@17a0000 { 2273 compatible = "qcom,qcs8300-mmss-noc"; 2274 reg = <0x0 0x017a0000 0x0 0x40000>; 2275 #interconnect-cells = <2>; 2276 qcom,bcm-voters = <&apps_bcm_voter>; 2277 }; 2278 2279 pcie0: pci@1c00000 { 2280 device_type = "pci"; 2281 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2282 reg = <0x0 0x01c00000 0x0 0x3000>, 2283 <0x0 0x40000000 0x0 0xf20>, 2284 <0x0 0x40000f20 0x0 0xa8>, 2285 <0x0 0x40001000 0x0 0x4000>, 2286 <0x0 0x40100000 0x0 0x100000>, 2287 <0x0 0x01c03000 0x0 0x1000>; 2288 reg-names = "parf", 2289 "dbi", 2290 "elbi", 2291 "atu", 2292 "config", 2293 "mhi"; 2294 #address-cells = <3>; 2295 #size-cells = <2>; 2296 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2297 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2298 bus-range = <0x00 0xff>; 2299 2300 dma-coherent; 2301 2302 linux,pci-domain = <0>; 2303 num-lanes = <2>; 2304 2305 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2314 interrupt-names = "msi0", 2315 "msi1", 2316 "msi2", 2317 "msi3", 2318 "msi4", 2319 "msi5", 2320 "msi6", 2321 "msi7", 2322 "global"; 2323 2324 #interrupt-cells = <1>; 2325 interrupt-map-mask = <0 0 0 0x7>; 2326 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2327 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2328 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2329 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2330 2331 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2332 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2333 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2334 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2335 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2336 clock-names = "aux", 2337 "cfg", 2338 "bus_master", 2339 "bus_slave", 2340 "slave_q2a"; 2341 2342 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2343 assigned-clock-rates = <19200000>; 2344 2345 interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2348 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2349 interconnect-names = "pcie-mem", 2350 "cpu-pcie"; 2351 2352 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 2353 <0x100 &pcie_smmu 0x0001 0x1>; 2354 2355 resets = <&gcc GCC_PCIE_0_BCR>, 2356 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2357 reset-names = "pci", 2358 "link_down"; 2359 2360 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2361 2362 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2363 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2364 2365 operating-points-v2 = <&pcie0_opp_table>; 2366 2367 status = "disabled"; 2368 2369 pcie0_opp_table: opp-table { 2370 compatible = "operating-points-v2"; 2371 2372 /* GEN 1 x1 */ 2373 opp-2500000 { 2374 opp-hz = /bits/ 64 <2500000>; 2375 required-opps = <&rpmhpd_opp_svs_l1>; 2376 opp-peak-kBps = <250000 1>; 2377 }; 2378 2379 /* GEN 1 x2 and GEN 2 x1 */ 2380 opp-5000000 { 2381 opp-hz = /bits/ 64 <5000000>; 2382 required-opps = <&rpmhpd_opp_svs_l1>; 2383 opp-peak-kBps = <500000 1>; 2384 }; 2385 2386 /* GEN 2 x2 */ 2387 opp-10000000 { 2388 opp-hz = /bits/ 64 <10000000>; 2389 required-opps = <&rpmhpd_opp_svs_l1>; 2390 opp-peak-kBps = <1000000 1>; 2391 }; 2392 2393 /* GEN 3 x1 */ 2394 opp-8000000 { 2395 opp-hz = /bits/ 64 <8000000>; 2396 required-opps = <&rpmhpd_opp_svs_l1>; 2397 opp-peak-kBps = <984500 1>; 2398 }; 2399 2400 /* GEN 3 x2 and GEN 4 x1 */ 2401 opp-16000000 { 2402 opp-hz = /bits/ 64 <16000000>; 2403 required-opps = <&rpmhpd_opp_nom>; 2404 opp-peak-kBps = <1969000 1>; 2405 }; 2406 2407 /* GEN 4 x2 */ 2408 opp-32000000 { 2409 opp-hz = /bits/ 64 <32000000>; 2410 required-opps = <&rpmhpd_opp_nom>; 2411 opp-peak-kBps = <3938000 1>; 2412 }; 2413 }; 2414 2415 pcieport0: pcie@0 { 2416 device_type = "pci"; 2417 reg = <0x0 0x0 0x0 0x0 0x0>; 2418 bus-range = <0x01 0xff>; 2419 2420 #address-cells = <3>; 2421 #size-cells = <2>; 2422 ranges; 2423 phys = <&pcie0_phy>; 2424 }; 2425 }; 2426 2427 pcie0_phy: phy@1c04000 { 2428 compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; 2429 reg = <0x0 0x01c04000 0x0 0x2000>; 2430 2431 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2432 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2433 <&gcc GCC_PCIE_CLKREF_EN>, 2434 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2435 <&gcc GCC_PCIE_0_PIPE_CLK>, 2436 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2437 clock-names = "aux", 2438 "cfg_ahb", 2439 "ref", 2440 "rchng", 2441 "pipe", 2442 "pipediv2"; 2443 2444 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2445 reset-names = "phy"; 2446 2447 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2448 assigned-clock-rates = <100000000>; 2449 2450 #clock-cells = <0>; 2451 clock-output-names = "pcie_0_pipe_clk"; 2452 2453 #phy-cells = <0>; 2454 2455 status = "disabled"; 2456 }; 2457 2458 pcie1: pci@1c10000 { 2459 device_type = "pci"; 2460 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2461 reg = <0x0 0x01c10000 0x0 0x3000>, 2462 <0x0 0x60000000 0x0 0xf20>, 2463 <0x0 0x60000f20 0x0 0xa8>, 2464 <0x0 0x60001000 0x0 0x4000>, 2465 <0x0 0x60100000 0x0 0x100000>, 2466 <0x0 0x01c13000 0x0 0x1000>; 2467 reg-names = "parf", 2468 "dbi", 2469 "elbi", 2470 "atu", 2471 "config", 2472 "mhi"; 2473 #address-cells = <3>; 2474 #size-cells = <2>; 2475 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2476 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2477 bus-range = <0x00 0xff>; 2478 2479 dma-coherent; 2480 2481 linux,pci-domain = <1>; 2482 num-lanes = <4>; 2483 2484 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2493 interrupt-names = "msi0", 2494 "msi1", 2495 "msi2", 2496 "msi3", 2497 "msi4", 2498 "msi5", 2499 "msi6", 2500 "msi7", 2501 "global"; 2502 #interrupt-cells = <1>; 2503 interrupt-map-mask = <0 0 0 0x7>; 2504 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2505 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2506 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2507 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2510 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2511 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2512 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2513 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2514 clock-names = "aux", 2515 "cfg", 2516 "bus_master", 2517 "bus_slave", 2518 "slave_q2a"; 2519 2520 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2521 assigned-clock-rates = <19200000>; 2522 2523 interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2525 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2526 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2527 interconnect-names = "pcie-mem", "cpu-pcie"; 2528 2529 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 2530 <0x100 &pcie_smmu 0x0081 0x1>; 2531 2532 resets = <&gcc GCC_PCIE_1_BCR>, 2533 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2534 reset-names = "pci", 2535 "link_down"; 2536 2537 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2538 2539 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2540 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2541 2542 operating-points-v2 = <&pcie1_opp_table>; 2543 2544 status = "disabled"; 2545 2546 pcie1_opp_table: opp-table { 2547 compatible = "operating-points-v2"; 2548 2549 /* GEN 1 x1 */ 2550 opp-2500000 { 2551 opp-hz = /bits/ 64 <2500000>; 2552 required-opps = <&rpmhpd_opp_svs_l1>; 2553 opp-peak-kBps = <250000 1>; 2554 }; 2555 2556 /* GEN 1 x2 and GEN 2 x1 */ 2557 opp-5000000 { 2558 opp-hz = /bits/ 64 <5000000>; 2559 required-opps = <&rpmhpd_opp_svs_l1>; 2560 opp-peak-kBps = <500000 1>; 2561 }; 2562 2563 /* GEN 1 x4 and GEN 2 x2 */ 2564 opp-10000000 { 2565 opp-hz = /bits/ 64 <10000000>; 2566 required-opps = <&rpmhpd_opp_svs_l1>; 2567 opp-peak-kBps = <1000000 1>; 2568 }; 2569 2570 /* GEN 2 x4 */ 2571 opp-20000000 { 2572 opp-hz = /bits/ 64 <20000000>; 2573 required-opps = <&rpmhpd_opp_low_svs>; 2574 opp-peak-kBps = <2000000 1>; 2575 }; 2576 2577 /* GEN 3 x1 */ 2578 opp-8000000 { 2579 opp-hz = /bits/ 64 <8000000>; 2580 required-opps = <&rpmhpd_opp_svs_l1>; 2581 opp-peak-kBps = <984500 1>; 2582 }; 2583 2584 /* GEN 3 x2 and GEN 4 x1 */ 2585 opp-16000000 { 2586 opp-hz = /bits/ 64 <16000000>; 2587 required-opps = <&rpmhpd_opp_nom>; 2588 opp-peak-kBps = <1969000 1>; 2589 }; 2590 2591 /* GEN 3 x4 and GEN 4 x2 */ 2592 opp-32000000 { 2593 opp-hz = /bits/ 64 <32000000>; 2594 required-opps = <&rpmhpd_opp_nom>; 2595 opp-peak-kBps = <3938000 1>; 2596 }; 2597 2598 /* GEN 4 x4 */ 2599 opp-64000000 { 2600 opp-hz = /bits/ 64 <64000000>; 2601 required-opps = <&rpmhpd_opp_nom>; 2602 opp-peak-kBps = <7876000 1>; 2603 }; 2604 }; 2605 2606 pcieport1: pcie@0 { 2607 device_type = "pci"; 2608 reg = <0x0 0x0 0x0 0x0 0x0>; 2609 bus-range = <0x01 0xff>; 2610 2611 #address-cells = <3>; 2612 #size-cells = <2>; 2613 ranges; 2614 phys = <&pcie1_phy>; 2615 }; 2616 }; 2617 2618 pcie1_phy: phy@1c14000 { 2619 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2620 reg = <0x0 0x01c14000 0x0 0x4000>; 2621 2622 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2623 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2624 <&gcc GCC_PCIE_CLKREF_EN>, 2625 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2626 <&gcc GCC_PCIE_1_PIPE_CLK>, 2627 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 2628 clock-names = "aux", 2629 "cfg_ahb", 2630 "ref", 2631 "rchng", 2632 "pipe", 2633 "pipediv2"; 2634 2635 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2636 assigned-clock-rates = <100000000>; 2637 2638 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2639 reset-names = "phy"; 2640 2641 #clock-cells = <0>; 2642 clock-output-names = "pcie_1_pipe_clk"; 2643 2644 #phy-cells = <0>; 2645 2646 status = "disabled"; 2647 }; 2648 2649 ufs_mem_hc: ufs@1d84000 { 2650 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2651 reg = <0x0 0x01d84000 0x0 0x3000>; 2652 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2653 phys = <&ufs_mem_phy>; 2654 phy-names = "ufsphy"; 2655 lanes-per-direction = <2>; 2656 #reset-cells = <1>; 2657 resets = <&gcc GCC_UFS_PHY_BCR>; 2658 reset-names = "rst"; 2659 2660 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2661 required-opps = <&rpmhpd_opp_nom>; 2662 2663 iommus = <&apps_smmu 0x100 0x0>; 2664 dma-coherent; 2665 2666 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2667 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2668 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2669 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2670 interconnect-names = "ufs-ddr", 2671 "cpu-ufs"; 2672 2673 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2674 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2675 <&gcc GCC_UFS_PHY_AHB_CLK>, 2676 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2677 <&rpmhcc RPMH_CXO_CLK>, 2678 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2679 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2680 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2681 clock-names = "core_clk", 2682 "bus_aggr_clk", 2683 "iface_clk", 2684 "core_clk_unipro", 2685 "ref_clk", 2686 "tx_lane0_sync_clk", 2687 "rx_lane0_sync_clk", 2688 "rx_lane1_sync_clk"; 2689 freq-table-hz = <75000000 300000000>, 2690 <0 0>, 2691 <0 0>, 2692 <75000000 300000000>, 2693 <0 0>, 2694 <0 0>, 2695 <0 0>, 2696 <0 0>; 2697 qcom,ice = <&ice>; 2698 status = "disabled"; 2699 }; 2700 2701 ufs_mem_phy: phy@1d87000 { 2702 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2703 reg = <0x0 0x01d87000 0x0 0xe10>; 2704 /* 2705 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2706 * enables the CXO clock to eDP *and* UFS PHY. 2707 */ 2708 clocks = <&rpmhcc RPMH_CXO_CLK>, 2709 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2710 <&gcc GCC_EDP_REF_CLKREF_EN>; 2711 clock-names = "ref", 2712 "ref_aux", 2713 "qref"; 2714 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2715 2716 resets = <&ufs_mem_hc 0>; 2717 reset-names = "ufsphy"; 2718 2719 #phy-cells = <0>; 2720 status = "disabled"; 2721 }; 2722 2723 cryptobam: dma-controller@1dc4000 { 2724 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2725 reg = <0x0 0x01dc4000 0x0 0x28000>; 2726 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2727 #dma-cells = <1>; 2728 qcom,ee = <0>; 2729 qcom,controlled-remotely; 2730 num-channels = <20>; 2731 qcom,num-ees = <4>; 2732 iommus = <&apps_smmu 0x480 0x00>, 2733 <&apps_smmu 0x481 0x00>; 2734 }; 2735 2736 ice: crypto@1d88000 { 2737 compatible = "qcom,qcs8300-inline-crypto-engine", 2738 "qcom,inline-crypto-engine"; 2739 reg = <0x0 0x01d88000 0x0 0x18000>; 2740 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 2741 <&gcc GCC_UFS_PHY_AHB_CLK>; 2742 clock-names = "core", 2743 "iface"; 2744 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2745 }; 2746 2747 crypto: crypto@1dfa000 { 2748 compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; 2749 reg = <0x0 0x01dfa000 0x0 0x6000>; 2750 dmas = <&cryptobam 4>, <&cryptobam 5>; 2751 dma-names = "rx", "tx"; 2752 iommus = <&apps_smmu 0x480 0x0>, 2753 <&apps_smmu 0x481 0x0>; 2754 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2755 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2756 interconnect-names = "memory"; 2757 }; 2758 2759 tcsr_mutex: hwlock@1f40000 { 2760 compatible = "qcom,tcsr-mutex"; 2761 reg = <0x0 0x01f40000 0x0 0x20000>; 2762 #hwlock-cells = <1>; 2763 }; 2764 2765 tcsr: syscon@1fc0000 { 2766 compatible = "qcom,qcs8300-tcsr", "syscon"; 2767 reg = <0x0 0x1fc0000 0x0 0x30000>; 2768 }; 2769 2770 remoteproc_adsp: remoteproc@3000000 { 2771 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2772 reg = <0x0 0x3000000 0x0 0x00100>; 2773 2774 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2775 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2776 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2777 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2778 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2779 interrupt-names = "wdog", 2780 "fatal", 2781 "ready", 2782 "handover", 2783 "stop-ack"; 2784 2785 clocks = <&rpmhcc RPMH_CXO_CLK>; 2786 clock-names = "xo"; 2787 2788 power-domains = <&rpmhpd RPMHPD_LCX>, 2789 <&rpmhpd RPMHPD_LMX>; 2790 power-domain-names = "lcx", 2791 "lmx"; 2792 2793 memory-region = <&adsp_mem>; 2794 2795 qcom,qmp = <&aoss_qmp>; 2796 2797 qcom,smem-states = <&smp2p_adsp_out 0>; 2798 qcom,smem-state-names = "stop"; 2799 2800 status = "disabled"; 2801 2802 glink-edge { 2803 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2804 IPCC_MPROC_SIGNAL_GLINK_QMP 2805 IRQ_TYPE_EDGE_RISING>; 2806 mboxes = <&ipcc IPCC_CLIENT_LPASS 2807 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2808 2809 label = "lpass"; 2810 qcom,remote-pid = <2>; 2811 2812 fastrpc { 2813 compatible = "qcom,fastrpc"; 2814 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2815 label = "adsp"; 2816 memory-region = <&adsp_rpc_remote_heap_mem>; 2817 qcom,vmids = <QCOM_SCM_VMID_LPASS 2818 QCOM_SCM_VMID_ADSP_HEAP>; 2819 #address-cells = <1>; 2820 #size-cells = <0>; 2821 2822 compute-cb@3 { 2823 compatible = "qcom,fastrpc-compute-cb"; 2824 reg = <3>; 2825 iommus = <&apps_smmu 0x2003 0x0>; 2826 dma-coherent; 2827 }; 2828 2829 compute-cb@4 { 2830 compatible = "qcom,fastrpc-compute-cb"; 2831 reg = <4>; 2832 iommus = <&apps_smmu 0x2004 0x0>; 2833 dma-coherent; 2834 }; 2835 2836 compute-cb@5 { 2837 compatible = "qcom,fastrpc-compute-cb"; 2838 reg = <5>; 2839 iommus = <&apps_smmu 0x2005 0x0>; 2840 dma-coherent; 2841 }; 2842 }; 2843 2844 gpr { 2845 compatible = "qcom,gpr"; 2846 qcom,glink-channels = "adsp_apps"; 2847 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2848 qcom,intents = <512 20>; 2849 #address-cells = <1>; 2850 #size-cells = <0>; 2851 2852 q6apm: service@1 { 2853 compatible = "qcom,q6apm"; 2854 reg = <GPR_APM_MODULE_IID>; 2855 #sound-dai-cells = <0>; 2856 qcom,protection-domain = "avs/audio", 2857 "msm/adsp/audio_pd"; 2858 2859 q6apmbedai: bedais { 2860 compatible = "qcom,q6apm-lpass-dais"; 2861 #sound-dai-cells = <1>; 2862 }; 2863 2864 q6apmdai: dais { 2865 compatible = "qcom,q6apm-dais"; 2866 iommus = <&apps_smmu 0x2001 0x0>; 2867 }; 2868 }; 2869 2870 q6prm: service@2 { 2871 compatible = "qcom,q6prm"; 2872 reg = <GPR_PRM_MODULE_IID>; 2873 qcom,protection-domain = "avs/audio", 2874 "msm/adsp/audio_pd"; 2875 2876 q6prmcc: clock-controller { 2877 compatible = "qcom,q6prm-lpass-clocks"; 2878 #clock-cells = <2>; 2879 }; 2880 }; 2881 }; 2882 }; 2883 }; 2884 2885 lpass_tlmm: pinctrl@3440000 { 2886 compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; 2887 reg = <0x0 0x03440000 0x0 0x20000>, 2888 <0x0 0x034d0000 0x0 0x10000>; 2889 2890 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2891 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2892 clock-names = "core", "audio"; 2893 2894 gpio-controller; 2895 #gpio-cells = <2>; 2896 gpio-ranges = <&lpass_tlmm 0 0 23>; 2897 2898 quad_mclk_active: quad-mclk-state { 2899 clk-pins { 2900 pins = "gpio5"; 2901 function = "ext_mclk1_c"; 2902 drive-strength = <8>; 2903 bias-disable; 2904 }; 2905 }; 2906 2907 quad_mi2s_active: quad-active-state { 2908 data-pins { 2909 pins = "gpio2", "gpio3"; 2910 function = "qua_mi2s_data"; 2911 drive-strength = <8>; 2912 bias-disable; 2913 }; 2914 2915 sclk-pins { 2916 pins = "gpio0"; 2917 function = "qua_mi2s_sclk"; 2918 drive-strength = <8>; 2919 bias-disable; 2920 }; 2921 2922 ws-pins { 2923 pins = "gpio1"; 2924 function = "qua_mi2s_ws"; 2925 drive-strength = <8>; 2926 bias-disable; 2927 }; 2928 }; 2929 2930 lpi_i2s4_active: lpi_i2s4-active-state { 2931 data0-pins { 2932 pins = "gpio17"; 2933 function = "i2s4_data"; 2934 drive-strength = <8>; 2935 bias-disable; 2936 }; 2937 2938 clk-pins { 2939 pins = "gpio12"; 2940 function = "i2s4_clk"; 2941 drive-strength = <8>; 2942 bias-disable; 2943 }; 2944 2945 ws-pins { 2946 pins = "gpio13"; 2947 function = "i2s4_ws"; 2948 drive-strength = <8>; 2949 bias-disable; 2950 }; 2951 }; 2952 }; 2953 2954 lpass_ag_noc: interconnect@3c40000 { 2955 compatible = "qcom,qcs8300-lpass-ag-noc"; 2956 reg = <0x0 0x03c40000 0x0 0x17200>; 2957 #interconnect-cells = <2>; 2958 qcom,bcm-voters = <&apps_bcm_voter>; 2959 }; 2960 2961 ctcu@4001000 { 2962 compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; 2963 reg = <0x0 0x04001000 0x0 0x1000>; 2964 2965 clocks = <&aoss_qmp>; 2966 clock-names = "apb"; 2967 2968 in-ports { 2969 #address-cells = <1>; 2970 #size-cells = <0>; 2971 2972 port@0 { 2973 reg = <0>; 2974 2975 ctcu_in0: endpoint { 2976 remote-endpoint = <&etr0_out>; 2977 }; 2978 }; 2979 2980 port@1 { 2981 reg = <1>; 2982 2983 ctcu_in1: endpoint { 2984 remote-endpoint = <&etr1_out>; 2985 }; 2986 }; 2987 }; 2988 }; 2989 2990 stm@4002000 { 2991 compatible = "arm,coresight-stm", "arm,primecell"; 2992 reg = <0x0 0x04002000 0x0 0x1000>, 2993 <0x0 0x16280000 0x0 0x180000>; 2994 reg-names = "stm-base", 2995 "stm-stimulus-base"; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 3000 out-ports { 3001 port { 3002 stm_out: endpoint { 3003 remote-endpoint = <&funnel0_in7>; 3004 }; 3005 }; 3006 }; 3007 }; 3008 3009 tpda@4004000 { 3010 compatible = "qcom,coresight-tpda", "arm,primecell"; 3011 reg = <0x0 0x04004000 0x0 0x1000>; 3012 3013 clocks = <&aoss_qmp>; 3014 clock-names = "apb_pclk"; 3015 3016 in-ports { 3017 #address-cells = <1>; 3018 #size-cells = <0>; 3019 3020 port@0 { 3021 reg = <0>; 3022 3023 swao_rep_out0: endpoint { 3024 remote-endpoint = <&qdss_rep_in>; 3025 }; 3026 }; 3027 3028 port@1 { 3029 reg = <1>; 3030 3031 qdss_tpda_in1: endpoint { 3032 remote-endpoint = <&qdss_tpdm1_out>; 3033 }; 3034 }; 3035 }; 3036 3037 out-ports { 3038 port { 3039 qdss_tpda_out: endpoint { 3040 remote-endpoint = <&funnel0_in6>; 3041 }; 3042 }; 3043 }; 3044 }; 3045 3046 tpdm@400f000 { 3047 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3048 reg = <0x0 0x0400f000 0x0 0x1000>; 3049 3050 clocks = <&aoss_qmp>; 3051 clock-names = "apb_pclk"; 3052 3053 qcom,cmb-element-bits = <32>; 3054 qcom,cmb-msrs-num = <32>; 3055 3056 out-ports { 3057 port { 3058 qdss_tpdm1_out: endpoint { 3059 remote-endpoint = <&qdss_tpda_in1>; 3060 }; 3061 }; 3062 }; 3063 }; 3064 3065 funnel@4041000 { 3066 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3067 reg = <0x0 0x04041000 0x0 0x1000>; 3068 3069 clocks = <&aoss_qmp>; 3070 clock-names = "apb_pclk"; 3071 3072 in-ports { 3073 #address-cells = <1>; 3074 #size-cells = <0>; 3075 3076 port@6 { 3077 reg = <6>; 3078 3079 funnel0_in6: endpoint { 3080 remote-endpoint = <&qdss_tpda_out>; 3081 }; 3082 }; 3083 3084 port@7 { 3085 reg = <7>; 3086 3087 funnel0_in7: endpoint { 3088 remote-endpoint = <&stm_out>; 3089 }; 3090 }; 3091 }; 3092 3093 out-ports { 3094 port { 3095 funnel0_out: endpoint { 3096 remote-endpoint = <&qdss_funnel_in0>; 3097 }; 3098 }; 3099 }; 3100 }; 3101 3102 funnel@4042000 { 3103 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3104 reg = <0x0 0x04042000 0x0 0x1000>; 3105 3106 clocks = <&aoss_qmp>; 3107 clock-names = "apb_pclk"; 3108 3109 in-ports { 3110 #address-cells = <1>; 3111 #size-cells = <0>; 3112 3113 port@4 { 3114 reg = <4>; 3115 3116 funnel1_in4: endpoint { 3117 remote-endpoint = <&apss_funnel1_out>; 3118 }; 3119 }; 3120 3121 port@5 { 3122 reg = <5>; 3123 3124 funnel1_in5: endpoint { 3125 remote-endpoint = <&dlct0_funnel_out>; 3126 }; 3127 }; 3128 3129 port@6 { 3130 reg = <6>; 3131 3132 funnel1_in6: endpoint { 3133 remote-endpoint = <&dlmm_funnel_out>; 3134 }; 3135 }; 3136 3137 port@7 { 3138 reg = <7>; 3139 3140 funnel1_in7: endpoint { 3141 remote-endpoint = <&dlst_ch_funnel_out>; 3142 }; 3143 }; 3144 }; 3145 3146 out-ports { 3147 port { 3148 funnel1_out: endpoint { 3149 remote-endpoint = <&qdss_funnel_in1>; 3150 }; 3151 }; 3152 }; 3153 }; 3154 3155 funnel@4045000 { 3156 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3157 reg = <0x0 0x04045000 0x0 0x1000>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 3162 in-ports { 3163 #address-cells = <1>; 3164 #size-cells = <0>; 3165 3166 port@0 { 3167 reg = <0>; 3168 3169 qdss_funnel_in0: endpoint { 3170 remote-endpoint = <&funnel0_out>; 3171 }; 3172 }; 3173 3174 port@1 { 3175 reg = <1>; 3176 3177 qdss_funnel_in1: endpoint { 3178 remote-endpoint = <&funnel1_out>; 3179 }; 3180 }; 3181 }; 3182 3183 out-ports { 3184 port { 3185 qdss_funnel_out: endpoint { 3186 remote-endpoint = <&aoss_funnel_in7>; 3187 }; 3188 }; 3189 }; 3190 }; 3191 3192 replicator@4046000 { 3193 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3194 reg = <0x0 0x04046000 0x0 0x1000>; 3195 3196 clocks = <&aoss_qmp>; 3197 clock-names = "apb_pclk"; 3198 3199 in-ports { 3200 port { 3201 qdss_rep_in: endpoint { 3202 remote-endpoint = <&swao_rep_out0>; 3203 }; 3204 }; 3205 }; 3206 3207 out-ports { 3208 port { 3209 qdss_rep_out0: endpoint { 3210 remote-endpoint = <&etr_rep_in>; 3211 }; 3212 }; 3213 }; 3214 }; 3215 3216 tmc@4048000 { 3217 compatible = "arm,coresight-tmc", "arm,primecell"; 3218 reg = <0x0 0x04048000 0x0 0x1000>; 3219 3220 clocks = <&aoss_qmp>; 3221 clock-names = "apb_pclk"; 3222 iommus = <&apps_smmu 0x04c0 0x00>; 3223 3224 arm,scatter-gather; 3225 3226 in-ports { 3227 port { 3228 etr0_in: endpoint { 3229 remote-endpoint = <&etr_rep_out0>; 3230 }; 3231 }; 3232 }; 3233 3234 out-ports { 3235 port { 3236 etr0_out: endpoint { 3237 remote-endpoint = <&ctcu_in0>; 3238 }; 3239 }; 3240 }; 3241 }; 3242 3243 replicator@404e000 { 3244 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3245 reg = <0x0 0x0404e000 0x0 0x1000>; 3246 3247 clocks = <&aoss_qmp>; 3248 clock-names = "apb_pclk"; 3249 3250 in-ports { 3251 port { 3252 etr_rep_in: endpoint { 3253 remote-endpoint = <&qdss_rep_out0>; 3254 }; 3255 }; 3256 }; 3257 3258 out-ports { 3259 #address-cells = <1>; 3260 #size-cells = <0>; 3261 3262 port@0 { 3263 reg = <0>; 3264 3265 etr_rep_out0: endpoint { 3266 remote-endpoint = <&etr0_in>; 3267 }; 3268 }; 3269 3270 port@1 { 3271 reg = <1>; 3272 3273 etr_rep_out1: endpoint { 3274 remote-endpoint = <&etr1_in>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 tmc@404f000 { 3281 compatible = "arm,coresight-tmc", "arm,primecell"; 3282 reg = <0x0 0x0404f000 0x0 0x1000>; 3283 3284 clocks = <&aoss_qmp>; 3285 clock-names = "apb_pclk"; 3286 iommus = <&apps_smmu 0x04a0 0x40>; 3287 3288 arm,scatter-gather; 3289 arm,buffer-size = <0x400000>; 3290 3291 in-ports { 3292 port { 3293 etr1_in: endpoint { 3294 remote-endpoint = <&etr_rep_out1>; 3295 }; 3296 }; 3297 }; 3298 3299 out-ports { 3300 port { 3301 etr1_out: endpoint { 3302 remote-endpoint = <&ctcu_in1>; 3303 }; 3304 }; 3305 }; 3306 }; 3307 3308 tpdm@4841000 { 3309 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3310 reg = <0x0 0x04841000 0x0 0x1000>; 3311 3312 clocks = <&aoss_qmp>; 3313 clock-names = "apb_pclk"; 3314 3315 qcom,cmb-element-bits = <32>; 3316 qcom,cmb-msrs-num = <32>; 3317 3318 out-ports { 3319 port { 3320 prng_tpdm_out: endpoint { 3321 remote-endpoint = <&dlct0_tpda_in19>; 3322 }; 3323 }; 3324 }; 3325 }; 3326 3327 tpdm@4850000 { 3328 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3329 reg = <0x0 0x04850000 0x0 0x1000>; 3330 3331 clocks = <&aoss_qmp>; 3332 clock-names = "apb_pclk"; 3333 3334 qcom,cmb-element-bits = <64>; 3335 qcom,cmb-msrs-num = <32>; 3336 qcom,dsb-element-bits = <32>; 3337 qcom,dsb-msrs-num = <32>; 3338 3339 out-ports { 3340 port { 3341 pimem_tpdm_out: endpoint { 3342 remote-endpoint = <&dlct0_tpda_in25>; 3343 }; 3344 }; 3345 }; 3346 }; 3347 3348 tpdm@4860000 { 3349 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3350 reg = <0x0 0x04860000 0x0 0x1000>; 3351 3352 clocks = <&aoss_qmp>; 3353 clock-names = "apb_pclk"; 3354 3355 qcom,dsb-element-bits = <32>; 3356 qcom,dsb-msrs-num = <32>; 3357 3358 out-ports { 3359 port { 3360 dlst_ch_tpdm0_out: endpoint { 3361 remote-endpoint = <&dlst_ch_tpda_in8>; 3362 }; 3363 }; 3364 }; 3365 }; 3366 3367 tpda@4864000 { 3368 compatible = "qcom,coresight-tpda", "arm,primecell"; 3369 reg = <0x0 0x04864000 0x0 0x1000>; 3370 3371 clocks = <&aoss_qmp>; 3372 clock-names = "apb_pclk"; 3373 3374 in-ports { 3375 #address-cells = <1>; 3376 #size-cells = <0>; 3377 3378 port@8 { 3379 reg = <8>; 3380 3381 dlst_ch_tpda_in8: endpoint { 3382 remote-endpoint = <&dlst_ch_tpdm0_out>; 3383 }; 3384 }; 3385 }; 3386 3387 out-ports { 3388 port { 3389 dlst_ch_tpda_out: endpoint { 3390 remote-endpoint = <&dlst_ch_funnel_in0>; 3391 }; 3392 }; 3393 }; 3394 }; 3395 3396 funnel@4865000 { 3397 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3398 reg = <0x0 0x04865000 0x0 0x1000>; 3399 3400 clocks = <&aoss_qmp>; 3401 clock-names = "apb_pclk"; 3402 3403 in-ports { 3404 #address-cells = <1>; 3405 #size-cells = <0>; 3406 3407 port@0 { 3408 reg = <0>; 3409 3410 dlst_ch_funnel_in0: endpoint { 3411 remote-endpoint = <&dlst_ch_tpda_out>; 3412 }; 3413 }; 3414 3415 port@4 { 3416 reg = <4>; 3417 3418 dlst_ch_funnel_in4: endpoint { 3419 remote-endpoint = <&dlst_funnel_out>; 3420 }; 3421 }; 3422 3423 port@6 { 3424 reg = <6>; 3425 3426 dlst_ch_funnel_in6: endpoint { 3427 remote-endpoint = <&gdsp_funnel_out>; 3428 }; 3429 }; 3430 }; 3431 3432 out-ports { 3433 port { 3434 dlst_ch_funnel_out: endpoint { 3435 remote-endpoint = <&funnel1_in7>; 3436 }; 3437 }; 3438 }; 3439 }; 3440 3441 tpdm@4980000 { 3442 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3443 reg = <0x0 0x04980000 0x0 0x1000>; 3444 3445 clocks = <&aoss_qmp>; 3446 clock-names = "apb_pclk"; 3447 3448 qcom,dsb-element-bits = <32>; 3449 qcom,dsb-msrs-num = <32>; 3450 3451 out-ports { 3452 port { 3453 turing2_tpdm_out: endpoint { 3454 remote-endpoint = <&turing2_funnel_in0>; 3455 }; 3456 }; 3457 }; 3458 }; 3459 3460 funnel@4983000 { 3461 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3462 reg = <0x0 0x04983000 0x0 0x1000>; 3463 3464 clocks = <&aoss_qmp>; 3465 clock-names = "apb_pclk"; 3466 3467 in-ports { 3468 port { 3469 turing2_funnel_in0: endpoint { 3470 remote-endpoint = <&turing2_tpdm_out>; 3471 }; 3472 }; 3473 }; 3474 3475 out-ports { 3476 port { 3477 turing2_funnel_out0: endpoint { 3478 remote-endpoint = <&gdsp_tpda_in5>; 3479 }; 3480 }; 3481 }; 3482 }; 3483 3484 tpdm@4ac0000 { 3485 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3486 reg = <0x0 0x04ac0000 0x0 0x1000>; 3487 3488 clocks = <&aoss_qmp>; 3489 clock-names = "apb_pclk"; 3490 3491 qcom,dsb-element-bits = <32>; 3492 qcom,dsb-msrs-num = <32>; 3493 3494 out-ports { 3495 port { 3496 dlmm_tpdm0_out: endpoint { 3497 remote-endpoint = <&dlmm_tpda_in27>; 3498 }; 3499 }; 3500 }; 3501 }; 3502 3503 tpda@4ac4000 { 3504 compatible = "qcom,coresight-tpda", "arm,primecell"; 3505 reg = <0x0 0x04ac4000 0x0 0x1000>; 3506 3507 clocks = <&aoss_qmp>; 3508 clock-names = "apb_pclk"; 3509 3510 in-ports { 3511 #address-cells = <1>; 3512 #size-cells = <0>; 3513 3514 port@1b { 3515 reg = <27>; 3516 3517 dlmm_tpda_in27: endpoint { 3518 remote-endpoint = <&dlmm_tpdm0_out>; 3519 }; 3520 }; 3521 }; 3522 3523 out-ports { 3524 port { 3525 dlmm_tpda_out: endpoint { 3526 remote-endpoint = <&dlmm_funnel_in0>; 3527 }; 3528 }; 3529 }; 3530 }; 3531 3532 funnel@4ac5000 { 3533 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3534 reg = <0x0 0x04ac5000 0x0 0x1000>; 3535 3536 clocks = <&aoss_qmp>; 3537 clock-names = "apb_pclk"; 3538 3539 in-ports { 3540 port { 3541 dlmm_funnel_in0: endpoint { 3542 remote-endpoint = <&dlmm_tpda_out>; 3543 }; 3544 }; 3545 }; 3546 3547 out-ports { 3548 port { 3549 dlmm_funnel_out: endpoint { 3550 remote-endpoint = <&funnel1_in6>; 3551 }; 3552 }; 3553 }; 3554 }; 3555 3556 tpdm@4ad0000 { 3557 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3558 reg = <0x0 0x04ad0000 0x0 0x1000>; 3559 3560 clocks = <&aoss_qmp>; 3561 clock-names = "apb_pclk"; 3562 3563 qcom,dsb-element-bits = <32>; 3564 qcom,dsb-msrs-num = <32>; 3565 3566 out-ports { 3567 port { 3568 dlct0_tpdm0_out: endpoint { 3569 remote-endpoint = <&dlct0_tpda_in26>; 3570 }; 3571 }; 3572 }; 3573 }; 3574 3575 tpda@4ad3000 { 3576 compatible = "qcom,coresight-tpda", "arm,primecell"; 3577 reg = <0x0 0x04ad3000 0x0 0x1000>; 3578 3579 clocks = <&aoss_qmp>; 3580 clock-names = "apb_pclk"; 3581 3582 in-ports { 3583 #address-cells = <1>; 3584 #size-cells = <0>; 3585 3586 port@13 { 3587 reg = <19>; 3588 3589 dlct0_tpda_in19: endpoint { 3590 remote-endpoint = <&prng_tpdm_out>; 3591 }; 3592 }; 3593 3594 port@19 { 3595 reg = <25>; 3596 3597 dlct0_tpda_in25: endpoint { 3598 remote-endpoint = <&pimem_tpdm_out>; 3599 }; 3600 }; 3601 3602 port@1a { 3603 reg = <26>; 3604 3605 dlct0_tpda_in26: endpoint { 3606 remote-endpoint = <&dlct0_tpdm0_out>; 3607 }; 3608 }; 3609 }; 3610 3611 out-ports { 3612 port { 3613 dlct0_tpda_out: endpoint { 3614 remote-endpoint = <&dlct0_funnel_in0>; 3615 }; 3616 }; 3617 }; 3618 }; 3619 3620 funnel@4ad4000 { 3621 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3622 reg = <0x0 0x04ad4000 0x0 0x1000>; 3623 3624 clocks = <&aoss_qmp>; 3625 clock-names = "apb_pclk"; 3626 3627 in-ports { 3628 #address-cells = <1>; 3629 #size-cells = <0>; 3630 3631 port@0 { 3632 reg = <0>; 3633 3634 dlct0_funnel_in0: endpoint { 3635 remote-endpoint = <&dlct0_tpda_out>; 3636 }; 3637 }; 3638 3639 port@4 { 3640 reg = <4>; 3641 3642 dlct0_funnel_in4: endpoint { 3643 remote-endpoint = <&ddr_funnel5_out>; 3644 }; 3645 }; 3646 }; 3647 3648 out-ports { 3649 port { 3650 dlct0_funnel_out: endpoint { 3651 remote-endpoint = <&funnel1_in5>; 3652 }; 3653 }; 3654 }; 3655 }; 3656 3657 funnel@4b04000 { 3658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3659 reg = <0x0 0x04b04000 0x0 0x1000>; 3660 3661 clocks = <&aoss_qmp>; 3662 clock-names = "apb_pclk"; 3663 3664 in-ports { 3665 #address-cells = <1>; 3666 #size-cells = <0>; 3667 3668 port@6 { 3669 reg = <6>; 3670 3671 aoss_funnel_in6: endpoint { 3672 remote-endpoint = <&aoss_tpda_out>; 3673 }; 3674 }; 3675 3676 port@7 { 3677 reg = <7>; 3678 3679 aoss_funnel_in7: endpoint { 3680 remote-endpoint = <&qdss_funnel_out>; 3681 }; 3682 }; 3683 }; 3684 3685 out-ports { 3686 port { 3687 aoss_funnel_out: endpoint { 3688 remote-endpoint = <&etf0_in>; 3689 }; 3690 }; 3691 }; 3692 }; 3693 3694 tmc_etf: tmc@4b05000 { 3695 compatible = "arm,coresight-tmc", "arm,primecell"; 3696 reg = <0x0 0x04b05000 0x0 0x1000>; 3697 3698 clocks = <&aoss_qmp>; 3699 clock-names = "apb_pclk"; 3700 3701 in-ports { 3702 port { 3703 etf0_in: endpoint { 3704 remote-endpoint = <&aoss_funnel_out>; 3705 }; 3706 }; 3707 }; 3708 3709 out-ports { 3710 port { 3711 etf0_out: endpoint { 3712 remote-endpoint = <&swao_rep_in>; 3713 }; 3714 }; 3715 }; 3716 }; 3717 3718 replicator@4b06000 { 3719 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3720 reg = <0x0 0x04b06000 0x0 0x1000>; 3721 3722 clocks = <&aoss_qmp>; 3723 clock-names = "apb_pclk"; 3724 3725 in-ports { 3726 port { 3727 swao_rep_in: endpoint { 3728 remote-endpoint = <&etf0_out>; 3729 }; 3730 }; 3731 }; 3732 3733 out-ports { 3734 #address-cells = <1>; 3735 #size-cells = <0>; 3736 3737 port@1 { 3738 reg = <1>; 3739 3740 swao_rep_out1: endpoint { 3741 remote-endpoint = <&eud_in>; 3742 }; 3743 }; 3744 }; 3745 }; 3746 3747 tpda@4b08000 { 3748 compatible = "qcom,coresight-tpda", "arm,primecell"; 3749 reg = <0x0 0x04b08000 0x0 0x1000>; 3750 3751 clocks = <&aoss_qmp>; 3752 clock-names = "apb_pclk"; 3753 3754 in-ports { 3755 #address-cells = <1>; 3756 #size-cells = <0>; 3757 3758 port@0 { 3759 reg = <0>; 3760 3761 aoss_tpda_in0: endpoint { 3762 remote-endpoint = <&aoss_tpdm0_out>; 3763 }; 3764 }; 3765 3766 port@1 { 3767 reg = <1>; 3768 3769 aoss_tpda_in1: endpoint { 3770 remote-endpoint = <&aoss_tpdm1_out>; 3771 }; 3772 }; 3773 3774 port@2 { 3775 reg = <2>; 3776 3777 aoss_tpda_in2: endpoint { 3778 remote-endpoint = <&aoss_tpdm2_out>; 3779 }; 3780 }; 3781 3782 port@3 { 3783 reg = <3>; 3784 3785 aoss_tpda_in3: endpoint { 3786 remote-endpoint = <&aoss_tpdm3_out>; 3787 }; 3788 }; 3789 3790 port@4 { 3791 reg = <4>; 3792 3793 aoss_tpda_in4: endpoint { 3794 remote-endpoint = <&aoss_tpdm4_out>; 3795 }; 3796 }; 3797 }; 3798 3799 out-ports { 3800 port { 3801 aoss_tpda_out: endpoint { 3802 remote-endpoint = <&aoss_funnel_in6>; 3803 }; 3804 }; 3805 }; 3806 }; 3807 3808 tpdm@4b09000 { 3809 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3810 reg = <0x0 0x04b09000 0x0 0x1000>; 3811 3812 clocks = <&aoss_qmp>; 3813 clock-names = "apb_pclk"; 3814 3815 qcom,cmb-element-bits = <64>; 3816 qcom,cmb-msrs-num = <32>; 3817 3818 out-ports { 3819 port { 3820 aoss_tpdm0_out: endpoint { 3821 remote-endpoint = <&aoss_tpda_in0>; 3822 }; 3823 }; 3824 }; 3825 }; 3826 3827 tpdm@4b0a000 { 3828 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3829 reg = <0x0 0x04b0a000 0x0 0x1000>; 3830 3831 clocks = <&aoss_qmp>; 3832 clock-names = "apb_pclk"; 3833 3834 qcom,cmb-element-bits = <64>; 3835 qcom,cmb-msrs-num = <32>; 3836 3837 out-ports { 3838 port { 3839 aoss_tpdm1_out: endpoint { 3840 remote-endpoint = <&aoss_tpda_in1>; 3841 }; 3842 }; 3843 }; 3844 }; 3845 3846 tpdm@4b0b000 { 3847 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3848 reg = <0x0 0x04b0b000 0x0 0x1000>; 3849 3850 clocks = <&aoss_qmp>; 3851 clock-names = "apb_pclk"; 3852 3853 qcom,cmb-element-bits = <64>; 3854 qcom,cmb-msrs-num = <32>; 3855 3856 out-ports { 3857 port { 3858 aoss_tpdm2_out: endpoint { 3859 remote-endpoint = <&aoss_tpda_in2>; 3860 }; 3861 }; 3862 }; 3863 }; 3864 3865 tpdm@4b0c000 { 3866 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3867 reg = <0x0 0x04b0c000 0x0 0x1000>; 3868 3869 clocks = <&aoss_qmp>; 3870 clock-names = "apb_pclk"; 3871 3872 qcom,cmb-element-bits = <64>; 3873 qcom,cmb-msrs-num = <32>; 3874 3875 out-ports { 3876 port { 3877 aoss_tpdm3_out: endpoint { 3878 remote-endpoint = <&aoss_tpda_in3>; 3879 }; 3880 }; 3881 }; 3882 }; 3883 3884 tpdm@4b0d000 { 3885 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3886 reg = <0x0 0x04b0d000 0x0 0x1000>; 3887 3888 clocks = <&aoss_qmp>; 3889 clock-names = "apb_pclk"; 3890 3891 qcom,dsb-element-bits = <32>; 3892 qcom,dsb-msrs-num = <32>; 3893 3894 out-ports { 3895 port { 3896 aoss_tpdm4_out: endpoint { 3897 remote-endpoint = <&aoss_tpda_in4>; 3898 }; 3899 }; 3900 }; 3901 }; 3902 3903 cti@4b13000 { 3904 compatible = "arm,coresight-cti", "arm,primecell"; 3905 reg = <0x0 0x04b13000 0x0 0x1000>; 3906 3907 clocks = <&aoss_qmp>; 3908 clock-names = "apb_pclk"; 3909 }; 3910 3911 tpdm@4b80000 { 3912 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3913 reg = <0x0 0x04b80000 0x0 0x1000>; 3914 3915 clocks = <&aoss_qmp>; 3916 clock-names = "apb_pclk"; 3917 3918 qcom,dsb-element-bits = <32>; 3919 qcom,dsb-msrs-num = <32>; 3920 3921 out-ports { 3922 port { 3923 turing0_tpdm0_out: endpoint { 3924 remote-endpoint = <&turing0_tpda_in0>; 3925 }; 3926 }; 3927 }; 3928 }; 3929 3930 tpda@4b86000 { 3931 compatible = "qcom,coresight-tpda", "arm,primecell"; 3932 reg = <0x0 0x04b86000 0x0 0x1000>; 3933 3934 clocks = <&aoss_qmp>; 3935 clock-names = "apb_pclk"; 3936 3937 in-ports { 3938 port { 3939 turing0_tpda_in0: endpoint { 3940 remote-endpoint = <&turing0_tpdm0_out>; 3941 }; 3942 }; 3943 }; 3944 3945 out-ports { 3946 port { 3947 turing0_tpda_out: endpoint { 3948 remote-endpoint = <&turing0_funnel_in0>; 3949 }; 3950 }; 3951 }; 3952 }; 3953 3954 funnel@4b87000 { 3955 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3956 reg = <0x0 0x04b87000 0x0 0x1000>; 3957 3958 clocks = <&aoss_qmp>; 3959 clock-names = "apb_pclk"; 3960 3961 in-ports { 3962 port { 3963 turing0_funnel_in0: endpoint { 3964 remote-endpoint = <&turing0_tpda_out>; 3965 }; 3966 }; 3967 }; 3968 3969 out-ports { 3970 port { 3971 turing0_funnel_out: endpoint { 3972 remote-endpoint = <&gdsp_funnel_in4>; 3973 }; 3974 }; 3975 }; 3976 }; 3977 3978 cti@4b8b000 { 3979 compatible = "arm,coresight-cti", "arm,primecell"; 3980 reg = <0x0 0x04b8b000 0x0 0x1000>; 3981 3982 clocks = <&aoss_qmp>; 3983 clock-names = "apb_pclk"; 3984 }; 3985 3986 tpdm@4c40000 { 3987 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3988 reg = <0x0 0x04c40000 0x0 0x1000>; 3989 3990 clocks = <&aoss_qmp>; 3991 clock-names = "apb_pclk"; 3992 3993 qcom,dsb-element-bits = <32>; 3994 qcom,dsb-msrs-num = <32>; 3995 3996 out-ports { 3997 port { 3998 gdsp_tpdm0_out: endpoint { 3999 remote-endpoint = <&gdsp_tpda_in8>; 4000 }; 4001 }; 4002 }; 4003 }; 4004 4005 tpda@4c44000 { 4006 compatible = "qcom,coresight-tpda", "arm,primecell"; 4007 reg = <0x0 0x04c44000 0x0 0x1000>; 4008 4009 clocks = <&aoss_qmp>; 4010 clock-names = "apb_pclk"; 4011 4012 in-ports { 4013 #address-cells = <1>; 4014 #size-cells = <0>; 4015 4016 port@5 { 4017 reg = <5>; 4018 4019 gdsp_tpda_in5: endpoint { 4020 remote-endpoint = <&turing2_funnel_out0>; 4021 }; 4022 }; 4023 4024 port@8 { 4025 reg = <8>; 4026 4027 gdsp_tpda_in8: endpoint { 4028 remote-endpoint = <&gdsp_tpdm0_out>; 4029 }; 4030 }; 4031 }; 4032 4033 out-ports { 4034 port { 4035 gdsp_tpda_out: endpoint { 4036 remote-endpoint = <&gdsp_funnel_in0>; 4037 }; 4038 }; 4039 }; 4040 }; 4041 4042 funnel@4c45000 { 4043 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4044 reg = <0x0 0x04c45000 0x0 0x1000>; 4045 4046 clocks = <&aoss_qmp>; 4047 clock-names = "apb_pclk"; 4048 4049 in-ports { 4050 #address-cells = <1>; 4051 #size-cells = <0>; 4052 4053 port@0 { 4054 reg = <0>; 4055 4056 gdsp_funnel_in0: endpoint { 4057 remote-endpoint = <&gdsp_tpda_out>; 4058 }; 4059 }; 4060 4061 port@4 { 4062 reg = <4>; 4063 4064 gdsp_funnel_in4: endpoint { 4065 remote-endpoint = <&turing0_funnel_out>; 4066 }; 4067 }; 4068 }; 4069 4070 out-ports { 4071 port { 4072 gdsp_funnel_out: endpoint { 4073 remote-endpoint = <&dlst_ch_funnel_in6>; 4074 }; 4075 }; 4076 }; 4077 }; 4078 4079 tpdm@4c50000 { 4080 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4081 reg = <0x0 0x04c50000 0x0 0x1000>; 4082 4083 clocks = <&aoss_qmp>; 4084 clock-names = "apb_pclk"; 4085 4086 qcom,dsb-element-bits = <32>; 4087 qcom,dsb-msrs-num = <32>; 4088 4089 out-ports { 4090 port { 4091 dlst_tpdm0_out: endpoint { 4092 remote-endpoint = <&dlst_tpda_in8>; 4093 }; 4094 }; 4095 }; 4096 }; 4097 4098 tpda@4c54000 { 4099 compatible = "qcom,coresight-tpda", "arm,primecell"; 4100 reg = <0x0 0x04c54000 0x0 0x1000>; 4101 4102 clocks = <&aoss_qmp>; 4103 clock-names = "apb_pclk"; 4104 4105 in-ports { 4106 #address-cells = <1>; 4107 #size-cells = <0>; 4108 4109 port@8 { 4110 reg = <8>; 4111 4112 dlst_tpda_in8: endpoint { 4113 remote-endpoint = <&dlst_tpdm0_out>; 4114 }; 4115 }; 4116 }; 4117 4118 out-ports { 4119 port { 4120 dlst_tpda_out: endpoint { 4121 remote-endpoint = <&dlst_funnel_in0>; 4122 }; 4123 }; 4124 }; 4125 }; 4126 4127 funnel@4c55000 { 4128 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4129 reg = <0x0 0x04c55000 0x0 0x1000>; 4130 4131 clocks = <&aoss_qmp>; 4132 clock-names = "apb_pclk"; 4133 4134 in-ports { 4135 port { 4136 dlst_funnel_in0: endpoint { 4137 remote-endpoint = <&dlst_tpda_out>; 4138 }; 4139 }; 4140 }; 4141 4142 out-ports { 4143 port { 4144 dlst_funnel_out: endpoint { 4145 remote-endpoint = <&dlst_ch_funnel_in4>; 4146 }; 4147 }; 4148 }; 4149 }; 4150 4151 tpdm@4e00000 { 4152 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4153 reg = <0x0 0x04e00000 0x0 0x1000>; 4154 4155 clocks = <&aoss_qmp>; 4156 clock-names = "apb_pclk"; 4157 4158 qcom,dsb-element-bits = <32>; 4159 qcom,dsb-msrs-num = <32>; 4160 qcom,cmb-element-bits = <32>; 4161 qcom,cmb-msrs-num = <32>; 4162 4163 out-ports { 4164 port { 4165 ddr_tpdm3_out: endpoint { 4166 remote-endpoint = <&ddr_tpda_in4>; 4167 }; 4168 }; 4169 }; 4170 }; 4171 4172 tpda@4e03000 { 4173 compatible = "qcom,coresight-tpda", "arm,primecell"; 4174 reg = <0x0 0x04e03000 0x0 0x1000>; 4175 4176 clocks = <&aoss_qmp>; 4177 clock-names = "apb_pclk"; 4178 4179 in-ports { 4180 #address-cells = <1>; 4181 #size-cells = <0>; 4182 4183 port@0 { 4184 reg = <0>; 4185 4186 ddr_tpda_in0: endpoint { 4187 remote-endpoint = <&ddr_funnel0_out0>; 4188 }; 4189 }; 4190 4191 port@1 { 4192 reg = <1>; 4193 4194 ddr_tpda_in1: endpoint { 4195 remote-endpoint = <&ddr_funnel1_out0>; 4196 }; 4197 }; 4198 4199 port@4 { 4200 reg = <4>; 4201 4202 ddr_tpda_in4: endpoint { 4203 remote-endpoint = <&ddr_tpdm3_out>; 4204 }; 4205 }; 4206 }; 4207 4208 out-ports { 4209 port { 4210 ddr_tpda_out: endpoint { 4211 remote-endpoint = <&ddr_funnel5_in0>; 4212 }; 4213 }; 4214 }; 4215 }; 4216 4217 funnel@4e04000 { 4218 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4219 reg = <0x0 0x04e04000 0x0 0x1000>; 4220 4221 clocks = <&aoss_qmp>; 4222 clock-names = "apb_pclk"; 4223 4224 in-ports { 4225 port { 4226 ddr_funnel5_in0: endpoint { 4227 remote-endpoint = <&ddr_tpda_out>; 4228 }; 4229 }; 4230 }; 4231 4232 out-ports { 4233 port { 4234 ddr_funnel5_out: endpoint { 4235 remote-endpoint = <&dlct0_funnel_in4>; 4236 }; 4237 }; 4238 }; 4239 }; 4240 4241 tpdm@4e10000 { 4242 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4243 reg = <0x0 0x04e10000 0x0 0x1000>; 4244 4245 clocks = <&aoss_qmp>; 4246 clock-names = "apb_pclk"; 4247 4248 qcom,dsb-element-bits = <32>; 4249 qcom,dsb-msrs-num = <32>; 4250 4251 out-ports { 4252 port { 4253 ddr_tpdm0_out: endpoint { 4254 remote-endpoint = <&ddr_funnel0_in0>; 4255 }; 4256 }; 4257 }; 4258 }; 4259 4260 funnel@4e12000 { 4261 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4262 reg = <0x0 0x04e12000 0x0 0x1000>; 4263 4264 clocks = <&aoss_qmp>; 4265 clock-names = "apb_pclk"; 4266 4267 in-ports { 4268 port { 4269 ddr_funnel0_in0: endpoint { 4270 remote-endpoint = <&ddr_tpdm0_out>; 4271 }; 4272 }; 4273 }; 4274 4275 out-ports { 4276 port { 4277 ddr_funnel0_out0: endpoint { 4278 remote-endpoint = <&ddr_tpda_in0>; 4279 }; 4280 }; 4281 }; 4282 }; 4283 4284 tpdm@4e20000 { 4285 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4286 reg = <0x0 0x04e20000 0x0 0x1000>; 4287 4288 clocks = <&aoss_qmp>; 4289 clock-names = "apb_pclk"; 4290 4291 qcom,dsb-element-bits = <32>; 4292 qcom,dsb-msrs-num = <32>; 4293 4294 out-ports { 4295 port { 4296 ddr_tpdm1_out: endpoint { 4297 remote-endpoint = <&ddr_funnel1_in0>; 4298 }; 4299 }; 4300 }; 4301 }; 4302 4303 funnel@4e22000 { 4304 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4305 reg = <0x0 0x04e22000 0x0 0x1000>; 4306 4307 clocks = <&aoss_qmp>; 4308 clock-names = "apb_pclk"; 4309 4310 in-ports { 4311 port { 4312 ddr_funnel1_in0: endpoint { 4313 remote-endpoint = <&ddr_tpdm1_out>; 4314 }; 4315 }; 4316 }; 4317 4318 out-ports { 4319 port { 4320 ddr_funnel1_out0: endpoint { 4321 remote-endpoint = <&ddr_tpda_in1>; 4322 }; 4323 }; 4324 }; 4325 }; 4326 4327 etm@6040000 { 4328 compatible = "arm,primecell"; 4329 reg = <0x0 0x06040000 0x0 0x1000>; 4330 cpu = <&cpu0>; 4331 4332 clocks = <&aoss_qmp>; 4333 clock-names = "apb_pclk"; 4334 4335 arm,coresight-loses-context-with-cpu; 4336 qcom,skip-power-up; 4337 4338 out-ports { 4339 port { 4340 etm0_out: endpoint { 4341 remote-endpoint = <&apss_funnel0_in0>; 4342 }; 4343 }; 4344 }; 4345 }; 4346 4347 etm@6140000 { 4348 compatible = "arm,primecell"; 4349 reg = <0x0 0x06140000 0x0 0x1000>; 4350 cpu = <&cpu1>; 4351 4352 clocks = <&aoss_qmp>; 4353 clock-names = "apb_pclk"; 4354 4355 arm,coresight-loses-context-with-cpu; 4356 qcom,skip-power-up; 4357 4358 out-ports { 4359 port { 4360 etm1_out: endpoint { 4361 remote-endpoint = <&apss_funnel0_in1>; 4362 }; 4363 }; 4364 }; 4365 }; 4366 4367 etm@6240000 { 4368 compatible = "arm,primecell"; 4369 reg = <0x0 0x06240000 0x0 0x1000>; 4370 cpu = <&cpu2>; 4371 4372 clocks = <&aoss_qmp>; 4373 clock-names = "apb_pclk"; 4374 4375 arm,coresight-loses-context-with-cpu; 4376 qcom,skip-power-up; 4377 4378 out-ports { 4379 port { 4380 etm2_out: endpoint { 4381 remote-endpoint = <&apss_funnel0_in2>; 4382 }; 4383 }; 4384 }; 4385 }; 4386 4387 etm@6340000 { 4388 compatible = "arm,primecell"; 4389 reg = <0x0 0x06340000 0x0 0x1000>; 4390 cpu = <&cpu3>; 4391 4392 clocks = <&aoss_qmp>; 4393 clock-names = "apb_pclk"; 4394 4395 arm,coresight-loses-context-with-cpu; 4396 qcom,skip-power-up; 4397 4398 out-ports { 4399 port { 4400 etm3_out: endpoint { 4401 remote-endpoint = <&apss_funnel0_in3>; 4402 }; 4403 }; 4404 }; 4405 }; 4406 4407 etm@6440000 { 4408 compatible = "arm,primecell"; 4409 reg = <0x0 0x06440000 0x0 0x1000>; 4410 cpu = <&cpu4>; 4411 4412 clocks = <&aoss_qmp>; 4413 clock-names = "apb_pclk"; 4414 4415 arm,coresight-loses-context-with-cpu; 4416 qcom,skip-power-up; 4417 4418 out-ports { 4419 port { 4420 etm4_out: endpoint { 4421 remote-endpoint = <&apss_funnel0_in4>; 4422 }; 4423 }; 4424 }; 4425 }; 4426 4427 etm@6540000 { 4428 compatible = "arm,primecell"; 4429 reg = <0x0 0x06540000 0x0 0x1000>; 4430 cpu = <&cpu5>; 4431 4432 clocks = <&aoss_qmp>; 4433 clock-names = "apb_pclk"; 4434 4435 arm,coresight-loses-context-with-cpu; 4436 qcom,skip-power-up; 4437 4438 out-ports { 4439 port { 4440 etm5_out: endpoint { 4441 remote-endpoint = <&apss_funnel0_in5>; 4442 }; 4443 }; 4444 }; 4445 }; 4446 4447 etm@6640000 { 4448 compatible = "arm,primecell"; 4449 reg = <0x0 0x06640000 0x0 0x1000>; 4450 cpu = <&cpu6>; 4451 4452 clocks = <&aoss_qmp>; 4453 clock-names = "apb_pclk"; 4454 4455 arm,coresight-loses-context-with-cpu; 4456 qcom,skip-power-up; 4457 4458 out-ports { 4459 port { 4460 etm6_out: endpoint { 4461 remote-endpoint = <&apss_funnel0_in6>; 4462 }; 4463 }; 4464 }; 4465 }; 4466 4467 etm@6740000 { 4468 compatible = "arm,primecell"; 4469 reg = <0x0 0x06740000 0x0 0x1000>; 4470 cpu = <&cpu7>; 4471 4472 clocks = <&aoss_qmp>; 4473 clock-names = "apb_pclk"; 4474 4475 arm,coresight-loses-context-with-cpu; 4476 qcom,skip-power-up; 4477 4478 out-ports { 4479 port { 4480 etm7_out: endpoint { 4481 remote-endpoint = <&apss_funnel0_in7>; 4482 }; 4483 }; 4484 }; 4485 }; 4486 4487 funnel@6800000 { 4488 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4489 reg = <0x0 0x06800000 0x0 0x1000>; 4490 4491 clocks = <&aoss_qmp>; 4492 clock-names = "apb_pclk"; 4493 4494 in-ports { 4495 #address-cells = <1>; 4496 #size-cells = <0>; 4497 4498 port@0 { 4499 reg = <0>; 4500 4501 apss_funnel0_in0: endpoint { 4502 remote-endpoint = <&etm0_out>; 4503 }; 4504 }; 4505 4506 port@1 { 4507 reg = <1>; 4508 4509 apss_funnel0_in1: endpoint { 4510 remote-endpoint = <&etm1_out>; 4511 }; 4512 }; 4513 4514 port@2 { 4515 reg = <2>; 4516 4517 apss_funnel0_in2: endpoint { 4518 remote-endpoint = <&etm2_out>; 4519 }; 4520 }; 4521 4522 port@3 { 4523 reg = <3>; 4524 4525 apss_funnel0_in3: endpoint { 4526 remote-endpoint = <&etm3_out>; 4527 }; 4528 }; 4529 4530 port@4 { 4531 reg = <4>; 4532 4533 apss_funnel0_in4: endpoint { 4534 remote-endpoint = <&etm4_out>; 4535 }; 4536 }; 4537 4538 port@5 { 4539 reg = <5>; 4540 4541 apss_funnel0_in5: endpoint { 4542 remote-endpoint = <&etm5_out>; 4543 }; 4544 }; 4545 4546 port@6 { 4547 reg = <6>; 4548 4549 apss_funnel0_in6: endpoint { 4550 remote-endpoint = <&etm6_out>; 4551 }; 4552 }; 4553 4554 port@7 { 4555 reg = <7>; 4556 4557 apss_funnel0_in7: endpoint { 4558 remote-endpoint = <&etm7_out>; 4559 }; 4560 }; 4561 }; 4562 4563 out-ports { 4564 port { 4565 apss_funnel0_out: endpoint { 4566 remote-endpoint = <&apss_funnel1_in0>; 4567 }; 4568 }; 4569 }; 4570 }; 4571 4572 funnel@6810000 { 4573 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4574 reg = <0x0 0x06810000 0x0 0x1000>; 4575 4576 clocks = <&aoss_qmp>; 4577 clock-names = "apb_pclk"; 4578 4579 in-ports { 4580 #address-cells = <1>; 4581 #size-cells = <0>; 4582 4583 port@0 { 4584 reg = <0>; 4585 4586 apss_funnel1_in0: endpoint { 4587 remote-endpoint = <&apss_funnel0_out>; 4588 }; 4589 }; 4590 4591 port@3 { 4592 reg = <3>; 4593 4594 apss_funnel1_in3: endpoint { 4595 remote-endpoint = <&apss_tpda_out>; 4596 }; 4597 }; 4598 }; 4599 4600 out-ports { 4601 port { 4602 apss_funnel1_out: endpoint { 4603 remote-endpoint = <&funnel1_in4>; 4604 }; 4605 }; 4606 }; 4607 }; 4608 4609 cti@682b000 { 4610 compatible = "arm,coresight-cti", "arm,primecell"; 4611 reg = <0x0 0x0682b000 0x0 0x1000>; 4612 4613 clocks = <&aoss_qmp>; 4614 clock-names = "apb_pclk"; 4615 }; 4616 4617 tpdm@6860000 { 4618 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4619 reg = <0x0 0x06860000 0x0 0x1000>; 4620 4621 clocks = <&aoss_qmp>; 4622 clock-names = "apb_pclk"; 4623 4624 qcom,cmb-element-bits = <64>; 4625 qcom,cmb-msrs-num = <32>; 4626 4627 out-ports { 4628 port { 4629 apss_tpdm3_out: endpoint { 4630 remote-endpoint = <&apss_tpda_in3>; 4631 }; 4632 }; 4633 }; 4634 }; 4635 4636 tpdm@6861000 { 4637 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4638 reg = <0x0 0x06861000 0x0 0x1000>; 4639 4640 clocks = <&aoss_qmp>; 4641 clock-names = "apb_pclk"; 4642 4643 qcom,dsb-element-bits = <32>; 4644 qcom,dsb-msrs-num = <32>; 4645 4646 out-ports { 4647 port { 4648 apss_tpdm4_out: endpoint { 4649 remote-endpoint = <&apss_tpda_in4>; 4650 }; 4651 }; 4652 }; 4653 }; 4654 4655 tpda@6863000 { 4656 compatible = "qcom,coresight-tpda", "arm,primecell"; 4657 reg = <0x0 0x06863000 0x0 0x1000>; 4658 4659 clocks = <&aoss_qmp>; 4660 clock-names = "apb_pclk"; 4661 4662 in-ports { 4663 #address-cells = <1>; 4664 #size-cells = <0>; 4665 4666 port@0 { 4667 reg = <0>; 4668 4669 apss_tpda_in0: endpoint { 4670 remote-endpoint = <&apss_tpdm0_out>; 4671 }; 4672 }; 4673 4674 port@1 { 4675 reg = <1>; 4676 4677 apss_tpda_in1: endpoint { 4678 remote-endpoint = <&apss_tpdm1_out>; 4679 }; 4680 }; 4681 4682 port@2 { 4683 reg = <2>; 4684 4685 apss_tpda_in2: endpoint { 4686 remote-endpoint = <&apss_tpdm2_out>; 4687 }; 4688 }; 4689 4690 port@3 { 4691 reg = <3>; 4692 4693 apss_tpda_in3: endpoint { 4694 remote-endpoint = <&apss_tpdm3_out>; 4695 }; 4696 }; 4697 4698 port@4 { 4699 reg = <4>; 4700 4701 apss_tpda_in4: endpoint { 4702 remote-endpoint = <&apss_tpdm4_out>; 4703 }; 4704 }; 4705 }; 4706 4707 out-ports { 4708 port { 4709 apss_tpda_out: endpoint { 4710 remote-endpoint = <&apss_funnel1_in3>; 4711 }; 4712 }; 4713 }; 4714 }; 4715 4716 tpdm@68a0000 { 4717 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4718 reg = <0x0 0x068a0000 0x0 0x1000>; 4719 4720 clocks = <&aoss_qmp>; 4721 clock-names = "apb_pclk"; 4722 4723 qcom,cmb-element-bits = <32>; 4724 qcom,cmb-msrs-num = <32>; 4725 4726 out-ports { 4727 port { 4728 apss_tpdm1_out: endpoint { 4729 remote-endpoint = <&apss_tpda_in1>; 4730 }; 4731 }; 4732 }; 4733 }; 4734 4735 tpdm@68b0000 { 4736 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4737 reg = <0x0 0x068b0000 0x0 0x1000>; 4738 4739 clocks = <&aoss_qmp>; 4740 clock-names = "apb_pclk"; 4741 4742 qcom,cmb-element-bits = <32>; 4743 qcom,cmb-msrs-num = <32>; 4744 4745 out-ports { 4746 port { 4747 apss_tpdm0_out: endpoint { 4748 remote-endpoint = <&apss_tpda_in0>; 4749 }; 4750 }; 4751 }; 4752 }; 4753 4754 tpdm@68c0000 { 4755 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4756 reg = <0x0 0x068c0000 0x0 0x1000>; 4757 4758 clocks = <&aoss_qmp>; 4759 clock-names = "apb_pclk"; 4760 4761 qcom,dsb-element-bits = <32>; 4762 qcom,dsb-msrs-num = <32>; 4763 4764 out-ports { 4765 port { 4766 apss_tpdm2_out: endpoint { 4767 remote-endpoint = <&apss_tpda_in2>; 4768 }; 4769 }; 4770 }; 4771 }; 4772 4773 cti@68e0000 { 4774 compatible = "arm,coresight-cti", "arm,primecell"; 4775 reg = <0x0 0x068e0000 0x0 0x1000>; 4776 4777 clocks = <&aoss_qmp>; 4778 clock-names = "apb_pclk"; 4779 }; 4780 4781 cti@68f0000 { 4782 compatible = "arm,coresight-cti", "arm,primecell"; 4783 reg = <0x0 0x068f0000 0x0 0x1000>; 4784 4785 clocks = <&aoss_qmp>; 4786 clock-names = "apb_pclk"; 4787 }; 4788 4789 cti@6900000 { 4790 compatible = "arm,coresight-cti", "arm,primecell"; 4791 reg = <0x0 0x06900000 0x0 0x1000>; 4792 4793 clocks = <&aoss_qmp>; 4794 clock-names = "apb_pclk"; 4795 }; 4796 4797 sdhc_1: mmc@87c4000 { 4798 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4799 reg = <0x0 0x087c4000 0x0 0x1000>, 4800 <0x0 0x087c5000 0x0 0x1000>; 4801 reg-names = "hc", 4802 "cqhci"; 4803 4804 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4805 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4806 interrupt-names = "hc_irq", 4807 "pwr_irq"; 4808 4809 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4810 <&gcc GCC_SDCC1_APPS_CLK>, 4811 <&rpmhcc RPMH_CXO_CLK>; 4812 clock-names = "iface", 4813 "core", 4814 "xo"; 4815 4816 resets = <&gcc GCC_SDCC1_BCR>; 4817 4818 power-domains = <&rpmhpd RPMHPD_CX>; 4819 operating-points-v2 = <&sdhc1_opp_table>; 4820 iommus = <&apps_smmu 0x0 0x0>; 4821 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4823 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4824 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4825 interconnect-names = "sdhc-ddr", 4826 "cpu-sdhc"; 4827 4828 pinctrl-names = "default", "sleep"; 4829 pinctrl-0 = <&sdc1_state_on>; 4830 pinctrl-1 = <&sdc1_state_off>; 4831 4832 qcom,dll-config = <0x000f64ee>; 4833 qcom,ddr-config = <0x80040868>; 4834 bus-width = <8>; 4835 supports-cqe; 4836 dma-coherent; 4837 4838 mmc-ddr-1_8v; 4839 mmc-hs200-1_8v; 4840 mmc-hs400-1_8v; 4841 mmc-hs400-enhanced-strobe; 4842 4843 status = "disabled"; 4844 4845 sdhc1_opp_table: opp-table { 4846 compatible = "operating-points-v2"; 4847 4848 opp-50000000 { 4849 opp-hz = /bits/ 64 <50000000>; 4850 required-opps = <&rpmhpd_opp_low_svs>; 4851 }; 4852 4853 opp-100000000 { 4854 opp-hz = /bits/ 64 <100000000>; 4855 required-opps = <&rpmhpd_opp_svs>; 4856 }; 4857 4858 opp-200000000 { 4859 opp-hz = /bits/ 64 <200000000>; 4860 required-opps = <&rpmhpd_opp_svs_l1>; 4861 }; 4862 4863 opp-384000000 { 4864 opp-hz = /bits/ 64 <384000000>; 4865 required-opps = <&rpmhpd_opp_nom>; 4866 }; 4867 }; 4868 }; 4869 4870 usb_1_hsphy: phy@8904000 { 4871 compatible = "qcom,qcs8300-usb-hs-phy", 4872 "qcom,usb-snps-hs-7nm-phy"; 4873 reg = <0x0 0x08904000 0x0 0x400>; 4874 4875 clocks = <&rpmhcc RPMH_CXO_CLK>; 4876 clock-names = "ref"; 4877 4878 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4879 4880 #phy-cells = <0>; 4881 4882 status = "disabled"; 4883 }; 4884 4885 usb_2_hsphy: phy@8906000 { 4886 compatible = "qcom,qcs8300-usb-hs-phy", 4887 "qcom,usb-snps-hs-7nm-phy"; 4888 reg = <0x0 0x08906000 0x0 0x400>; 4889 4890 clocks = <&rpmhcc RPMH_CXO_CLK>; 4891 clock-names = "ref"; 4892 4893 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4894 4895 #phy-cells = <0>; 4896 4897 status = "disabled"; 4898 }; 4899 4900 usb_qmpphy: phy@8907000 { 4901 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4902 reg = <0x0 0x08907000 0x0 0x2000>; 4903 4904 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4905 <&gcc GCC_USB_CLKREF_EN>, 4906 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4907 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4908 clock-names = "aux", 4909 "ref", 4910 "com_aux", 4911 "pipe"; 4912 4913 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4914 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4915 reset-names = "phy", "phy_phy"; 4916 4917 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4918 4919 #clock-cells = <0>; 4920 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4921 4922 #phy-cells = <0>; 4923 4924 status = "disabled"; 4925 }; 4926 4927 serdes0: phy@8909000 { 4928 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4929 reg = <0x0 0x08909000 0x0 0x00000e10>; 4930 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4931 clock-names = "sgmi_ref"; 4932 #phy-cells = <0>; 4933 status = "disabled"; 4934 }; 4935 4936 refgen: regulator@891c000 { 4937 compatible = "qcom,qcs8300-refgen-regulator", 4938 "qcom,sm8250-refgen-regulator"; 4939 reg = <0x0 0x0891c000 0x0 0x84>; 4940 }; 4941 4942 gpu: gpu@3d00000 { 4943 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4944 reg = <0x0 0x03d00000 0x0 0x40000>, 4945 <0x0 0x03d9e000 0x0 0x1000>, 4946 <0x0 0x03d61000 0x0 0x800>; 4947 reg-names = "kgsl_3d0_reg_memory", 4948 "cx_mem", 4949 "cx_dbgc"; 4950 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4951 iommus = <&adreno_smmu 0 0xc00>, 4952 <&adreno_smmu 1 0xc00>; 4953 operating-points-v2 = <&gpu_opp_table>; 4954 qcom,gmu = <&gmu>; 4955 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4956 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4957 interconnect-names = "gfx-mem"; 4958 #cooling-cells = <2>; 4959 4960 nvmem-cells = <&gpu_speed_bin>; 4961 nvmem-cell-names = "speed_bin"; 4962 4963 status = "disabled"; 4964 4965 gpu_zap_shader: zap-shader { 4966 memory-region = <&gpu_microcode_mem>; 4967 }; 4968 4969 gpu_opp_table: opp-table { 4970 compatible = "operating-points-v2"; 4971 4972 opp-877000000 { 4973 opp-hz = /bits/ 64 <877000000>; 4974 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4975 opp-peak-kBps = <12484375>; 4976 opp-supported-hw = <0x1>; 4977 }; 4978 4979 opp-780000000 { 4980 opp-hz = /bits/ 64 <780000000>; 4981 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4982 opp-peak-kBps = <10687500>; 4983 opp-supported-hw = <0x1>; 4984 }; 4985 4986 opp-599000000 { 4987 opp-hz = /bits/ 64 <599000000>; 4988 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4989 opp-peak-kBps = <8171875>; 4990 opp-supported-hw = <0x3>; 4991 }; 4992 4993 opp-479000000 { 4994 opp-hz = /bits/ 64 <479000000>; 4995 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4996 opp-peak-kBps = <5285156>; 4997 opp-supported-hw = <0x3>; 4998 }; 4999 }; 5000 }; 5001 5002 gmu: gmu@3d6a000 { 5003 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 5004 reg = <0x0 0x03d6a000 0x0 0x34000>, 5005 <0x0 0x03de0000 0x0 0x10000>, 5006 <0x0 0x0b290000 0x0 0x10000>; 5007 reg-names = "gmu", "rscc", "gmu_pdc"; 5008 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 5010 interrupt-names = "hfi", "gmu"; 5011 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 5012 <&gpucc GPU_CC_CXO_CLK>, 5013 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 5014 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5015 <&gpucc GPU_CC_AHB_CLK>, 5016 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 5017 clock-names = "gmu", 5018 "cxo", 5019 "axi", 5020 "memnoc", 5021 "ahb", 5022 "hub"; 5023 power-domains = <&gpucc GPU_CC_CX_GDSC>, 5024 <&gpucc GPU_CC_GX_GDSC>; 5025 power-domain-names = "cx", 5026 "gx"; 5027 iommus = <&adreno_smmu 5 0xc00>; 5028 operating-points-v2 = <&gmu_opp_table>; 5029 5030 gmu_opp_table: opp-table { 5031 compatible = "operating-points-v2"; 5032 5033 opp-500000000 { 5034 opp-hz = /bits/ 64 <500000000>; 5035 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5036 }; 5037 }; 5038 }; 5039 5040 gpucc: clock-controller@3d90000 { 5041 compatible = "qcom,qcs8300-gpucc"; 5042 reg = <0x0 0x03d90000 0x0 0xa000>; 5043 clocks = <&rpmhcc RPMH_CXO_CLK>, 5044 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 5045 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 5046 clock-names = "bi_tcxo", 5047 "gcc_gpu_gpll0_clk_src", 5048 "gcc_gpu_gpll0_div_clk_src"; 5049 #clock-cells = <1>; 5050 #reset-cells = <1>; 5051 #power-domain-cells = <1>; 5052 }; 5053 5054 adreno_smmu: iommu@3da0000 { 5055 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 5056 "qcom,smmu-500", "arm,mmu-500"; 5057 reg = <0x0 0x3da0000 0x0 0x20000>; 5058 #iommu-cells = <2>; 5059 #global-interrupts = <2>; 5060 5061 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 5069 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 5070 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 5071 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 5072 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 5073 5074 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5075 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 5076 <&gpucc GPU_CC_AHB_CLK>, 5077 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 5078 <&gpucc GPU_CC_CX_GMU_CLK>, 5079 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 5080 <&gpucc GPU_CC_HUB_AON_CLK>; 5081 5082 clock-names = "gcc_gpu_memnoc_gfx_clk", 5083 "gcc_gpu_snoc_dvm_gfx_clk", 5084 "gpu_cc_ahb_clk", 5085 "gpu_cc_hlos1_vote_gpu_smmu_clk", 5086 "gpu_cc_cx_gmu_clk", 5087 "gpu_cc_hub_cx_int_clk", 5088 "gpu_cc_hub_aon_clk"; 5089 power-domains = <&gpucc GPU_CC_CX_GDSC>; 5090 dma-coherent; 5091 }; 5092 5093 pmu@9091000 { 5094 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5095 reg = <0x0 0x9091000 0x0 0x1000>; 5096 5097 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 5098 5099 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5100 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5101 5102 operating-points-v2 = <&llcc_bwmon_opp_table>; 5103 5104 llcc_bwmon_opp_table: opp-table { 5105 compatible = "operating-points-v2"; 5106 5107 opp-0 { 5108 opp-peak-kBps = <762000>; 5109 }; 5110 5111 opp-1 { 5112 opp-peak-kBps = <1720000>; 5113 }; 5114 5115 opp-2 { 5116 opp-peak-kBps = <2086000>; 5117 }; 5118 5119 opp-3 { 5120 opp-peak-kBps = <2601000>; 5121 }; 5122 5123 opp-4 { 5124 opp-peak-kBps = <2929000>; 5125 }; 5126 5127 opp-5 { 5128 opp-peak-kBps = <5931000>; 5129 }; 5130 5131 opp-6 { 5132 opp-peak-kBps = <6515000>; 5133 }; 5134 5135 opp-7 { 5136 opp-peak-kBps = <7984000>; 5137 }; 5138 5139 opp-8 { 5140 opp-peak-kBps = <10437000>; 5141 }; 5142 5143 opp-9 { 5144 opp-peak-kBps = <12195000>; 5145 }; 5146 }; 5147 }; 5148 5149 pmu@90b5400 { 5150 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5151 reg = <0x0 0x90b5400 0x0 0x600>; 5152 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5153 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5154 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5155 5156 operating-points-v2 = <&cpu_bwmon_opp_table>; 5157 5158 cpu_bwmon_opp_table: opp-table { 5159 compatible = "operating-points-v2"; 5160 5161 opp-0 { 5162 opp-peak-kBps = <9155000>; 5163 }; 5164 5165 opp-1 { 5166 opp-peak-kBps = <12298000>; 5167 }; 5168 5169 opp-2 { 5170 opp-peak-kBps = <14236000>; 5171 }; 5172 5173 opp-3 { 5174 opp-peak-kBps = <16265000>; 5175 }; 5176 }; 5177 }; 5178 5179 pmu@90b6400 { 5180 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5181 reg = <0x0 0x90b6400 0x0 0x600>; 5182 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5183 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5184 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5185 5186 operating-points-v2 = <&cpu_bwmon_opp_table>; 5187 }; 5188 5189 dc_noc: interconnect@90e0000 { 5190 compatible = "qcom,qcs8300-dc-noc"; 5191 reg = <0x0 0x090e0000 0x0 0x5080>; 5192 #interconnect-cells = <2>; 5193 qcom,bcm-voters = <&apps_bcm_voter>; 5194 }; 5195 5196 gem_noc: interconnect@9100000 { 5197 compatible = "qcom,qcs8300-gem-noc"; 5198 reg = <0x0 0x9100000 0x0 0xf7080>; 5199 #interconnect-cells = <2>; 5200 qcom,bcm-voters = <&apps_bcm_voter>; 5201 clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; 5202 }; 5203 5204 llcc: system-cache-controller@9200000 { 5205 compatible = "qcom,qcs8300-llcc"; 5206 reg = <0x0 0x09200000 0x0 0x80000>, 5207 <0x0 0x09300000 0x0 0x80000>, 5208 <0x0 0x09400000 0x0 0x80000>, 5209 <0x0 0x09500000 0x0 0x80000>, 5210 <0x0 0x09a00000 0x0 0x80000>; 5211 reg-names = "llcc0_base", 5212 "llcc1_base", 5213 "llcc2_base", 5214 "llcc3_base", 5215 "llcc_broadcast_base"; 5216 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 5217 }; 5218 5219 usb_1: usb@a600000 { 5220 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5221 reg = <0x0 0x0a600000 0x0 0xfc100>; 5222 5223 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5224 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5225 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5226 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5227 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 5228 clock-names = "cfg_noc", 5229 "core", 5230 "iface", 5231 "sleep", 5232 "mock_utmi"; 5233 5234 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5235 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5236 assigned-clock-rates = <19200000>, <200000000>; 5237 5238 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 5239 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 5240 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 5241 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5242 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5243 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 5244 interrupt-names = "dwc_usb3", 5245 "pwr_event", 5246 "hs_phy_irq", 5247 "dp_hs_phy_irq", 5248 "dm_hs_phy_irq", 5249 "ss_phy_irq"; 5250 5251 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5252 required-opps = <&rpmhpd_opp_nom>; 5253 5254 resets = <&gcc GCC_USB30_PRIM_BCR>; 5255 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5256 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5257 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5258 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 5259 interconnect-names = "usb-ddr", "apps-usb"; 5260 5261 iommus = <&apps_smmu 0x80 0x0>; 5262 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5263 phy-names = "usb2-phy", "usb3-phy"; 5264 snps,dis_enblslpm_quirk; 5265 snps,dis-u1-entry-quirk; 5266 snps,dis-u2-entry-quirk; 5267 snps,dis_u2_susphy_quirk; 5268 snps,dis_u3_susphy_quirk; 5269 5270 usb-role-switch; 5271 wakeup-source; 5272 5273 status = "disabled"; 5274 5275 ports { 5276 #address-cells = <1>; 5277 #size-cells = <0>; 5278 5279 port@0 { 5280 reg = <0>; 5281 5282 usb_1_dwc3_hs: endpoint { 5283 }; 5284 }; 5285 5286 port@1 { 5287 reg = <1>; 5288 5289 usb_1_dwc3_ss: endpoint { 5290 }; 5291 }; 5292 }; 5293 }; 5294 5295 usb_2: usb@a400000 { 5296 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5297 reg = <0x0 0x0a400000 0x0 0xfc100>; 5298 5299 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5300 <&gcc GCC_USB20_MASTER_CLK>, 5301 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5302 <&gcc GCC_USB20_SLEEP_CLK>, 5303 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5304 clock-names = "cfg_noc", 5305 "core", 5306 "iface", 5307 "sleep", 5308 "mock_utmi"; 5309 5310 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5311 <&gcc GCC_USB20_MASTER_CLK>; 5312 assigned-clock-rates = <19200000>, <120000000>; 5313 5314 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 5315 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 5316 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 5317 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 5318 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 5319 interrupt-names = "dwc_usb3", 5320 "pwr_event", 5321 "hs_phy_irq", 5322 "dp_hs_phy_irq", 5323 "dm_hs_phy_irq"; 5324 5325 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5326 required-opps = <&rpmhpd_opp_nom>; 5327 5328 resets = <&gcc GCC_USB20_PRIM_BCR>; 5329 5330 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5331 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5332 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5333 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 5334 interconnect-names = "usb-ddr", "apps-usb"; 5335 5336 iommus = <&apps_smmu 0x20 0x0>; 5337 5338 phys = <&usb_2_hsphy>; 5339 phy-names = "usb2-phy"; 5340 maximum-speed = "high-speed"; 5341 5342 snps,dis-u1-entry-quirk; 5343 snps,dis-u2-entry-quirk; 5344 snps,dis_u2_susphy_quirk; 5345 snps,dis_u3_susphy_quirk; 5346 snps,dis_enblslpm_quirk; 5347 5348 qcom,select-utmi-as-pipe-clk; 5349 wakeup-source; 5350 5351 usb-role-switch; 5352 5353 status = "disabled"; 5354 5355 port { 5356 usb_2_dwc3_hs: endpoint { 5357 }; 5358 }; 5359 }; 5360 5361 iris: video-codec@aa00000 { 5362 compatible = "qcom,qcs8300-iris"; 5363 5364 reg = <0x0 0x0aa00000 0x0 0xf0000>; 5365 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5366 5367 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5368 <&videocc VIDEO_CC_MVS0_GDSC>, 5369 <&rpmhpd RPMHPD_MX>, 5370 <&rpmhpd RPMHPD_MMCX>; 5371 power-domain-names = "venus", 5372 "vcodec0", 5373 "mxc", 5374 "mmcx"; 5375 5376 operating-points-v2 = <&iris_opp_table>; 5377 5378 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5379 <&videocc VIDEO_CC_MVS0C_CLK>, 5380 <&videocc VIDEO_CC_MVS0_CLK>; 5381 clock-names = "iface", 5382 "core", 5383 "vcodec0_core"; 5384 5385 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5386 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5387 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 5388 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5389 interconnect-names = "cpu-cfg", 5390 "video-mem"; 5391 5392 memory-region = <&video_mem>; 5393 5394 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5395 reset-names = "bus"; 5396 5397 iommus = <&apps_smmu 0x0880 0x0400>, 5398 <&apps_smmu 0x0887 0x0400>; 5399 dma-coherent; 5400 5401 status = "disabled"; 5402 5403 iris_opp_table: opp-table { 5404 compatible = "operating-points-v2"; 5405 5406 opp-366000000 { 5407 opp-hz = /bits/ 64 <366000000>; 5408 required-opps = <&rpmhpd_opp_svs_l1>, 5409 <&rpmhpd_opp_svs_l1>; 5410 }; 5411 5412 opp-444000000 { 5413 opp-hz = /bits/ 64 <444000000>; 5414 required-opps = <&rpmhpd_opp_svs_l1>, 5415 <&rpmhpd_opp_nom>; 5416 }; 5417 5418 opp-533000000 { 5419 opp-hz = /bits/ 64 <533000000>; 5420 required-opps = <&rpmhpd_opp_nom>, 5421 <&rpmhpd_opp_turbo>; 5422 }; 5423 5424 opp-560000000 { 5425 opp-hz = /bits/ 64 <560000000>; 5426 required-opps = <&rpmhpd_opp_nom>, 5427 <&rpmhpd_opp_turbo_l1>; 5428 }; 5429 }; 5430 }; 5431 5432 videocc: clock-controller@abf0000 { 5433 compatible = "qcom,qcs8300-videocc"; 5434 reg = <0x0 0x0abf0000 0x0 0x10000>; 5435 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5436 <&rpmhcc RPMH_CXO_CLK>, 5437 <&rpmhcc RPMH_CXO_CLK_A>, 5438 <&sleep_clk>; 5439 power-domains = <&rpmhpd RPMHPD_MMCX>; 5440 #clock-cells = <1>; 5441 #reset-cells = <1>; 5442 #power-domain-cells = <1>; 5443 }; 5444 5445 cci0: cci@ac13000 { 5446 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5447 reg = <0x0 0x0ac13000 0x0 0x1000>; 5448 5449 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5450 5451 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5452 <&camcc CAM_CC_CCI_0_CLK>; 5453 clock-names = "ahb", 5454 "cci"; 5455 5456 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5457 5458 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5459 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5460 pinctrl-names = "default", "sleep"; 5461 5462 #address-cells = <1>; 5463 #size-cells = <0>; 5464 5465 status = "disabled"; 5466 5467 cci0_i2c0: i2c-bus@0 { 5468 reg = <0>; 5469 clock-frequency = <1000000>; 5470 #address-cells = <1>; 5471 #size-cells = <0>; 5472 }; 5473 5474 cci0_i2c1: i2c-bus@1 { 5475 reg = <1>; 5476 clock-frequency = <1000000>; 5477 #address-cells = <1>; 5478 #size-cells = <0>; 5479 }; 5480 }; 5481 5482 cci1: cci@ac14000 { 5483 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5484 reg = <0x0 0x0ac14000 0x0 0x1000>; 5485 5486 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5487 5488 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5489 <&camcc CAM_CC_CCI_1_CLK>; 5490 clock-names = "ahb", 5491 "cci"; 5492 5493 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5494 5495 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5496 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5497 pinctrl-names = "default", "sleep"; 5498 5499 #address-cells = <1>; 5500 #size-cells = <0>; 5501 5502 status = "disabled"; 5503 5504 cci1_i2c0: i2c-bus@0 { 5505 reg = <0>; 5506 clock-frequency = <1000000>; 5507 #address-cells = <1>; 5508 #size-cells = <0>; 5509 }; 5510 5511 cci1_i2c1: i2c-bus@1 { 5512 reg = <1>; 5513 clock-frequency = <1000000>; 5514 #address-cells = <1>; 5515 #size-cells = <0>; 5516 }; 5517 }; 5518 5519 cci2: cci@ac15000 { 5520 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5521 reg = <0x0 0x0ac15000 0x0 0x1000>; 5522 5523 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 5524 5525 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5526 <&camcc CAM_CC_CCI_2_CLK>; 5527 clock-names = "ahb", 5528 "cci"; 5529 5530 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5531 5532 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5533 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5534 pinctrl-names = "default", "sleep"; 5535 5536 #address-cells = <1>; 5537 #size-cells = <0>; 5538 5539 status = "disabled"; 5540 5541 cci2_i2c0: i2c-bus@0 { 5542 reg = <0>; 5543 clock-frequency = <1000000>; 5544 #address-cells = <1>; 5545 #size-cells = <0>; 5546 }; 5547 5548 cci2_i2c1: i2c-bus@1 { 5549 reg = <1>; 5550 clock-frequency = <1000000>; 5551 #address-cells = <1>; 5552 #size-cells = <0>; 5553 }; 5554 }; 5555 5556 camss: isp@ac78000 { 5557 compatible = "qcom,qcs8300-camss"; 5558 5559 reg = <0x0 0xac78000 0x0 0x1000>, 5560 <0x0 0xac7a000 0x0 0xf00>, 5561 <0x0 0xac7c000 0x0 0xf00>, 5562 <0x0 0xac84000 0x0 0xf00>, 5563 <0x0 0xac88000 0x0 0xf00>, 5564 <0x0 0xac8c000 0x0 0xf00>, 5565 <0x0 0xac90000 0x0 0xf00>, 5566 <0x0 0xac94000 0x0 0xf00>, 5567 <0x0 0xac9c000 0x0 0x2000>, 5568 <0x0 0xac9e000 0x0 0x2000>, 5569 <0x0 0xaca0000 0x0 0x2000>, 5570 <0x0 0xacac000 0x0 0x400>, 5571 <0x0 0xacad000 0x0 0x400>, 5572 <0x0 0xacae000 0x0 0x400>, 5573 <0x0 0xac4d000 0x0 0xf000>, 5574 <0x0 0xac60000 0x0 0xf000>, 5575 <0x0 0xac85000 0x0 0xd00>, 5576 <0x0 0xac89000 0x0 0xd00>, 5577 <0x0 0xac8d000 0x0 0xd00>, 5578 <0x0 0xac91000 0x0 0xd00>, 5579 <0x0 0xac95000 0x0 0xd00>; 5580 reg-names = "csid_wrapper", 5581 "csid0", 5582 "csid1", 5583 "csid_lite0", 5584 "csid_lite1", 5585 "csid_lite2", 5586 "csid_lite3", 5587 "csid_lite4", 5588 "csiphy0", 5589 "csiphy1", 5590 "csiphy2", 5591 "tpg0", 5592 "tpg1", 5593 "tpg2", 5594 "vfe0", 5595 "vfe1", 5596 "vfe_lite0", 5597 "vfe_lite1", 5598 "vfe_lite2", 5599 "vfe_lite3", 5600 "vfe_lite4"; 5601 5602 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5603 <&camcc CAM_CC_CORE_AHB_CLK>, 5604 <&camcc CAM_CC_CPAS_AHB_CLK>, 5605 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5606 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5607 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5608 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5609 <&camcc CAM_CC_CSID_CLK>, 5610 <&camcc CAM_CC_CSIPHY0_CLK>, 5611 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5612 <&camcc CAM_CC_CSIPHY1_CLK>, 5613 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5614 <&camcc CAM_CC_CSIPHY2_CLK>, 5615 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5616 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5617 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5618 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5619 <&camcc CAM_CC_ICP_AHB_CLK>, 5620 <&camcc CAM_CC_IFE_0_CLK>, 5621 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5622 <&camcc CAM_CC_IFE_1_CLK>, 5623 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5624 <&camcc CAM_CC_IFE_LITE_CLK>, 5625 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5626 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5627 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5628 clock-names = "camnoc_axi", 5629 "core_ahb", 5630 "cpas_ahb", 5631 "cpas_fast_ahb_clk", 5632 "cpas_vfe_lite", 5633 "cpas_vfe0", 5634 "cpas_vfe1", 5635 "csid", 5636 "csiphy0", 5637 "csiphy0_timer", 5638 "csiphy1", 5639 "csiphy1_timer", 5640 "csiphy2", 5641 "csiphy2_timer", 5642 "csiphy_rx", 5643 "gcc_axi_hf", 5644 "gcc_axi_sf", 5645 "icp_ahb", 5646 "vfe0", 5647 "vfe0_fast_ahb", 5648 "vfe1", 5649 "vfe1_fast_ahb", 5650 "vfe_lite", 5651 "vfe_lite_ahb", 5652 "vfe_lite_cphy_rx", 5653 "vfe_lite_csid"; 5654 5655 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5656 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5657 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5658 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5659 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5660 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5661 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5662 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5663 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5664 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5665 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5666 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5667 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5668 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5669 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5670 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5671 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5672 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5673 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5674 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5675 interrupt-names = "csid0", 5676 "csid1", 5677 "csid_lite0", 5678 "csid_lite1", 5679 "csid_lite2", 5680 "csid_lite3", 5681 "csid_lite4", 5682 "csiphy0", 5683 "csiphy1", 5684 "csiphy2", 5685 "tpg0", 5686 "tpg1", 5687 "tpg2", 5688 "vfe0", 5689 "vfe1", 5690 "vfe_lite0", 5691 "vfe_lite1", 5692 "vfe_lite2", 5693 "vfe_lite3", 5694 "vfe_lite4"; 5695 5696 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5697 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5698 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5699 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5700 interconnect-names = "ahb", 5701 "hf_0"; 5702 5703 iommus = <&apps_smmu 0x2400 0x20>; 5704 5705 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5706 power-domain-names = "top"; 5707 5708 status = "disabled"; 5709 5710 ports { 5711 #address-cells = <1>; 5712 #size-cells = <0>; 5713 5714 port@0 { 5715 reg = <0>; 5716 }; 5717 5718 port@1 { 5719 reg = <1>; 5720 }; 5721 5722 port@2 { 5723 reg = <2>; 5724 }; 5725 }; 5726 }; 5727 5728 camcc: clock-controller@ade0000 { 5729 compatible = "qcom,qcs8300-camcc"; 5730 reg = <0x0 0x0ade0000 0x0 0x20000>; 5731 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5732 <&rpmhcc RPMH_CXO_CLK>, 5733 <&rpmhcc RPMH_CXO_CLK_A>, 5734 <&sleep_clk>; 5735 power-domains = <&rpmhpd RPMHPD_MMCX>; 5736 #clock-cells = <1>; 5737 #reset-cells = <1>; 5738 #power-domain-cells = <1>; 5739 }; 5740 5741 mdss: display-subsystem@ae00000 { 5742 compatible = "qcom,qcs8300-mdss"; 5743 reg = <0x0 0x0ae00000 0x0 0x1000>; 5744 reg-names = "mdss"; 5745 5746 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5747 5748 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5749 <&gcc GCC_DISP_HF_AXI_CLK>, 5750 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; 5751 5752 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; 5753 5754 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5755 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5756 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5758 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5759 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5760 interconnect-names = "mdp0-mem", 5761 "mdp1-mem", 5762 "cpu-cfg"; 5763 5764 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; 5765 5766 iommus = <&apps_smmu 0x1000 0x402>; 5767 5768 interrupt-controller; 5769 #interrupt-cells = <1>; 5770 5771 #address-cells = <2>; 5772 #size-cells = <2>; 5773 ranges; 5774 5775 status = "disabled"; 5776 5777 mdss_mdp: display-controller@ae01000 { 5778 compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; 5779 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5780 <0x0 0x0aeb0000 0x0 0x2008>; 5781 reg-names = "mdp", "vbif"; 5782 5783 interrupts-extended = <&mdss 0>; 5784 5785 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5786 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5787 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5788 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, 5789 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5790 clock-names = "nrt_bus", 5791 "iface", 5792 "lut", 5793 "core", 5794 "vsync"; 5795 5796 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5797 assigned-clock-rates = <19200000>; 5798 5799 operating-points-v2 = <&mdp_opp_table>; 5800 power-domains = <&rpmhpd RPMHPD_MMCX>; 5801 5802 ports { 5803 #address-cells = <1>; 5804 #size-cells = <0>; 5805 5806 port@0 { 5807 reg = <0>; 5808 5809 dpu_intf0_out: endpoint { 5810 5811 remote-endpoint = <&mdss_dp0_in>; 5812 }; 5813 }; 5814 5815 port@1 { 5816 reg = <1>; 5817 5818 dpu_intf1_out: endpoint { 5819 5820 remote-endpoint = <&mdss_dsi0_in>; 5821 }; 5822 }; 5823 }; 5824 5825 mdp_opp_table: opp-table { 5826 compatible = "operating-points-v2"; 5827 5828 opp-375000000 { 5829 opp-hz = /bits/ 64 <375000000>; 5830 required-opps = <&rpmhpd_opp_svs_l1>; 5831 }; 5832 5833 opp-500000000 { 5834 opp-hz = /bits/ 64 <500000000>; 5835 required-opps = <&rpmhpd_opp_nom>; 5836 }; 5837 5838 opp-575000000 { 5839 opp-hz = /bits/ 64 <575000000>; 5840 required-opps = <&rpmhpd_opp_turbo>; 5841 }; 5842 5843 opp-650000000 { 5844 opp-hz = /bits/ 64 <650000000>; 5845 required-opps = <&rpmhpd_opp_turbo_l1>; 5846 }; 5847 }; 5848 }; 5849 5850 mdss_dsi0: dsi@ae94000 { 5851 compatible = "qcom,qcs8300-dsi-ctrl", 5852 "qcom,sa8775p-dsi-ctrl", 5853 "qcom,mdss-dsi-ctrl"; 5854 reg = <0x0 0x0ae94000 0x0 0x400>; 5855 reg-names = "dsi_ctrl"; 5856 5857 interrupt-parent = <&mdss>; 5858 interrupts = <4>; 5859 5860 clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5861 <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5862 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5863 <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, 5864 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5865 <&gcc GCC_DISP_HF_AXI_CLK>; 5866 clock-names = "byte", 5867 "byte_intf", 5868 "pixel", 5869 "core", 5870 "iface", 5871 "bus"; 5872 5873 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5874 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5875 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5876 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5877 5878 phys = <&mdss_dsi0_phy>; 5879 5880 operating-points-v2 = <&mdss_dsi_opp_table>; 5881 power-domains = <&rpmhpd RPMHPD_MMCX>; 5882 5883 refgen-supply = <&refgen>; 5884 5885 #address-cells = <1>; 5886 #size-cells = <0>; 5887 5888 status = "disabled"; 5889 5890 ports { 5891 #address-cells = <1>; 5892 #size-cells = <0>; 5893 5894 port@0 { 5895 reg = <0>; 5896 5897 mdss_dsi0_in: endpoint { 5898 5899 remote-endpoint = <&dpu_intf1_out>; 5900 }; 5901 }; 5902 5903 port@1 { 5904 reg = <1>; 5905 5906 mdss_dsi0_out: endpoint { 5907 }; 5908 }; 5909 }; 5910 5911 mdss_dsi_opp_table: opp-table { 5912 compatible = "operating-points-v2"; 5913 5914 opp-358000000 { 5915 opp-hz = /bits/ 64 <358000000>; 5916 required-opps = <&rpmhpd_opp_svs_l1>; 5917 }; 5918 }; 5919 }; 5920 5921 mdss_dsi0_phy: phy@ae94400 { 5922 compatible = "qcom,qcs8300-dsi-phy-5nm", 5923 "qcom,sa8775p-dsi-phy-5nm"; 5924 reg = <0x0 0x0ae94400 0x0 0x200>, 5925 <0x0 0x0ae94600 0x0 0x280>, 5926 <0x0 0x0ae94900 0x0 0x280>; 5927 reg-names = "dsi_phy", 5928 "dsi_phy_lane", 5929 "dsi_pll"; 5930 5931 #clock-cells = <1>; 5932 #phy-cells = <0>; 5933 5934 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5935 <&rpmhcc RPMH_CXO_CLK>; 5936 clock-names = "iface", 5937 "ref"; 5938 5939 status = "disabled"; 5940 }; 5941 5942 mdss_dp0_phy: phy@aec2a00 { 5943 compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; 5944 5945 reg = <0x0 0x0aec2a00 0x0 0x19c>, 5946 <0x0 0x0aec2200 0x0 0xec>, 5947 <0x0 0x0aec2600 0x0 0xec>, 5948 <0x0 0x0aec2000 0x0 0x1c8>; 5949 5950 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5951 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; 5952 clock-names = "aux", 5953 "cfg_ahb"; 5954 5955 power-domains = <&rpmhpd RPMHPD_MX>; 5956 5957 #clock-cells = <1>; 5958 #phy-cells = <0>; 5959 5960 status = "disabled"; 5961 }; 5962 5963 mdss_dp0: displayport-controller@af54000 { 5964 compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; 5965 5966 reg = <0x0 0x0af54000 0x0 0x200>, 5967 <0x0 0x0af54200 0x0 0x200>, 5968 <0x0 0x0af55000 0x0 0xc00>, 5969 <0x0 0x0af56000 0x0 0x09c>, 5970 <0x0 0x0af57000 0x0 0x09c>, 5971 <0x0 0x0af58000 0x0 0x09c>, 5972 <0x0 0x0af59000 0x0 0x09c>, 5973 <0x0 0x0af5a000 0x0 0x23c>, 5974 <0x0 0x0af5b000 0x0 0x23c>; 5975 5976 interrupts-extended = <&mdss 12>; 5977 5978 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5979 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5980 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5981 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5982 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5983 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5984 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5985 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5986 clock-names = "core_iface", 5987 "core_aux", 5988 "ctrl_link", 5989 "ctrl_link_iface", 5990 "stream_pixel", 5991 "stream_1_pixel", 5992 "stream_2_pixel", 5993 "stream_3_pixel"; 5994 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5995 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5996 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5997 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5998 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5999 assigned-clock-parents = <&mdss_dp0_phy 0>, 6000 <&mdss_dp0_phy 1>, 6001 <&mdss_dp0_phy 1>, 6002 <&mdss_dp0_phy 1>, 6003 <&mdss_dp0_phy 1>; 6004 phys = <&mdss_dp0_phy>; 6005 phy-names = "dp"; 6006 6007 operating-points-v2 = <&dp_opp_table>; 6008 power-domains = <&rpmhpd RPMHPD_MMCX>; 6009 6010 #sound-dai-cells = <0>; 6011 6012 status = "disabled"; 6013 6014 ports { 6015 #address-cells = <1>; 6016 #size-cells = <0>; 6017 6018 port@0 { 6019 reg = <0>; 6020 6021 mdss_dp0_in: endpoint { 6022 remote-endpoint = <&dpu_intf0_out>; 6023 }; 6024 }; 6025 6026 port@1 { 6027 reg = <1>; 6028 6029 mdss_dp0_out: endpoint { }; 6030 }; 6031 }; 6032 6033 dp_opp_table: opp-table { 6034 compatible = "operating-points-v2"; 6035 6036 opp-162000000 { 6037 opp-hz = /bits/ 64 <162000000>; 6038 required-opps = <&rpmhpd_opp_low_svs>; 6039 }; 6040 6041 opp-270000000 { 6042 opp-hz = /bits/ 64 <270000000>; 6043 required-opps = <&rpmhpd_opp_svs>; 6044 }; 6045 6046 opp-540000000 { 6047 opp-hz = /bits/ 64 <540000000>; 6048 required-opps = <&rpmhpd_opp_svs_l1>; 6049 }; 6050 6051 opp-810000000 { 6052 opp-hz = /bits/ 64 <810000000>; 6053 required-opps = <&rpmhpd_opp_nom>; 6054 }; 6055 }; 6056 }; 6057 }; 6058 6059 dispcc: clock-controller@af00000 { 6060 compatible = "qcom,sa8775p-dispcc0"; 6061 reg = <0x0 0x0af00000 0x0 0x20000>; 6062 clocks = <&gcc GCC_DISP_AHB_CLK>, 6063 <&rpmhcc RPMH_CXO_CLK>, 6064 <&rpmhcc RPMH_CXO_CLK_A>, 6065 <&sleep_clk>, 6066 <&mdss_dp0_phy 0>, 6067 <&mdss_dp0_phy 1>, 6068 <0>, <0>, 6069 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 6070 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 6071 <0>, <0>; 6072 power-domains = <&rpmhpd RPMHPD_MMCX>; 6073 #clock-cells = <1>; 6074 #reset-cells = <1>; 6075 #power-domain-cells = <1>; 6076 }; 6077 6078 pdc: interrupt-controller@b220000 { 6079 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 6080 reg = <0x0 0xb220000 0x0 0x30000>, 6081 <0x0 0x17c000f0 0x0 0x64>; 6082 interrupt-parent = <&intc>; 6083 #interrupt-cells = <2>; 6084 interrupt-controller; 6085 qcom,pdc-ranges = <0 480 40>, 6086 <40 140 14>, 6087 <54 263 1>, 6088 <55 306 4>, 6089 <59 312 3>, 6090 <62 374 2>, 6091 <64 434 2>, 6092 <66 438 2>, 6093 <70 520 1>, 6094 <73 523 1>, 6095 <118 568 6>, 6096 <124 609 3>, 6097 <159 638 1>, 6098 <160 720 3>, 6099 <169 728 30>, 6100 <199 416 2>, 6101 <201 449 1>, 6102 <202 89 1>, 6103 <203 451 1>, 6104 <204 462 1>, 6105 <205 264 1>, 6106 <206 579 1>, 6107 <207 653 1>, 6108 <208 656 1>, 6109 <209 659 1>, 6110 <210 122 1>, 6111 <211 699 1>, 6112 <212 705 1>, 6113 <213 450 1>, 6114 <214 643 2>, 6115 <216 646 5>, 6116 <221 390 5>, 6117 <226 700 2>, 6118 <228 440 1>, 6119 <229 663 1>, 6120 <230 524 2>, 6121 <232 612 3>, 6122 <235 723 5>; 6123 }; 6124 6125 tsens2: thermal-sensor@c251000 { 6126 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6127 reg = <0x0 0x0c251000 0x0 0x1000>, 6128 <0x0 0x0c224000 0x0 0x1000>; 6129 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 6130 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 6131 interrupt-names = "uplow", "critical"; 6132 #qcom,sensors = <10>; 6133 #thermal-sensor-cells = <1>; 6134 }; 6135 6136 tsens3: thermal-sensor@c252000 { 6137 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6138 reg = <0x0 0x0c252000 0x0 0x1000>, 6139 <0x0 0x0c225000 0x0 0x1000>; 6140 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 6141 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 6142 interrupt-names = "uplow", "critical"; 6143 #qcom,sensors = <10>; 6144 #thermal-sensor-cells = <1>; 6145 }; 6146 6147 tsens0: thermal-sensor@c263000 { 6148 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6149 reg = <0x0 0x0c263000 0x0 0x1000>, 6150 <0x0 0x0c222000 0x0 0x1000>; 6151 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 6152 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 6153 interrupt-names = "uplow", "critical"; 6154 #qcom,sensors = <10>; 6155 #thermal-sensor-cells = <1>; 6156 }; 6157 6158 tsens1: thermal-sensor@c265000 { 6159 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6160 reg = <0x0 0x0c265000 0x0 0x1000>, 6161 <0x0 0x0c223000 0x0 0x1000>; 6162 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 6163 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 6164 interrupt-names = "uplow", "critical"; 6165 #qcom,sensors = <10>; 6166 #thermal-sensor-cells = <1>; 6167 }; 6168 6169 aoss_qmp: power-management@c300000 { 6170 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 6171 reg = <0x0 0x0c300000 0x0 0x400>; 6172 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 6173 IPCC_MPROC_SIGNAL_GLINK_QMP 6174 IRQ_TYPE_EDGE_RISING>; 6175 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6176 #clock-cells = <0>; 6177 }; 6178 6179 sram@c3f0000 { 6180 compatible = "qcom,rpmh-stats"; 6181 reg = <0x0 0x0c3f0000 0x0 0x400>; 6182 }; 6183 6184 spmi_bus: spmi@c440000 { 6185 compatible = "qcom,spmi-pmic-arb"; 6186 reg = <0x0 0x0c440000 0x0 0x1100>, 6187 <0x0 0x0c600000 0x0 0x2000000>, 6188 <0x0 0x0e600000 0x0 0x100000>, 6189 <0x0 0x0e700000 0x0 0xa0000>, 6190 <0x0 0x0c40a000 0x0 0x26000>; 6191 reg-names = "core", 6192 "chnls", 6193 "obsrvr", 6194 "intr", 6195 "cnfg"; 6196 qcom,channel = <0>; 6197 qcom,ee = <0>; 6198 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6199 interrupt-names = "periph_irq"; 6200 interrupt-controller; 6201 #interrupt-cells = <4>; 6202 #address-cells = <2>; 6203 #size-cells = <0>; 6204 }; 6205 6206 tlmm: pinctrl@f100000 { 6207 compatible = "qcom,qcs8300-tlmm"; 6208 reg = <0x0 0x0f100000 0x0 0x300000>; 6209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6210 gpio-controller; 6211 #gpio-cells = <2>; 6212 gpio-ranges = <&tlmm 0 0 134>; 6213 interrupt-controller; 6214 #interrupt-cells = <2>; 6215 wakeup-parent = <&pdc>; 6216 6217 cam0_default: cam0-default-state { 6218 pins = "gpio67"; 6219 function = "cam_mclk"; 6220 drive-strength = <2>; 6221 bias-disable; 6222 }; 6223 6224 cam1_default: cam1-default-state { 6225 pins = "gpio68"; 6226 function = "cam_mclk"; 6227 drive-strength = <2>; 6228 bias-disable; 6229 }; 6230 6231 cam2_default: cam2-default-state { 6232 pins = "gpio69"; 6233 function = "cam_mclk"; 6234 drive-strength = <2>; 6235 bias-disable; 6236 }; 6237 6238 cci0_0_default: cci0-0-default-state { 6239 sda-pins { 6240 pins = "gpio57"; 6241 function = "cci_i2c_sda"; 6242 drive-strength = <2>; 6243 bias-pull-up = <2200>; 6244 }; 6245 6246 scl-pins { 6247 pins = "gpio58"; 6248 function = "cci_i2c_scl"; 6249 drive-strength = <2>; 6250 bias-pull-up = <2200>; 6251 }; 6252 }; 6253 6254 cci0_0_sleep: cci0-0-sleep-state { 6255 sda-pins { 6256 pins = "gpio57"; 6257 function = "cci_i2c_sda"; 6258 drive-strength = <2>; 6259 bias-pull-down; 6260 }; 6261 6262 scl-pins { 6263 pins = "gpio58"; 6264 function = "cci_i2c_scl"; 6265 drive-strength = <2>; 6266 bias-pull-down; 6267 }; 6268 }; 6269 6270 cci0_1_default: cci0-1-default-state { 6271 sda-pins { 6272 pins = "gpio29"; 6273 function = "cci_i2c_sda"; 6274 drive-strength = <2>; 6275 bias-pull-up = <2200>; 6276 }; 6277 6278 scl-pins { 6279 pins = "gpio30"; 6280 function = "cci_i2c_scl"; 6281 drive-strength = <2>; 6282 bias-pull-up = <2200>; 6283 }; 6284 }; 6285 6286 cci0_1_sleep: cci0-1-sleep-state { 6287 sda-pins { 6288 pins = "gpio29"; 6289 function = "cci_i2c_sda"; 6290 drive-strength = <2>; 6291 bias-pull-down; 6292 }; 6293 6294 scl-pins { 6295 pins = "gpio30"; 6296 function = "cci_i2c_scl"; 6297 drive-strength = <2>; 6298 bias-pull-down; 6299 }; 6300 }; 6301 6302 cci1_0_default: cci1-0-default-state { 6303 sda-pins { 6304 pins = "gpio59"; 6305 function = "cci_i2c_sda"; 6306 drive-strength = <2>; 6307 bias-pull-up = <2200>; 6308 }; 6309 6310 scl-pins { 6311 pins = "gpio60"; 6312 function = "cci_i2c_scl"; 6313 drive-strength = <2>; 6314 bias-pull-up = <2200>; 6315 }; 6316 }; 6317 6318 cci1_0_sleep: cci1-0-sleep-state { 6319 sda-pins { 6320 pins = "gpio59"; 6321 function = "cci_i2c_sda"; 6322 drive-strength = <2>; 6323 bias-pull-down; 6324 }; 6325 6326 scl-pins { 6327 pins = "gpio60"; 6328 function = "cci_i2c_scl"; 6329 drive-strength = <2>; 6330 bias-pull-down; 6331 }; 6332 }; 6333 6334 cci1_1_default: cci1-1-default-state { 6335 sda-pins { 6336 pins = "gpio31"; 6337 function = "cci_i2c_sda"; 6338 drive-strength = <2>; 6339 bias-pull-up = <2200>; 6340 }; 6341 6342 scl-pins { 6343 pins = "gpio32"; 6344 function = "cci_i2c_scl"; 6345 drive-strength = <2>; 6346 bias-pull-up = <2200>; 6347 }; 6348 }; 6349 6350 cci1_1_sleep: cci1-1-sleep-state { 6351 sda-pins { 6352 pins = "gpio31"; 6353 function = "cci_i2c_sda"; 6354 drive-strength = <2>; 6355 bias-pull-down; 6356 }; 6357 6358 scl-pins { 6359 pins = "gpio32"; 6360 function = "cci_i2c_scl"; 6361 drive-strength = <2>; 6362 bias-pull-down; 6363 }; 6364 }; 6365 6366 cci2_0_default: cci2-0-default-state { 6367 sda-pins { 6368 pins = "gpio61"; 6369 function = "cci_i2c_sda"; 6370 drive-strength = <2>; 6371 bias-pull-up = <2200>; 6372 }; 6373 6374 scl-pins { 6375 pins = "gpio62"; 6376 function = "cci_i2c_scl"; 6377 drive-strength = <2>; 6378 bias-pull-up = <2200>; 6379 }; 6380 }; 6381 6382 cci2_0_sleep: cci2-0-sleep-state { 6383 sda-pins { 6384 pins = "gpio61"; 6385 function = "cci_i2c_sda"; 6386 drive-strength = <2>; 6387 bias-pull-down; 6388 }; 6389 6390 scl-pins { 6391 pins = "gpio62"; 6392 function = "cci_i2c_scl"; 6393 drive-strength = <2>; 6394 bias-pull-down; 6395 }; 6396 }; 6397 6398 cci2_1_default: cci2-1-default-state { 6399 sda-pins { 6400 pins = "gpio54"; 6401 function = "cci_i2c_sda"; 6402 drive-strength = <2>; 6403 bias-pull-up = <2200>; 6404 }; 6405 6406 scl-pins { 6407 pins = "gpio55"; 6408 function = "cci_i2c_scl"; 6409 drive-strength = <2>; 6410 bias-pull-up = <2200>; 6411 }; 6412 }; 6413 6414 cci2_1_sleep: cci2-1-sleep-state { 6415 sda-pins { 6416 pins = "gpio54"; 6417 function = "cci_i2c_sda"; 6418 drive-strength = <2>; 6419 bias-pull-down; 6420 }; 6421 6422 scl-pins { 6423 pins = "gpio55"; 6424 function = "cci_i2c_scl"; 6425 drive-strength = <2>; 6426 bias-pull-down; 6427 }; 6428 }; 6429 6430 dp_hot_plug_det: dp-hot-plug-det-state { 6431 pins = "gpio94"; 6432 function = "edp0_hot"; 6433 bias-disable; 6434 }; 6435 6436 hs0_mi2s_active: hs0-mi2s-active-state { 6437 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 6438 function = "hs0_mi2s"; 6439 drive-strength = <8>; 6440 bias-disable; 6441 }; 6442 6443 mi2s1_active: mi2s1-active-state { 6444 data0-pins { 6445 pins = "gpio100"; 6446 function = "mi2s1_data0"; 6447 drive-strength = <8>; 6448 bias-disable; 6449 }; 6450 6451 data1-pins { 6452 pins = "gpio101"; 6453 function = "mi2s1_data1"; 6454 drive-strength = <8>; 6455 bias-disable; 6456 }; 6457 6458 sclk-pins { 6459 pins = "gpio98"; 6460 function = "mi2s1_sck"; 6461 drive-strength = <8>; 6462 bias-disable; 6463 }; 6464 6465 ws-pins { 6466 pins = "gpio99"; 6467 function = "mi2s1_ws"; 6468 drive-strength = <8>; 6469 bias-disable; 6470 }; 6471 }; 6472 6473 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6474 pins = "gpio17", "gpio18"; 6475 function = "qup0_se0"; 6476 }; 6477 6478 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6479 pins = "gpio19", "gpio20"; 6480 function = "qup0_se1"; 6481 }; 6482 6483 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6484 pins = "gpio33", "gpio34"; 6485 function = "qup0_se2"; 6486 }; 6487 6488 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6489 pins = "gpio25", "gpio26"; 6490 function = "qup0_se3"; 6491 }; 6492 6493 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6494 pins = "gpio29", "gpio30"; 6495 function = "qup0_se4"; 6496 }; 6497 6498 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6499 pins = "gpio21", "gpio22"; 6500 function = "qup0_se5"; 6501 }; 6502 6503 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6504 pins = "gpio80", "gpio81"; 6505 function = "qup0_se6"; 6506 }; 6507 6508 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6509 pins = "gpio37", "gpio38"; 6510 function = "qup1_se0"; 6511 }; 6512 6513 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6514 pins = "gpio39", "gpio40"; 6515 function = "qup1_se1"; 6516 }; 6517 6518 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6519 pins = "gpio84", "gpio85"; 6520 function = "qup1_se2"; 6521 }; 6522 6523 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6524 pins = "gpio41", "gpio42"; 6525 function = "qup1_se3"; 6526 }; 6527 6528 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6529 pins = "gpio45", "gpio46"; 6530 function = "qup1_se4"; 6531 }; 6532 6533 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6534 pins = "gpio49", "gpio50"; 6535 function = "qup1_se5"; 6536 }; 6537 6538 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6539 pins = "gpio89", "gpio90"; 6540 function = "qup1_se6"; 6541 }; 6542 6543 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6544 pins = "gpio91", "gpio92"; 6545 function = "qup1_se7"; 6546 }; 6547 6548 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6549 pins = "gpio10", "gpio11"; 6550 function = "qup2_se0"; 6551 }; 6552 6553 qup_spi0_data_clk: qup-spi0-data-clk-state { 6554 pins = "gpio17", "gpio18", "gpio19"; 6555 function = "qup0_se0"; 6556 }; 6557 6558 qup_spi0_cs: qup-spi0-cs-state { 6559 pins = "gpio20"; 6560 function = "qup0_se0"; 6561 }; 6562 6563 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6564 pins = "gpio20"; 6565 function = "gpio"; 6566 }; 6567 6568 qup_spi1_data_clk: qup-spi1-data-clk-state { 6569 pins = "gpio19", "gpio20", "gpio17"; 6570 function = "qup0_se1"; 6571 }; 6572 6573 qup_spi1_cs: qup-spi1-cs-state { 6574 pins = "gpio18"; 6575 function = "qup0_se1"; 6576 }; 6577 6578 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6579 pins = "gpio18"; 6580 function = "gpio"; 6581 }; 6582 6583 qup_spi2_data_clk: qup-spi2-data-clk-state { 6584 pins = "gpio33", "gpio34", "gpio35"; 6585 function = "qup0_se2"; 6586 }; 6587 6588 qup_spi2_cs: qup-spi2-cs-state { 6589 pins = "gpio36"; 6590 function = "qup0_se2"; 6591 }; 6592 6593 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6594 pins = "gpio36"; 6595 function = "gpio"; 6596 }; 6597 6598 qup_spi3_data_clk: qup-spi3-data-clk-state { 6599 pins = "gpio25", "gpio26", "gpio27"; 6600 function = "qup0_se3"; 6601 }; 6602 6603 qup_spi3_cs: qup-spi3-cs-state { 6604 pins = "gpio28"; 6605 function = "qup0_se3"; 6606 }; 6607 6608 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6609 pins = "gpio28"; 6610 function = "gpio"; 6611 }; 6612 6613 qup_spi4_data_clk: qup-spi4-data-clk-state { 6614 pins = "gpio29", "gpio30", "gpio31"; 6615 function = "qup0_se4"; 6616 }; 6617 6618 qup_spi4_cs: qup-spi4-cs-state { 6619 pins = "gpio32"; 6620 function = "qup0_se4"; 6621 }; 6622 6623 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6624 pins = "gpio32"; 6625 function = "gpio"; 6626 }; 6627 6628 qup_spi5_data_clk: qup-spi5-data-clk-state { 6629 pins = "gpio21", "gpio22", "gpio23"; 6630 function = "qup0_se5"; 6631 }; 6632 6633 qup_spi5_cs: qup-spi5-cs-state { 6634 pins = "gpio24"; 6635 function = "qup0_se5"; 6636 }; 6637 6638 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6639 pins = "gpio24"; 6640 function = "gpio"; 6641 }; 6642 6643 qup_spi6_data_clk: qup-spi6-data-clk-state { 6644 pins = "gpio80", "gpio81", "gpio82"; 6645 function = "qup0_se6"; 6646 }; 6647 6648 qup_spi6_cs: qup-spi6-cs-state { 6649 pins = "gpio83"; 6650 function = "qup0_se6"; 6651 }; 6652 6653 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6654 pins = "gpio83"; 6655 function = "gpio"; 6656 }; 6657 6658 qup_spi8_data_clk: qup-spi8-data-clk-state { 6659 pins = "gpio37", "gpio38", "gpio39"; 6660 function = "qup1_se0"; 6661 }; 6662 6663 qup_spi8_cs: qup-spi8-cs-state { 6664 pins = "gpio40"; 6665 function = "qup1_se0"; 6666 }; 6667 6668 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6669 pins = "gpio40"; 6670 function = "gpio"; 6671 }; 6672 6673 qup_spi9_data_clk: qup-spi9-data-clk-state { 6674 pins = "gpio39", "gpio40", "gpio37"; 6675 function = "qup1_se1"; 6676 }; 6677 6678 qup_spi9_cs: qup-spi9-cs-state { 6679 pins = "gpio38"; 6680 function = "qup1_se1"; 6681 }; 6682 6683 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6684 pins = "gpio38"; 6685 function = "gpio"; 6686 }; 6687 6688 qup_spi10_data_clk: qup-spi10-data-clk-state { 6689 pins = "gpio84", "gpio85", "gpio86"; 6690 function = "qup1_se2"; 6691 }; 6692 6693 qup_spi10_cs: qup-spi10-cs-state { 6694 pins = "gpio87"; 6695 function = "qup1_se2"; 6696 }; 6697 6698 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6699 pins = "gpio87"; 6700 function = "gpio"; 6701 }; 6702 6703 qup_spi12_data_clk: qup-spi12-data-clk-state { 6704 pins = "gpio45", "gpio46", "gpio47"; 6705 function = "qup1_se4"; 6706 }; 6707 6708 qup_spi12_cs: qup-spi12-cs-state { 6709 pins = "gpio48"; 6710 function = "qup1_se4"; 6711 }; 6712 6713 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6714 pins = "gpio48"; 6715 function = "gpio"; 6716 }; 6717 6718 qup_spi13_data_clk: qup-spi13-data-clk-state { 6719 pins = "gpio49", "gpio50", "gpio51"; 6720 function = "qup1_se5"; 6721 }; 6722 6723 qup_spi13_cs: qup-spi13-cs-state { 6724 pins = "gpio52"; 6725 function = "qup1_se5"; 6726 }; 6727 6728 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6729 pins = "gpio52"; 6730 function = "gpio"; 6731 }; 6732 6733 qup_spi14_data_clk: qup-spi14-data-clk-state { 6734 pins = "gpio89", "gpio90", "gpio91"; 6735 function = "qup1_se6"; 6736 }; 6737 6738 qup_spi14_cs: qup-spi14-cs-state { 6739 pins = "gpio92"; 6740 function = "qup1_se6"; 6741 }; 6742 6743 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6744 pins = "gpio92"; 6745 function = "gpio"; 6746 }; 6747 6748 qup_spi15_data_clk: qup-spi15-data-clk-state { 6749 pins = "gpio91", "gpio92", "gpio89"; 6750 function = "qup1_se7"; 6751 }; 6752 6753 qup_spi15_cs: qup-spi15-cs-state { 6754 pins = "gpio90"; 6755 function = "qup1_se7"; 6756 }; 6757 6758 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6759 pins = "gpio90"; 6760 function = "gpio"; 6761 }; 6762 6763 qup_spi16_data_clk: qup-spi16-data-clk-state { 6764 pins = "gpio10", "gpio11", "gpio12"; 6765 function = "qup2_se0"; 6766 }; 6767 6768 qup_spi16_cs: qup-spi16-cs-state { 6769 pins = "gpio13"; 6770 function = "qup2_se0"; 6771 }; 6772 6773 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 6774 pins = "gpio13"; 6775 function = "gpio"; 6776 }; 6777 6778 qup_uart0_cts: qup-uart0-cts-state { 6779 pins = "gpio17"; 6780 function = "qup0_se0"; 6781 }; 6782 6783 qup_uart0_rts: qup-uart0-rts-state { 6784 pins = "gpio18"; 6785 function = "qup0_se0"; 6786 }; 6787 6788 qup_uart0_tx: qup-uart0-tx-state { 6789 pins = "gpio19"; 6790 function = "qup0_se0"; 6791 }; 6792 6793 qup_uart0_rx: qup-uart0-rx-state { 6794 pins = "gpio20"; 6795 function = "qup0_se0"; 6796 }; 6797 6798 qup_uart1_cts: qup-uart1-cts-state { 6799 pins = "gpio19"; 6800 function = "qup0_se1"; 6801 }; 6802 6803 qup_uart1_rts: qup-uart1-rts-state { 6804 pins = "gpio20"; 6805 function = "qup0_se1"; 6806 }; 6807 6808 qup_uart1_tx: qup-uart1-tx-state { 6809 pins = "gpio17"; 6810 function = "qup0_se1"; 6811 }; 6812 6813 qup_uart1_rx: qup-uart1-rx-state { 6814 pins = "gpio18"; 6815 function = "qup0_se1"; 6816 }; 6817 6818 qup_uart2_cts: qup-uart2-cts-state { 6819 pins = "gpio33"; 6820 function = "qup0_se2"; 6821 }; 6822 6823 qup_uart2_rts: qup-uart2-rts-state { 6824 pins = "gpio34"; 6825 function = "qup0_se2"; 6826 }; 6827 6828 qup_uart2_tx: qup-uart2-tx-state { 6829 pins = "gpio35"; 6830 function = "qup0_se2"; 6831 }; 6832 6833 qup_uart2_rx: qup-uart2-rx-state { 6834 pins = "gpio36"; 6835 function = "qup0_se2"; 6836 }; 6837 6838 qup_uart3_cts: qup-uart3-cts-state { 6839 pins = "gpio25"; 6840 function = "qup0_se3"; 6841 }; 6842 6843 qup_uart3_rts: qup-uart3-rts-state { 6844 pins = "gpio26"; 6845 function = "qup0_se3"; 6846 }; 6847 6848 qup_uart3_tx: qup-uart3-tx-state { 6849 pins = "gpio27"; 6850 function = "qup0_se3"; 6851 }; 6852 6853 qup_uart3_rx: qup-uart3-rx-state { 6854 pins = "gpio28"; 6855 function = "qup0_se3"; 6856 }; 6857 6858 qup_uart4_cts: qup-uart4-cts-state { 6859 pins = "gpio29"; 6860 function = "qup0_se4"; 6861 }; 6862 6863 qup_uart4_rts: qup-uart4-rts-state { 6864 pins = "gpio30"; 6865 function = "qup0_se4"; 6866 }; 6867 6868 qup_uart4_tx: qup-uart4-tx-state { 6869 pins = "gpio31"; 6870 function = "qup0_se4"; 6871 }; 6872 6873 qup_uart4_rx: qup-uart4-rx-state { 6874 pins = "gpio32"; 6875 function = "qup0_se4"; 6876 }; 6877 6878 qup_uart5_cts: qup-uart5-cts-state { 6879 pins = "gpio21"; 6880 function = "qup0_se5"; 6881 }; 6882 6883 qup_uart5_rts: qup-uart5-rts-state { 6884 pins = "gpio22"; 6885 function = "qup0_se5"; 6886 }; 6887 6888 qup_uart5_tx: qup-uart5-tx-state { 6889 pins = "gpio23"; 6890 function = "qup0_se5"; 6891 }; 6892 6893 qup_uart5_rx: qup-uart5-rx-state { 6894 pins = "gpio23"; 6895 function = "qup0_se5"; 6896 }; 6897 6898 qup_uart6_cts: qup-uart6-cts-state { 6899 pins = "gpio80"; 6900 function = "qup0_se6"; 6901 }; 6902 6903 qup_uart6_rts: qup-uart6-rts-state { 6904 pins = "gpio81"; 6905 function = "qup0_se6"; 6906 }; 6907 6908 qup_uart6_tx: qup-uart6-tx-state { 6909 pins = "gpio82"; 6910 function = "qup0_se6"; 6911 }; 6912 6913 qup_uart6_rx: qup-uart6-rx-state { 6914 pins = "gpio83"; 6915 function = "qup0_se6"; 6916 }; 6917 6918 qup_uart7_tx: qup-uart7-tx-state { 6919 pins = "gpio43"; 6920 function = "qup0_se7"; 6921 }; 6922 6923 qup_uart7_rx: qup-uart7-rx-state { 6924 pins = "gpio44"; 6925 function = "qup0_se7"; 6926 }; 6927 6928 qup_uart8_cts: qup-uart8-cts-state { 6929 pins = "gpio37"; 6930 function = "qup1_se0"; 6931 }; 6932 6933 qup_uart8_rts: qup-uart8-rts-state { 6934 pins = "gpio38"; 6935 function = "qup1_se0"; 6936 }; 6937 6938 qup_uart8_tx: qup-uart8-tx-state { 6939 pins = "gpio39"; 6940 function = "qup1_se0"; 6941 }; 6942 6943 qup_uart8_rx: qup-uart8-rx-state { 6944 pins = "gpio40"; 6945 function = "qup1_se0"; 6946 }; 6947 6948 qup_uart9_cts: qup-uart9-cts-state { 6949 pins = "gpio39"; 6950 function = "qup1_se1"; 6951 }; 6952 6953 qup_uart9_rts: qup-uart9-rts-state { 6954 pins = "gpio40"; 6955 function = "qup1_se1"; 6956 }; 6957 6958 qup_uart9_tx: qup-uart9-tx-state { 6959 pins = "gpio37"; 6960 function = "qup1_se1"; 6961 }; 6962 6963 qup_uart9_rx: qup-uart9-rx-state { 6964 pins = "gpio38"; 6965 function = "qup1_se1"; 6966 }; 6967 6968 qup_uart10_cts: qup-uart10-cts-state { 6969 pins = "gpio84"; 6970 function = "qup1_se2"; 6971 }; 6972 6973 qup_uart10_rts: qup-uart10-rts-state { 6974 pins = "gpio85"; 6975 function = "qup1_se2"; 6976 }; 6977 6978 qup_uart10_tx: qup-uart10-tx-state { 6979 pins = "gpio86"; 6980 function = "qup1_se2"; 6981 }; 6982 6983 qup_uart10_rx: qup-uart10-rx-state { 6984 pins = "gpio87"; 6985 function = "qup1_se2"; 6986 }; 6987 6988 qup_uart11_tx: qup-uart11-tx-state { 6989 pins = "gpio41"; 6990 function = "qup1_se3"; 6991 }; 6992 6993 qup_uart11_rx: qup-uart11-rx-state { 6994 pins = "gpio42"; 6995 function = "qup1_se3"; 6996 }; 6997 6998 qup_uart12_cts: qup-uart12-cts-state { 6999 pins = "gpio45"; 7000 function = "qup1_se4"; 7001 }; 7002 7003 qup_uart12_rts: qup-uart12-rts-state { 7004 pins = "gpio46"; 7005 function = "qup1_se4"; 7006 }; 7007 7008 qup_uart12_tx: qup-uart12-tx-state { 7009 pins = "gpio47"; 7010 function = "qup1_se4"; 7011 }; 7012 7013 qup_uart12_rx: qup-uart12-rx-state { 7014 pins = "gpio48"; 7015 function = "qup1_se4"; 7016 }; 7017 7018 qup_uart13_cts: qup-uart13-cts-state { 7019 pins = "gpio49"; 7020 function = "qup1_se5"; 7021 }; 7022 7023 qup_uart13_rts: qup-uart13-rts-state { 7024 pins = "gpio50"; 7025 function = "qup1_se5"; 7026 }; 7027 7028 qup_uart13_tx: qup-uart13-tx-state { 7029 pins = "gpio51"; 7030 function = "qup1_se5"; 7031 }; 7032 7033 qup_uart13_rx: qup-uart13-rx-state { 7034 pins = "gpio52"; 7035 function = "qup1_se5"; 7036 }; 7037 7038 qup_uart14_cts: qup-uart14-cts-state { 7039 pins = "gpio89"; 7040 function = "qup1_se6"; 7041 }; 7042 7043 qup_uart14_rts: qup-uart14-rts-state { 7044 pins = "gpio90"; 7045 function = "qup1_se6"; 7046 }; 7047 7048 qup_uart14_tx: qup-uart14-tx-state { 7049 pins = "gpio91"; 7050 function = "qup1_se6"; 7051 }; 7052 7053 qup_uart14_rx: qup-uart14-rx-state { 7054 pins = "gpio92"; 7055 function = "qup1_se6"; 7056 }; 7057 7058 qup_uart15_cts: qup-uart15-cts-state { 7059 pins = "gpio91"; 7060 function = "qup1_se7"; 7061 }; 7062 7063 qup_uart15_rts: qup-uart15-rts-state { 7064 pins = "gpio92"; 7065 function = "qup1_se7"; 7066 }; 7067 7068 qup_uart15_tx: qup-uart15-tx-state { 7069 pins = "gpio89"; 7070 function = "qup1_se7"; 7071 }; 7072 7073 qup_uart15_rx: qup-uart15-rx-state { 7074 pins = "gpio90"; 7075 function = "qup1_se7"; 7076 }; 7077 7078 qup_uart16_cts: qup-uart16-cts-state { 7079 pins = "gpio10"; 7080 function = "qup2_se0"; 7081 }; 7082 7083 qup_uart16_rts: qup-uart16-rts-state { 7084 pins = "gpio11"; 7085 function = "qup2_se0"; 7086 }; 7087 7088 qup_uart16_tx: qup-uart16-tx-state { 7089 pins = "gpio12"; 7090 function = "qup2_se0"; 7091 }; 7092 7093 qup_uart16_rx: qup-uart16-rx-state { 7094 pins = "gpio13"; 7095 function = "qup2_se0"; 7096 }; 7097 7098 sdc1_state_on: sdc1-on-state { 7099 clk-pins { 7100 pins = "sdc1_clk"; 7101 drive-strength = <16>; 7102 bias-disable; 7103 }; 7104 7105 cmd-pins { 7106 pins = "sdc1_cmd"; 7107 drive-strength = <10>; 7108 bias-pull-up; 7109 }; 7110 7111 data-pins { 7112 pins = "sdc1_data"; 7113 drive-strength = <10>; 7114 bias-pull-up; 7115 }; 7116 7117 rclk-pins { 7118 pins = "sdc1_rclk"; 7119 bias-pull-down; 7120 }; 7121 }; 7122 7123 sdc1_state_off: sdc1-off-state { 7124 clk-pins { 7125 pins = "sdc1_clk"; 7126 drive-strength = <2>; 7127 bias-bus-hold; 7128 }; 7129 7130 cmd-pins { 7131 pins = "sdc1_cmd"; 7132 drive-strength = <2>; 7133 bias-bus-hold; 7134 }; 7135 7136 data-pins { 7137 pins = "sdc1_data"; 7138 drive-strength = <2>; 7139 bias-bus-hold; 7140 }; 7141 7142 rclk-pins { 7143 pins = "sdc1_rclk"; 7144 bias-bus-hold; 7145 }; 7146 }; 7147 }; 7148 7149 sram: sram@146d8000 { 7150 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 7151 reg = <0x0 0x146d8000 0x0 0x1000>; 7152 ranges = <0x0 0x0 0x146d8000 0x1000>; 7153 7154 #address-cells = <1>; 7155 #size-cells = <1>; 7156 7157 pil-reloc@94c { 7158 compatible = "qcom,pil-reloc-info"; 7159 reg = <0x94c 0xc8>; 7160 }; 7161 }; 7162 7163 apps_smmu: iommu@15000000 { 7164 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7165 7166 reg = <0x0 0x15000000 0x0 0x100000>; 7167 #iommu-cells = <2>; 7168 #global-interrupts = <2>; 7169 dma-coherent; 7170 7171 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 7172 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 7173 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7174 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7175 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7176 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7177 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7178 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7179 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7180 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7181 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7182 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7183 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7184 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7185 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7186 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7187 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7188 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7189 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7190 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7191 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7192 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7193 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7194 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7195 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7196 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7197 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7198 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7199 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7200 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7201 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7202 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7203 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7204 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7205 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7206 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7207 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7208 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7209 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7210 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7211 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7212 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7213 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7214 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7215 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7216 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7217 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7218 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7219 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7220 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7221 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7222 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7223 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7224 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7225 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7226 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7227 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7228 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7229 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7230 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7231 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7232 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7233 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7234 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7235 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7236 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7237 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7238 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7239 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7240 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7241 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7242 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7243 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7244 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7245 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7246 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7247 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7248 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7249 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7250 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7251 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7252 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7253 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7254 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7255 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7256 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 7257 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7258 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7259 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7260 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 7261 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7262 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7263 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7264 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7265 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7266 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7267 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7268 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 7269 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 7270 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 7271 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 7272 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 7273 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7274 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 7275 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 7276 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 7277 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 7278 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 7279 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 7280 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 7281 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 7282 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 7283 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 7284 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 7285 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 7286 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 7287 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 7288 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 7289 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 7290 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 7291 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 7292 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 7293 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 7294 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 7295 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 7296 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 7297 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 7298 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 7299 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 7300 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 7301 }; 7302 7303 pcie_smmu: iommu@15200000 { 7304 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7305 reg = <0x0 0x15200000 0x0 0x80000>; 7306 #iommu-cells = <2>; 7307 #global-interrupts = <2>; 7308 dma-coherent; 7309 7310 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 7311 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 7312 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 7313 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 7314 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 7315 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 7316 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 7317 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 7318 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 7319 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 7320 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 7321 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 7322 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 7323 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 7324 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 7325 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 7326 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 7327 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 7328 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 7329 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 7330 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 7331 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 7332 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 7333 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 7334 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 7335 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 7336 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 7337 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 7338 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 7339 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 7340 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 7341 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 7342 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 7343 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 7344 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 7345 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 7346 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 7347 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 7348 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 7349 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 7350 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 7351 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 7352 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 7353 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 7354 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 7355 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 7356 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 7357 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 7358 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 7359 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 7360 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 7361 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 7362 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 7363 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 7364 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 7365 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 7366 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 7367 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 7368 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 7369 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 7370 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 7371 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 7372 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 7373 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 7374 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 7375 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 7376 }; 7377 7378 intc: interrupt-controller@17a00000 { 7379 compatible = "arm,gic-v3"; 7380 reg = <0x0 0x17a00000 0x0 0x10000>, 7381 <0x0 0x17a60000 0x0 0x100000>; 7382 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7383 #interrupt-cells = <3>; 7384 interrupt-controller; 7385 #redistributor-regions = <1>; 7386 redistributor-stride = <0x0 0x20000>; 7387 }; 7388 7389 watchdog@17c10000 { 7390 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 7391 reg = <0x0 0x17c10000 0x0 0x1000>; 7392 clocks = <&sleep_clk>; 7393 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7394 }; 7395 7396 timer@17c20000 { 7397 compatible = "arm,armv7-timer-mem"; 7398 reg = <0x0 0x17c20000 0x0 0x1000>; 7399 ranges = <0x0 0x0 0x0 0x20000000>; 7400 #address-cells = <1>; 7401 #size-cells = <1>; 7402 7403 frame@17c21000 { 7404 reg = <0x17c21000 0x1000>, 7405 <0x17c22000 0x1000>; 7406 frame-number = <0>; 7407 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7408 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7409 }; 7410 7411 frame@17c23000 { 7412 reg = <0x17c23000 0x1000>; 7413 frame-number = <1>; 7414 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7415 status = "disabled"; 7416 }; 7417 7418 frame@17c25000 { 7419 reg = <0x17c25000 0x1000>; 7420 frame-number = <2>; 7421 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7422 status = "disabled"; 7423 }; 7424 7425 frame@17c27000 { 7426 reg = <0x17c27000 0x1000>; 7427 frame-number = <3>; 7428 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7429 status = "disabled"; 7430 }; 7431 7432 frame@17c29000 { 7433 reg = <0x17c29000 0x1000>; 7434 frame-number = <4>; 7435 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7436 status = "disabled"; 7437 }; 7438 7439 frame@17c2b000 { 7440 reg = <0x17c2b000 0x1000>; 7441 frame-number = <5>; 7442 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7443 status = "disabled"; 7444 }; 7445 7446 frame@17c2d000 { 7447 reg = <0x17c2d000 0x1000>; 7448 frame-number = <6>; 7449 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7450 status = "disabled"; 7451 }; 7452 }; 7453 7454 apps_rsc: rsc@18200000 { 7455 compatible = "qcom,rpmh-rsc"; 7456 reg = <0x0 0x18200000 0x0 0x10000>, 7457 <0x0 0x18210000 0x0 0x10000>, 7458 <0x0 0x18220000 0x0 0x10000>; 7459 reg-names = "drv-0", 7460 "drv-1", 7461 "drv-2"; 7462 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7463 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7464 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7465 7466 power-domains = <&system_pd>; 7467 label = "apps_rsc"; 7468 7469 qcom,tcs-offset = <0xd00>; 7470 qcom,drv-id = <2>; 7471 qcom,tcs-config = <ACTIVE_TCS 2>, 7472 <SLEEP_TCS 3>, 7473 <WAKE_TCS 3>, 7474 <CONTROL_TCS 0>; 7475 7476 apps_bcm_voter: bcm-voter { 7477 compatible = "qcom,bcm-voter"; 7478 }; 7479 7480 rpmhcc: clock-controller { 7481 compatible = "qcom,sa8775p-rpmh-clk"; 7482 #clock-cells = <1>; 7483 clocks = <&xo_board_clk>; 7484 clock-names = "xo"; 7485 }; 7486 7487 rpmhpd: power-controller { 7488 compatible = "qcom,qcs8300-rpmhpd"; 7489 #power-domain-cells = <1>; 7490 operating-points-v2 = <&rpmhpd_opp_table>; 7491 7492 rpmhpd_opp_table: opp-table { 7493 compatible = "operating-points-v2"; 7494 7495 rpmhpd_opp_ret: opp-0 { 7496 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7497 }; 7498 7499 rpmhpd_opp_min_svs: opp-1 { 7500 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7501 }; 7502 7503 rpmhpd_opp_low_svs: opp-2 { 7504 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7505 }; 7506 7507 rpmhpd_opp_svs: opp-3 { 7508 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7509 }; 7510 7511 rpmhpd_opp_svs_l1: opp-4 { 7512 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7513 }; 7514 7515 rpmhpd_opp_nom: opp-5 { 7516 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7517 }; 7518 7519 rpmhpd_opp_nom_l1: opp-6 { 7520 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7521 }; 7522 7523 rpmhpd_opp_nom_l2: opp-7 { 7524 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7525 }; 7526 7527 rpmhpd_opp_turbo: opp-8 { 7528 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7529 }; 7530 7531 rpmhpd_opp_turbo_l1: opp-9 { 7532 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7533 }; 7534 }; 7535 }; 7536 }; 7537 7538 epss_l3_cl0: interconnect@18590000 { 7539 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7540 "qcom,epss-l3"; 7541 reg = <0x0 0x18590000 0x0 0x1000>; 7542 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7543 clock-names = "xo", "alternate"; 7544 #interconnect-cells = <1>; 7545 }; 7546 7547 cpufreq_hw: cpufreq@18591000 { 7548 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 7549 reg = <0x0 0x18591000 0x0 0x1000>, 7550 <0x0 0x18593000 0x0 0x1000>, 7551 <0x0 0x18594000 0x0 0x1000>; 7552 reg-names = "freq-domain0", 7553 "freq-domain1", 7554 "freq-domain2"; 7555 7556 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7557 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 7558 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 7559 interrupt-names = "dcvsh-irq-0", 7560 "dcvsh-irq-1", 7561 "dcvsh-irq-2"; 7562 7563 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7564 clock-names = "xo", "alternate"; 7565 7566 #freq-domain-cells = <1>; 7567 }; 7568 7569 epss_l3_cl1: interconnect@18592000 { 7570 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7571 "qcom,epss-l3"; 7572 reg = <0x0 0x18592000 0x0 0x1000>; 7573 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7574 clock-names = "xo", "alternate"; 7575 #interconnect-cells = <1>; 7576 }; 7577 7578 remoteproc_gpdsp: remoteproc@20c00000 { 7579 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 7580 reg = <0x0 0x20c00000 0x0 0x10000>; 7581 7582 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7583 <&smp2p_gpdsp_in 0 0>, 7584 <&smp2p_gpdsp_in 1 0>, 7585 <&smp2p_gpdsp_in 2 0>, 7586 <&smp2p_gpdsp_in 3 0>; 7587 interrupt-names = "wdog", 7588 "fatal", 7589 "ready", 7590 "handover", 7591 "stop-ack"; 7592 7593 clocks = <&rpmhcc RPMH_CXO_CLK>; 7594 clock-names = "xo"; 7595 7596 power-domains = <&rpmhpd RPMHPD_CX>, 7597 <&rpmhpd RPMHPD_MXC>; 7598 power-domain-names = "cx", 7599 "mxc"; 7600 7601 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 7602 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 7603 7604 memory-region = <&gpdsp_mem>; 7605 7606 qcom,qmp = <&aoss_qmp>; 7607 7608 qcom,smem-states = <&smp2p_gpdsp_out 0>; 7609 qcom,smem-state-names = "stop"; 7610 7611 status = "disabled"; 7612 7613 glink-edge { 7614 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7615 IPCC_MPROC_SIGNAL_GLINK_QMP 7616 IRQ_TYPE_EDGE_RISING>; 7617 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7618 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7619 7620 label = "gpdsp"; 7621 qcom,remote-pid = <17>; 7622 7623 fastrpc { 7624 compatible = "qcom,fastrpc"; 7625 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7626 label = "gdsp0"; 7627 #address-cells = <1>; 7628 #size-cells = <0>; 7629 7630 compute-cb@1 { 7631 compatible = "qcom,fastrpc-compute-cb"; 7632 reg = <1>; 7633 iommus = <&apps_smmu 0x28a1 0x0>; 7634 dma-coherent; 7635 }; 7636 7637 compute-cb@2 { 7638 compatible = "qcom,fastrpc-compute-cb"; 7639 reg = <2>; 7640 iommus = <&apps_smmu 0x28a2 0x0>; 7641 dma-coherent; 7642 }; 7643 7644 compute-cb@3 { 7645 compatible = "qcom,fastrpc-compute-cb"; 7646 reg = <3>; 7647 iommus = <&apps_smmu 0x28a3 0x0>; 7648 dma-coherent; 7649 }; 7650 }; 7651 }; 7652 }; 7653 7654 ethernet0: ethernet@23040000 { 7655 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 7656 reg = <0x0 0x23040000 0x0 0x00010000>, 7657 <0x0 0x23056000 0x0 0x00000100>; 7658 reg-names = "stmmaceth", "rgmii"; 7659 7660 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7661 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 7662 interrupt-names = "macirq", "sfty"; 7663 7664 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7665 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7666 <&gcc GCC_EMAC0_PTP_CLK>, 7667 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7668 clock-names = "stmmaceth", 7669 "pclk", 7670 "ptp_ref", 7671 "phyaux"; 7672 power-domains = <&gcc GCC_EMAC0_GDSC>; 7673 7674 phys = <&serdes0>; 7675 phy-names = "serdes"; 7676 7677 iommus = <&apps_smmu 0x120 0xf>; 7678 dma-coherent; 7679 7680 snps,tso; 7681 snps,pbl = <32>; 7682 rx-fifo-depth = <16384>; 7683 tx-fifo-depth = <20480>; 7684 7685 status = "disabled"; 7686 }; 7687 7688 nspa_noc: interconnect@260c0000 { 7689 compatible = "qcom,qcs8300-nspa-noc"; 7690 reg = <0x0 0x260c0000 0x0 0x16080>; 7691 #interconnect-cells = <2>; 7692 qcom,bcm-voters = <&apps_bcm_voter>; 7693 }; 7694 7695 remoteproc_cdsp: remoteproc@26300000 { 7696 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 7697 reg = <0x0 0x26300000 0x0 0x10000>; 7698 7699 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7700 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7701 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7702 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7703 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7704 interrupt-names = "wdog", 7705 "fatal", 7706 "ready", 7707 "handover", 7708 "stop-ack"; 7709 7710 clocks = <&rpmhcc RPMH_CXO_CLK>; 7711 clock-names = "xo"; 7712 7713 power-domains = <&rpmhpd RPMHPD_CX>, 7714 <&rpmhpd RPMHPD_MXC>, 7715 <&rpmhpd RPMHPD_NSP0>; 7716 7717 power-domain-names = "cx", 7718 "mxc", 7719 "nsp"; 7720 7721 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7722 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7723 7724 memory-region = <&cdsp_mem>; 7725 7726 qcom,qmp = <&aoss_qmp>; 7727 7728 qcom,smem-states = <&smp2p_cdsp_out 0>; 7729 qcom,smem-state-names = "stop"; 7730 7731 status = "disabled"; 7732 7733 glink-edge { 7734 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7735 IPCC_MPROC_SIGNAL_GLINK_QMP 7736 IRQ_TYPE_EDGE_RISING>; 7737 mboxes = <&ipcc IPCC_CLIENT_CDSP 7738 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7739 7740 label = "cdsp"; 7741 qcom,remote-pid = <5>; 7742 7743 fastrpc { 7744 compatible = "qcom,fastrpc"; 7745 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7746 label = "cdsp"; 7747 #address-cells = <1>; 7748 #size-cells = <0>; 7749 7750 compute-cb@1 { 7751 compatible = "qcom,fastrpc-compute-cb"; 7752 reg = <1>; 7753 iommus = <&apps_smmu 0x19c1 0x0440>, 7754 <&apps_smmu 0x1961 0x0400>; 7755 dma-coherent; 7756 }; 7757 7758 compute-cb@2 { 7759 compatible = "qcom,fastrpc-compute-cb"; 7760 reg = <2>; 7761 iommus = <&apps_smmu 0x19c2 0x0440>, 7762 <&apps_smmu 0x1962 0x0400>; 7763 dma-coherent; 7764 }; 7765 7766 compute-cb@3 { 7767 compatible = "qcom,fastrpc-compute-cb"; 7768 reg = <3>; 7769 iommus = <&apps_smmu 0x19c3 0x0440>, 7770 <&apps_smmu 0x1963 0x0400>; 7771 dma-coherent; 7772 }; 7773 7774 compute-cb@4 { 7775 compatible = "qcom,fastrpc-compute-cb"; 7776 reg = <4>; 7777 iommus = <&apps_smmu 0x19c4 0x0440>, 7778 <&apps_smmu 0x1964 0x0400>; 7779 dma-coherent; 7780 }; 7781 7782 compute-cb@5 { 7783 compatible = "qcom,fastrpc-compute-cb"; 7784 reg = <5>; 7785 iommus = <&apps_smmu 0x19c5 0x0400>; 7786 dma-coherent; 7787 }; 7788 7789 compute-cb@6 { 7790 compatible = "qcom,fastrpc-compute-cb"; 7791 reg = <6>; 7792 iommus = <&apps_smmu 0x19c6 0x0400>; 7793 dma-coherent; 7794 }; 7795 7796 compute-cb@7 { 7797 compatible = "qcom,fastrpc-compute-cb"; 7798 reg = <7>; 7799 iommus = <&apps_smmu 0x19c7 0x0400>; 7800 dma-coherent; 7801 }; 7802 7803 compute-cb@8 { 7804 compatible = "qcom,fastrpc-compute-cb"; 7805 reg = <8>; 7806 iommus = <&apps_smmu 0x19c8 0x0400>; 7807 dma-coherent; 7808 }; 7809 7810 compute-cb@9 { 7811 compatible = "qcom,fastrpc-compute-cb"; 7812 reg = <9>; 7813 iommus = <&apps_smmu 0x19c9 0x0400>; 7814 dma-coherent; 7815 }; 7816 7817 compute-cb@11 { 7818 compatible = "qcom,fastrpc-compute-cb"; 7819 reg = <0xb>; 7820 iommus = <&apps_smmu 0x19cb 0x0400>; 7821 dma-coherent; 7822 }; 7823 7824 compute-cb@12 { 7825 compatible = "qcom,fastrpc-compute-cb"; 7826 reg = <0xc>; 7827 iommus = <&apps_smmu 0x19cc 0x000>; 7828 dma-coherent; 7829 }; 7830 }; 7831 }; 7832 }; 7833 }; 7834 7835 thermal_zones: thermal-zones { 7836 aoss-0-thermal { 7837 thermal-sensors = <&tsens0 0>; 7838 7839 trips { 7840 aoss0-critical { 7841 temperature = <125000>; 7842 hysteresis = <1000>; 7843 type = "critical"; 7844 }; 7845 }; 7846 }; 7847 7848 cpu-0-0-0-thermal { 7849 thermal-sensors = <&tsens0 1>; 7850 7851 trips { 7852 cpu-critical { 7853 temperature = <125000>; 7854 hysteresis = <1000>; 7855 type = "critical"; 7856 }; 7857 }; 7858 }; 7859 7860 cpu-0-1-0-thermal { 7861 thermal-sensors = <&tsens0 2>; 7862 7863 trips { 7864 cpu-critical { 7865 temperature = <125000>; 7866 hysteresis = <1000>; 7867 type = "critical"; 7868 }; 7869 }; 7870 }; 7871 7872 cpu-0-2-0-thermal { 7873 thermal-sensors = <&tsens0 3>; 7874 7875 trips { 7876 cpu-critical { 7877 temperature = <125000>; 7878 hysteresis = <1000>; 7879 type = "critical"; 7880 }; 7881 }; 7882 }; 7883 7884 cpu-0-3-0-thermal { 7885 thermal-sensors = <&tsens0 4>; 7886 7887 trips { 7888 cpu-critical { 7889 temperature = <125000>; 7890 hysteresis = <1000>; 7891 type = "critical"; 7892 }; 7893 }; 7894 }; 7895 7896 gpuss-0-thermal { 7897 thermal-sensors = <&tsens0 5>; 7898 7899 trips { 7900 gpuss0_alert0: trip-point0 { 7901 temperature = <115000>; 7902 hysteresis = <5000>; 7903 type = "passive"; 7904 }; 7905 7906 gpuss0-critical { 7907 temperature = <125000>; 7908 hysteresis = <1000>; 7909 type = "critical"; 7910 }; 7911 }; 7912 7913 cooling-maps { 7914 map0 { 7915 trip = <&gpuss0_alert0>; 7916 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7917 }; 7918 }; 7919 }; 7920 7921 audio-thermal { 7922 thermal-sensors = <&tsens0 6>; 7923 7924 trips { 7925 audio-critical { 7926 temperature = <125000>; 7927 hysteresis = <1000>; 7928 type = "critical"; 7929 }; 7930 }; 7931 }; 7932 7933 camss-0-thermal { 7934 thermal-sensors = <&tsens0 7>; 7935 7936 trips { 7937 camss-critical { 7938 temperature = <125000>; 7939 hysteresis = <1000>; 7940 type = "critical"; 7941 }; 7942 }; 7943 }; 7944 7945 pcie-0-thermal { 7946 thermal-sensors = <&tsens0 8>; 7947 7948 trips { 7949 pcie-critical { 7950 temperature = <125000>; 7951 hysteresis = <1000>; 7952 type = "critical"; 7953 }; 7954 }; 7955 }; 7956 7957 cpuss-0-0-thermal { 7958 thermal-sensors = <&tsens0 9>; 7959 7960 trips { 7961 cpuss0-critical { 7962 temperature = <125000>; 7963 hysteresis = <1000>; 7964 type = "critical"; 7965 }; 7966 }; 7967 }; 7968 7969 aoss-1-thermal { 7970 thermal-sensors = <&tsens1 0>; 7971 7972 trips { 7973 aoss1-critical { 7974 temperature = <125000>; 7975 hysteresis = <1000>; 7976 type = "critical"; 7977 }; 7978 }; 7979 }; 7980 7981 cpu-0-0-1-thermal { 7982 thermal-sensors = <&tsens1 1>; 7983 7984 trips { 7985 cpu-critical { 7986 temperature = <125000>; 7987 hysteresis = <1000>; 7988 type = "critical"; 7989 }; 7990 }; 7991 }; 7992 7993 cpu-0-1-1-thermal { 7994 thermal-sensors = <&tsens1 2>; 7995 7996 trips { 7997 cpu-critical { 7998 temperature = <125000>; 7999 hysteresis = <1000>; 8000 type = "critical"; 8001 }; 8002 }; 8003 }; 8004 8005 cpu-0-2-1-thermal { 8006 thermal-sensors = <&tsens1 3>; 8007 8008 trips { 8009 cpu-critical { 8010 temperature = <125000>; 8011 hysteresis = <1000>; 8012 type = "critical"; 8013 }; 8014 }; 8015 }; 8016 8017 cpu-0-3-1-thermal { 8018 thermal-sensors = <&tsens1 4>; 8019 8020 trips { 8021 cpu-critical { 8022 temperature = <125000>; 8023 hysteresis = <1000>; 8024 type = "critical"; 8025 }; 8026 }; 8027 }; 8028 8029 gpuss-1-thermal { 8030 thermal-sensors = <&tsens1 5>; 8031 8032 trips { 8033 gpuss1_alert0: trip-point0 { 8034 temperature = <115000>; 8035 hysteresis = <5000>; 8036 type = "passive"; 8037 }; 8038 8039 gpuss1-critical { 8040 temperature = <125000>; 8041 hysteresis = <1000>; 8042 type = "critical"; 8043 }; 8044 }; 8045 8046 cooling-maps { 8047 map0 { 8048 trip = <&gpuss1_alert0>; 8049 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8050 }; 8051 }; 8052 }; 8053 8054 video-thermal { 8055 thermal-sensors = <&tsens1 6>; 8056 8057 trips { 8058 video-critical { 8059 temperature = <125000>; 8060 hysteresis = <1000>; 8061 type = "critical"; 8062 }; 8063 }; 8064 }; 8065 8066 camss-1-thermal { 8067 thermal-sensors = <&tsens1 7>; 8068 8069 trips { 8070 camss1-critical { 8071 temperature = <125000>; 8072 hysteresis = <1000>; 8073 type = "critical"; 8074 }; 8075 }; 8076 }; 8077 8078 pcie-1-thermal { 8079 thermal-sensors = <&tsens1 8>; 8080 8081 trips { 8082 pcie-critical { 8083 temperature = <125000>; 8084 hysteresis = <1000>; 8085 type = "critical"; 8086 }; 8087 }; 8088 }; 8089 8090 cpuss-0-1-thermal { 8091 thermal-sensors = <&tsens1 9>; 8092 8093 trips { 8094 cpuss0-critical { 8095 temperature = <125000>; 8096 hysteresis = <1000>; 8097 type = "critical"; 8098 }; 8099 }; 8100 }; 8101 8102 aoss-2-thermal { 8103 thermal-sensors = <&tsens2 0>; 8104 8105 trips { 8106 aoss2-critical { 8107 temperature = <125000>; 8108 hysteresis = <1000>; 8109 type = "critical"; 8110 }; 8111 }; 8112 }; 8113 8114 cpu-1-0-0-thermal { 8115 thermal-sensors = <&tsens2 1>; 8116 8117 trips { 8118 cpu-critical { 8119 temperature = <125000>; 8120 hysteresis = <1000>; 8121 type = "critical"; 8122 }; 8123 }; 8124 }; 8125 8126 cpu-1-1-0-thermal { 8127 thermal-sensors = <&tsens2 2>; 8128 8129 trips { 8130 cpu-critical { 8131 temperature = <125000>; 8132 hysteresis = <1000>; 8133 type = "critical"; 8134 }; 8135 }; 8136 }; 8137 8138 cpu-1-2-0-thermal { 8139 thermal-sensors = <&tsens2 3>; 8140 8141 trips { 8142 cpu-critical { 8143 temperature = <125000>; 8144 hysteresis = <1000>; 8145 type = "critical"; 8146 }; 8147 }; 8148 }; 8149 8150 cpu-1-3-0-thermal { 8151 thermal-sensors = <&tsens2 4>; 8152 8153 trips { 8154 cpu-critical { 8155 temperature = <125000>; 8156 hysteresis = <1000>; 8157 type = "critical"; 8158 }; 8159 }; 8160 }; 8161 8162 nsp-0-0-0-thermal { 8163 thermal-sensors = <&tsens2 5>; 8164 8165 trips { 8166 nsp-critical { 8167 temperature = <125000>; 8168 hysteresis = <1000>; 8169 type = "critical"; 8170 }; 8171 }; 8172 }; 8173 8174 nsp-0-1-0-thermal { 8175 thermal-sensors = <&tsens2 6>; 8176 8177 trips { 8178 nsp-critical { 8179 temperature = <125000>; 8180 hysteresis = <1000>; 8181 type = "critical"; 8182 }; 8183 }; 8184 }; 8185 8186 nsp-0-2-0-thermal { 8187 thermal-sensors = <&tsens2 7>; 8188 8189 trips { 8190 nsp-critical { 8191 temperature = <125000>; 8192 hysteresis = <1000>; 8193 type = "critical"; 8194 }; 8195 }; 8196 }; 8197 8198 ddrss-0-thermal { 8199 thermal-sensors = <&tsens2 8>; 8200 8201 trips { 8202 ddrss-critical { 8203 temperature = <125000>; 8204 hysteresis = <1000>; 8205 type = "critical"; 8206 }; 8207 }; 8208 }; 8209 8210 cpuss-1-0-thermal { 8211 thermal-sensors = <&tsens2 9>; 8212 8213 trips { 8214 cpuss1-critical { 8215 temperature = <125000>; 8216 hysteresis = <1000>; 8217 type = "critical"; 8218 }; 8219 }; 8220 }; 8221 8222 aoss-3-thermal { 8223 thermal-sensors = <&tsens3 0>; 8224 8225 trips { 8226 aoss3-critical { 8227 temperature = <125000>; 8228 hysteresis = <1000>; 8229 type = "critical"; 8230 }; 8231 }; 8232 }; 8233 8234 cpu-1-0-1-thermal { 8235 thermal-sensors = <&tsens3 1>; 8236 8237 trips { 8238 cpu-critical { 8239 temperature = <125000>; 8240 hysteresis = <1000>; 8241 type = "critical"; 8242 }; 8243 }; 8244 }; 8245 8246 cpu-1-1-1-thermal { 8247 thermal-sensors = <&tsens3 2>; 8248 8249 trips { 8250 cpu-critical { 8251 temperature = <125000>; 8252 hysteresis = <1000>; 8253 type = "critical"; 8254 }; 8255 }; 8256 }; 8257 8258 cpu-1-2-1-thermal { 8259 thermal-sensors = <&tsens3 3>; 8260 8261 trips { 8262 cpu-critical { 8263 temperature = <125000>; 8264 hysteresis = <1000>; 8265 type = "critical"; 8266 }; 8267 }; 8268 }; 8269 8270 cpu-1-3-1-thermal { 8271 thermal-sensors = <&tsens3 4>; 8272 8273 trips { 8274 cpu-critical { 8275 temperature = <125000>; 8276 hysteresis = <1000>; 8277 type = "critical"; 8278 }; 8279 }; 8280 }; 8281 8282 nsp-0-0-1-thermal { 8283 thermal-sensors = <&tsens3 5>; 8284 8285 trips { 8286 nsp-critical { 8287 temperature = <125000>; 8288 hysteresis = <1000>; 8289 type = "critical"; 8290 }; 8291 }; 8292 }; 8293 8294 nsp-0-1-1-thermal { 8295 thermal-sensors = <&tsens3 6>; 8296 8297 trips { 8298 nsp-critical { 8299 temperature = <125000>; 8300 hysteresis = <1000>; 8301 type = "critical"; 8302 }; 8303 }; 8304 }; 8305 8306 nsp-0-2-1-thermal { 8307 thermal-sensors = <&tsens3 7>; 8308 8309 trips { 8310 nsp-critical { 8311 temperature = <125000>; 8312 hysteresis = <1000>; 8313 type = "critical"; 8314 }; 8315 }; 8316 }; 8317 8318 ddrss-1-thermal { 8319 thermal-sensors = <&tsens3 8>; 8320 8321 trips { 8322 ddrss-critical { 8323 temperature = <125000>; 8324 hysteresis = <1000>; 8325 type = "critical"; 8326 }; 8327 }; 8328 }; 8329 8330 cpuss-1-1-thermal { 8331 thermal-sensors = <&tsens3 9>; 8332 8333 trips { 8334 cpuss1-critical { 8335 temperature = <125000>; 8336 hysteresis = <1000>; 8337 type = "critical"; 8338 }; 8339 }; 8340 }; 8341 }; 8342 8343 timer { 8344 compatible = "arm,armv8-timer"; 8345 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8346 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8347 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8348 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8349 }; 8350}; 8351