1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10 #include "mpi3mr.h"
11 #include <linux/io-64-nonatomic-lo-hi.h>
12 #include <linux/sched/mm.h>
13
14 static int
15 mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u16 reset_reason);
16 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
17 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
18 struct mpi3_ioc_facts_data *facts_data);
19 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
20 struct mpi3mr_drv_cmd *drv_cmd);
21 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc);
22 static int poll_queues;
23 module_param(poll_queues, int, 0444);
24 MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
25 static bool threaded_isr_poll = true;
26 module_param(threaded_isr_poll, bool, 0444);
27 MODULE_PARM_DESC(threaded_isr_poll,
28 "Enablement of IRQ polling thread (default=true)");
29
30 #if defined(writeq) && defined(CONFIG_64BIT)
mpi3mr_writeq(__u64 b,void __iomem * addr,spinlock_t * write_queue_lock)31 static inline void mpi3mr_writeq(__u64 b, void __iomem *addr,
32 spinlock_t *write_queue_lock)
33 {
34 writeq(b, addr);
35 }
36 #else
mpi3mr_writeq(__u64 b,void __iomem * addr,spinlock_t * write_queue_lock)37 static inline void mpi3mr_writeq(__u64 b, void __iomem *addr,
38 spinlock_t *write_queue_lock)
39 {
40 __u64 data_out = b;
41 unsigned long flags;
42
43 spin_lock_irqsave(write_queue_lock, flags);
44 writel((u32)(data_out), addr);
45 writel((u32)(data_out >> 32), (addr + 4));
46 spin_unlock_irqrestore(write_queue_lock, flags);
47 }
48 #endif
49
50 static inline bool
mpi3mr_check_req_qfull(struct op_req_qinfo * op_req_q)51 mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
52 {
53 u16 pi, ci, max_entries;
54 bool is_qfull = false;
55
56 pi = op_req_q->pi;
57 ci = READ_ONCE(op_req_q->ci);
58 max_entries = op_req_q->num_requests;
59
60 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
61 is_qfull = true;
62
63 return is_qfull;
64 }
65
mpi3mr_sync_irqs(struct mpi3mr_ioc * mrioc)66 static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
67 {
68 u16 i, max_vectors;
69
70 max_vectors = mrioc->intr_info_count;
71
72 for (i = 0; i < max_vectors; i++)
73 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
74 }
75
mpi3mr_ioc_disable_intr(struct mpi3mr_ioc * mrioc)76 void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
77 {
78 mrioc->intr_enabled = 0;
79 mpi3mr_sync_irqs(mrioc);
80 }
81
mpi3mr_ioc_enable_intr(struct mpi3mr_ioc * mrioc)82 void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
83 {
84 mrioc->intr_enabled = 1;
85 }
86
mpi3mr_cleanup_isr(struct mpi3mr_ioc * mrioc)87 static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
88 {
89 u16 i;
90
91 mpi3mr_ioc_disable_intr(mrioc);
92
93 if (!mrioc->intr_info)
94 return;
95
96 for (i = 0; i < mrioc->intr_info_count; i++)
97 free_irq(pci_irq_vector(mrioc->pdev, i),
98 (mrioc->intr_info + i));
99
100 kfree(mrioc->intr_info);
101 mrioc->intr_info = NULL;
102 mrioc->intr_info_count = 0;
103 mrioc->is_intr_info_set = false;
104 pci_free_irq_vectors(mrioc->pdev);
105 }
106
mpi3mr_add_sg_single(void * paddr,u8 flags,u32 length,dma_addr_t dma_addr)107 void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
108 dma_addr_t dma_addr)
109 {
110 struct mpi3_sge_common *sgel = paddr;
111
112 sgel->flags = flags;
113 sgel->length = cpu_to_le32(length);
114 sgel->address = cpu_to_le64(dma_addr);
115 }
116
mpi3mr_build_zero_len_sge(void * paddr)117 void mpi3mr_build_zero_len_sge(void *paddr)
118 {
119 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
120
121 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
122 }
123
mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)124 void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
125 dma_addr_t phys_addr)
126 {
127 if (!phys_addr)
128 return NULL;
129
130 if ((phys_addr < mrioc->reply_buf_dma) ||
131 (phys_addr > mrioc->reply_buf_dma_max_address))
132 return NULL;
133
134 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
135 }
136
mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc * mrioc,dma_addr_t phys_addr)137 void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
138 dma_addr_t phys_addr)
139 {
140 if (!phys_addr)
141 return NULL;
142
143 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
144 }
145
mpi3mr_repost_reply_buf(struct mpi3mr_ioc * mrioc,u64 reply_dma)146 static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
147 u64 reply_dma)
148 {
149 u32 old_idx = 0;
150 unsigned long flags;
151
152 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
153 old_idx = mrioc->reply_free_queue_host_index;
154 mrioc->reply_free_queue_host_index = (
155 (mrioc->reply_free_queue_host_index ==
156 (mrioc->reply_free_qsz - 1)) ? 0 :
157 (mrioc->reply_free_queue_host_index + 1));
158 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
159 writel(mrioc->reply_free_queue_host_index,
160 &mrioc->sysif_regs->reply_free_host_index);
161 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
162 }
163
mpi3mr_repost_sense_buf(struct mpi3mr_ioc * mrioc,u64 sense_buf_dma)164 void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
165 u64 sense_buf_dma)
166 {
167 u32 old_idx = 0;
168 unsigned long flags;
169
170 spin_lock_irqsave(&mrioc->sbq_lock, flags);
171 old_idx = mrioc->sbq_host_index;
172 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
173 (mrioc->sense_buf_q_sz - 1)) ? 0 :
174 (mrioc->sbq_host_index + 1));
175 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
176 writel(mrioc->sbq_host_index,
177 &mrioc->sysif_regs->sense_buffer_free_host_index);
178 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
179 }
180
mpi3mr_print_event_data(struct mpi3mr_ioc * mrioc,struct mpi3_event_notification_reply * event_reply)181 static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
182 struct mpi3_event_notification_reply *event_reply)
183 {
184 char *desc = NULL;
185 u16 event;
186
187 if (!(mrioc->logging_level & MPI3_DEBUG_EVENT))
188 return;
189
190 event = event_reply->event;
191
192 switch (event) {
193 case MPI3_EVENT_LOG_DATA:
194 desc = "Log Data";
195 break;
196 case MPI3_EVENT_CHANGE:
197 desc = "Event Change";
198 break;
199 case MPI3_EVENT_GPIO_INTERRUPT:
200 desc = "GPIO Interrupt";
201 break;
202 case MPI3_EVENT_CABLE_MGMT:
203 desc = "Cable Management";
204 break;
205 case MPI3_EVENT_ENERGY_PACK_CHANGE:
206 desc = "Energy Pack Change";
207 break;
208 case MPI3_EVENT_DEVICE_ADDED:
209 {
210 struct mpi3_device_page0 *event_data =
211 (struct mpi3_device_page0 *)event_reply->event_data;
212 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
213 event_data->dev_handle, event_data->device_form);
214 return;
215 }
216 case MPI3_EVENT_DEVICE_INFO_CHANGED:
217 {
218 struct mpi3_device_page0 *event_data =
219 (struct mpi3_device_page0 *)event_reply->event_data;
220 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
221 event_data->dev_handle, event_data->device_form);
222 return;
223 }
224 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
225 {
226 struct mpi3_event_data_device_status_change *event_data =
227 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
228 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
229 event_data->dev_handle, event_data->reason_code);
230 return;
231 }
232 case MPI3_EVENT_SAS_DISCOVERY:
233 {
234 struct mpi3_event_data_sas_discovery *event_data =
235 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
236 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
237 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
238 "start" : "stop",
239 le32_to_cpu(event_data->discovery_status));
240 return;
241 }
242 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
243 desc = "SAS Broadcast Primitive";
244 break;
245 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
246 desc = "SAS Notify Primitive";
247 break;
248 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
249 desc = "SAS Init Device Status Change";
250 break;
251 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
252 desc = "SAS Init Table Overflow";
253 break;
254 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
255 desc = "SAS Topology Change List";
256 break;
257 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
258 desc = "Enclosure Device Status Change";
259 break;
260 case MPI3_EVENT_ENCL_DEVICE_ADDED:
261 desc = "Enclosure Added";
262 break;
263 case MPI3_EVENT_HARD_RESET_RECEIVED:
264 desc = "Hard Reset Received";
265 break;
266 case MPI3_EVENT_SAS_PHY_COUNTER:
267 desc = "SAS PHY Counter";
268 break;
269 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
270 desc = "SAS Device Discovery Error";
271 break;
272 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
273 desc = "PCIE Topology Change List";
274 break;
275 case MPI3_EVENT_PCIE_ENUMERATION:
276 {
277 struct mpi3_event_data_pcie_enumeration *event_data =
278 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
279 ioc_info(mrioc, "PCIE Enumeration: (%s)",
280 (event_data->reason_code ==
281 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
282 if (event_data->enumeration_status)
283 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
284 le32_to_cpu(event_data->enumeration_status));
285 return;
286 }
287 case MPI3_EVENT_PREPARE_FOR_RESET:
288 desc = "Prepare For Reset";
289 break;
290 case MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE:
291 desc = "Diagnostic Buffer Status Change";
292 break;
293 }
294
295 if (!desc)
296 return;
297
298 ioc_info(mrioc, "%s\n", desc);
299 }
300
mpi3mr_handle_events(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply * def_reply)301 static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
302 struct mpi3_default_reply *def_reply)
303 {
304 struct mpi3_event_notification_reply *event_reply =
305 (struct mpi3_event_notification_reply *)def_reply;
306
307 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
308 mpi3mr_print_event_data(mrioc, event_reply);
309 mpi3mr_os_handle_events(mrioc, event_reply);
310 }
311
312 static struct mpi3mr_drv_cmd *
mpi3mr_get_drv_cmd(struct mpi3mr_ioc * mrioc,u16 host_tag,struct mpi3_default_reply * def_reply)313 mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
314 struct mpi3_default_reply *def_reply)
315 {
316 u16 idx;
317
318 switch (host_tag) {
319 case MPI3MR_HOSTTAG_INITCMDS:
320 return &mrioc->init_cmds;
321 case MPI3MR_HOSTTAG_CFG_CMDS:
322 return &mrioc->cfg_cmds;
323 case MPI3MR_HOSTTAG_BSG_CMDS:
324 return &mrioc->bsg_cmds;
325 case MPI3MR_HOSTTAG_BLK_TMS:
326 return &mrioc->host_tm_cmds;
327 case MPI3MR_HOSTTAG_PEL_ABORT:
328 return &mrioc->pel_abort_cmd;
329 case MPI3MR_HOSTTAG_PEL_WAIT:
330 return &mrioc->pel_cmds;
331 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
332 return &mrioc->transport_cmds;
333 case MPI3MR_HOSTTAG_INVALID:
334 if (def_reply && def_reply->function ==
335 MPI3_FUNCTION_EVENT_NOTIFICATION)
336 mpi3mr_handle_events(mrioc, def_reply);
337 return NULL;
338 default:
339 break;
340 }
341 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
342 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
343 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
344 return &mrioc->dev_rmhs_cmds[idx];
345 }
346
347 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
348 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
349 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
350 return &mrioc->evtack_cmds[idx];
351 }
352
353 return NULL;
354 }
355
mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc * mrioc,struct mpi3_default_reply_descriptor * reply_desc,u64 * reply_dma)356 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
357 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
358 {
359 u16 reply_desc_type, host_tag = 0;
360 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
361 u16 masked_ioc_status = MPI3_IOCSTATUS_SUCCESS;
362 u32 ioc_loginfo = 0, sense_count = 0;
363 struct mpi3_status_reply_descriptor *status_desc;
364 struct mpi3_address_reply_descriptor *addr_desc;
365 struct mpi3_success_reply_descriptor *success_desc;
366 struct mpi3_default_reply *def_reply = NULL;
367 struct mpi3mr_drv_cmd *cmdptr = NULL;
368 struct mpi3_scsi_io_reply *scsi_reply;
369 struct scsi_sense_hdr sshdr;
370 u8 *sense_buf = NULL;
371
372 *reply_dma = 0;
373 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
374 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
375 switch (reply_desc_type) {
376 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
377 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
378 host_tag = le16_to_cpu(status_desc->host_tag);
379 ioc_status = le16_to_cpu(status_desc->ioc_status);
380 if (ioc_status &
381 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
382 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
383 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
384 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
385 break;
386 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
387 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
388 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
389 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
390 if (!def_reply)
391 goto out;
392 host_tag = le16_to_cpu(def_reply->host_tag);
393 ioc_status = le16_to_cpu(def_reply->ioc_status);
394 if (ioc_status &
395 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
396 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
397 masked_ioc_status = ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
398 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
399 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
400 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
401 le64_to_cpu(scsi_reply->sense_data_buffer_address));
402 sense_count = le32_to_cpu(scsi_reply->sense_count);
403 if (sense_buf) {
404 scsi_normalize_sense(sense_buf, sense_count,
405 &sshdr);
406 mpi3mr_scsisense_trigger(mrioc, sshdr.sense_key,
407 sshdr.asc, sshdr.ascq);
408 }
409 }
410 mpi3mr_reply_trigger(mrioc, masked_ioc_status, ioc_loginfo);
411 break;
412 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
413 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
414 host_tag = le16_to_cpu(success_desc->host_tag);
415 break;
416 default:
417 break;
418 }
419
420 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
421 if (cmdptr) {
422 if (cmdptr->state & MPI3MR_CMD_PENDING) {
423 cmdptr->state |= MPI3MR_CMD_COMPLETE;
424 cmdptr->ioc_loginfo = ioc_loginfo;
425 if (host_tag == MPI3MR_HOSTTAG_BSG_CMDS)
426 cmdptr->ioc_status = ioc_status;
427 else
428 cmdptr->ioc_status = masked_ioc_status;
429 cmdptr->state &= ~MPI3MR_CMD_PENDING;
430 if (def_reply) {
431 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
432 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
433 mrioc->reply_sz);
434 }
435 if (sense_buf && cmdptr->sensebuf) {
436 cmdptr->is_sense = 1;
437 memcpy(cmdptr->sensebuf, sense_buf,
438 MPI3MR_SENSE_BUF_SZ);
439 }
440 if (cmdptr->is_waiting) {
441 cmdptr->is_waiting = 0;
442 complete(&cmdptr->done);
443 } else if (cmdptr->callback)
444 cmdptr->callback(mrioc, cmdptr);
445 }
446 }
447 out:
448 if (sense_buf)
449 mpi3mr_repost_sense_buf(mrioc,
450 le64_to_cpu(scsi_reply->sense_data_buffer_address));
451 }
452
mpi3mr_process_admin_reply_q(struct mpi3mr_ioc * mrioc)453 int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
454 {
455 u32 exp_phase = mrioc->admin_reply_ephase;
456 u32 admin_reply_ci = mrioc->admin_reply_ci;
457 u32 num_admin_replies = 0;
458 u64 reply_dma = 0;
459 u16 threshold_comps = 0;
460 struct mpi3_default_reply_descriptor *reply_desc;
461
462 if (!atomic_add_unless(&mrioc->admin_reply_q_in_use, 1, 1)) {
463 atomic_inc(&mrioc->admin_pend_isr);
464 return 0;
465 }
466
467 atomic_set(&mrioc->admin_pend_isr, 0);
468 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
469 admin_reply_ci;
470
471 if ((le16_to_cpu(reply_desc->reply_flags) &
472 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
473 atomic_dec(&mrioc->admin_reply_q_in_use);
474 return 0;
475 }
476
477 do {
478 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
479 break;
480
481 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
482 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
483 if (reply_dma)
484 mpi3mr_repost_reply_buf(mrioc, reply_dma);
485 num_admin_replies++;
486 threshold_comps++;
487 if (++admin_reply_ci == mrioc->num_admin_replies) {
488 admin_reply_ci = 0;
489 exp_phase ^= 1;
490 }
491 reply_desc =
492 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
493 admin_reply_ci;
494 if ((le16_to_cpu(reply_desc->reply_flags) &
495 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
496 break;
497 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
498 writel(admin_reply_ci,
499 &mrioc->sysif_regs->admin_reply_queue_ci);
500 threshold_comps = 0;
501 }
502 } while (1);
503
504 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
505 mrioc->admin_reply_ci = admin_reply_ci;
506 mrioc->admin_reply_ephase = exp_phase;
507 atomic_dec(&mrioc->admin_reply_q_in_use);
508
509 return num_admin_replies;
510 }
511
512 /**
513 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
514 * queue's consumer index from operational reply descriptor queue.
515 * @op_reply_q: op_reply_qinfo object
516 * @reply_ci: operational reply descriptor's queue consumer index
517 *
518 * Returns: reply descriptor frame address
519 */
520 static inline struct mpi3_default_reply_descriptor *
mpi3mr_get_reply_desc(struct op_reply_qinfo * op_reply_q,u32 reply_ci)521 mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
522 {
523 void *segment_base_addr;
524 struct segments *segments = op_reply_q->q_segments;
525 struct mpi3_default_reply_descriptor *reply_desc = NULL;
526
527 segment_base_addr =
528 segments[reply_ci / op_reply_q->segment_qd].segment;
529 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
530 (reply_ci % op_reply_q->segment_qd);
531 return reply_desc;
532 }
533
534 /**
535 * mpi3mr_process_op_reply_q - Operational reply queue handler
536 * @mrioc: Adapter instance reference
537 * @op_reply_q: Operational reply queue info
538 *
539 * Checks the specific operational reply queue and drains the
540 * reply queue entries until the queue is empty and process the
541 * individual reply descriptors.
542 *
543 * Return: 0 if queue is already processed,or number of reply
544 * descriptors processed.
545 */
mpi3mr_process_op_reply_q(struct mpi3mr_ioc * mrioc,struct op_reply_qinfo * op_reply_q)546 int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
547 struct op_reply_qinfo *op_reply_q)
548 {
549 struct op_req_qinfo *op_req_q;
550 u32 exp_phase;
551 u32 reply_ci;
552 u32 num_op_reply = 0;
553 u64 reply_dma = 0;
554 struct mpi3_default_reply_descriptor *reply_desc;
555 u16 req_q_idx = 0, reply_qidx, threshold_comps = 0;
556
557 reply_qidx = op_reply_q->qid - 1;
558
559 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
560 return 0;
561
562 exp_phase = op_reply_q->ephase;
563 reply_ci = op_reply_q->ci;
564
565 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
566 if ((le16_to_cpu(reply_desc->reply_flags) &
567 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
568 atomic_dec(&op_reply_q->in_use);
569 return 0;
570 }
571
572 do {
573 if (mrioc->unrecoverable || mrioc->io_admin_reset_sync)
574 break;
575
576 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
577 op_req_q = &mrioc->req_qinfo[req_q_idx];
578
579 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
580 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
581 reply_qidx);
582
583 if (reply_dma)
584 mpi3mr_repost_reply_buf(mrioc, reply_dma);
585 num_op_reply++;
586 threshold_comps++;
587
588 if (++reply_ci == op_reply_q->num_replies) {
589 reply_ci = 0;
590 exp_phase ^= 1;
591 }
592
593 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
594
595 if ((le16_to_cpu(reply_desc->reply_flags) &
596 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
597 break;
598 #ifndef CONFIG_PREEMPT_RT
599 /*
600 * Exit completion loop to avoid CPU lockup
601 * Ensure remaining completion happens from threaded ISR.
602 */
603 if ((num_op_reply > mrioc->max_host_ios) &&
604 (threaded_isr_poll == true)) {
605 op_reply_q->enable_irq_poll = true;
606 break;
607 }
608 #endif
609 if (threshold_comps == MPI3MR_THRESHOLD_REPLY_COUNT) {
610 writel(reply_ci,
611 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
612 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
613 threshold_comps = 0;
614 }
615 } while (1);
616
617 writel(reply_ci,
618 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
619 op_reply_q->ci = reply_ci;
620 op_reply_q->ephase = exp_phase;
621 atomic_sub(threshold_comps, &op_reply_q->pend_ios);
622 atomic_dec(&op_reply_q->in_use);
623 return num_op_reply;
624 }
625
626 /**
627 * mpi3mr_blk_mq_poll - Operational reply queue handler
628 * @shost: SCSI Host reference
629 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
630 *
631 * Checks the specific operational reply queue and drains the
632 * reply queue entries until the queue is empty and process the
633 * individual reply descriptors.
634 *
635 * Return: 0 if queue is already processed,or number of reply
636 * descriptors processed.
637 */
mpi3mr_blk_mq_poll(struct Scsi_Host * shost,unsigned int queue_num)638 int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
639 {
640 int num_entries = 0;
641 struct mpi3mr_ioc *mrioc;
642
643 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
644
645 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
646 mrioc->unrecoverable || mrioc->pci_err_recovery))
647 return 0;
648
649 num_entries = mpi3mr_process_op_reply_q(mrioc,
650 &mrioc->op_reply_qinfo[queue_num]);
651
652 return num_entries;
653 }
654
mpi3mr_isr_primary(int irq,void * privdata)655 static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
656 {
657 struct mpi3mr_intr_info *intr_info = privdata;
658 struct mpi3mr_ioc *mrioc;
659 u16 midx;
660 u32 num_admin_replies = 0, num_op_reply = 0;
661
662 if (!intr_info)
663 return IRQ_NONE;
664
665 mrioc = intr_info->mrioc;
666
667 if (!mrioc->intr_enabled)
668 return IRQ_NONE;
669
670 midx = intr_info->msix_index;
671
672 if (!midx)
673 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
674 if (intr_info->op_reply_q)
675 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
676 intr_info->op_reply_q);
677
678 if (num_admin_replies || num_op_reply)
679 return IRQ_HANDLED;
680 else
681 return IRQ_NONE;
682 }
683
684 #ifndef CONFIG_PREEMPT_RT
685
mpi3mr_isr(int irq,void * privdata)686 static irqreturn_t mpi3mr_isr(int irq, void *privdata)
687 {
688 struct mpi3mr_intr_info *intr_info = privdata;
689 int ret;
690
691 if (!intr_info)
692 return IRQ_NONE;
693
694 /* Call primary ISR routine */
695 ret = mpi3mr_isr_primary(irq, privdata);
696
697 /*
698 * If more IOs are expected, schedule IRQ polling thread.
699 * Otherwise exit from ISR.
700 */
701 if ((threaded_isr_poll == false) || !intr_info->op_reply_q)
702 return ret;
703
704 if (!intr_info->op_reply_q->enable_irq_poll ||
705 !atomic_read(&intr_info->op_reply_q->pend_ios))
706 return ret;
707
708 disable_irq_nosync(intr_info->os_irq);
709
710 return IRQ_WAKE_THREAD;
711 }
712
713 /**
714 * mpi3mr_isr_poll - Reply queue polling routine
715 * @irq: IRQ
716 * @privdata: Interrupt info
717 *
718 * poll for pending I/O completions in a loop until pending I/Os
719 * present or controller queue depth I/Os are processed.
720 *
721 * Return: IRQ_NONE or IRQ_HANDLED
722 */
mpi3mr_isr_poll(int irq,void * privdata)723 static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
724 {
725 struct mpi3mr_intr_info *intr_info = privdata;
726 struct mpi3mr_ioc *mrioc;
727 u16 midx;
728 u32 num_op_reply = 0;
729
730 if (!intr_info || !intr_info->op_reply_q)
731 return IRQ_NONE;
732
733 mrioc = intr_info->mrioc;
734 midx = intr_info->msix_index;
735
736 /* Poll for pending IOs completions */
737 do {
738 if (!mrioc->intr_enabled || mrioc->unrecoverable)
739 break;
740
741 if (!midx)
742 mpi3mr_process_admin_reply_q(mrioc);
743 if (intr_info->op_reply_q)
744 num_op_reply +=
745 mpi3mr_process_op_reply_q(mrioc,
746 intr_info->op_reply_q);
747
748 usleep_range(MPI3MR_IRQ_POLL_SLEEP, MPI3MR_IRQ_POLL_SLEEP + 1);
749
750 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
751 (num_op_reply < mrioc->max_host_ios));
752
753 intr_info->op_reply_q->enable_irq_poll = false;
754 enable_irq(intr_info->os_irq);
755
756 return IRQ_HANDLED;
757 }
758
759 #endif
760
761 /**
762 * mpi3mr_request_irq - Request IRQ and register ISR
763 * @mrioc: Adapter instance reference
764 * @index: IRQ vector index
765 *
766 * Request threaded ISR with primary ISR and secondary
767 *
768 * Return: 0 on success and non zero on failures.
769 */
mpi3mr_request_irq(struct mpi3mr_ioc * mrioc,u16 index)770 static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
771 {
772 struct pci_dev *pdev = mrioc->pdev;
773 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
774 int retval = 0;
775
776 intr_info->mrioc = mrioc;
777 intr_info->msix_index = index;
778 intr_info->op_reply_q = NULL;
779
780 scnprintf(intr_info->name, MPI3MR_NAME_LENGTH,
781 "%.32s%d-msix%u", mrioc->driver_name, mrioc->id, index);
782
783 #ifndef CONFIG_PREEMPT_RT
784 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
785 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
786 #else
787 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
788 NULL, IRQF_SHARED, intr_info->name, intr_info);
789 #endif
790 if (retval) {
791 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
792 intr_info->name, pci_irq_vector(pdev, index));
793 return retval;
794 }
795
796 intr_info->os_irq = pci_irq_vector(pdev, index);
797 return retval;
798 }
799
mpi3mr_calc_poll_queues(struct mpi3mr_ioc * mrioc,u16 max_vectors)800 static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
801 {
802 if (!mrioc->requested_poll_qcount)
803 return;
804
805 /* Reserved for Admin and Default Queue */
806 if (max_vectors > 2 &&
807 (mrioc->requested_poll_qcount < max_vectors - 2)) {
808 ioc_info(mrioc,
809 "enabled polled queues (%d) msix (%d)\n",
810 mrioc->requested_poll_qcount, max_vectors);
811 } else {
812 ioc_info(mrioc,
813 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
814 mrioc->requested_poll_qcount, max_vectors);
815 mrioc->requested_poll_qcount = 0;
816 }
817 }
818
819 /**
820 * mpi3mr_setup_isr - Setup ISR for the controller
821 * @mrioc: Adapter instance reference
822 * @setup_one: Request one IRQ or more
823 *
824 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
825 *
826 * Return: 0 on success and non zero on failures.
827 */
mpi3mr_setup_isr(struct mpi3mr_ioc * mrioc,u8 setup_one)828 static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
829 {
830 unsigned int irq_flags = PCI_IRQ_MSIX;
831 int max_vectors, min_vec;
832 int retval;
833 int i;
834 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
835
836 if (mrioc->is_intr_info_set)
837 return 0;
838
839 mpi3mr_cleanup_isr(mrioc);
840
841 if (setup_one || reset_devices) {
842 max_vectors = 1;
843 retval = pci_alloc_irq_vectors(mrioc->pdev,
844 1, max_vectors, irq_flags);
845 if (retval < 0) {
846 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
847 retval);
848 goto out_failed;
849 }
850 } else {
851 max_vectors =
852 min_t(int, mrioc->cpu_count + 1 +
853 mrioc->requested_poll_qcount, mrioc->msix_count);
854
855 mpi3mr_calc_poll_queues(mrioc, max_vectors);
856
857 ioc_info(mrioc,
858 "MSI-X vectors supported: %d, no of cores: %d,",
859 mrioc->msix_count, mrioc->cpu_count);
860 ioc_info(mrioc,
861 "MSI-x vectors requested: %d poll_queues %d\n",
862 max_vectors, mrioc->requested_poll_qcount);
863
864 desc.post_vectors = mrioc->requested_poll_qcount;
865 min_vec = desc.pre_vectors + desc.post_vectors;
866 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
867
868 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
869 min_vec, max_vectors, irq_flags, &desc);
870
871 if (retval < 0) {
872 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
873 retval);
874 goto out_failed;
875 }
876
877
878 /*
879 * If only one MSI-x is allocated, then MSI-x 0 will be shared
880 * between Admin queue and operational queue
881 */
882 if (retval == min_vec)
883 mrioc->op_reply_q_offset = 0;
884 else if (retval != (max_vectors)) {
885 ioc_info(mrioc,
886 "allocated vectors (%d) are less than configured (%d)\n",
887 retval, max_vectors);
888 }
889
890 max_vectors = retval;
891 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
892
893 mpi3mr_calc_poll_queues(mrioc, max_vectors);
894
895 }
896
897 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
898 GFP_KERNEL);
899 if (!mrioc->intr_info) {
900 retval = -ENOMEM;
901 pci_free_irq_vectors(mrioc->pdev);
902 goto out_failed;
903 }
904 for (i = 0; i < max_vectors; i++) {
905 retval = mpi3mr_request_irq(mrioc, i);
906 if (retval) {
907 mrioc->intr_info_count = i;
908 goto out_failed;
909 }
910 }
911 if (reset_devices || !setup_one)
912 mrioc->is_intr_info_set = true;
913 mrioc->intr_info_count = max_vectors;
914 mpi3mr_ioc_enable_intr(mrioc);
915 return 0;
916
917 out_failed:
918 mpi3mr_cleanup_isr(mrioc);
919
920 return retval;
921 }
922
923 static const struct {
924 enum mpi3mr_iocstate value;
925 char *name;
926 } mrioc_states[] = {
927 { MRIOC_STATE_READY, "ready" },
928 { MRIOC_STATE_FAULT, "fault" },
929 { MRIOC_STATE_RESET, "reset" },
930 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
931 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
932 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
933 };
934
mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)935 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
936 {
937 int i;
938 char *name = NULL;
939
940 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
941 if (mrioc_states[i].value == mrioc_state) {
942 name = mrioc_states[i].name;
943 break;
944 }
945 }
946 return name;
947 }
948
949 /* Reset reason to name mapper structure*/
950 static const struct {
951 enum mpi3mr_reset_reason value;
952 char *name;
953 } mpi3mr_reset_reason_codes[] = {
954 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
955 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
956 { MPI3MR_RESET_FROM_APP, "application invocation" },
957 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
958 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
959 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
960 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
961 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
962 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
963 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
964 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
965 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
966 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
967 {
968 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
969 "create request queue timeout"
970 },
971 {
972 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
973 "create reply queue timeout"
974 },
975 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
976 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
977 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
978 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
979 {
980 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
981 "component image activation timeout"
982 },
983 {
984 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
985 "get package version timeout"
986 },
987 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
988 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
989 {
990 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT,
991 "diagnostic buffer post timeout"
992 },
993 {
994 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT,
995 "diagnostic buffer release timeout"
996 },
997 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
998 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
999 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
1000 { MPI3MR_RESET_FROM_INVALID_COMPLETION, "invalid cmd completion" },
1001 };
1002
1003 /**
1004 * mpi3mr_reset_rc_name - get reset reason code name
1005 * @reason_code: reset reason code value
1006 *
1007 * Map reset reason to an NULL terminated ASCII string
1008 *
1009 * Return: name corresponding to reset reason value or NULL.
1010 */
mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)1011 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
1012 {
1013 int i;
1014 char *name = NULL;
1015
1016 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
1017 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
1018 name = mpi3mr_reset_reason_codes[i].name;
1019 break;
1020 }
1021 }
1022 return name;
1023 }
1024
1025 /* Reset type to name mapper structure*/
1026 static const struct {
1027 u16 reset_type;
1028 char *name;
1029 } mpi3mr_reset_types[] = {
1030 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
1031 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
1032 };
1033
1034 /**
1035 * mpi3mr_reset_type_name - get reset type name
1036 * @reset_type: reset type value
1037 *
1038 * Map reset type to an NULL terminated ASCII string
1039 *
1040 * Return: name corresponding to reset type value or NULL.
1041 */
mpi3mr_reset_type_name(u16 reset_type)1042 static const char *mpi3mr_reset_type_name(u16 reset_type)
1043 {
1044 int i;
1045 char *name = NULL;
1046
1047 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
1048 if (mpi3mr_reset_types[i].reset_type == reset_type) {
1049 name = mpi3mr_reset_types[i].name;
1050 break;
1051 }
1052 }
1053 return name;
1054 }
1055
1056 /**
1057 * mpi3mr_is_fault_recoverable - Read fault code and decide
1058 * whether the controller can be recoverable
1059 * @mrioc: Adapter instance reference
1060 * Return: true if fault is recoverable, false otherwise.
1061 */
mpi3mr_is_fault_recoverable(struct mpi3mr_ioc * mrioc)1062 static inline bool mpi3mr_is_fault_recoverable(struct mpi3mr_ioc *mrioc)
1063 {
1064 u32 fault;
1065
1066 fault = (readl(&mrioc->sysif_regs->fault) &
1067 MPI3_SYSIF_FAULT_CODE_MASK);
1068
1069 switch (fault) {
1070 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
1071 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
1072 ioc_warn(mrioc,
1073 "controller requires system power cycle, marking controller as unrecoverable\n");
1074 return false;
1075 case MPI3_SYSIF_FAULT_CODE_INSUFFICIENT_PCI_SLOT_POWER:
1076 ioc_warn(mrioc,
1077 "controller faulted due to insufficient power,\n"
1078 " try by connecting it to a different slot\n");
1079 return false;
1080 default:
1081 break;
1082 }
1083 return true;
1084 }
1085
1086 /**
1087 * mpi3mr_print_fault_info - Display fault information
1088 * @mrioc: Adapter instance reference
1089 *
1090 * Display the controller fault information if there is a
1091 * controller fault.
1092 *
1093 * Return: Nothing.
1094 */
mpi3mr_print_fault_info(struct mpi3mr_ioc * mrioc)1095 void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
1096 {
1097 u32 ioc_status, code, code1, code2, code3;
1098
1099 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1100
1101 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1102 code = readl(&mrioc->sysif_regs->fault);
1103 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1104 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1105 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1106
1107 ioc_info(mrioc,
1108 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1109 code, code1, code2, code3);
1110 }
1111 }
1112
1113 /**
1114 * mpi3mr_save_fault_info - Save fault information
1115 * @mrioc: Adapter instance reference
1116 *
1117 * Save the controller fault information if there is a
1118 * controller fault.
1119 *
1120 * Return: Nothing.
1121 */
mpi3mr_save_fault_info(struct mpi3mr_ioc * mrioc)1122 static void mpi3mr_save_fault_info(struct mpi3mr_ioc *mrioc)
1123 {
1124 u32 ioc_status, i;
1125
1126 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1127
1128 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1129 mrioc->saved_fault_code = readl(&mrioc->sysif_regs->fault) &
1130 MPI3_SYSIF_FAULT_CODE_MASK;
1131 for (i = 0; i < 3; i++) {
1132 mrioc->saved_fault_info[i] =
1133 readl(&mrioc->sysif_regs->fault_info[i]);
1134 }
1135 }
1136 }
1137
1138 /**
1139 * mpi3mr_get_iocstate - Get IOC State
1140 * @mrioc: Adapter instance reference
1141 *
1142 * Return a proper IOC state enum based on the IOC status and
1143 * IOC configuration and unrcoverable state of the controller.
1144 *
1145 * Return: Current IOC state.
1146 */
mpi3mr_get_iocstate(struct mpi3mr_ioc * mrioc)1147 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1148 {
1149 u32 ioc_status, ioc_config;
1150 u8 ready, enabled;
1151
1152 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1153 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1154
1155 if (mrioc->unrecoverable)
1156 return MRIOC_STATE_UNRECOVERABLE;
1157 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1158 return MRIOC_STATE_FAULT;
1159
1160 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1161 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1162
1163 if (ready && enabled)
1164 return MRIOC_STATE_READY;
1165 if ((!ready) && (!enabled))
1166 return MRIOC_STATE_RESET;
1167 if ((!ready) && (enabled))
1168 return MRIOC_STATE_BECOMING_READY;
1169
1170 return MRIOC_STATE_RESET_REQUESTED;
1171 }
1172
1173 /**
1174 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma
1175 * @mrioc: Adapter instance reference
1176 *
1177 * Free the DMA memory allocated for IOCTL handling purpose.
1178 *
1179 * Return: None
1180 */
mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1181 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1182 {
1183 struct dma_memory_desc *mem_desc;
1184 u16 i;
1185
1186 if (!mrioc->ioctl_dma_pool)
1187 return;
1188
1189 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1190 mem_desc = &mrioc->ioctl_sge[i];
1191 if (mem_desc->addr) {
1192 dma_pool_free(mrioc->ioctl_dma_pool,
1193 mem_desc->addr,
1194 mem_desc->dma_addr);
1195 mem_desc->addr = NULL;
1196 }
1197 }
1198 dma_pool_destroy(mrioc->ioctl_dma_pool);
1199 mrioc->ioctl_dma_pool = NULL;
1200 mem_desc = &mrioc->ioctl_chain_sge;
1201
1202 if (mem_desc->addr) {
1203 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1204 mem_desc->addr, mem_desc->dma_addr);
1205 mem_desc->addr = NULL;
1206 }
1207 mem_desc = &mrioc->ioctl_resp_sge;
1208 if (mem_desc->addr) {
1209 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
1210 mem_desc->addr, mem_desc->dma_addr);
1211 mem_desc->addr = NULL;
1212 }
1213
1214 mrioc->ioctl_sges_allocated = false;
1215 }
1216
1217 /**
1218 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma
1219 * @mrioc: Adapter instance reference
1220 *
1221 * This function allocates dmaable memory required to handle the
1222 * application issued MPI3 IOCTL requests.
1223 *
1224 * Return: None
1225 */
mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc * mrioc)1226 static void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_ioc *mrioc)
1227
1228 {
1229 struct dma_memory_desc *mem_desc;
1230 u16 i;
1231
1232 mrioc->ioctl_dma_pool = dma_pool_create("ioctl dma pool",
1233 &mrioc->pdev->dev,
1234 MPI3MR_IOCTL_SGE_SIZE,
1235 MPI3MR_PAGE_SIZE_4K, 0);
1236
1237 if (!mrioc->ioctl_dma_pool) {
1238 ioc_err(mrioc, "ioctl_dma_pool: dma_pool_create failed\n");
1239 goto out_failed;
1240 }
1241
1242 for (i = 0; i < MPI3MR_NUM_IOCTL_SGE; i++) {
1243 mem_desc = &mrioc->ioctl_sge[i];
1244 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE;
1245 mem_desc->addr = dma_pool_zalloc(mrioc->ioctl_dma_pool,
1246 GFP_KERNEL,
1247 &mem_desc->dma_addr);
1248 if (!mem_desc->addr)
1249 goto out_failed;
1250 }
1251
1252 mem_desc = &mrioc->ioctl_chain_sge;
1253 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1254 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1255 mem_desc->size,
1256 &mem_desc->dma_addr,
1257 GFP_KERNEL);
1258 if (!mem_desc->addr)
1259 goto out_failed;
1260
1261 mem_desc = &mrioc->ioctl_resp_sge;
1262 mem_desc->size = MPI3MR_PAGE_SIZE_4K;
1263 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
1264 mem_desc->size,
1265 &mem_desc->dma_addr,
1266 GFP_KERNEL);
1267 if (!mem_desc->addr)
1268 goto out_failed;
1269
1270 mrioc->ioctl_sges_allocated = true;
1271
1272 return;
1273 out_failed:
1274 ioc_warn(mrioc, "cannot allocate DMA memory for the mpt commands\n"
1275 "from the applications, application interface for MPT command is disabled\n");
1276 mpi3mr_free_ioctl_dma_memory(mrioc);
1277 }
1278
1279 /**
1280 * mpi3mr_fault_uevent_emit - Emit uevent for any controller
1281 * fault
1282 * @mrioc: Pointer to the mpi3mr_ioc structure for the controller instance
1283 *
1284 * This function is invoked when the controller undergoes any
1285 * type of fault.
1286 */
1287
mpi3mr_fault_uevent_emit(struct mpi3mr_ioc * mrioc)1288 static void mpi3mr_fault_uevent_emit(struct mpi3mr_ioc *mrioc)
1289 {
1290 struct kobj_uevent_env *env;
1291 unsigned int noio_flag;
1292 int ret;
1293
1294 noio_flag = memalloc_noio_save();
1295
1296 env = kzalloc_obj(*env);
1297 if (!env)
1298 goto out_restore;
1299
1300 ret = add_uevent_var(env, "DRIVER=%s", mrioc->driver_name);
1301 if (ret)
1302 goto out_free;
1303
1304 ret = add_uevent_var(env, "IOC_ID=%u", mrioc->id);
1305 if (ret)
1306 goto out_free;
1307
1308 ret = add_uevent_var(env, "FAULT_CODE=0x%08x",
1309 mrioc->saved_fault_code);
1310 if (ret)
1311 goto out_free;
1312
1313 ret = add_uevent_var(env, "FAULT_INFO0=0x%08x",
1314 mrioc->saved_fault_info[0]);
1315 if (ret)
1316 goto out_free;
1317
1318 ret = add_uevent_var(env, "FAULT_INFO1=0x%08x",
1319 mrioc->saved_fault_info[1]);
1320 if (ret)
1321 goto out_free;
1322
1323 ret = add_uevent_var(env, "FAULT_INFO2=0x%08x",
1324 mrioc->saved_fault_info[2]);
1325 if (ret)
1326 goto out_free;
1327
1328 kobject_uevent_env(&mrioc->shost->shost_gendev.kobj,
1329 KOBJ_CHANGE, env->envp);
1330
1331 out_free:
1332 kfree(env);
1333 out_restore:
1334 memalloc_noio_restore(noio_flag);
1335 }
1336
1337 /**
1338 * mpi3mr_clear_reset_history - clear reset history
1339 * @mrioc: Adapter instance reference
1340 *
1341 * Write the reset history bit in IOC status to clear the bit,
1342 * if it is already set.
1343 *
1344 * Return: Nothing.
1345 */
mpi3mr_clear_reset_history(struct mpi3mr_ioc * mrioc)1346 static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1347 {
1348 u32 ioc_status;
1349
1350 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1351 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1352 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1353 }
1354
1355 /**
1356 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1357 * @mrioc: Adapter instance reference
1358 * @reset_reason: Reset reason code
1359 *
1360 * Issue Message unit Reset to the controller and wait for it to
1361 * be complete.
1362 *
1363 * Return: 0 on success, -1 on failure.
1364 */
mpi3mr_issue_and_process_mur(struct mpi3mr_ioc * mrioc,u32 reset_reason)1365 static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1366 u32 reset_reason)
1367 {
1368 u32 ioc_config, timeout, ioc_status, scratch_pad0;
1369 int retval = -1;
1370
1371 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1372 if (mrioc->unrecoverable) {
1373 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1374 return retval;
1375 }
1376 mpi3mr_clear_reset_history(mrioc);
1377 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1378 MPI3MR_RESET_REASON_OSTYPE_SHIFT) |
1379 (mrioc->facts.ioc_num <<
1380 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1381 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1382 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1383 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1384 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1385
1386 timeout = MPI3MR_MUR_TIMEOUT * 10;
1387 do {
1388 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1389 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1390 mpi3mr_clear_reset_history(mrioc);
1391 break;
1392 }
1393 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1394 mpi3mr_print_fault_info(mrioc);
1395 break;
1396 }
1397 msleep(100);
1398 } while (--timeout);
1399
1400 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1401 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1402 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1403 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1404 retval = 0;
1405
1406 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%08x)/(0x%08x)\n",
1407 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1408 return retval;
1409 }
1410
1411 /**
1412 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1413 * during reset/resume
1414 * @mrioc: Adapter instance reference
1415 *
1416 * Return: zero if the new IOCFacts parameters value is compatible with
1417 * older values else return -EPERM
1418 */
1419 static int
mpi3mr_revalidate_factsdata(struct mpi3mr_ioc * mrioc)1420 mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1421 {
1422 unsigned long *removepend_bitmap;
1423
1424 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1425 ioc_err(mrioc,
1426 "cannot increase reply size from %d to %d\n",
1427 mrioc->reply_sz, mrioc->facts.reply_sz);
1428 return -EPERM;
1429 }
1430
1431 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1432 ioc_err(mrioc,
1433 "cannot reduce number of operational reply queues from %d to %d\n",
1434 mrioc->num_op_reply_q,
1435 mrioc->facts.max_op_reply_q);
1436 return -EPERM;
1437 }
1438
1439 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1440 ioc_err(mrioc,
1441 "cannot reduce number of operational request queues from %d to %d\n",
1442 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1443 return -EPERM;
1444 }
1445
1446 if (mrioc->shost->max_sectors != (mrioc->facts.max_data_length / 512))
1447 ioc_err(mrioc, "Warning: The maximum data transfer length\n"
1448 "\tchanged after reset: previous(%d), new(%d),\n"
1449 "the driver cannot change this at run time\n",
1450 mrioc->shost->max_sectors * 512, mrioc->facts.max_data_length);
1451
1452 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1453 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED))
1454 ioc_err(mrioc,
1455 "critical error: multipath capability is enabled at the\n"
1456 "\tcontroller while sas transport support is enabled at the\n"
1457 "\tdriver, please reboot the system or reload the driver\n");
1458
1459 if (mrioc->seg_tb_support) {
1460 if (!(mrioc->facts.ioc_capabilities &
1461 MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED)) {
1462 ioc_err(mrioc,
1463 "critical error: previously enabled segmented trace\n"
1464 " buffer capability is disabled after reset. Please\n"
1465 " update the firmware or reboot the system or\n"
1466 " reload the driver to enable trace diag buffer\n");
1467 mrioc->diag_buffers[0].disabled_after_reset = true;
1468 } else
1469 mrioc->diag_buffers[0].disabled_after_reset = false;
1470 }
1471
1472 if (mrioc->facts.max_devhandle > mrioc->dev_handle_bitmap_bits) {
1473 removepend_bitmap = bitmap_zalloc(mrioc->facts.max_devhandle,
1474 GFP_KERNEL);
1475 if (!removepend_bitmap) {
1476 ioc_err(mrioc,
1477 "failed to increase removepend_bitmap bits from %d to %d\n",
1478 mrioc->dev_handle_bitmap_bits,
1479 mrioc->facts.max_devhandle);
1480 return -EPERM;
1481 }
1482 bitmap_free(mrioc->removepend_bitmap);
1483 mrioc->removepend_bitmap = removepend_bitmap;
1484 ioc_info(mrioc,
1485 "increased bits of dev_handle_bitmap from %d to %d\n",
1486 mrioc->dev_handle_bitmap_bits,
1487 mrioc->facts.max_devhandle);
1488 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
1489 }
1490
1491 return 0;
1492 }
1493
1494 /**
1495 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1496 * @mrioc: Adapter instance reference
1497 *
1498 * Set Enable IOC bit in IOC configuration register and wait for
1499 * the controller to become ready.
1500 *
1501 * Return: 0 on success, appropriate error on failure.
1502 */
mpi3mr_bring_ioc_ready(struct mpi3mr_ioc * mrioc)1503 static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1504 {
1505 u32 ioc_config, ioc_status, timeout, host_diagnostic;
1506 int retval = 0;
1507 enum mpi3mr_iocstate ioc_state;
1508 u64 base_info;
1509 u8 retry = 0;
1510 u64 start_time, elapsed_time_sec;
1511
1512 retry_bring_ioc_ready:
1513
1514 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1515 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1516 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1517 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1518 ioc_status, ioc_config, base_info);
1519
1520 if (!mpi3mr_is_fault_recoverable(mrioc)) {
1521 mrioc->unrecoverable = 1;
1522 goto out_device_not_present;
1523 }
1524
1525 /*The timeout value is in 2sec unit, changing it to seconds*/
1526 mrioc->ready_timeout =
1527 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1528 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1529
1530 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1531
1532 ioc_state = mpi3mr_get_iocstate(mrioc);
1533 ioc_info(mrioc, "controller is in %s state during detection\n",
1534 mpi3mr_iocstate_name(ioc_state));
1535
1536 timeout = mrioc->ready_timeout * 10;
1537
1538 do {
1539 ioc_state = mpi3mr_get_iocstate(mrioc);
1540
1541 if (ioc_state != MRIOC_STATE_BECOMING_READY &&
1542 ioc_state != MRIOC_STATE_RESET_REQUESTED)
1543 break;
1544
1545 if (!pci_device_is_present(mrioc->pdev)) {
1546 mrioc->unrecoverable = 1;
1547 ioc_err(mrioc, "controller is not present while waiting to reset\n");
1548 goto out_device_not_present;
1549 }
1550
1551 msleep(100);
1552 } while (--timeout);
1553
1554 if (ioc_state == MRIOC_STATE_READY) {
1555 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1556 retval = mpi3mr_issue_and_process_mur(mrioc,
1557 MPI3MR_RESET_FROM_BRINGUP);
1558 ioc_state = mpi3mr_get_iocstate(mrioc);
1559 if (retval)
1560 ioc_err(mrioc,
1561 "message unit reset failed with error %d current state %s\n",
1562 retval, mpi3mr_iocstate_name(ioc_state));
1563 }
1564 if (ioc_state != MRIOC_STATE_RESET) {
1565 if (ioc_state == MRIOC_STATE_FAULT) {
1566 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
1567 mpi3mr_print_fault_info(mrioc);
1568 mpi3mr_save_fault_info(mrioc);
1569 mrioc->fault_during_init = 1;
1570 mrioc->fwfault_counter++;
1571
1572 do {
1573 host_diagnostic =
1574 readl(&mrioc->sysif_regs->host_diagnostic);
1575 if (!(host_diagnostic &
1576 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
1577 break;
1578 if (!pci_device_is_present(mrioc->pdev)) {
1579 mrioc->unrecoverable = 1;
1580 ioc_err(mrioc, "controller is not present at the bringup\n");
1581 goto out_device_not_present;
1582 }
1583 msleep(100);
1584 } while (--timeout);
1585 }
1586 mpi3mr_print_fault_info(mrioc);
1587 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1588 retval = mpi3mr_issue_reset(mrioc,
1589 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1590 MPI3MR_RESET_FROM_BRINGUP);
1591 if (retval) {
1592 ioc_err(mrioc,
1593 "soft reset failed with error %d\n", retval);
1594 goto out_failed;
1595 }
1596 }
1597 ioc_state = mpi3mr_get_iocstate(mrioc);
1598 if (ioc_state != MRIOC_STATE_RESET) {
1599 ioc_err(mrioc,
1600 "cannot bring controller to reset state, current state: %s\n",
1601 mpi3mr_iocstate_name(ioc_state));
1602 goto out_failed;
1603 }
1604 mpi3mr_clear_reset_history(mrioc);
1605 retval = mpi3mr_setup_admin_qpair(mrioc);
1606 if (retval) {
1607 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1608 retval);
1609 goto out_failed;
1610 }
1611
1612 ioc_info(mrioc, "bringing controller to ready state\n");
1613 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1614 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1615 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1616
1617 if (retry == 0)
1618 start_time = jiffies;
1619
1620 timeout = mrioc->ready_timeout * 10;
1621 do {
1622 ioc_state = mpi3mr_get_iocstate(mrioc);
1623 if (ioc_state == MRIOC_STATE_READY) {
1624 ioc_info(mrioc,
1625 "successfully transitioned to %s state\n",
1626 mpi3mr_iocstate_name(ioc_state));
1627 mpi3mr_clear_reset_history(mrioc);
1628 return 0;
1629 }
1630 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1631 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
1632 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
1633 mpi3mr_print_fault_info(mrioc);
1634 goto out_failed;
1635 }
1636 if (!pci_device_is_present(mrioc->pdev)) {
1637 mrioc->unrecoverable = 1;
1638 ioc_err(mrioc,
1639 "controller is not present at the bringup\n");
1640 retval = -1;
1641 goto out_device_not_present;
1642 }
1643 msleep(100);
1644 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1645 } while (elapsed_time_sec < mrioc->ready_timeout);
1646
1647 ioc_state = mpi3mr_get_iocstate(mrioc);
1648 if (ioc_state == MRIOC_STATE_READY) {
1649 ioc_info(mrioc,
1650 "successfully transitioned to %s state after %llu seconds\n",
1651 mpi3mr_iocstate_name(ioc_state), elapsed_time_sec);
1652 mpi3mr_clear_reset_history(mrioc);
1653 return 0;
1654 }
1655
1656 out_failed:
1657 elapsed_time_sec = jiffies_to_msecs(jiffies - start_time)/1000;
1658 if ((retry < 2) && (elapsed_time_sec < (mrioc->ready_timeout - 60))) {
1659 retry++;
1660
1661 ioc_warn(mrioc, "retrying to bring IOC ready, retry_count:%d\n"
1662 " elapsed time =%llu\n", retry, elapsed_time_sec);
1663
1664 goto retry_bring_ioc_ready;
1665 }
1666 ioc_state = mpi3mr_get_iocstate(mrioc);
1667 ioc_err(mrioc,
1668 "failed to bring to ready state, current state: %s\n",
1669 mpi3mr_iocstate_name(ioc_state));
1670 out_device_not_present:
1671 return retval;
1672 }
1673
1674 /**
1675 * mpi3mr_soft_reset_success - Check softreset is success or not
1676 * @ioc_status: IOC status register value
1677 * @ioc_config: IOC config register value
1678 *
1679 * Check whether the soft reset is successful or not based on
1680 * IOC status and IOC config register values.
1681 *
1682 * Return: True when the soft reset is success, false otherwise.
1683 */
1684 static inline bool
mpi3mr_soft_reset_success(u32 ioc_status,u32 ioc_config)1685 mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1686 {
1687 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1688 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1689 return true;
1690 return false;
1691 }
1692
1693 /**
1694 * mpi3mr_diagfault_success - Check diag fault is success or not
1695 * @mrioc: Adapter reference
1696 * @ioc_status: IOC status register value
1697 *
1698 * Check whether the controller hit diag reset fault code.
1699 *
1700 * Return: True when there is diag fault, false otherwise.
1701 */
mpi3mr_diagfault_success(struct mpi3mr_ioc * mrioc,u32 ioc_status)1702 static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1703 u32 ioc_status)
1704 {
1705 u32 fault;
1706
1707 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1708 return false;
1709 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1710 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1711 mpi3mr_print_fault_info(mrioc);
1712 return true;
1713 }
1714 return false;
1715 }
1716
1717 /**
1718 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1719 * @mrioc: Adapter reference
1720 *
1721 * Set diag save bit in IOC configuration register to enable
1722 * snapdump.
1723 *
1724 * Return: Nothing.
1725 */
mpi3mr_set_diagsave(struct mpi3mr_ioc * mrioc)1726 static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1727 {
1728 u32 ioc_config;
1729
1730 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1731 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1732 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1733 }
1734
1735 /**
1736 * mpi3mr_issue_reset - Issue reset to the controller
1737 * @mrioc: Adapter reference
1738 * @reset_type: Reset type
1739 * @reset_reason: Reset reason code
1740 *
1741 * Unlock the host diagnostic registers and write the specific
1742 * reset type to that, wait for reset acknowledgment from the
1743 * controller, if the reset is not successful retry for the
1744 * predefined number of times.
1745 *
1746 * Return: 0 on success, non-zero on failure.
1747 */
mpi3mr_issue_reset(struct mpi3mr_ioc * mrioc,u16 reset_type,u16 reset_reason)1748 static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1749 u16 reset_reason)
1750 {
1751 int retval = -1;
1752 u8 unlock_retry_count = 0;
1753 u32 host_diagnostic, ioc_status, ioc_config, scratch_pad0;
1754 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1755
1756 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1757 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1758 return retval;
1759 if (mrioc->unrecoverable)
1760 return retval;
1761 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1762 retval = 0;
1763 return retval;
1764 }
1765
1766 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1767 mpi3mr_reset_type_name(reset_type),
1768 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1769
1770 mpi3mr_clear_reset_history(mrioc);
1771 do {
1772 ioc_info(mrioc,
1773 "Write magic sequence to unlock host diag register (retry=%d)\n",
1774 ++unlock_retry_count);
1775 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1776 ioc_err(mrioc,
1777 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1778 mpi3mr_reset_type_name(reset_type),
1779 host_diagnostic);
1780 mrioc->unrecoverable = 1;
1781 return retval;
1782 }
1783
1784 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1785 &mrioc->sysif_regs->write_sequence);
1786 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1787 &mrioc->sysif_regs->write_sequence);
1788 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1789 &mrioc->sysif_regs->write_sequence);
1790 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1791 &mrioc->sysif_regs->write_sequence);
1792 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1793 &mrioc->sysif_regs->write_sequence);
1794 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1795 &mrioc->sysif_regs->write_sequence);
1796 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1797 &mrioc->sysif_regs->write_sequence);
1798 usleep_range(1000, 1100);
1799 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1800 ioc_info(mrioc,
1801 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1802 unlock_retry_count, host_diagnostic);
1803 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1804
1805 scratch_pad0 = ((MPI3MR_RESET_REASON_OSTYPE_LINUX <<
1806 MPI3MR_RESET_REASON_OSTYPE_SHIFT) | (mrioc->facts.ioc_num <<
1807 MPI3MR_RESET_REASON_IOCNUM_SHIFT) | reset_reason);
1808 writel(scratch_pad0, &mrioc->sysif_regs->scratchpad[0]);
1809 if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)
1810 mpi3mr_set_diagsave(mrioc);
1811 writel(host_diagnostic | reset_type,
1812 &mrioc->sysif_regs->host_diagnostic);
1813 switch (reset_type) {
1814 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1815 do {
1816 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1817 ioc_config =
1818 readl(&mrioc->sysif_regs->ioc_configuration);
1819 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1820 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1821 ) {
1822 mpi3mr_clear_reset_history(mrioc);
1823 retval = 0;
1824 break;
1825 }
1826 msleep(100);
1827 } while (--timeout);
1828 mpi3mr_print_fault_info(mrioc);
1829 break;
1830 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1831 do {
1832 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1833 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1834 retval = 0;
1835 break;
1836 }
1837 msleep(100);
1838 } while (--timeout);
1839 break;
1840 default:
1841 break;
1842 }
1843
1844 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1845 &mrioc->sysif_regs->write_sequence);
1846
1847 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1848 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1849 ioc_info(mrioc,
1850 "ioc_status/ioc_config after %s reset is (0x%08x)/(0x%08x)\n",
1851 (!retval)?"successful":"failed", ioc_status,
1852 ioc_config);
1853 if (retval)
1854 mrioc->unrecoverable = 1;
1855 return retval;
1856 }
1857
1858 /**
1859 * mpi3mr_admin_request_post - Post request to admin queue
1860 * @mrioc: Adapter reference
1861 * @admin_req: MPI3 request
1862 * @admin_req_sz: Request size
1863 * @ignore_reset: Ignore reset in process
1864 *
1865 * Post the MPI3 request into admin request queue and
1866 * inform the controller, if the queue is full return
1867 * appropriate error.
1868 *
1869 * Return: 0 on success, non-zero on failure.
1870 */
mpi3mr_admin_request_post(struct mpi3mr_ioc * mrioc,void * admin_req,u16 admin_req_sz,u8 ignore_reset)1871 int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1872 u16 admin_req_sz, u8 ignore_reset)
1873 {
1874 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1875 int retval = 0;
1876 unsigned long flags;
1877 u8 *areq_entry;
1878
1879 if (mrioc->unrecoverable) {
1880 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1881 return -EFAULT;
1882 }
1883
1884 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1885 areq_pi = mrioc->admin_req_pi;
1886 areq_ci = mrioc->admin_req_ci;
1887 max_entries = mrioc->num_admin_req;
1888 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1889 (areq_pi == (max_entries - 1)))) {
1890 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1891 retval = -EAGAIN;
1892 goto out;
1893 }
1894 if (!ignore_reset && mrioc->reset_in_progress) {
1895 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1896 retval = -EAGAIN;
1897 goto out;
1898 }
1899 if (mrioc->pci_err_recovery) {
1900 ioc_err(mrioc, "admin request queue submission failed due to pci error recovery in progress\n");
1901 retval = -EAGAIN;
1902 goto out;
1903 }
1904
1905 areq_entry = (u8 *)mrioc->admin_req_base +
1906 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1907 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1908 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1909
1910 if (++areq_pi == max_entries)
1911 areq_pi = 0;
1912 mrioc->admin_req_pi = areq_pi;
1913
1914 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1915
1916 out:
1917 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1918
1919 return retval;
1920 }
1921
1922 /**
1923 * mpi3mr_free_op_req_q_segments - free request memory segments
1924 * @mrioc: Adapter instance reference
1925 * @q_idx: operational request queue index
1926 *
1927 * Free memory segments allocated for operational request queue
1928 *
1929 * Return: Nothing.
1930 */
mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1931 static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1932 {
1933 u16 j;
1934 int size;
1935 struct segments *segments;
1936
1937 segments = mrioc->req_qinfo[q_idx].q_segments;
1938 if (!segments)
1939 return;
1940
1941 if (mrioc->enable_segqueue) {
1942 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1943 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1944 dma_free_coherent(&mrioc->pdev->dev,
1945 MPI3MR_MAX_SEG_LIST_SIZE,
1946 mrioc->req_qinfo[q_idx].q_segment_list,
1947 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1948 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1949 }
1950 } else
1951 size = mrioc->req_qinfo[q_idx].segment_qd *
1952 mrioc->facts.op_req_sz;
1953
1954 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1955 if (!segments[j].segment)
1956 continue;
1957 dma_free_coherent(&mrioc->pdev->dev,
1958 size, segments[j].segment, segments[j].segment_dma);
1959 segments[j].segment = NULL;
1960 }
1961 kfree(mrioc->req_qinfo[q_idx].q_segments);
1962 mrioc->req_qinfo[q_idx].q_segments = NULL;
1963 mrioc->req_qinfo[q_idx].qid = 0;
1964 }
1965
1966 /**
1967 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1968 * @mrioc: Adapter instance reference
1969 * @q_idx: operational reply queue index
1970 *
1971 * Free memory segments allocated for operational reply queue
1972 *
1973 * Return: Nothing.
1974 */
mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 q_idx)1975 static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1976 {
1977 u16 j;
1978 int size;
1979 struct segments *segments;
1980
1981 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1982 if (!segments)
1983 return;
1984
1985 if (mrioc->enable_segqueue) {
1986 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1987 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1988 dma_free_coherent(&mrioc->pdev->dev,
1989 MPI3MR_MAX_SEG_LIST_SIZE,
1990 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1991 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1992 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1993 }
1994 } else
1995 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1996 mrioc->op_reply_desc_sz;
1997
1998 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1999 if (!segments[j].segment)
2000 continue;
2001 dma_free_coherent(&mrioc->pdev->dev,
2002 size, segments[j].segment, segments[j].segment_dma);
2003 segments[j].segment = NULL;
2004 }
2005
2006 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
2007 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
2008 mrioc->op_reply_qinfo[q_idx].qid = 0;
2009 }
2010
2011 /**
2012 * mpi3mr_delete_op_reply_q - delete operational reply queue
2013 * @mrioc: Adapter instance reference
2014 * @qidx: operational reply queue index
2015 *
2016 * Delete operatinal reply queue by issuing MPI request
2017 * through admin queue.
2018 *
2019 * Return: 0 on success, non-zero on failure.
2020 */
mpi3mr_delete_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)2021 static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2022 {
2023 struct mpi3_delete_reply_queue_request delq_req;
2024 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2025 int retval = 0;
2026 u16 reply_qid = 0, midx;
2027
2028 reply_qid = op_reply_q->qid;
2029
2030 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2031
2032 if (!reply_qid) {
2033 retval = -1;
2034 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
2035 goto out;
2036 }
2037
2038 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
2039 mrioc->active_poll_qcount--;
2040
2041 memset(&delq_req, 0, sizeof(delq_req));
2042 mutex_lock(&mrioc->init_cmds.mutex);
2043 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2044 retval = -1;
2045 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
2046 mutex_unlock(&mrioc->init_cmds.mutex);
2047 goto out;
2048 }
2049 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2050 mrioc->init_cmds.is_waiting = 1;
2051 mrioc->init_cmds.callback = NULL;
2052 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2053 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
2054 delq_req.queue_id = cpu_to_le16(reply_qid);
2055
2056 init_completion(&mrioc->init_cmds.done);
2057 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
2058 1);
2059 if (retval) {
2060 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
2061 goto out_unlock;
2062 }
2063 wait_for_completion_timeout(&mrioc->init_cmds.done,
2064 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2065 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2066 ioc_err(mrioc, "delete reply queue timed out\n");
2067 mpi3mr_check_rh_fault_ioc(mrioc,
2068 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
2069 retval = -1;
2070 goto out_unlock;
2071 }
2072 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2073 != MPI3_IOCSTATUS_SUCCESS) {
2074 ioc_err(mrioc,
2075 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2076 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2077 mrioc->init_cmds.ioc_loginfo);
2078 retval = -1;
2079 goto out_unlock;
2080 }
2081 mrioc->intr_info[midx].op_reply_q = NULL;
2082
2083 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2084 out_unlock:
2085 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2086 mutex_unlock(&mrioc->init_cmds.mutex);
2087 out:
2088
2089 return retval;
2090 }
2091
2092 /**
2093 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
2094 * @mrioc: Adapter instance reference
2095 * @qidx: request queue index
2096 *
2097 * Allocate segmented memory pools for operational reply
2098 * queue.
2099 *
2100 * Return: 0 on success, non-zero on failure.
2101 */
mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)2102 static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2103 {
2104 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2105 int i, size;
2106 u64 *q_segment_list_entry = NULL;
2107 struct segments *segments;
2108
2109 if (mrioc->enable_segqueue) {
2110 op_reply_q->segment_qd =
2111 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
2112
2113 size = MPI3MR_OP_REP_Q_SEG_SIZE;
2114
2115 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2116 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
2117 GFP_KERNEL);
2118 if (!op_reply_q->q_segment_list)
2119 return -ENOMEM;
2120 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
2121 } else {
2122 op_reply_q->segment_qd = op_reply_q->num_replies;
2123 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
2124 }
2125
2126 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
2127 op_reply_q->segment_qd);
2128
2129 op_reply_q->q_segments = kzalloc_objs(struct segments,
2130 op_reply_q->num_segments);
2131 if (!op_reply_q->q_segments)
2132 return -ENOMEM;
2133
2134 segments = op_reply_q->q_segments;
2135 for (i = 0; i < op_reply_q->num_segments; i++) {
2136 segments[i].segment =
2137 dma_alloc_coherent(&mrioc->pdev->dev,
2138 size, &segments[i].segment_dma, GFP_KERNEL);
2139 if (!segments[i].segment)
2140 return -ENOMEM;
2141 if (mrioc->enable_segqueue)
2142 q_segment_list_entry[i] =
2143 (unsigned long)segments[i].segment_dma;
2144 }
2145
2146 return 0;
2147 }
2148
2149 /**
2150 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
2151 * @mrioc: Adapter instance reference
2152 * @qidx: request queue index
2153 *
2154 * Allocate segmented memory pools for operational request
2155 * queue.
2156 *
2157 * Return: 0 on success, non-zero on failure.
2158 */
mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc * mrioc,u16 qidx)2159 static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
2160 {
2161 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
2162 int i, size;
2163 u64 *q_segment_list_entry = NULL;
2164 struct segments *segments;
2165
2166 if (mrioc->enable_segqueue) {
2167 op_req_q->segment_qd =
2168 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
2169
2170 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
2171
2172 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
2173 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
2174 GFP_KERNEL);
2175 if (!op_req_q->q_segment_list)
2176 return -ENOMEM;
2177 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
2178
2179 } else {
2180 op_req_q->segment_qd = op_req_q->num_requests;
2181 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
2182 }
2183
2184 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
2185 op_req_q->segment_qd);
2186
2187 op_req_q->q_segments = kzalloc_objs(struct segments,
2188 op_req_q->num_segments);
2189 if (!op_req_q->q_segments)
2190 return -ENOMEM;
2191
2192 segments = op_req_q->q_segments;
2193 for (i = 0; i < op_req_q->num_segments; i++) {
2194 segments[i].segment =
2195 dma_alloc_coherent(&mrioc->pdev->dev,
2196 size, &segments[i].segment_dma, GFP_KERNEL);
2197 if (!segments[i].segment)
2198 return -ENOMEM;
2199 if (mrioc->enable_segqueue)
2200 q_segment_list_entry[i] =
2201 (unsigned long)segments[i].segment_dma;
2202 }
2203
2204 return 0;
2205 }
2206
2207 /**
2208 * mpi3mr_create_op_reply_q - create operational reply queue
2209 * @mrioc: Adapter instance reference
2210 * @qidx: operational reply queue index
2211 *
2212 * Create operatinal reply queue by issuing MPI request
2213 * through admin queue.
2214 *
2215 * Return: 0 on success, non-zero on failure.
2216 */
mpi3mr_create_op_reply_q(struct mpi3mr_ioc * mrioc,u16 qidx)2217 static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
2218 {
2219 struct mpi3_create_reply_queue_request create_req;
2220 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
2221 int retval = 0;
2222 u16 reply_qid = 0, midx;
2223
2224 reply_qid = op_reply_q->qid;
2225
2226 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
2227
2228 if (reply_qid) {
2229 retval = -1;
2230 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
2231 reply_qid);
2232
2233 return retval;
2234 }
2235
2236 reply_qid = qidx + 1;
2237
2238 if (mrioc->pdev->device == MPI3_MFGPAGE_DEVID_SAS4116) {
2239 if (mrioc->pdev->revision)
2240 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
2241 else
2242 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
2243 } else
2244 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD2K;
2245
2246 op_reply_q->ci = 0;
2247 op_reply_q->ephase = 1;
2248 atomic_set(&op_reply_q->pend_ios, 0);
2249 atomic_set(&op_reply_q->in_use, 0);
2250 op_reply_q->enable_irq_poll = false;
2251 op_reply_q->qfull_watermark =
2252 op_reply_q->num_replies - (MPI3MR_THRESHOLD_REPLY_COUNT * 2);
2253
2254 if (!op_reply_q->q_segments) {
2255 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
2256 if (retval) {
2257 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
2258 goto out;
2259 }
2260 }
2261
2262 memset(&create_req, 0, sizeof(create_req));
2263 mutex_lock(&mrioc->init_cmds.mutex);
2264 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2265 retval = -1;
2266 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
2267 goto out_unlock;
2268 }
2269 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2270 mrioc->init_cmds.is_waiting = 1;
2271 mrioc->init_cmds.callback = NULL;
2272 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2273 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
2274 create_req.queue_id = cpu_to_le16(reply_qid);
2275
2276 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
2277 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
2278 else
2279 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
2280
2281 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
2282 create_req.flags =
2283 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
2284 create_req.msix_index =
2285 cpu_to_le16(mrioc->intr_info[midx].msix_index);
2286 } else {
2287 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
2288 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
2289 reply_qid, midx);
2290 if (!mrioc->active_poll_qcount)
2291 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
2292 mrioc->intr_info_count - 1));
2293 }
2294
2295 if (mrioc->enable_segqueue) {
2296 create_req.flags |=
2297 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2298 create_req.base_address = cpu_to_le64(
2299 op_reply_q->q_segment_list_dma);
2300 } else
2301 create_req.base_address = cpu_to_le64(
2302 op_reply_q->q_segments[0].segment_dma);
2303
2304 create_req.size = cpu_to_le16(op_reply_q->num_replies);
2305
2306 init_completion(&mrioc->init_cmds.done);
2307 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2308 sizeof(create_req), 1);
2309 if (retval) {
2310 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
2311 goto out_unlock;
2312 }
2313 wait_for_completion_timeout(&mrioc->init_cmds.done,
2314 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2315 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2316 ioc_err(mrioc, "create reply queue timed out\n");
2317 mpi3mr_check_rh_fault_ioc(mrioc,
2318 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
2319 retval = -1;
2320 goto out_unlock;
2321 }
2322 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2323 != MPI3_IOCSTATUS_SUCCESS) {
2324 ioc_err(mrioc,
2325 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2326 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2327 mrioc->init_cmds.ioc_loginfo);
2328 retval = -1;
2329 goto out_unlock;
2330 }
2331 op_reply_q->qid = reply_qid;
2332 if (midx < mrioc->intr_info_count)
2333 mrioc->intr_info[midx].op_reply_q = op_reply_q;
2334
2335 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
2336 mrioc->active_poll_qcount++;
2337
2338 out_unlock:
2339 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2340 mutex_unlock(&mrioc->init_cmds.mutex);
2341 out:
2342
2343 return retval;
2344 }
2345
2346 /**
2347 * mpi3mr_create_op_req_q - create operational request queue
2348 * @mrioc: Adapter instance reference
2349 * @idx: operational request queue index
2350 * @reply_qid: Reply queue ID
2351 *
2352 * Create operatinal request queue by issuing MPI request
2353 * through admin queue.
2354 *
2355 * Return: 0 on success, non-zero on failure.
2356 */
mpi3mr_create_op_req_q(struct mpi3mr_ioc * mrioc,u16 idx,u16 reply_qid)2357 static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
2358 u16 reply_qid)
2359 {
2360 struct mpi3_create_request_queue_request create_req;
2361 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
2362 int retval = 0;
2363 u16 req_qid = 0;
2364
2365 req_qid = op_req_q->qid;
2366
2367 if (req_qid) {
2368 retval = -1;
2369 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
2370 req_qid);
2371
2372 return retval;
2373 }
2374 req_qid = idx + 1;
2375
2376 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
2377 op_req_q->ci = 0;
2378 op_req_q->pi = 0;
2379 op_req_q->reply_qid = reply_qid;
2380 op_req_q->last_full_host_tag = MPI3MR_HOSTTAG_INVALID;
2381 op_req_q->qfull_io_count = 0;
2382 op_req_q->qfull_instances = 0;
2383 spin_lock_init(&op_req_q->q_lock);
2384
2385 if (!op_req_q->q_segments) {
2386 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2387 if (retval) {
2388 mpi3mr_free_op_req_q_segments(mrioc, idx);
2389 goto out;
2390 }
2391 }
2392
2393 memset(&create_req, 0, sizeof(create_req));
2394 mutex_lock(&mrioc->init_cmds.mutex);
2395 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2396 retval = -1;
2397 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2398 goto out_unlock;
2399 }
2400 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2401 mrioc->init_cmds.is_waiting = 1;
2402 mrioc->init_cmds.callback = NULL;
2403 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2404 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2405 create_req.queue_id = cpu_to_le16(req_qid);
2406 if (mrioc->enable_segqueue) {
2407 create_req.flags =
2408 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2409 create_req.base_address = cpu_to_le64(
2410 op_req_q->q_segment_list_dma);
2411 } else
2412 create_req.base_address = cpu_to_le64(
2413 op_req_q->q_segments[0].segment_dma);
2414 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2415 create_req.size = cpu_to_le16(op_req_q->num_requests);
2416
2417 init_completion(&mrioc->init_cmds.done);
2418 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2419 sizeof(create_req), 1);
2420 if (retval) {
2421 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2422 goto out_unlock;
2423 }
2424 wait_for_completion_timeout(&mrioc->init_cmds.done,
2425 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2426 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2427 ioc_err(mrioc, "create request queue timed out\n");
2428 mpi3mr_check_rh_fault_ioc(mrioc,
2429 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2430 retval = -1;
2431 goto out_unlock;
2432 }
2433 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2434 != MPI3_IOCSTATUS_SUCCESS) {
2435 ioc_err(mrioc,
2436 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2437 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2438 mrioc->init_cmds.ioc_loginfo);
2439 retval = -1;
2440 goto out_unlock;
2441 }
2442 op_req_q->qid = req_qid;
2443
2444 out_unlock:
2445 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2446 mutex_unlock(&mrioc->init_cmds.mutex);
2447 out:
2448
2449 return retval;
2450 }
2451
2452 /**
2453 * mpi3mr_create_op_queues - create operational queue pairs
2454 * @mrioc: Adapter instance reference
2455 *
2456 * Allocate memory for operational queue meta data and call
2457 * create request and reply queue functions.
2458 *
2459 * Return: 0 on success, non-zero on failures.
2460 */
mpi3mr_create_op_queues(struct mpi3mr_ioc * mrioc)2461 static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2462 {
2463 int retval = 0;
2464 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2465 u32 ioc_status;
2466 enum mpi3mr_iocstate ioc_state;
2467
2468 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2469 mrioc->facts.max_op_req_q);
2470
2471 msix_count_op_q =
2472 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2473 if (!mrioc->num_queues)
2474 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2475 /*
2476 * During reset set the num_queues to the number of queues
2477 * that was set before the reset.
2478 */
2479 num_queues = mrioc->num_op_reply_q ?
2480 mrioc->num_op_reply_q : mrioc->num_queues;
2481 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2482 num_queues);
2483
2484 if (!mrioc->req_qinfo) {
2485 mrioc->req_qinfo = kzalloc_objs(struct op_req_qinfo, num_queues);
2486 if (!mrioc->req_qinfo) {
2487 retval = -1;
2488 goto out_failed;
2489 }
2490
2491 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2492 num_queues, GFP_KERNEL);
2493 if (!mrioc->op_reply_qinfo) {
2494 retval = -1;
2495 goto out_failed;
2496 }
2497 }
2498
2499 if (mrioc->enable_segqueue)
2500 ioc_info(mrioc,
2501 "allocating operational queues through segmented queues\n");
2502
2503 for (i = 0; i < num_queues; i++) {
2504 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2505 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2506 break;
2507 }
2508 if (mpi3mr_create_op_req_q(mrioc, i,
2509 mrioc->op_reply_qinfo[i].qid)) {
2510 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2511 mpi3mr_delete_op_reply_q(mrioc, i);
2512 break;
2513 }
2514 }
2515
2516 if (i == 0) {
2517 /* Not even one queue is created successfully*/
2518 retval = -1;
2519 goto out_failed;
2520 }
2521 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2522 ioc_state = mpi3mr_get_iocstate(mrioc);
2523 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2524 ioc_state != MRIOC_STATE_READY) {
2525 mpi3mr_print_fault_info(mrioc);
2526 retval = -1;
2527 goto out_failed;
2528 }
2529 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2530 ioc_info(mrioc,
2531 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2532 mrioc->num_op_reply_q, mrioc->default_qcount,
2533 mrioc->active_poll_qcount);
2534
2535 return retval;
2536 out_failed:
2537 kfree(mrioc->req_qinfo);
2538 mrioc->req_qinfo = NULL;
2539
2540 kfree(mrioc->op_reply_qinfo);
2541 mrioc->op_reply_qinfo = NULL;
2542
2543 return retval;
2544 }
2545
2546 /**
2547 * mpi3mr_op_request_post - Post request to operational queue
2548 * @mrioc: Adapter reference
2549 * @op_req_q: Operational request queue info
2550 * @req: MPI3 request
2551 *
2552 * Post the MPI3 request into operational request queue and
2553 * inform the controller, if the queue is full return
2554 * appropriate error.
2555 *
2556 * Return: 0 on success, non-zero on failure.
2557 */
mpi3mr_op_request_post(struct mpi3mr_ioc * mrioc,struct op_req_qinfo * op_req_q,u8 * req)2558 int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2559 struct op_req_qinfo *op_req_q, u8 *req)
2560 {
2561 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2562 int retval = 0;
2563 unsigned long flags;
2564 u8 *req_entry;
2565 void *segment_base_addr;
2566 u16 req_sz = mrioc->facts.op_req_sz;
2567 struct segments *segments = op_req_q->q_segments;
2568 struct op_reply_qinfo *op_reply_q = NULL;
2569 struct mpi3_scsi_io_request *scsiio_req =
2570 (struct mpi3_scsi_io_request *)req;
2571
2572 reply_qidx = op_req_q->reply_qid - 1;
2573 op_reply_q = mrioc->op_reply_qinfo + reply_qidx;
2574
2575 if (mrioc->unrecoverable)
2576 return -EFAULT;
2577
2578 spin_lock_irqsave(&op_req_q->q_lock, flags);
2579 pi = op_req_q->pi;
2580 max_entries = op_req_q->num_requests;
2581
2582 if (mpi3mr_check_req_qfull(op_req_q)) {
2583 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2584 reply_qidx, mrioc->op_reply_q_offset);
2585 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2586
2587 if (mpi3mr_check_req_qfull(op_req_q)) {
2588
2589 if (op_req_q->last_full_host_tag ==
2590 MPI3MR_HOSTTAG_INVALID)
2591 op_req_q->qfull_instances++;
2592
2593 op_req_q->last_full_host_tag = scsiio_req->host_tag;
2594 op_req_q->qfull_io_count++;
2595 retval = -EAGAIN;
2596 goto out;
2597 }
2598 }
2599
2600 if (op_req_q->last_full_host_tag != MPI3MR_HOSTTAG_INVALID)
2601 op_req_q->last_full_host_tag = MPI3MR_HOSTTAG_INVALID;
2602
2603 if (mrioc->reset_in_progress) {
2604 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2605 retval = -EAGAIN;
2606 goto out;
2607 }
2608 if (mrioc->pci_err_recovery) {
2609 ioc_err(mrioc, "operational request queue submission failed due to pci error recovery in progress\n");
2610 retval = -EAGAIN;
2611 goto out;
2612 }
2613
2614 /* Reply queue is nearing to get full, push back IOs to SML */
2615 if ((mrioc->prevent_reply_qfull == true) &&
2616 (atomic_read(&op_reply_q->pend_ios) >
2617 (op_reply_q->qfull_watermark))) {
2618 atomic_inc(&mrioc->reply_qfull_count);
2619 retval = -EAGAIN;
2620 goto out;
2621 }
2622
2623 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2624 req_entry = (u8 *)segment_base_addr +
2625 ((pi % op_req_q->segment_qd) * req_sz);
2626
2627 memset(req_entry, 0, req_sz);
2628 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2629
2630 if (++pi == max_entries)
2631 pi = 0;
2632 op_req_q->pi = pi;
2633
2634 #ifndef CONFIG_PREEMPT_RT
2635 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2636 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2637 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2638 #else
2639 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2640 #endif
2641
2642 writel(op_req_q->pi,
2643 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2644
2645 out:
2646 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2647 return retval;
2648 }
2649
2650 /**
2651 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2652 * controller
2653 * @mrioc: Adapter instance reference
2654 * @reason_code: reason code for the fault.
2655 *
2656 * This routine will save snapdump and fault the controller with
2657 * the given reason code if it is not already in the fault or
2658 * not asynchronosuly reset. This will be used to handle
2659 * initilaization time faults/resets/timeout as in those cases
2660 * immediate soft reset invocation is not required.
2661 *
2662 * Return: None.
2663 */
mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc * mrioc,u32 reason_code)2664 void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2665 {
2666 u32 ioc_status, host_diagnostic, timeout;
2667 union mpi3mr_trigger_data trigger_data;
2668
2669 if (mrioc->unrecoverable) {
2670 ioc_err(mrioc, "controller is unrecoverable\n");
2671 return;
2672 }
2673
2674 if (!pci_device_is_present(mrioc->pdev)) {
2675 mrioc->unrecoverable = 1;
2676 ioc_err(mrioc, "controller is not present\n");
2677 return;
2678 }
2679 memset(&trigger_data, 0, sizeof(trigger_data));
2680 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2681
2682 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2683 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2684 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2685 return;
2686 } else if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
2687 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2688 MPI3_SYSIF_FAULT_CODE_MASK);
2689
2690 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2691 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2692 mpi3mr_print_fault_info(mrioc);
2693 mpi3mr_save_fault_info(mrioc);
2694 mrioc->fault_during_init = 1;
2695 mrioc->fwfault_counter++;
2696 return;
2697 }
2698
2699 mpi3mr_set_diagsave(mrioc);
2700 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2701 reason_code);
2702 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
2703 MPI3_SYSIF_FAULT_CODE_MASK);
2704 mpi3mr_set_trigger_data_in_all_hdb(mrioc, MPI3MR_HDB_TRIGGER_TYPE_FAULT,
2705 &trigger_data, 0);
2706 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2707 do {
2708 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2709 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2710 break;
2711 msleep(100);
2712 } while (--timeout);
2713
2714 mpi3mr_save_fault_info(mrioc);
2715 mrioc->fault_during_init = 1;
2716 mrioc->fwfault_counter++;
2717 }
2718
2719 /**
2720 * mpi3mr_sync_timestamp - Issue time stamp sync request
2721 * @mrioc: Adapter reference
2722 *
2723 * Issue IO unit control MPI request to synchronize firmware
2724 * timestamp with host time.
2725 *
2726 * Return: 0 on success, non-zero on failure.
2727 */
mpi3mr_sync_timestamp(struct mpi3mr_ioc * mrioc)2728 static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2729 {
2730 ktime_t current_time;
2731 struct mpi3_iounit_control_request iou_ctrl;
2732 int retval = 0;
2733
2734 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2735 mutex_lock(&mrioc->init_cmds.mutex);
2736 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2737 retval = -1;
2738 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2739 mutex_unlock(&mrioc->init_cmds.mutex);
2740 goto out;
2741 }
2742 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2743 mrioc->init_cmds.is_waiting = 1;
2744 mrioc->init_cmds.callback = NULL;
2745 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2746 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2747 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2748 current_time = ktime_get_real();
2749 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2750
2751 init_completion(&mrioc->init_cmds.done);
2752 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2753 sizeof(iou_ctrl), 0);
2754 if (retval) {
2755 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2756 goto out_unlock;
2757 }
2758
2759 wait_for_completion_timeout(&mrioc->init_cmds.done,
2760 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2761 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2762 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2763 mrioc->init_cmds.is_waiting = 0;
2764 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2765 mpi3mr_check_rh_fault_ioc(mrioc,
2766 MPI3MR_RESET_FROM_TSU_TIMEOUT);
2767 retval = -1;
2768 goto out_unlock;
2769 }
2770 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2771 != MPI3_IOCSTATUS_SUCCESS) {
2772 ioc_err(mrioc,
2773 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2774 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2775 mrioc->init_cmds.ioc_loginfo);
2776 retval = -1;
2777 goto out_unlock;
2778 }
2779
2780 out_unlock:
2781 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2782 mutex_unlock(&mrioc->init_cmds.mutex);
2783
2784 out:
2785 return retval;
2786 }
2787
2788 /**
2789 * mpi3mr_print_pkg_ver - display controller fw package version
2790 * @mrioc: Adapter reference
2791 *
2792 * Retrieve firmware package version from the component image
2793 * header of the controller flash and display it.
2794 *
2795 * Return: 0 on success and non-zero on failure.
2796 */
mpi3mr_print_pkg_ver(struct mpi3mr_ioc * mrioc)2797 static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2798 {
2799 struct mpi3_ci_upload_request ci_upload;
2800 int retval = -1;
2801 void *data = NULL;
2802 dma_addr_t data_dma;
2803 struct mpi3_ci_manifest_mpi *manifest;
2804 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2805 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2806
2807 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2808 GFP_KERNEL);
2809 if (!data)
2810 return -ENOMEM;
2811
2812 memset(&ci_upload, 0, sizeof(ci_upload));
2813 mutex_lock(&mrioc->init_cmds.mutex);
2814 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2815 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2816 mutex_unlock(&mrioc->init_cmds.mutex);
2817 goto out;
2818 }
2819 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2820 mrioc->init_cmds.is_waiting = 1;
2821 mrioc->init_cmds.callback = NULL;
2822 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2823 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2824 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2825 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2826 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2827 ci_upload.segment_size = cpu_to_le32(data_len);
2828
2829 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2830 data_dma);
2831 init_completion(&mrioc->init_cmds.done);
2832 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2833 sizeof(ci_upload), 1);
2834 if (retval) {
2835 ioc_err(mrioc, "posting get package version failed\n");
2836 goto out_unlock;
2837 }
2838 wait_for_completion_timeout(&mrioc->init_cmds.done,
2839 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2840 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2841 ioc_err(mrioc, "get package version timed out\n");
2842 mpi3mr_check_rh_fault_ioc(mrioc,
2843 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2844 retval = -1;
2845 goto out_unlock;
2846 }
2847 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2848 == MPI3_IOCSTATUS_SUCCESS) {
2849 manifest = (struct mpi3_ci_manifest_mpi *) data;
2850 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2851 ioc_info(mrioc,
2852 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2853 manifest->package_version.gen_major,
2854 manifest->package_version.gen_minor,
2855 manifest->package_version.phase_major,
2856 manifest->package_version.phase_minor,
2857 manifest->package_version.customer_id,
2858 manifest->package_version.build_num);
2859 }
2860 }
2861 retval = 0;
2862 out_unlock:
2863 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2864 mutex_unlock(&mrioc->init_cmds.mutex);
2865
2866 out:
2867 if (data)
2868 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2869 data_dma);
2870 return retval;
2871 }
2872
2873 /**
2874 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2875 * @work: work struct
2876 *
2877 * Watch dog work periodically executed (1 second interval) to
2878 * monitor firmware fault and to issue periodic timer sync to
2879 * the firmware.
2880 *
2881 * Return: Nothing.
2882 */
mpi3mr_watchdog_work(struct work_struct * work)2883 static void mpi3mr_watchdog_work(struct work_struct *work)
2884 {
2885 struct mpi3mr_ioc *mrioc =
2886 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2887 unsigned long flags;
2888 enum mpi3mr_iocstate ioc_state;
2889 u32 host_diagnostic, ioc_status;
2890 union mpi3mr_trigger_data trigger_data;
2891 u16 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2892
2893 if (mrioc->fault_during_init) {
2894 mpi3mr_fault_uevent_emit(mrioc);
2895 mrioc->fault_during_init = 0;
2896 }
2897
2898 if (mrioc->reset_in_progress || mrioc->pci_err_recovery)
2899 return;
2900
2901 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2902 ioc_err(mrioc, "watchdog could not detect the controller\n");
2903 mrioc->unrecoverable = 1;
2904 }
2905
2906 if (mrioc->unrecoverable) {
2907 ioc_err(mrioc,
2908 "flush pending commands for unrecoverable controller\n");
2909 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2910 return;
2911 }
2912
2913 if (mrioc->invalid_io_comp) {
2914 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_INVALID_COMPLETION, 1);
2915 return;
2916 }
2917
2918 if (atomic_read(&mrioc->admin_pend_isr)) {
2919 ioc_err(mrioc, "Unprocessed admin ISR instance found\n"
2920 "flush admin replies\n");
2921 mpi3mr_process_admin_reply_q(mrioc);
2922 }
2923
2924 if (!(mrioc->facts.ioc_capabilities &
2925 MPI3_IOCFACTS_CAPABILITY_NON_SUPERVISOR_IOC) &&
2926 (mrioc->ts_update_counter++ >= mrioc->ts_update_interval)) {
2927
2928 mrioc->ts_update_counter = 0;
2929 mpi3mr_sync_timestamp(mrioc);
2930 }
2931
2932 if ((mrioc->prepare_for_reset) &&
2933 ((mrioc->prepare_for_reset_timeout_counter++) >=
2934 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2935 mpi3mr_soft_reset_handler(mrioc,
2936 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2937 return;
2938 }
2939
2940 memset(&trigger_data, 0, sizeof(trigger_data));
2941 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2942 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2943 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2944 MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED, NULL, 0);
2945 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2946 return;
2947 }
2948
2949 /*Check for fault state every one second and issue Soft reset*/
2950 ioc_state = mpi3mr_get_iocstate(mrioc);
2951 if (ioc_state != MRIOC_STATE_FAULT)
2952 goto schedule_work;
2953
2954 trigger_data.fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2955 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
2956 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
2957 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2958 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2959 if (!mrioc->diagsave_timeout) {
2960 mpi3mr_print_fault_info(mrioc);
2961 ioc_warn(mrioc, "diag save in progress\n");
2962 }
2963 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2964 goto schedule_work;
2965 }
2966
2967 mpi3mr_print_fault_info(mrioc);
2968 mrioc->diagsave_timeout = 0;
2969
2970 if (!mpi3mr_is_fault_recoverable(mrioc)) {
2971 mrioc->unrecoverable = 1;
2972 goto schedule_work;
2973 }
2974
2975 mpi3mr_save_fault_info(mrioc);
2976 mpi3mr_fault_uevent_emit(mrioc);
2977 mrioc->fwfault_counter++;
2978
2979 switch (trigger_data.fault) {
2980 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2981 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2982 ioc_warn(mrioc,
2983 "controller requires system power cycle, marking controller as unrecoverable\n");
2984 mrioc->unrecoverable = 1;
2985 goto schedule_work;
2986 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2987 goto schedule_work;
2988 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2989 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2990 break;
2991 default:
2992 break;
2993 }
2994 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2995 return;
2996
2997 schedule_work:
2998 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2999 if (mrioc->watchdog_work_q)
3000 queue_delayed_work(mrioc->watchdog_work_q,
3001 &mrioc->watchdog_work,
3002 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
3003 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
3004 return;
3005 }
3006
3007 /**
3008 * mpi3mr_start_watchdog - Start watchdog
3009 * @mrioc: Adapter instance reference
3010 *
3011 * Create and start the watchdog thread to monitor controller
3012 * faults.
3013 *
3014 * Return: Nothing.
3015 */
mpi3mr_start_watchdog(struct mpi3mr_ioc * mrioc)3016 void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
3017 {
3018 if (mrioc->watchdog_work_q)
3019 return;
3020
3021 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
3022 mrioc->watchdog_work_q = alloc_ordered_workqueue(
3023 "watchdog_%s%d", WQ_MEM_RECLAIM, mrioc->name, mrioc->id);
3024 if (!mrioc->watchdog_work_q) {
3025 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
3026 return;
3027 }
3028
3029 if (mrioc->watchdog_work_q)
3030 queue_delayed_work(mrioc->watchdog_work_q,
3031 &mrioc->watchdog_work,
3032 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
3033 }
3034
3035 /**
3036 * mpi3mr_stop_watchdog - Stop watchdog
3037 * @mrioc: Adapter instance reference
3038 *
3039 * Stop the watchdog thread created to monitor controller
3040 * faults.
3041 *
3042 * Return: Nothing.
3043 */
mpi3mr_stop_watchdog(struct mpi3mr_ioc * mrioc)3044 void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
3045 {
3046 unsigned long flags;
3047 struct workqueue_struct *wq;
3048
3049 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
3050 wq = mrioc->watchdog_work_q;
3051 mrioc->watchdog_work_q = NULL;
3052 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
3053 if (wq) {
3054 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
3055 flush_workqueue(wq);
3056 destroy_workqueue(wq);
3057 }
3058 }
3059
3060 /**
3061 * mpi3mr_setup_admin_qpair - Setup admin queue pair
3062 * @mrioc: Adapter instance reference
3063 *
3064 * Allocate memory for admin queue pair if required and register
3065 * the admin queue with the controller.
3066 *
3067 * Return: 0 on success, non-zero on failures.
3068 */
mpi3mr_setup_admin_qpair(struct mpi3mr_ioc * mrioc)3069 static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
3070 {
3071 int retval = 0;
3072 u32 num_admin_entries = 0;
3073
3074 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
3075 mrioc->num_admin_req = mrioc->admin_req_q_sz /
3076 MPI3MR_ADMIN_REQ_FRAME_SZ;
3077 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
3078
3079 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
3080 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
3081 MPI3MR_ADMIN_REPLY_FRAME_SZ;
3082 mrioc->admin_reply_ci = 0;
3083 mrioc->admin_reply_ephase = 1;
3084 atomic_set(&mrioc->admin_reply_q_in_use, 0);
3085 atomic_set(&mrioc->admin_pend_isr, 0);
3086
3087 if (!mrioc->admin_req_base) {
3088 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
3089 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
3090
3091 if (!mrioc->admin_req_base) {
3092 retval = -1;
3093 goto out_failed;
3094 }
3095
3096 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
3097 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
3098 GFP_KERNEL);
3099
3100 if (!mrioc->admin_reply_base) {
3101 retval = -1;
3102 goto out_failed;
3103 }
3104 }
3105
3106 num_admin_entries = (mrioc->num_admin_replies << 16) |
3107 (mrioc->num_admin_req);
3108 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
3109 mpi3mr_writeq(mrioc->admin_req_dma,
3110 &mrioc->sysif_regs->admin_request_queue_address,
3111 &mrioc->adm_req_q_bar_writeq_lock);
3112 mpi3mr_writeq(mrioc->admin_reply_dma,
3113 &mrioc->sysif_regs->admin_reply_queue_address,
3114 &mrioc->adm_reply_q_bar_writeq_lock);
3115 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
3116 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
3117 return retval;
3118
3119 out_failed:
3120
3121 if (mrioc->admin_reply_base) {
3122 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
3123 mrioc->admin_reply_base, mrioc->admin_reply_dma);
3124 mrioc->admin_reply_base = NULL;
3125 }
3126 if (mrioc->admin_req_base) {
3127 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
3128 mrioc->admin_req_base, mrioc->admin_req_dma);
3129 mrioc->admin_req_base = NULL;
3130 }
3131 return retval;
3132 }
3133
3134 /**
3135 * mpi3mr_issue_iocfacts - Send IOC Facts
3136 * @mrioc: Adapter instance reference
3137 * @facts_data: Cached IOC facts data
3138 *
3139 * Issue IOC Facts MPI request through admin queue and wait for
3140 * the completion of it or time out.
3141 *
3142 * Return: 0 on success, non-zero on failures.
3143 */
mpi3mr_issue_iocfacts(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)3144 static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
3145 struct mpi3_ioc_facts_data *facts_data)
3146 {
3147 struct mpi3_ioc_facts_request iocfacts_req;
3148 void *data = NULL;
3149 dma_addr_t data_dma;
3150 u32 data_len = sizeof(*facts_data);
3151 int retval = 0;
3152 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
3153
3154 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3155 GFP_KERNEL);
3156
3157 if (!data) {
3158 retval = -1;
3159 goto out;
3160 }
3161
3162 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
3163 mutex_lock(&mrioc->init_cmds.mutex);
3164 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3165 retval = -1;
3166 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
3167 mutex_unlock(&mrioc->init_cmds.mutex);
3168 goto out;
3169 }
3170 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3171 mrioc->init_cmds.is_waiting = 1;
3172 mrioc->init_cmds.callback = NULL;
3173 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3174 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
3175
3176 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
3177 data_dma);
3178
3179 init_completion(&mrioc->init_cmds.done);
3180 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
3181 sizeof(iocfacts_req), 1);
3182 if (retval) {
3183 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
3184 goto out_unlock;
3185 }
3186 wait_for_completion_timeout(&mrioc->init_cmds.done,
3187 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3188 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3189 ioc_err(mrioc, "ioc_facts timed out\n");
3190 mpi3mr_check_rh_fault_ioc(mrioc,
3191 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
3192 retval = -1;
3193 goto out_unlock;
3194 }
3195 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3196 != MPI3_IOCSTATUS_SUCCESS) {
3197 ioc_err(mrioc,
3198 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3199 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3200 mrioc->init_cmds.ioc_loginfo);
3201 retval = -1;
3202 goto out_unlock;
3203 }
3204 memcpy(facts_data, (u8 *)data, data_len);
3205 mpi3mr_process_factsdata(mrioc, facts_data);
3206 out_unlock:
3207 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3208 mutex_unlock(&mrioc->init_cmds.mutex);
3209
3210 out:
3211 if (data)
3212 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
3213
3214 return retval;
3215 }
3216
3217 /**
3218 * mpi3mr_check_reset_dma_mask - Process IOC facts data
3219 * @mrioc: Adapter instance reference
3220 *
3221 * Check whether the new DMA mask requested through IOCFacts by
3222 * firmware needs to be set, if so set it .
3223 *
3224 * Return: 0 on success, non-zero on failure.
3225 */
mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc * mrioc)3226 static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
3227 {
3228 struct pci_dev *pdev = mrioc->pdev;
3229 int r;
3230 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
3231
3232 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
3233 return 0;
3234
3235 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
3236 mrioc->dma_mask, facts_dma_mask);
3237
3238 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
3239 if (r) {
3240 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
3241 facts_dma_mask, r);
3242 return r;
3243 }
3244 mrioc->dma_mask = facts_dma_mask;
3245 return r;
3246 }
3247
3248 /**
3249 * mpi3mr_process_factsdata - Process IOC facts data
3250 * @mrioc: Adapter instance reference
3251 * @facts_data: Cached IOC facts data
3252 *
3253 * Convert IOC facts data into cpu endianness and cache it in
3254 * the driver .
3255 *
3256 * Return: Nothing.
3257 */
mpi3mr_process_factsdata(struct mpi3mr_ioc * mrioc,struct mpi3_ioc_facts_data * facts_data)3258 static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
3259 struct mpi3_ioc_facts_data *facts_data)
3260 {
3261 u32 ioc_config, req_sz, facts_flags;
3262
3263 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
3264 (sizeof(*facts_data) / 4)) {
3265 ioc_warn(mrioc,
3266 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
3267 sizeof(*facts_data),
3268 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
3269 }
3270
3271 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
3272 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
3273 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
3274 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
3275 ioc_err(mrioc,
3276 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
3277 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
3278 }
3279
3280 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
3281
3282 facts_flags = le32_to_cpu(facts_data->flags);
3283 mrioc->facts.op_req_sz = req_sz;
3284 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
3285 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
3286 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
3287
3288 mrioc->facts.ioc_num = facts_data->ioc_number;
3289 mrioc->facts.who_init = facts_data->who_init;
3290 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
3291 mrioc->facts.personality = (facts_flags &
3292 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
3293 mrioc->facts.dma_mask = (facts_flags &
3294 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3295 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3296 mrioc->facts.dma_mask = (facts_flags &
3297 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
3298 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
3299 mrioc->facts.max_req_limit = (facts_flags &
3300 MPI3_IOCFACTS_FLAGS_MAX_REQ_PER_REPLY_QUEUE_LIMIT);
3301 mrioc->facts.protocol_flags = facts_data->protocol_flags;
3302 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
3303 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
3304 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
3305 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
3306 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
3307 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
3308 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
3309 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
3310 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
3311 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
3312 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
3313 mrioc->facts.max_pcie_switches =
3314 le16_to_cpu(facts_data->max_pcie_switches);
3315 mrioc->facts.max_sasexpanders =
3316 le16_to_cpu(facts_data->max_sas_expanders);
3317 mrioc->facts.max_data_length = le16_to_cpu(facts_data->max_data_length);
3318 mrioc->facts.max_sasinitiators =
3319 le16_to_cpu(facts_data->max_sas_initiators);
3320 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
3321 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
3322 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
3323 mrioc->facts.max_op_req_q =
3324 le16_to_cpu(facts_data->max_operational_request_queues);
3325 mrioc->facts.max_op_reply_q =
3326 le16_to_cpu(facts_data->max_operational_reply_queues);
3327 mrioc->facts.ioc_capabilities =
3328 le32_to_cpu(facts_data->ioc_capabilities);
3329 mrioc->facts.fw_ver.build_num =
3330 le16_to_cpu(facts_data->fw_version.build_num);
3331 mrioc->facts.fw_ver.cust_id =
3332 le16_to_cpu(facts_data->fw_version.customer_id);
3333 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
3334 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
3335 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
3336 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
3337 mrioc->msix_count = min_t(int, mrioc->msix_count,
3338 mrioc->facts.max_msix_vectors);
3339 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
3340 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
3341 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
3342 mrioc->facts.shutdown_timeout =
3343 le16_to_cpu(facts_data->shutdown_timeout);
3344 mrioc->facts.diag_trace_sz =
3345 le32_to_cpu(facts_data->diag_trace_size);
3346 mrioc->facts.diag_fw_sz =
3347 le32_to_cpu(facts_data->diag_fw_size);
3348 mrioc->facts.diag_drvr_sz = le32_to_cpu(facts_data->diag_driver_size);
3349 mrioc->facts.max_dev_per_tg =
3350 facts_data->max_devices_per_throttle_group;
3351 mrioc->facts.io_throttle_data_length =
3352 le16_to_cpu(facts_data->io_throttle_data_length);
3353 mrioc->facts.max_io_throttle_group =
3354 le16_to_cpu(facts_data->max_io_throttle_group);
3355 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
3356 mrioc->facts.io_throttle_high =
3357 le16_to_cpu(facts_data->io_throttle_high);
3358
3359 if (mrioc->facts.max_data_length ==
3360 MPI3_IOCFACTS_MAX_DATA_LENGTH_NOT_REPORTED)
3361 mrioc->facts.max_data_length = MPI3MR_DEFAULT_MAX_IO_SIZE;
3362 else
3363 mrioc->facts.max_data_length *= MPI3MR_PAGE_SIZE_4K;
3364 /* Store in 512b block count */
3365 if (mrioc->facts.io_throttle_data_length)
3366 mrioc->io_throttle_data_length =
3367 (mrioc->facts.io_throttle_data_length * 2 * 4);
3368 else
3369 /* set the length to 1MB + 1K to disable throttle */
3370 mrioc->io_throttle_data_length = (mrioc->facts.max_data_length / 512) + 2;
3371
3372 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
3373 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
3374
3375 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
3376 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
3377 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
3378 ioc_info(mrioc,
3379 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
3380 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
3381 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
3382 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
3383 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
3384 mrioc->facts.sge_mod_shift);
3385 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x max_data_len (%d)\n",
3386 mrioc->facts.dma_mask, (facts_flags &
3387 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK), mrioc->facts.max_data_length);
3388 ioc_info(mrioc,
3389 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
3390 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
3391 ioc_info(mrioc,
3392 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
3393 mrioc->facts.io_throttle_data_length * 4,
3394 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
3395 }
3396
3397 /**
3398 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
3399 * @mrioc: Adapter instance reference
3400 *
3401 * Allocate and initialize the reply free buffers, sense
3402 * buffers, reply free queue and sense buffer queue.
3403 *
3404 * Return: 0 on success, non-zero on failures.
3405 */
mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc * mrioc)3406 static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
3407 {
3408 int retval = 0;
3409 u32 sz, i;
3410
3411 if (mrioc->init_cmds.reply)
3412 return retval;
3413
3414 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3415 if (!mrioc->init_cmds.reply)
3416 goto out_failed;
3417
3418 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3419 if (!mrioc->bsg_cmds.reply)
3420 goto out_failed;
3421
3422 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3423 if (!mrioc->transport_cmds.reply)
3424 goto out_failed;
3425
3426 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
3427 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
3428 GFP_KERNEL);
3429 if (!mrioc->dev_rmhs_cmds[i].reply)
3430 goto out_failed;
3431 }
3432
3433 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
3434 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
3435 GFP_KERNEL);
3436 if (!mrioc->evtack_cmds[i].reply)
3437 goto out_failed;
3438 }
3439
3440 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3441 if (!mrioc->host_tm_cmds.reply)
3442 goto out_failed;
3443
3444 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3445 if (!mrioc->pel_cmds.reply)
3446 goto out_failed;
3447
3448 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
3449 if (!mrioc->pel_abort_cmd.reply)
3450 goto out_failed;
3451
3452 mrioc->dev_handle_bitmap_bits = mrioc->facts.max_devhandle;
3453 mrioc->removepend_bitmap = bitmap_zalloc(mrioc->dev_handle_bitmap_bits,
3454 GFP_KERNEL);
3455 if (!mrioc->removepend_bitmap)
3456 goto out_failed;
3457
3458 mrioc->devrem_bitmap = bitmap_zalloc(MPI3MR_NUM_DEVRMCMD, GFP_KERNEL);
3459 if (!mrioc->devrem_bitmap)
3460 goto out_failed;
3461
3462 mrioc->evtack_cmds_bitmap = bitmap_zalloc(MPI3MR_NUM_EVTACKCMD,
3463 GFP_KERNEL);
3464 if (!mrioc->evtack_cmds_bitmap)
3465 goto out_failed;
3466
3467 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
3468 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
3469 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
3470 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
3471
3472 /* reply buffer pool, 16 byte align */
3473 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3474 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
3475 &mrioc->pdev->dev, sz, 16, 0);
3476 if (!mrioc->reply_buf_pool) {
3477 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
3478 goto out_failed;
3479 }
3480
3481 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
3482 &mrioc->reply_buf_dma);
3483 if (!mrioc->reply_buf)
3484 goto out_failed;
3485
3486 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3487
3488 /* reply free queue, 8 byte align */
3489 sz = mrioc->reply_free_qsz * 8;
3490 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3491 &mrioc->pdev->dev, sz, 8, 0);
3492 if (!mrioc->reply_free_q_pool) {
3493 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3494 goto out_failed;
3495 }
3496 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3497 GFP_KERNEL, &mrioc->reply_free_q_dma);
3498 if (!mrioc->reply_free_q)
3499 goto out_failed;
3500
3501 /* sense buffer pool, 4 byte align */
3502 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3503 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3504 &mrioc->pdev->dev, sz, 4, 0);
3505 if (!mrioc->sense_buf_pool) {
3506 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3507 goto out_failed;
3508 }
3509 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3510 &mrioc->sense_buf_dma);
3511 if (!mrioc->sense_buf)
3512 goto out_failed;
3513
3514 /* sense buffer queue, 8 byte align */
3515 sz = mrioc->sense_buf_q_sz * 8;
3516 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3517 &mrioc->pdev->dev, sz, 8, 0);
3518 if (!mrioc->sense_buf_q_pool) {
3519 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3520 goto out_failed;
3521 }
3522 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3523 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3524 if (!mrioc->sense_buf_q)
3525 goto out_failed;
3526
3527 return retval;
3528
3529 out_failed:
3530 retval = -1;
3531 return retval;
3532 }
3533
3534 /**
3535 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3536 * buffers
3537 * @mrioc: Adapter instance reference
3538 *
3539 * Helper function to initialize reply and sense buffers along
3540 * with some debug prints.
3541 *
3542 * Return: None.
3543 */
mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc * mrioc)3544 static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3545 {
3546 u32 sz, i;
3547 dma_addr_t phy_addr;
3548
3549 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3550 ioc_info(mrioc,
3551 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3552 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3553 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3554 sz = mrioc->reply_free_qsz * 8;
3555 ioc_info(mrioc,
3556 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3557 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3558 (unsigned long long)mrioc->reply_free_q_dma);
3559 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3560 ioc_info(mrioc,
3561 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3562 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3563 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3564 sz = mrioc->sense_buf_q_sz * 8;
3565 ioc_info(mrioc,
3566 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3567 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3568 (unsigned long long)mrioc->sense_buf_q_dma);
3569
3570 /* initialize Reply buffer Queue */
3571 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3572 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3573 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3574 mrioc->reply_free_q[i] = cpu_to_le64(0);
3575
3576 /* initialize Sense Buffer Queue */
3577 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3578 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3579 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3580 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3581 }
3582
3583 /**
3584 * mpi3mr_issue_iocinit - Send IOC Init
3585 * @mrioc: Adapter instance reference
3586 *
3587 * Issue IOC Init MPI request through admin queue and wait for
3588 * the completion of it or time out.
3589 *
3590 * Return: 0 on success, non-zero on failures.
3591 */
mpi3mr_issue_iocinit(struct mpi3mr_ioc * mrioc)3592 static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3593 {
3594 struct mpi3_ioc_init_request iocinit_req;
3595 struct mpi3_driver_info_layout *drv_info;
3596 dma_addr_t data_dma;
3597 u32 data_len = sizeof(*drv_info);
3598 int retval = 0;
3599 ktime_t current_time;
3600
3601 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3602 GFP_KERNEL);
3603 if (!drv_info) {
3604 retval = -1;
3605 goto out;
3606 }
3607 mpimr_initialize_reply_sbuf_queues(mrioc);
3608
3609 drv_info->information_length = cpu_to_le32(data_len);
3610 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3611 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3612 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3613 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3614 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3615 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3616 sizeof(drv_info->driver_release_date));
3617 drv_info->driver_capabilities = 0;
3618 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3619 sizeof(mrioc->driver_info));
3620
3621 memset(&iocinit_req, 0, sizeof(iocinit_req));
3622 mutex_lock(&mrioc->init_cmds.mutex);
3623 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3624 retval = -1;
3625 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3626 mutex_unlock(&mrioc->init_cmds.mutex);
3627 goto out;
3628 }
3629 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3630 mrioc->init_cmds.is_waiting = 1;
3631 mrioc->init_cmds.callback = NULL;
3632 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3633 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3634 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3635 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3636 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3637 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3638 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3639 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3640 iocinit_req.reply_free_queue_address =
3641 cpu_to_le64(mrioc->reply_free_q_dma);
3642 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3643 iocinit_req.sense_buffer_free_queue_depth =
3644 cpu_to_le16(mrioc->sense_buf_q_sz);
3645 iocinit_req.sense_buffer_free_queue_address =
3646 cpu_to_le64(mrioc->sense_buf_q_dma);
3647 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3648
3649 current_time = ktime_get_real();
3650 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3651
3652 iocinit_req.msg_flags |=
3653 MPI3_IOCINIT_MSGFLAGS_SCSIIOSTATUSREPLY_SUPPORTED;
3654 iocinit_req.msg_flags |=
3655 MPI3_IOCINIT_MSGFLAGS_WRITESAMEDIVERT_SUPPORTED;
3656
3657 init_completion(&mrioc->init_cmds.done);
3658 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3659 sizeof(iocinit_req), 1);
3660 if (retval) {
3661 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3662 goto out_unlock;
3663 }
3664 wait_for_completion_timeout(&mrioc->init_cmds.done,
3665 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3666 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3667 mpi3mr_check_rh_fault_ioc(mrioc,
3668 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3669 ioc_err(mrioc, "ioc_init timed out\n");
3670 retval = -1;
3671 goto out_unlock;
3672 }
3673 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3674 != MPI3_IOCSTATUS_SUCCESS) {
3675 ioc_err(mrioc,
3676 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3677 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3678 mrioc->init_cmds.ioc_loginfo);
3679 retval = -1;
3680 goto out_unlock;
3681 }
3682
3683 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3684 writel(mrioc->reply_free_queue_host_index,
3685 &mrioc->sysif_regs->reply_free_host_index);
3686
3687 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3688 writel(mrioc->sbq_host_index,
3689 &mrioc->sysif_regs->sense_buffer_free_host_index);
3690 out_unlock:
3691 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3692 mutex_unlock(&mrioc->init_cmds.mutex);
3693
3694 out:
3695 if (drv_info)
3696 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3697 data_dma);
3698
3699 return retval;
3700 }
3701
3702 /**
3703 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3704 * @mrioc: Adapter instance reference
3705 * @event: MPI event ID
3706 *
3707 * Un mask the specific event by resetting the event_mask
3708 * bitmap.
3709 *
3710 * Return: 0 on success, non-zero on failures.
3711 */
mpi3mr_unmask_events(struct mpi3mr_ioc * mrioc,u16 event)3712 static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3713 {
3714 u32 desired_event;
3715 u8 word;
3716
3717 if (event >= 128)
3718 return;
3719
3720 desired_event = (1 << (event % 32));
3721 word = event / 32;
3722
3723 mrioc->event_masks[word] &= ~desired_event;
3724 }
3725
3726 /**
3727 * mpi3mr_issue_event_notification - Send event notification
3728 * @mrioc: Adapter instance reference
3729 *
3730 * Issue event notification MPI request through admin queue and
3731 * wait for the completion of it or time out.
3732 *
3733 * Return: 0 on success, non-zero on failures.
3734 */
mpi3mr_issue_event_notification(struct mpi3mr_ioc * mrioc)3735 static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3736 {
3737 struct mpi3_event_notification_request evtnotify_req;
3738 int retval = 0;
3739 u8 i;
3740
3741 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3742 mutex_lock(&mrioc->init_cmds.mutex);
3743 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3744 retval = -1;
3745 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3746 mutex_unlock(&mrioc->init_cmds.mutex);
3747 goto out;
3748 }
3749 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3750 mrioc->init_cmds.is_waiting = 1;
3751 mrioc->init_cmds.callback = NULL;
3752 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3753 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3754 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3755 evtnotify_req.event_masks[i] =
3756 cpu_to_le32(mrioc->event_masks[i]);
3757 init_completion(&mrioc->init_cmds.done);
3758 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3759 sizeof(evtnotify_req), 1);
3760 if (retval) {
3761 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3762 goto out_unlock;
3763 }
3764 wait_for_completion_timeout(&mrioc->init_cmds.done,
3765 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3766 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3767 ioc_err(mrioc, "event notification timed out\n");
3768 mpi3mr_check_rh_fault_ioc(mrioc,
3769 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3770 retval = -1;
3771 goto out_unlock;
3772 }
3773 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3774 != MPI3_IOCSTATUS_SUCCESS) {
3775 ioc_err(mrioc,
3776 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3777 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3778 mrioc->init_cmds.ioc_loginfo);
3779 retval = -1;
3780 goto out_unlock;
3781 }
3782
3783 out_unlock:
3784 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3785 mutex_unlock(&mrioc->init_cmds.mutex);
3786 out:
3787 return retval;
3788 }
3789
3790 /**
3791 * mpi3mr_process_event_ack - Process event acknowledgment
3792 * @mrioc: Adapter instance reference
3793 * @event: MPI3 event ID
3794 * @event_ctx: event context
3795 *
3796 * Send event acknowledgment through admin queue and wait for
3797 * it to complete.
3798 *
3799 * Return: 0 on success, non-zero on failures.
3800 */
mpi3mr_process_event_ack(struct mpi3mr_ioc * mrioc,u8 event,u32 event_ctx)3801 int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3802 u32 event_ctx)
3803 {
3804 struct mpi3_event_ack_request evtack_req;
3805 int retval = 0;
3806
3807 memset(&evtack_req, 0, sizeof(evtack_req));
3808 mutex_lock(&mrioc->init_cmds.mutex);
3809 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3810 retval = -1;
3811 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3812 mutex_unlock(&mrioc->init_cmds.mutex);
3813 goto out;
3814 }
3815 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3816 mrioc->init_cmds.is_waiting = 1;
3817 mrioc->init_cmds.callback = NULL;
3818 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3819 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3820 evtack_req.event = event;
3821 evtack_req.event_context = cpu_to_le32(event_ctx);
3822
3823 init_completion(&mrioc->init_cmds.done);
3824 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3825 sizeof(evtack_req), 1);
3826 if (retval) {
3827 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3828 goto out_unlock;
3829 }
3830 wait_for_completion_timeout(&mrioc->init_cmds.done,
3831 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3832 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3833 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3834 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3835 mpi3mr_check_rh_fault_ioc(mrioc,
3836 MPI3MR_RESET_FROM_EVTACK_TIMEOUT);
3837 retval = -1;
3838 goto out_unlock;
3839 }
3840 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3841 != MPI3_IOCSTATUS_SUCCESS) {
3842 ioc_err(mrioc,
3843 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3844 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3845 mrioc->init_cmds.ioc_loginfo);
3846 retval = -1;
3847 goto out_unlock;
3848 }
3849
3850 out_unlock:
3851 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3852 mutex_unlock(&mrioc->init_cmds.mutex);
3853 out:
3854 return retval;
3855 }
3856
3857 /**
3858 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3859 * @mrioc: Adapter instance reference
3860 *
3861 * Allocate chain buffers and set a bitmap to indicate free
3862 * chain buffers. Chain buffers are used to pass the SGE
3863 * information along with MPI3 SCSI IO requests for host I/O.
3864 *
3865 * Return: 0 on success, non-zero on failure
3866 */
mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc * mrioc)3867 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3868 {
3869 int retval = 0;
3870 u32 sz, i;
3871 u16 num_chains;
3872
3873 if (mrioc->chain_sgl_list)
3874 return retval;
3875
3876 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3877
3878 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3879 | SHOST_DIX_TYPE1_PROTECTION
3880 | SHOST_DIX_TYPE2_PROTECTION
3881 | SHOST_DIX_TYPE3_PROTECTION))
3882 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3883
3884 mrioc->chain_buf_count = num_chains;
3885 sz = sizeof(struct chain_element) * num_chains;
3886 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3887 if (!mrioc->chain_sgl_list)
3888 goto out_failed;
3889
3890 if (mrioc->max_sgl_entries > (mrioc->facts.max_data_length /
3891 MPI3MR_PAGE_SIZE_4K))
3892 mrioc->max_sgl_entries = mrioc->facts.max_data_length /
3893 MPI3MR_PAGE_SIZE_4K;
3894 sz = mrioc->max_sgl_entries * sizeof(struct mpi3_sge_common);
3895 ioc_info(mrioc, "number of sgl entries=%d chain buffer size=%dKB\n",
3896 mrioc->max_sgl_entries, sz/1024);
3897
3898 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3899 &mrioc->pdev->dev, sz, 16, 0);
3900 if (!mrioc->chain_buf_pool) {
3901 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3902 goto out_failed;
3903 }
3904
3905 for (i = 0; i < num_chains; i++) {
3906 mrioc->chain_sgl_list[i].addr =
3907 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3908 &mrioc->chain_sgl_list[i].dma_addr);
3909
3910 if (!mrioc->chain_sgl_list[i].addr)
3911 goto out_failed;
3912 }
3913 mrioc->chain_bitmap = bitmap_zalloc(num_chains, GFP_KERNEL);
3914 if (!mrioc->chain_bitmap)
3915 goto out_failed;
3916 return retval;
3917 out_failed:
3918 retval = -1;
3919 return retval;
3920 }
3921
3922 /**
3923 * mpi3mr_port_enable_complete - Mark port enable complete
3924 * @mrioc: Adapter instance reference
3925 * @drv_cmd: Internal command tracker
3926 *
3927 * Call back for asynchronous port enable request sets the
3928 * driver command to indicate port enable request is complete.
3929 *
3930 * Return: Nothing
3931 */
mpi3mr_port_enable_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)3932 static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3933 struct mpi3mr_drv_cmd *drv_cmd)
3934 {
3935 drv_cmd->callback = NULL;
3936 mrioc->scan_started = 0;
3937 if (drv_cmd->state & MPI3MR_CMD_RESET)
3938 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3939 else
3940 mrioc->scan_failed = drv_cmd->ioc_status;
3941 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3942 }
3943
3944 /**
3945 * mpi3mr_issue_port_enable - Issue Port Enable
3946 * @mrioc: Adapter instance reference
3947 * @async: Flag to wait for completion or not
3948 *
3949 * Issue Port Enable MPI request through admin queue and if the
3950 * async flag is not set wait for the completion of the port
3951 * enable or time out.
3952 *
3953 * Return: 0 on success, non-zero on failures.
3954 */
mpi3mr_issue_port_enable(struct mpi3mr_ioc * mrioc,u8 async)3955 int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3956 {
3957 struct mpi3_port_enable_request pe_req;
3958 int retval = 0;
3959 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3960
3961 memset(&pe_req, 0, sizeof(pe_req));
3962 mutex_lock(&mrioc->init_cmds.mutex);
3963 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3964 retval = -1;
3965 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3966 mutex_unlock(&mrioc->init_cmds.mutex);
3967 goto out;
3968 }
3969 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3970 if (async) {
3971 mrioc->init_cmds.is_waiting = 0;
3972 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3973 } else {
3974 mrioc->init_cmds.is_waiting = 1;
3975 mrioc->init_cmds.callback = NULL;
3976 init_completion(&mrioc->init_cmds.done);
3977 }
3978 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3979 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3980
3981 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3982 if (retval) {
3983 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3984 goto out_unlock;
3985 }
3986 if (async) {
3987 mutex_unlock(&mrioc->init_cmds.mutex);
3988 goto out;
3989 }
3990
3991 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3992 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3993 ioc_err(mrioc, "port enable timed out\n");
3994 retval = -1;
3995 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3996 goto out_unlock;
3997 }
3998 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3999
4000 out_unlock:
4001 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4002 mutex_unlock(&mrioc->init_cmds.mutex);
4003 out:
4004 return retval;
4005 }
4006
4007 /* Protocol type to name mapper structure */
4008 static const struct {
4009 u8 protocol;
4010 char *name;
4011 } mpi3mr_protocols[] = {
4012 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
4013 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
4014 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
4015 };
4016
4017 /* Capability to name mapper structure*/
4018 static const struct {
4019 u32 capability;
4020 char *name;
4021 } mpi3mr_capabilities[] = {
4022 { MPI3_IOCFACTS_CAPABILITY_RAID_SUPPORTED, "RAID" },
4023 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED, "MultiPath" },
4024 };
4025
4026 /**
4027 * mpi3mr_repost_diag_bufs - repost host diag buffers
4028 * @mrioc: Adapter instance reference
4029 *
4030 * repost firmware and trace diag buffers based on global
4031 * trigger flag from driver page 2
4032 *
4033 * Return: 0 on success, non-zero on failures.
4034 */
mpi3mr_repost_diag_bufs(struct mpi3mr_ioc * mrioc)4035 static int mpi3mr_repost_diag_bufs(struct mpi3mr_ioc *mrioc)
4036 {
4037 u64 global_trigger;
4038 union mpi3mr_trigger_data prev_trigger_data;
4039 struct diag_buffer_desc *trace_hdb = NULL;
4040 struct diag_buffer_desc *fw_hdb = NULL;
4041 int retval = 0;
4042 bool trace_repost_needed = false;
4043 bool fw_repost_needed = false;
4044 u8 prev_trigger_type;
4045
4046 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4047 if (retval)
4048 return -1;
4049
4050 trace_hdb = mpi3mr_diag_buffer_for_type(mrioc,
4051 MPI3_DIAG_BUFFER_TYPE_TRACE);
4052
4053 if (trace_hdb &&
4054 trace_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
4055 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
4056 trace_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
4057 trace_repost_needed = true;
4058
4059 fw_hdb = mpi3mr_diag_buffer_for_type(mrioc, MPI3_DIAG_BUFFER_TYPE_FW);
4060
4061 if (fw_hdb && fw_hdb->status != MPI3MR_HDB_BUFSTATUS_NOT_ALLOCATED &&
4062 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_GLOBAL &&
4063 fw_hdb->trigger_type != MPI3MR_HDB_TRIGGER_TYPE_ELEMENT)
4064 fw_repost_needed = true;
4065
4066 if (trace_repost_needed || fw_repost_needed) {
4067 global_trigger = le64_to_cpu(mrioc->driver_pg2->global_trigger);
4068 if (global_trigger &
4069 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED)
4070 trace_repost_needed = false;
4071 if (global_trigger &
4072 MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED)
4073 fw_repost_needed = false;
4074 }
4075
4076 if (trace_repost_needed) {
4077 prev_trigger_type = trace_hdb->trigger_type;
4078 memcpy(&prev_trigger_data, &trace_hdb->trigger_data,
4079 sizeof(trace_hdb->trigger_data));
4080 retval = mpi3mr_issue_diag_buf_post(mrioc, trace_hdb);
4081 if (!retval) {
4082 dprint_init(mrioc, "trace diag buffer reposted");
4083 mpi3mr_set_trigger_data_in_hdb(trace_hdb,
4084 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
4085 } else {
4086 trace_hdb->trigger_type = prev_trigger_type;
4087 memcpy(&trace_hdb->trigger_data, &prev_trigger_data,
4088 sizeof(prev_trigger_data));
4089 ioc_err(mrioc, "trace diag buffer repost failed");
4090 return -1;
4091 }
4092 }
4093
4094 if (fw_repost_needed) {
4095 prev_trigger_type = fw_hdb->trigger_type;
4096 memcpy(&prev_trigger_data, &fw_hdb->trigger_data,
4097 sizeof(fw_hdb->trigger_data));
4098 retval = mpi3mr_issue_diag_buf_post(mrioc, fw_hdb);
4099 if (!retval) {
4100 dprint_init(mrioc, "firmware diag buffer reposted");
4101 mpi3mr_set_trigger_data_in_hdb(fw_hdb,
4102 MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN, NULL, 1);
4103 } else {
4104 fw_hdb->trigger_type = prev_trigger_type;
4105 memcpy(&fw_hdb->trigger_data, &prev_trigger_data,
4106 sizeof(prev_trigger_data));
4107 ioc_err(mrioc, "firmware diag buffer repost failed");
4108 return -1;
4109 }
4110 }
4111 return retval;
4112 }
4113
4114 /**
4115 * mpi3mr_read_tsu_interval - Update time stamp interval
4116 * @mrioc: Adapter instance reference
4117 *
4118 * Update time stamp interval if its defined in driver page 1,
4119 * otherwise use default value.
4120 *
4121 * Return: Nothing
4122 */
4123 static void
mpi3mr_read_tsu_interval(struct mpi3mr_ioc * mrioc)4124 mpi3mr_read_tsu_interval(struct mpi3mr_ioc *mrioc)
4125 {
4126 struct mpi3_driver_page1 driver_pg1;
4127 u16 pg_sz = sizeof(driver_pg1);
4128 int retval = 0;
4129
4130 mrioc->ts_update_interval = MPI3MR_TSUPDATE_INTERVAL;
4131
4132 retval = mpi3mr_cfg_get_driver_pg1(mrioc, &driver_pg1, pg_sz);
4133 if (!retval && driver_pg1.time_stamp_update)
4134 mrioc->ts_update_interval = (driver_pg1.time_stamp_update * 60);
4135 }
4136
4137 /**
4138 * mpi3mr_print_ioc_info - Display controller information
4139 * @mrioc: Adapter instance reference
4140 *
4141 * Display controller personality, capability, supported
4142 * protocols etc.
4143 *
4144 * Return: Nothing
4145 */
4146 static void
mpi3mr_print_ioc_info(struct mpi3mr_ioc * mrioc)4147 mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
4148 {
4149 int i = 0, bytes_written = 0;
4150 const char *personality;
4151 char protocol[50] = {0};
4152 char capabilities[100] = {0};
4153 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
4154
4155 switch (mrioc->facts.personality) {
4156 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
4157 personality = "Enhanced HBA";
4158 break;
4159 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
4160 personality = "RAID";
4161 break;
4162 default:
4163 personality = "Unknown";
4164 break;
4165 }
4166
4167 ioc_info(mrioc, "Running in %s Personality", personality);
4168
4169 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
4170 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
4171 fwver->ph_minor, fwver->cust_id, fwver->build_num);
4172
4173 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
4174 if (mrioc->facts.protocol_flags &
4175 mpi3mr_protocols[i].protocol) {
4176 bytes_written += scnprintf(protocol + bytes_written,
4177 sizeof(protocol) - bytes_written, "%s%s",
4178 bytes_written ? "," : "",
4179 mpi3mr_protocols[i].name);
4180 }
4181 }
4182
4183 bytes_written = 0;
4184 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
4185 if (mrioc->facts.protocol_flags &
4186 mpi3mr_capabilities[i].capability) {
4187 bytes_written += scnprintf(capabilities + bytes_written,
4188 sizeof(capabilities) - bytes_written, "%s%s",
4189 bytes_written ? "," : "",
4190 mpi3mr_capabilities[i].name);
4191 }
4192 }
4193
4194 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
4195 protocol, capabilities);
4196 }
4197
4198 /**
4199 * mpi3mr_cleanup_resources - Free PCI resources
4200 * @mrioc: Adapter instance reference
4201 *
4202 * Unmap PCI device memory and disable PCI device.
4203 *
4204 * Return: 0 on success and non-zero on failure.
4205 */
mpi3mr_cleanup_resources(struct mpi3mr_ioc * mrioc)4206 void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
4207 {
4208 struct pci_dev *pdev = mrioc->pdev;
4209
4210 mpi3mr_cleanup_isr(mrioc);
4211
4212 if (mrioc->sysif_regs) {
4213 iounmap((void __iomem *)mrioc->sysif_regs);
4214 mrioc->sysif_regs = NULL;
4215 }
4216
4217 if (pci_is_enabled(pdev)) {
4218 if (mrioc->bars)
4219 pci_release_selected_regions(pdev, mrioc->bars);
4220 pci_disable_device(pdev);
4221 }
4222 }
4223
4224 /**
4225 * mpi3mr_setup_resources - Enable PCI resources
4226 * @mrioc: Adapter instance reference
4227 *
4228 * Enable PCI device memory, MSI-x registers and set DMA mask.
4229 *
4230 * Return: 0 on success and non-zero on failure.
4231 */
mpi3mr_setup_resources(struct mpi3mr_ioc * mrioc)4232 int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
4233 {
4234 struct pci_dev *pdev = mrioc->pdev;
4235 u32 memap_sz = 0;
4236 int i, retval = 0, capb = 0;
4237 u16 message_control;
4238 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
4239 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
4240
4241 if (pci_enable_device_mem(pdev)) {
4242 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
4243 retval = -ENODEV;
4244 goto out_failed;
4245 }
4246
4247 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
4248 if (!capb) {
4249 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
4250 retval = -ENODEV;
4251 goto out_failed;
4252 }
4253 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
4254
4255 if (pci_request_selected_regions(pdev, mrioc->bars,
4256 mrioc->driver_name)) {
4257 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
4258 retval = -ENODEV;
4259 goto out_failed;
4260 }
4261
4262 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
4263 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4264 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
4265 memap_sz = pci_resource_len(pdev, i);
4266 mrioc->sysif_regs =
4267 ioremap(mrioc->sysif_regs_phys, memap_sz);
4268 break;
4269 }
4270 }
4271
4272 pci_set_master(pdev);
4273
4274 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
4275 if (retval) {
4276 if (dma_mask != DMA_BIT_MASK(32)) {
4277 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
4278 dma_mask = DMA_BIT_MASK(32);
4279 retval = dma_set_mask_and_coherent(&pdev->dev,
4280 dma_mask);
4281 }
4282 if (retval) {
4283 mrioc->dma_mask = 0;
4284 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
4285 goto out_failed;
4286 }
4287 }
4288 mrioc->dma_mask = dma_mask;
4289
4290 if (!mrioc->sysif_regs) {
4291 ioc_err(mrioc,
4292 "Unable to map adapter memory or resource not found\n");
4293 retval = -EINVAL;
4294 goto out_failed;
4295 }
4296
4297 pci_read_config_word(pdev, capb + 2, &message_control);
4298 mrioc->msix_count = (message_control & 0x3FF) + 1;
4299
4300 pci_save_state(pdev);
4301
4302 pci_set_drvdata(pdev, mrioc->shost);
4303
4304 mpi3mr_ioc_disable_intr(mrioc);
4305
4306 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
4307 (unsigned long long)mrioc->sysif_regs_phys,
4308 mrioc->sysif_regs, memap_sz);
4309 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
4310 mrioc->msix_count);
4311
4312 if (!reset_devices && poll_queues > 0)
4313 mrioc->requested_poll_qcount = min_t(int, poll_queues,
4314 mrioc->msix_count - 2);
4315 return retval;
4316
4317 out_failed:
4318 mpi3mr_cleanup_resources(mrioc);
4319 return retval;
4320 }
4321
4322 /**
4323 * mpi3mr_enable_events - Enable required events
4324 * @mrioc: Adapter instance reference
4325 *
4326 * This routine unmasks the events required by the driver by
4327 * sennding appropriate event mask bitmapt through an event
4328 * notification request.
4329 *
4330 * Return: 0 on success and non-zero on failure.
4331 */
mpi3mr_enable_events(struct mpi3mr_ioc * mrioc)4332 static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
4333 {
4334 int retval = 0;
4335 u32 i;
4336
4337 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4338 mrioc->event_masks[i] = -1;
4339
4340 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
4341 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
4342 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
4343 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
4344 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
4345 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
4346 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
4347 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
4348 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
4349 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
4350 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
4351 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
4352 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
4353 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
4354 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DIAGNOSTIC_BUFFER_STATUS_CHANGE);
4355
4356 retval = mpi3mr_issue_event_notification(mrioc);
4357 if (retval)
4358 ioc_err(mrioc, "failed to issue event notification %d\n",
4359 retval);
4360 return retval;
4361 }
4362
4363 /**
4364 * mpi3mr_init_ioc - Initialize the controller
4365 * @mrioc: Adapter instance reference
4366 *
4367 * This the controller initialization routine, executed either
4368 * after soft reset or from pci probe callback.
4369 * Setup the required resources, memory map the controller
4370 * registers, create admin and operational reply queue pairs,
4371 * allocate required memory for reply pool, sense buffer pool,
4372 * issue IOC init request to the firmware, unmask the events and
4373 * issue port enable to discover SAS/SATA/NVMe devies and RAID
4374 * volumes.
4375 *
4376 * Return: 0 on success and non-zero on failure.
4377 */
mpi3mr_init_ioc(struct mpi3mr_ioc * mrioc)4378 int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
4379 {
4380 int retval = 0;
4381 u8 retry = 0;
4382 struct mpi3_ioc_facts_data facts_data;
4383 u32 sz;
4384
4385 retry_init:
4386 retval = mpi3mr_bring_ioc_ready(mrioc);
4387 if (retval) {
4388 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
4389 retval);
4390 goto out_failed_noretry;
4391 }
4392
4393 retval = mpi3mr_setup_isr(mrioc, 1);
4394 if (retval) {
4395 ioc_err(mrioc, "Failed to setup ISR error %d\n",
4396 retval);
4397 goto out_failed_noretry;
4398 }
4399
4400 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4401 if (retval) {
4402 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
4403 retval);
4404 goto out_failed;
4405 }
4406
4407 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
4408 mrioc->shost->max_sectors = mrioc->facts.max_data_length / 512;
4409 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
4410 atomic_set(&mrioc->pend_large_data_sz, 0);
4411
4412 if (reset_devices)
4413 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
4414 MPI3MR_HOST_IOS_KDUMP);
4415
4416 if (!(mrioc->facts.ioc_capabilities &
4417 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_SUPPORTED)) {
4418 mrioc->sas_transport_enabled = 1;
4419 mrioc->scsi_device_channel = 1;
4420 mrioc->shost->max_channel = 1;
4421 mrioc->shost->transportt = mpi3mr_transport_template;
4422 }
4423
4424 if (mrioc->facts.max_req_limit)
4425 mrioc->prevent_reply_qfull = true;
4426
4427 if (mrioc->facts.ioc_capabilities &
4428 MPI3_IOCFACTS_CAPABILITY_SEG_DIAG_TRACE_SUPPORTED)
4429 mrioc->seg_tb_support = true;
4430
4431 mrioc->reply_sz = mrioc->facts.reply_sz;
4432
4433 retval = mpi3mr_check_reset_dma_mask(mrioc);
4434 if (retval) {
4435 ioc_err(mrioc, "Resetting dma mask failed %d\n",
4436 retval);
4437 goto out_failed_noretry;
4438 }
4439
4440 mpi3mr_read_tsu_interval(mrioc);
4441 mpi3mr_print_ioc_info(mrioc);
4442
4443 dprint_init(mrioc, "allocating host diag buffers\n");
4444 mpi3mr_alloc_diag_bufs(mrioc);
4445
4446 dprint_init(mrioc, "allocating ioctl dma buffers\n");
4447 mpi3mr_alloc_ioctl_dma_memory(mrioc);
4448
4449 dprint_init(mrioc, "posting host diag buffers\n");
4450 retval = mpi3mr_post_diag_bufs(mrioc);
4451
4452 if (retval)
4453 ioc_warn(mrioc, "failed to post host diag buffers\n");
4454
4455 if (!mrioc->init_cmds.reply) {
4456 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
4457 if (retval) {
4458 ioc_err(mrioc,
4459 "%s :Failed to allocated reply sense buffers %d\n",
4460 __func__, retval);
4461 goto out_failed_noretry;
4462 }
4463 }
4464
4465 if (!mrioc->chain_sgl_list) {
4466 retval = mpi3mr_alloc_chain_bufs(mrioc);
4467 if (retval) {
4468 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
4469 retval);
4470 goto out_failed_noretry;
4471 }
4472 }
4473
4474 retval = mpi3mr_issue_iocinit(mrioc);
4475 if (retval) {
4476 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
4477 retval);
4478 goto out_failed;
4479 }
4480
4481 retval = mpi3mr_print_pkg_ver(mrioc);
4482 if (retval) {
4483 ioc_err(mrioc, "failed to get package version\n");
4484 goto out_failed;
4485 }
4486
4487 retval = mpi3mr_setup_isr(mrioc, 0);
4488 if (retval) {
4489 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
4490 retval);
4491 goto out_failed_noretry;
4492 }
4493
4494 retval = mpi3mr_create_op_queues(mrioc);
4495 if (retval) {
4496 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
4497 retval);
4498 goto out_failed;
4499 }
4500
4501 if (!mrioc->pel_seqnum_virt) {
4502 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
4503 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4504 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4505 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4506 GFP_KERNEL);
4507 if (!mrioc->pel_seqnum_virt) {
4508 retval = -ENOMEM;
4509 goto out_failed_noretry;
4510 }
4511 }
4512
4513 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
4514 dprint_init(mrioc, "allocating memory for throttle groups\n");
4515 sz = sizeof(struct mpi3mr_throttle_group_info);
4516 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
4517 if (!mrioc->throttle_groups) {
4518 retval = -1;
4519 goto out_failed_noretry;
4520 }
4521 }
4522
4523 retval = mpi3mr_enable_events(mrioc);
4524 if (retval) {
4525 ioc_err(mrioc, "failed to enable events %d\n",
4526 retval);
4527 goto out_failed;
4528 }
4529
4530 retval = mpi3mr_refresh_trigger(mrioc, MPI3_CONFIG_ACTION_READ_CURRENT);
4531 if (retval) {
4532 ioc_err(mrioc, "failed to refresh triggers\n");
4533 goto out_failed;
4534 }
4535
4536 ioc_info(mrioc, "controller initialization completed successfully\n");
4537 return retval;
4538 out_failed:
4539 if (retry < 2) {
4540 retry++;
4541 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
4542 retry);
4543 mpi3mr_memset_buffers(mrioc);
4544 goto retry_init;
4545 }
4546 retval = -1;
4547 out_failed_noretry:
4548 ioc_err(mrioc, "controller initialization failed\n");
4549 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4550 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4551 mrioc->unrecoverable = 1;
4552 return retval;
4553 }
4554
4555 /**
4556 * mpi3mr_reinit_ioc - Re-Initialize the controller
4557 * @mrioc: Adapter instance reference
4558 * @is_resume: Called from resume or reset path
4559 *
4560 * This the controller re-initialization routine, executed from
4561 * the soft reset handler or resume callback. Creates
4562 * operational reply queue pairs, allocate required memory for
4563 * reply pool, sense buffer pool, issue IOC init request to the
4564 * firmware, unmask the events and issue port enable to discover
4565 * SAS/SATA/NVMe devices and RAID volumes.
4566 *
4567 * Return: 0 on success and non-zero on failure.
4568 */
mpi3mr_reinit_ioc(struct mpi3mr_ioc * mrioc,u8 is_resume)4569 int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
4570 {
4571 int retval = 0;
4572 u8 retry = 0;
4573 struct mpi3_ioc_facts_data facts_data;
4574 u32 pe_timeout, ioc_status;
4575
4576 retry_init:
4577 pe_timeout =
4578 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
4579
4580 dprint_reset(mrioc, "bringing up the controller to ready state\n");
4581 retval = mpi3mr_bring_ioc_ready(mrioc);
4582 if (retval) {
4583 ioc_err(mrioc, "failed to bring to ready state\n");
4584 goto out_failed_noretry;
4585 }
4586
4587 mrioc->io_admin_reset_sync = 0;
4588 if (is_resume || mrioc->block_on_pci_err) {
4589 dprint_reset(mrioc, "setting up single ISR\n");
4590 retval = mpi3mr_setup_isr(mrioc, 1);
4591 if (retval) {
4592 ioc_err(mrioc, "failed to setup ISR\n");
4593 goto out_failed_noretry;
4594 }
4595 } else
4596 mpi3mr_ioc_enable_intr(mrioc);
4597
4598 dprint_reset(mrioc, "getting ioc_facts\n");
4599 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
4600 if (retval) {
4601 ioc_err(mrioc, "failed to get ioc_facts\n");
4602 goto out_failed;
4603 }
4604
4605 dprint_reset(mrioc, "validating ioc_facts\n");
4606 retval = mpi3mr_revalidate_factsdata(mrioc);
4607 if (retval) {
4608 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
4609 goto out_failed_noretry;
4610 }
4611
4612 mpi3mr_read_tsu_interval(mrioc);
4613 mpi3mr_print_ioc_info(mrioc);
4614
4615 if (is_resume) {
4616 dprint_reset(mrioc, "posting host diag buffers\n");
4617 retval = mpi3mr_post_diag_bufs(mrioc);
4618 if (retval)
4619 ioc_warn(mrioc, "failed to post host diag buffers\n");
4620 } else {
4621 retval = mpi3mr_repost_diag_bufs(mrioc);
4622 if (retval)
4623 ioc_warn(mrioc, "failed to re post host diag buffers\n");
4624 }
4625
4626 dprint_reset(mrioc, "sending ioc_init\n");
4627 retval = mpi3mr_issue_iocinit(mrioc);
4628 if (retval) {
4629 ioc_err(mrioc, "failed to send ioc_init\n");
4630 goto out_failed;
4631 }
4632
4633 dprint_reset(mrioc, "getting package version\n");
4634 retval = mpi3mr_print_pkg_ver(mrioc);
4635 if (retval) {
4636 ioc_err(mrioc, "failed to get package version\n");
4637 goto out_failed;
4638 }
4639
4640 if (is_resume || mrioc->block_on_pci_err) {
4641 dprint_reset(mrioc, "setting up multiple ISR\n");
4642 retval = mpi3mr_setup_isr(mrioc, 0);
4643 if (retval) {
4644 ioc_err(mrioc, "failed to re-setup ISR\n");
4645 goto out_failed_noretry;
4646 }
4647 }
4648
4649 dprint_reset(mrioc, "creating operational queue pairs\n");
4650 retval = mpi3mr_create_op_queues(mrioc);
4651 if (retval) {
4652 ioc_err(mrioc, "failed to create operational queue pairs\n");
4653 goto out_failed;
4654 }
4655
4656 if (!mrioc->pel_seqnum_virt) {
4657 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4658 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4659 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4660 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4661 GFP_KERNEL);
4662 if (!mrioc->pel_seqnum_virt) {
4663 retval = -ENOMEM;
4664 goto out_failed_noretry;
4665 }
4666 }
4667
4668 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4669 ioc_err(mrioc,
4670 "cannot create minimum number of operational queues expected:%d created:%d\n",
4671 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4672 retval = -1;
4673 goto out_failed_noretry;
4674 }
4675
4676 dprint_reset(mrioc, "enabling events\n");
4677 retval = mpi3mr_enable_events(mrioc);
4678 if (retval) {
4679 ioc_err(mrioc, "failed to enable events\n");
4680 goto out_failed;
4681 }
4682
4683 mrioc->device_refresh_on = 1;
4684 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4685
4686 ioc_info(mrioc, "sending port enable\n");
4687 retval = mpi3mr_issue_port_enable(mrioc, 1);
4688 if (retval) {
4689 ioc_err(mrioc, "failed to issue port enable\n");
4690 goto out_failed;
4691 }
4692 do {
4693 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4694 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4695 break;
4696 if (!pci_device_is_present(mrioc->pdev))
4697 mrioc->unrecoverable = 1;
4698 if (mrioc->unrecoverable) {
4699 retval = -1;
4700 goto out_failed_noretry;
4701 }
4702 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4703 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4704 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4705 mpi3mr_print_fault_info(mrioc);
4706 mrioc->init_cmds.is_waiting = 0;
4707 mrioc->init_cmds.callback = NULL;
4708 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4709 goto out_failed;
4710 }
4711 } while (--pe_timeout);
4712
4713 if (!pe_timeout) {
4714 ioc_err(mrioc, "port enable timed out\n");
4715 mpi3mr_check_rh_fault_ioc(mrioc,
4716 MPI3MR_RESET_FROM_PE_TIMEOUT);
4717 mrioc->init_cmds.is_waiting = 0;
4718 mrioc->init_cmds.callback = NULL;
4719 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4720 goto out_failed;
4721 } else if (mrioc->scan_failed) {
4722 ioc_err(mrioc,
4723 "port enable failed with status=0x%04x\n",
4724 mrioc->scan_failed);
4725 } else
4726 ioc_info(mrioc, "port enable completed successfully\n");
4727
4728 ioc_info(mrioc, "controller %s completed successfully\n",
4729 (is_resume)?"resume":"re-initialization");
4730 return retval;
4731 out_failed:
4732 if (retry < 2) {
4733 retry++;
4734 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4735 (is_resume)?"resume":"re-initialization", retry);
4736 mpi3mr_memset_buffers(mrioc);
4737 goto retry_init;
4738 }
4739 retval = -1;
4740 out_failed_noretry:
4741 ioc_err(mrioc, "controller %s is failed\n",
4742 (is_resume)?"resume":"re-initialization");
4743 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4744 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4745 mrioc->unrecoverable = 1;
4746 return retval;
4747 }
4748
4749 /**
4750 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4751 * segments
4752 * @mrioc: Adapter instance reference
4753 * @qidx: Operational reply queue index
4754 *
4755 * Return: Nothing.
4756 */
mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4757 static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4758 {
4759 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4760 struct segments *segments;
4761 int i, size;
4762
4763 if (!op_reply_q->q_segments)
4764 return;
4765
4766 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4767 segments = op_reply_q->q_segments;
4768 for (i = 0; i < op_reply_q->num_segments; i++)
4769 memset(segments[i].segment, 0, size);
4770 }
4771
4772 /**
4773 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4774 * segments
4775 * @mrioc: Adapter instance reference
4776 * @qidx: Operational request queue index
4777 *
4778 * Return: Nothing.
4779 */
mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc * mrioc,u16 qidx)4780 static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4781 {
4782 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4783 struct segments *segments;
4784 int i, size;
4785
4786 if (!op_req_q->q_segments)
4787 return;
4788
4789 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4790 segments = op_req_q->q_segments;
4791 for (i = 0; i < op_req_q->num_segments; i++)
4792 memset(segments[i].segment, 0, size);
4793 }
4794
4795 /**
4796 * mpi3mr_memset_buffers - memset memory for a controller
4797 * @mrioc: Adapter instance reference
4798 *
4799 * clear all the memory allocated for a controller, typically
4800 * called post reset to reuse the memory allocated during the
4801 * controller init.
4802 *
4803 * Return: Nothing.
4804 */
mpi3mr_memset_buffers(struct mpi3mr_ioc * mrioc)4805 void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4806 {
4807 u16 i;
4808 struct mpi3mr_throttle_group_info *tg;
4809
4810 mrioc->change_count = 0;
4811 mrioc->active_poll_qcount = 0;
4812 mrioc->default_qcount = 0;
4813 if (mrioc->admin_req_base)
4814 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4815 if (mrioc->admin_reply_base)
4816 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4817 atomic_set(&mrioc->admin_reply_q_in_use, 0);
4818 atomic_set(&mrioc->admin_pend_isr, 0);
4819
4820 if (mrioc->init_cmds.reply) {
4821 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4822 memset(mrioc->bsg_cmds.reply, 0,
4823 sizeof(*mrioc->bsg_cmds.reply));
4824 memset(mrioc->host_tm_cmds.reply, 0,
4825 sizeof(*mrioc->host_tm_cmds.reply));
4826 memset(mrioc->pel_cmds.reply, 0,
4827 sizeof(*mrioc->pel_cmds.reply));
4828 memset(mrioc->pel_abort_cmd.reply, 0,
4829 sizeof(*mrioc->pel_abort_cmd.reply));
4830 memset(mrioc->transport_cmds.reply, 0,
4831 sizeof(*mrioc->transport_cmds.reply));
4832 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4833 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4834 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4835 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4836 memset(mrioc->evtack_cmds[i].reply, 0,
4837 sizeof(*mrioc->evtack_cmds[i].reply));
4838 bitmap_clear(mrioc->removepend_bitmap, 0,
4839 mrioc->dev_handle_bitmap_bits);
4840 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
4841 bitmap_clear(mrioc->evtack_cmds_bitmap, 0,
4842 MPI3MR_NUM_EVTACKCMD);
4843 }
4844
4845 for (i = 0; i < mrioc->num_queues; i++) {
4846 if (mrioc->op_reply_qinfo) {
4847 mrioc->op_reply_qinfo[i].qid = 0;
4848 mrioc->op_reply_qinfo[i].ci = 0;
4849 mrioc->op_reply_qinfo[i].num_replies = 0;
4850 mrioc->op_reply_qinfo[i].ephase = 0;
4851 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4852 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4853 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4854 }
4855
4856 if (mrioc->req_qinfo) {
4857 mrioc->req_qinfo[i].ci = 0;
4858 mrioc->req_qinfo[i].pi = 0;
4859 mrioc->req_qinfo[i].num_requests = 0;
4860 mrioc->req_qinfo[i].qid = 0;
4861 mrioc->req_qinfo[i].reply_qid = 0;
4862 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4863 mrioc->req_qinfo[i].last_full_host_tag = 0;
4864 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4865 }
4866 }
4867
4868 atomic_set(&mrioc->pend_large_data_sz, 0);
4869 if (mrioc->throttle_groups) {
4870 tg = mrioc->throttle_groups;
4871 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4872 tg->id = 0;
4873 tg->fw_qd = 0;
4874 tg->modified_qd = 0;
4875 tg->io_divert = 0;
4876 tg->need_qd_reduction = 0;
4877 tg->high = 0;
4878 tg->low = 0;
4879 tg->qd_reduction = 0;
4880 atomic_set(&tg->pend_large_data_sz, 0);
4881 }
4882 }
4883 }
4884
4885 /**
4886 * mpi3mr_free_mem - Free memory allocated for a controller
4887 * @mrioc: Adapter instance reference
4888 *
4889 * Free all the memory allocated for a controller.
4890 *
4891 * Return: Nothing.
4892 */
mpi3mr_free_mem(struct mpi3mr_ioc * mrioc)4893 void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4894 {
4895 u16 i, j;
4896 struct mpi3mr_intr_info *intr_info;
4897 struct diag_buffer_desc *diag_buffer;
4898
4899 mpi3mr_free_enclosure_list(mrioc);
4900 mpi3mr_free_ioctl_dma_memory(mrioc);
4901
4902 if (mrioc->sense_buf_pool) {
4903 if (mrioc->sense_buf)
4904 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4905 mrioc->sense_buf_dma);
4906 dma_pool_destroy(mrioc->sense_buf_pool);
4907 mrioc->sense_buf = NULL;
4908 mrioc->sense_buf_pool = NULL;
4909 }
4910 if (mrioc->sense_buf_q_pool) {
4911 if (mrioc->sense_buf_q)
4912 dma_pool_free(mrioc->sense_buf_q_pool,
4913 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4914 dma_pool_destroy(mrioc->sense_buf_q_pool);
4915 mrioc->sense_buf_q = NULL;
4916 mrioc->sense_buf_q_pool = NULL;
4917 }
4918
4919 if (mrioc->reply_buf_pool) {
4920 if (mrioc->reply_buf)
4921 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4922 mrioc->reply_buf_dma);
4923 dma_pool_destroy(mrioc->reply_buf_pool);
4924 mrioc->reply_buf = NULL;
4925 mrioc->reply_buf_pool = NULL;
4926 }
4927 if (mrioc->reply_free_q_pool) {
4928 if (mrioc->reply_free_q)
4929 dma_pool_free(mrioc->reply_free_q_pool,
4930 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4931 dma_pool_destroy(mrioc->reply_free_q_pool);
4932 mrioc->reply_free_q = NULL;
4933 mrioc->reply_free_q_pool = NULL;
4934 }
4935
4936 for (i = 0; i < mrioc->num_op_req_q; i++)
4937 mpi3mr_free_op_req_q_segments(mrioc, i);
4938
4939 for (i = 0; i < mrioc->num_op_reply_q; i++)
4940 mpi3mr_free_op_reply_q_segments(mrioc, i);
4941
4942 for (i = 0; i < mrioc->intr_info_count; i++) {
4943 intr_info = mrioc->intr_info + i;
4944 intr_info->op_reply_q = NULL;
4945 }
4946
4947 kfree(mrioc->req_qinfo);
4948 mrioc->req_qinfo = NULL;
4949 mrioc->num_op_req_q = 0;
4950
4951 kfree(mrioc->op_reply_qinfo);
4952 mrioc->op_reply_qinfo = NULL;
4953 mrioc->num_op_reply_q = 0;
4954
4955 kfree(mrioc->init_cmds.reply);
4956 mrioc->init_cmds.reply = NULL;
4957
4958 kfree(mrioc->bsg_cmds.reply);
4959 mrioc->bsg_cmds.reply = NULL;
4960
4961 kfree(mrioc->host_tm_cmds.reply);
4962 mrioc->host_tm_cmds.reply = NULL;
4963
4964 kfree(mrioc->pel_cmds.reply);
4965 mrioc->pel_cmds.reply = NULL;
4966
4967 kfree(mrioc->pel_abort_cmd.reply);
4968 mrioc->pel_abort_cmd.reply = NULL;
4969
4970 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4971 kfree(mrioc->evtack_cmds[i].reply);
4972 mrioc->evtack_cmds[i].reply = NULL;
4973 }
4974
4975 bitmap_free(mrioc->removepend_bitmap);
4976 mrioc->removepend_bitmap = NULL;
4977
4978 bitmap_free(mrioc->devrem_bitmap);
4979 mrioc->devrem_bitmap = NULL;
4980
4981 bitmap_free(mrioc->evtack_cmds_bitmap);
4982 mrioc->evtack_cmds_bitmap = NULL;
4983
4984 bitmap_free(mrioc->chain_bitmap);
4985 mrioc->chain_bitmap = NULL;
4986
4987 kfree(mrioc->transport_cmds.reply);
4988 mrioc->transport_cmds.reply = NULL;
4989
4990 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4991 kfree(mrioc->dev_rmhs_cmds[i].reply);
4992 mrioc->dev_rmhs_cmds[i].reply = NULL;
4993 }
4994
4995 if (mrioc->chain_buf_pool) {
4996 for (i = 0; i < mrioc->chain_buf_count; i++) {
4997 if (mrioc->chain_sgl_list[i].addr) {
4998 dma_pool_free(mrioc->chain_buf_pool,
4999 mrioc->chain_sgl_list[i].addr,
5000 mrioc->chain_sgl_list[i].dma_addr);
5001 mrioc->chain_sgl_list[i].addr = NULL;
5002 }
5003 }
5004 dma_pool_destroy(mrioc->chain_buf_pool);
5005 mrioc->chain_buf_pool = NULL;
5006 }
5007
5008 kfree(mrioc->chain_sgl_list);
5009 mrioc->chain_sgl_list = NULL;
5010
5011 if (mrioc->admin_reply_base) {
5012 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
5013 mrioc->admin_reply_base, mrioc->admin_reply_dma);
5014 mrioc->admin_reply_base = NULL;
5015 }
5016 if (mrioc->admin_req_base) {
5017 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
5018 mrioc->admin_req_base, mrioc->admin_req_dma);
5019 mrioc->admin_req_base = NULL;
5020 }
5021
5022 if (mrioc->pel_seqnum_virt) {
5023 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
5024 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
5025 mrioc->pel_seqnum_virt = NULL;
5026 }
5027
5028 for (i = 0; i < MPI3MR_MAX_NUM_HDB; i++) {
5029 diag_buffer = &mrioc->diag_buffers[i];
5030 if ((i == 0) && mrioc->seg_tb_support) {
5031 if (mrioc->trace_buf_pool) {
5032 for (j = 0; j < mrioc->num_tb_segs; j++) {
5033 if (mrioc->trace_buf[j].segment) {
5034 dma_pool_free(mrioc->trace_buf_pool,
5035 mrioc->trace_buf[j].segment,
5036 mrioc->trace_buf[j].segment_dma);
5037 mrioc->trace_buf[j].segment = NULL;
5038 }
5039
5040 mrioc->trace_buf[j].segment = NULL;
5041 }
5042 dma_pool_destroy(mrioc->trace_buf_pool);
5043 mrioc->trace_buf_pool = NULL;
5044 }
5045
5046 kfree(mrioc->trace_buf);
5047 mrioc->trace_buf = NULL;
5048 diag_buffer->size = sizeof(u64) * mrioc->num_tb_segs;
5049 }
5050 if (diag_buffer->addr) {
5051 dma_free_coherent(&mrioc->pdev->dev,
5052 diag_buffer->size, diag_buffer->addr,
5053 diag_buffer->dma_addr);
5054 diag_buffer->addr = NULL;
5055 diag_buffer->size = 0;
5056 diag_buffer->type = 0;
5057 diag_buffer->status = 0;
5058 }
5059 }
5060
5061 kfree(mrioc->throttle_groups);
5062 mrioc->throttle_groups = NULL;
5063
5064 kfree(mrioc->logdata_buf);
5065 mrioc->logdata_buf = NULL;
5066
5067 }
5068
5069 /**
5070 * mpi3mr_issue_ioc_shutdown - shutdown controller
5071 * @mrioc: Adapter instance reference
5072 *
5073 * Send shutodwn notification to the controller and wait for the
5074 * shutdown_timeout for it to be completed.
5075 *
5076 * Return: Nothing.
5077 */
mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc * mrioc)5078 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
5079 {
5080 u32 ioc_config, ioc_status, shutdown_action;
5081 u8 retval = 1, retry = 0;
5082 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10, timeout_remaining = 0;
5083
5084 ioc_info(mrioc, "Issuing shutdown Notification\n");
5085 if (mrioc->unrecoverable) {
5086 ioc_warn(mrioc,
5087 "IOC is unrecoverable shutdown is not issued\n");
5088 return;
5089 }
5090 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
5091 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
5092 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
5093 ioc_info(mrioc, "shutdown already in progress\n");
5094 return;
5095 }
5096
5097 shutdown_action = MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL |
5098 MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
5099 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
5100 ioc_config |= shutdown_action;
5101
5102 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
5103
5104 if (mrioc->facts.shutdown_timeout)
5105 timeout = mrioc->facts.shutdown_timeout * 10;
5106 timeout_remaining = timeout;
5107
5108 do {
5109 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
5110 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
5111 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
5112 retval = 0;
5113 break;
5114 }
5115 if (mrioc->unrecoverable)
5116 break;
5117 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
5118 mpi3mr_print_fault_info(mrioc);
5119 if (retry >= MPI3MR_MAX_SHUTDOWN_RETRY_COUNT)
5120 break;
5121 if (mpi3mr_issue_reset(mrioc,
5122 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
5123 MPI3MR_RESET_FROM_CTLR_CLEANUP))
5124 break;
5125 ioc_config =
5126 readl(&mrioc->sysif_regs->ioc_configuration);
5127 ioc_config |= shutdown_action;
5128 writel(ioc_config,
5129 &mrioc->sysif_regs->ioc_configuration);
5130 timeout_remaining = timeout;
5131 retry++;
5132 }
5133 msleep(100);
5134 } while (--timeout_remaining);
5135
5136 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
5137 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
5138
5139 if (retval) {
5140 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
5141 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
5142 ioc_warn(mrioc,
5143 "shutdown still in progress after timeout\n");
5144 }
5145
5146 ioc_info(mrioc,
5147 "Base IOC Sts/Config after %s shutdown is (0x%08x)/(0x%08x)\n",
5148 (!retval) ? "successful" : "failed", ioc_status,
5149 ioc_config);
5150 }
5151
5152 /**
5153 * mpi3mr_cleanup_ioc - Cleanup controller
5154 * @mrioc: Adapter instance reference
5155 *
5156 * controller cleanup handler, Message unit reset or soft reset
5157 * and shutdown notification is issued to the controller.
5158 *
5159 * Return: Nothing.
5160 */
mpi3mr_cleanup_ioc(struct mpi3mr_ioc * mrioc)5161 void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
5162 {
5163 enum mpi3mr_iocstate ioc_state;
5164
5165 dprint_exit(mrioc, "cleaning up the controller\n");
5166 mpi3mr_ioc_disable_intr(mrioc);
5167
5168 ioc_state = mpi3mr_get_iocstate(mrioc);
5169
5170 if (!mrioc->unrecoverable && !mrioc->reset_in_progress &&
5171 !mrioc->pci_err_recovery &&
5172 (ioc_state == MRIOC_STATE_READY)) {
5173 if (mpi3mr_issue_and_process_mur(mrioc,
5174 MPI3MR_RESET_FROM_CTLR_CLEANUP))
5175 mpi3mr_issue_reset(mrioc,
5176 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
5177 MPI3MR_RESET_FROM_MUR_FAILURE);
5178 mpi3mr_issue_ioc_shutdown(mrioc);
5179 }
5180 dprint_exit(mrioc, "controller cleanup completed\n");
5181 }
5182
5183 /**
5184 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
5185 * @mrioc: Adapter instance reference
5186 * @cmdptr: Internal command tracker
5187 *
5188 * Complete an internal driver commands with state indicating it
5189 * is completed due to reset.
5190 *
5191 * Return: Nothing.
5192 */
mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * cmdptr)5193 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
5194 struct mpi3mr_drv_cmd *cmdptr)
5195 {
5196 if (cmdptr->state & MPI3MR_CMD_PENDING) {
5197 cmdptr->state |= MPI3MR_CMD_RESET;
5198 cmdptr->state &= ~MPI3MR_CMD_PENDING;
5199 if (cmdptr->is_waiting) {
5200 complete(&cmdptr->done);
5201 cmdptr->is_waiting = 0;
5202 } else if (cmdptr->callback)
5203 cmdptr->callback(mrioc, cmdptr);
5204 }
5205 }
5206
5207 /**
5208 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
5209 * @mrioc: Adapter instance reference
5210 *
5211 * Flush all internal driver commands post reset
5212 *
5213 * Return: Nothing.
5214 */
mpi3mr_flush_drv_cmds(struct mpi3mr_ioc * mrioc)5215 void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
5216 {
5217 struct mpi3mr_drv_cmd *cmdptr;
5218 u8 i;
5219
5220 cmdptr = &mrioc->init_cmds;
5221 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5222
5223 cmdptr = &mrioc->cfg_cmds;
5224 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5225
5226 cmdptr = &mrioc->bsg_cmds;
5227 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5228 cmdptr = &mrioc->host_tm_cmds;
5229 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5230
5231 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
5232 cmdptr = &mrioc->dev_rmhs_cmds[i];
5233 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5234 }
5235
5236 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
5237 cmdptr = &mrioc->evtack_cmds[i];
5238 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5239 }
5240
5241 cmdptr = &mrioc->pel_cmds;
5242 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5243
5244 cmdptr = &mrioc->pel_abort_cmd;
5245 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5246
5247 cmdptr = &mrioc->transport_cmds;
5248 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
5249 }
5250
5251 /**
5252 * mpi3mr_pel_wait_post - Issue PEL Wait
5253 * @mrioc: Adapter instance reference
5254 * @drv_cmd: Internal command tracker
5255 *
5256 * Issue PEL Wait MPI request through admin queue and return.
5257 *
5258 * Return: Nothing.
5259 */
mpi3mr_pel_wait_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5260 static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
5261 struct mpi3mr_drv_cmd *drv_cmd)
5262 {
5263 struct mpi3_pel_req_action_wait pel_wait;
5264
5265 mrioc->pel_abort_requested = false;
5266
5267 memset(&pel_wait, 0, sizeof(pel_wait));
5268 drv_cmd->state = MPI3MR_CMD_PENDING;
5269 drv_cmd->is_waiting = 0;
5270 drv_cmd->callback = mpi3mr_pel_wait_complete;
5271 drv_cmd->ioc_status = 0;
5272 drv_cmd->ioc_loginfo = 0;
5273 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5274 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5275 pel_wait.action = MPI3_PEL_ACTION_WAIT;
5276 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
5277 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
5278 pel_wait.class = cpu_to_le16(mrioc->pel_class);
5279 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
5280 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
5281 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
5282
5283 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
5284 dprint_bsg_err(mrioc,
5285 "Issuing PELWait: Admin post failed\n");
5286 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5287 drv_cmd->callback = NULL;
5288 drv_cmd->retry_count = 0;
5289 mrioc->pel_enabled = false;
5290 }
5291 }
5292
5293 /**
5294 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
5295 * @mrioc: Adapter instance reference
5296 * @drv_cmd: Internal command tracker
5297 *
5298 * Issue PEL get sequence number MPI request through admin queue
5299 * and return.
5300 *
5301 * Return: 0 on success, non-zero on failure.
5302 */
mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5303 int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
5304 struct mpi3mr_drv_cmd *drv_cmd)
5305 {
5306 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
5307 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5308 int retval = 0;
5309
5310 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
5311 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
5312 mrioc->pel_cmds.is_waiting = 0;
5313 mrioc->pel_cmds.ioc_status = 0;
5314 mrioc->pel_cmds.ioc_loginfo = 0;
5315 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
5316 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
5317 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
5318 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
5319 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
5320 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
5321
5322 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
5323 sizeof(pel_getseq_req), 0);
5324 if (retval) {
5325 if (drv_cmd) {
5326 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5327 drv_cmd->callback = NULL;
5328 drv_cmd->retry_count = 0;
5329 }
5330 mrioc->pel_enabled = false;
5331 }
5332
5333 return retval;
5334 }
5335
5336 /**
5337 * mpi3mr_pel_wait_complete - PELWait Completion callback
5338 * @mrioc: Adapter instance reference
5339 * @drv_cmd: Internal command tracker
5340 *
5341 * This is a callback handler for the PELWait request and
5342 * firmware completes a PELWait request when it is aborted or a
5343 * new PEL entry is available. This sends AEN to the application
5344 * and if the PELwait completion is not due to PELAbort then
5345 * this will send a request for new PEL Sequence number
5346 *
5347 * Return: Nothing.
5348 */
mpi3mr_pel_wait_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5349 static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
5350 struct mpi3mr_drv_cmd *drv_cmd)
5351 {
5352 struct mpi3_pel_reply *pel_reply = NULL;
5353 u16 ioc_status, pe_log_status;
5354 bool do_retry = false;
5355
5356 if (drv_cmd->state & MPI3MR_CMD_RESET)
5357 goto cleanup_drv_cmd;
5358
5359 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5360 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5361 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
5362 __func__, ioc_status, drv_cmd->ioc_loginfo);
5363 dprint_bsg_err(mrioc,
5364 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5365 ioc_status, drv_cmd->ioc_loginfo);
5366 do_retry = true;
5367 }
5368
5369 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5370 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5371
5372 if (!pel_reply) {
5373 dprint_bsg_err(mrioc,
5374 "pel_wait: failed due to no reply\n");
5375 goto out_failed;
5376 }
5377
5378 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
5379 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
5380 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
5381 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
5382 __func__, pe_log_status);
5383 dprint_bsg_err(mrioc,
5384 "pel_wait: failed due to pel_log_status(0x%04x)\n",
5385 pe_log_status);
5386 do_retry = true;
5387 }
5388
5389 if (do_retry) {
5390 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5391 drv_cmd->retry_count++;
5392 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
5393 drv_cmd->retry_count);
5394 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5395 return;
5396 }
5397 dprint_bsg_err(mrioc,
5398 "pel_wait: failed after all retries(%d)\n",
5399 drv_cmd->retry_count);
5400 goto out_failed;
5401 }
5402 atomic64_inc(&event_counter);
5403 if (!mrioc->pel_abort_requested) {
5404 mrioc->pel_cmds.retry_count = 0;
5405 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
5406 }
5407
5408 return;
5409 out_failed:
5410 mrioc->pel_enabled = false;
5411 cleanup_drv_cmd:
5412 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5413 drv_cmd->callback = NULL;
5414 drv_cmd->retry_count = 0;
5415 }
5416
5417 /**
5418 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
5419 * @mrioc: Adapter instance reference
5420 * @drv_cmd: Internal command tracker
5421 *
5422 * This is a callback handler for the PEL get sequence number
5423 * request and a new PEL wait request will be issued to the
5424 * firmware from this
5425 *
5426 * Return: Nothing.
5427 */
mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc * mrioc,struct mpi3mr_drv_cmd * drv_cmd)5428 void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
5429 struct mpi3mr_drv_cmd *drv_cmd)
5430 {
5431 struct mpi3_pel_reply *pel_reply = NULL;
5432 struct mpi3_pel_seq *pel_seqnum_virt;
5433 u16 ioc_status;
5434 bool do_retry = false;
5435
5436 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
5437
5438 if (drv_cmd->state & MPI3MR_CMD_RESET)
5439 goto cleanup_drv_cmd;
5440
5441 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5442 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5443 dprint_bsg_err(mrioc,
5444 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
5445 ioc_status, drv_cmd->ioc_loginfo);
5446 do_retry = true;
5447 }
5448
5449 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
5450 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
5451 if (!pel_reply) {
5452 dprint_bsg_err(mrioc,
5453 "pel_get_seqnum: failed due to no reply\n");
5454 goto out_failed;
5455 }
5456
5457 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
5458 dprint_bsg_err(mrioc,
5459 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
5460 le16_to_cpu(pel_reply->pe_log_status));
5461 do_retry = true;
5462 }
5463
5464 if (do_retry) {
5465 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
5466 drv_cmd->retry_count++;
5467 dprint_bsg_err(mrioc,
5468 "pel_get_seqnum: retrying(%d)\n",
5469 drv_cmd->retry_count);
5470 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
5471 return;
5472 }
5473
5474 dprint_bsg_err(mrioc,
5475 "pel_get_seqnum: failed after all retries(%d)\n",
5476 drv_cmd->retry_count);
5477 goto out_failed;
5478 }
5479 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
5480 drv_cmd->retry_count = 0;
5481 mpi3mr_pel_wait_post(mrioc, drv_cmd);
5482
5483 return;
5484 out_failed:
5485 mrioc->pel_enabled = false;
5486 cleanup_drv_cmd:
5487 drv_cmd->state = MPI3MR_CMD_NOTUSED;
5488 drv_cmd->callback = NULL;
5489 drv_cmd->retry_count = 0;
5490 }
5491
5492 /**
5493 * mpi3mr_check_op_admin_proc -
5494 * @mrioc: Adapter instance reference
5495 *
5496 * Check if any of the operation reply queues
5497 * or the admin reply queue are currently in use.
5498 * If any queue is in use, this function waits for
5499 * a maximum of 10 seconds for them to become available.
5500 *
5501 * Return: 0 on success, non-zero on failure.
5502 */
mpi3mr_check_op_admin_proc(struct mpi3mr_ioc * mrioc)5503 static int mpi3mr_check_op_admin_proc(struct mpi3mr_ioc *mrioc)
5504 {
5505
5506 u16 timeout = 10 * 10;
5507 u16 elapsed_time = 0;
5508 bool op_admin_in_use = false;
5509
5510 do {
5511 op_admin_in_use = false;
5512
5513 /* Check admin_reply queue first to exit early */
5514 if (atomic_read(&mrioc->admin_reply_q_in_use) == 1)
5515 op_admin_in_use = true;
5516 else {
5517 /* Check op_reply queues */
5518 int i;
5519
5520 for (i = 0; i < mrioc->num_queues; i++) {
5521 if (atomic_read(&mrioc->op_reply_qinfo[i].in_use) == 1) {
5522 op_admin_in_use = true;
5523 break;
5524 }
5525 }
5526 }
5527
5528 if (!op_admin_in_use)
5529 break;
5530
5531 msleep(100);
5532
5533 } while (++elapsed_time < timeout);
5534
5535 if (op_admin_in_use)
5536 return 1;
5537
5538 return 0;
5539 }
5540
5541 /**
5542 * mpi3mr_soft_reset_handler - Reset the controller
5543 * @mrioc: Adapter instance reference
5544 * @reset_reason: Reset reason code
5545 * @snapdump: Flag to generate snapdump in firmware or not
5546 *
5547 * This is an handler for recovering controller by issuing soft
5548 * reset are diag fault reset. This is a blocking function and
5549 * when one reset is executed if any other resets they will be
5550 * blocked. All BSG requests will be blocked during the reset. If
5551 * controller reset is successful then the controller will be
5552 * reinitalized, otherwise the controller will be marked as not
5553 * recoverable
5554 *
5555 * In snapdump bit is set, the controller is issued with diag
5556 * fault reset so that the firmware can create a snap dump and
5557 * post that the firmware will result in F000 fault and the
5558 * driver will issue soft reset to recover from that.
5559 *
5560 * Return: 0 on success, non-zero on failure.
5561 */
mpi3mr_soft_reset_handler(struct mpi3mr_ioc * mrioc,u16 reset_reason,u8 snapdump)5562 int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
5563 u16 reset_reason, u8 snapdump)
5564 {
5565 int retval = 0, i;
5566 unsigned long flags;
5567 enum mpi3mr_iocstate ioc_state;
5568 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
5569 union mpi3mr_trigger_data trigger_data;
5570
5571 /* Block the reset handler until diag save in progress*/
5572 dprint_reset(mrioc,
5573 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
5574 mrioc->diagsave_timeout);
5575 while (mrioc->diagsave_timeout)
5576 ssleep(1);
5577 /*
5578 * Block new resets until the currently executing one is finished and
5579 * return the status of the existing reset for all blocked resets
5580 */
5581 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
5582 if (!mutex_trylock(&mrioc->reset_mutex)) {
5583 ioc_info(mrioc,
5584 "controller reset triggered by %s is blocked due to another reset in progress\n",
5585 mpi3mr_reset_rc_name(reset_reason));
5586 do {
5587 ssleep(1);
5588 } while (mrioc->reset_in_progress == 1);
5589 ioc_info(mrioc,
5590 "returning previous reset result(%d) for the reset triggered by %s\n",
5591 mrioc->prev_reset_result,
5592 mpi3mr_reset_rc_name(reset_reason));
5593 return mrioc->prev_reset_result;
5594 }
5595 ioc_info(mrioc, "controller reset is triggered by %s\n",
5596 mpi3mr_reset_rc_name(reset_reason));
5597
5598 mrioc->device_refresh_on = 0;
5599 scsi_block_requests(mrioc->shost);
5600 mrioc->reset_in_progress = 1;
5601 mrioc->stop_bsgs = 1;
5602 mrioc->prev_reset_result = -1;
5603 memset(&trigger_data, 0, sizeof(trigger_data));
5604
5605 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
5606 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
5607 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
5608 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5609 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5610 dprint_reset(mrioc,
5611 "soft_reset_handler: releasing host diagnostic buffers\n");
5612 mpi3mr_release_diag_bufs(mrioc, 0);
5613 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
5614 mrioc->event_masks[i] = -1;
5615
5616 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
5617 mpi3mr_issue_event_notification(mrioc);
5618 }
5619
5620 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
5621
5622 mpi3mr_ioc_disable_intr(mrioc);
5623 mrioc->io_admin_reset_sync = 1;
5624
5625 if (snapdump) {
5626 retval = mpi3mr_issue_reset(mrioc,
5627 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5628 if (!retval) {
5629 trigger_data.fault = (readl(&mrioc->sysif_regs->fault) &
5630 MPI3_SYSIF_FAULT_CODE_MASK);
5631 do {
5632 host_diagnostic =
5633 readl(&mrioc->sysif_regs->host_diagnostic);
5634 if (!(host_diagnostic &
5635 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
5636 break;
5637 msleep(100);
5638 } while (--timeout);
5639
5640 mpi3mr_save_fault_info(mrioc);
5641 mpi3mr_fault_uevent_emit(mrioc);
5642 mrioc->fwfault_counter++;
5643 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5644 MPI3MR_HDB_TRIGGER_TYPE_FAULT, &trigger_data, 0);
5645 }
5646 }
5647
5648 retval = mpi3mr_issue_reset(mrioc,
5649 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
5650 if (retval) {
5651 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
5652 goto out;
5653 }
5654
5655 retval = mpi3mr_check_op_admin_proc(mrioc);
5656 if (retval) {
5657 ioc_err(mrioc, "Soft reset failed due to an Admin or I/O queue polling\n"
5658 "thread still processing replies even after a 10 second\n"
5659 "timeout. Marking the controller as unrecoverable!\n");
5660
5661 goto out;
5662 }
5663
5664 if (mrioc->num_io_throttle_group !=
5665 mrioc->facts.max_io_throttle_group) {
5666 ioc_err(mrioc,
5667 "max io throttle group doesn't match old(%d), new(%d)\n",
5668 mrioc->num_io_throttle_group,
5669 mrioc->facts.max_io_throttle_group);
5670 retval = -EPERM;
5671 goto out;
5672 }
5673
5674 mpi3mr_flush_delayed_cmd_lists(mrioc);
5675 mpi3mr_flush_drv_cmds(mrioc);
5676 bitmap_clear(mrioc->devrem_bitmap, 0, MPI3MR_NUM_DEVRMCMD);
5677 bitmap_clear(mrioc->removepend_bitmap, 0,
5678 mrioc->dev_handle_bitmap_bits);
5679 bitmap_clear(mrioc->evtack_cmds_bitmap, 0, MPI3MR_NUM_EVTACKCMD);
5680 mpi3mr_flush_host_io(mrioc);
5681 mpi3mr_cleanup_fwevt_list(mrioc);
5682 mpi3mr_invalidate_devhandles(mrioc);
5683 mpi3mr_free_enclosure_list(mrioc);
5684
5685 if (mrioc->prepare_for_reset) {
5686 mrioc->prepare_for_reset = 0;
5687 mrioc->prepare_for_reset_timeout_counter = 0;
5688 }
5689 mpi3mr_memset_buffers(mrioc);
5690 mpi3mr_release_diag_bufs(mrioc, 1);
5691 mrioc->fw_release_trigger_active = false;
5692 mrioc->trace_release_trigger_active = false;
5693 mrioc->snapdump_trigger_active = false;
5694 mpi3mr_set_trigger_data_in_all_hdb(mrioc,
5695 MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET, NULL, 0);
5696
5697 dprint_reset(mrioc,
5698 "soft_reset_handler: reinitializing the controller\n");
5699 retval = mpi3mr_reinit_ioc(mrioc, 0);
5700 if (retval) {
5701 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
5702 mrioc->name, reset_reason);
5703 goto out;
5704 }
5705 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
5706
5707 out:
5708 mrioc->invalid_io_comp = 0;
5709 if (!retval) {
5710 mrioc->diagsave_timeout = 0;
5711 mrioc->reset_in_progress = 0;
5712 scsi_unblock_requests(mrioc->shost);
5713 mrioc->pel_abort_requested = 0;
5714 if (mrioc->pel_enabled) {
5715 mrioc->pel_cmds.retry_count = 0;
5716 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
5717 }
5718
5719 mrioc->device_refresh_on = 0;
5720
5721 mrioc->ts_update_counter = 0;
5722 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
5723 if (mrioc->watchdog_work_q)
5724 queue_delayed_work(mrioc->watchdog_work_q,
5725 &mrioc->watchdog_work,
5726 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
5727 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
5728 mrioc->stop_bsgs = 0;
5729 if (mrioc->pel_enabled)
5730 atomic64_inc(&event_counter);
5731 } else {
5732 dprint_reset(mrioc,
5733 "soft_reset_handler failed, marking controller as unrecoverable\n");
5734 ioc_state = mpi3mr_get_iocstate(mrioc);
5735
5736 if (ioc_state != MRIOC_STATE_FAULT)
5737 mpi3mr_issue_reset(mrioc,
5738 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
5739 mrioc->device_refresh_on = 0;
5740 mrioc->unrecoverable = 1;
5741 mrioc->reset_in_progress = 0;
5742 scsi_unblock_requests(mrioc->shost);
5743 mrioc->stop_bsgs = 0;
5744 retval = -1;
5745 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
5746 }
5747 mrioc->prev_reset_result = retval;
5748 mutex_unlock(&mrioc->reset_mutex);
5749 ioc_info(mrioc, "controller reset is %s\n",
5750 ((retval == 0) ? "successful" : "failed"));
5751 return retval;
5752 }
5753
5754 /**
5755 * mpi3mr_post_cfg_req - Issue config requests and wait
5756 * @mrioc: Adapter instance reference
5757 * @cfg_req: Configuration request
5758 * @timeout: Timeout in seconds
5759 * @ioc_status: Pointer to return ioc status
5760 *
5761 * A generic function for posting MPI3 configuration request to
5762 * the firmware. This blocks for the completion of request for
5763 * timeout seconds and if the request times out this function
5764 * faults the controller with proper reason code.
5765 *
5766 * On successful completion of the request this function returns
5767 * appropriate ioc status from the firmware back to the caller.
5768 *
5769 * Return: 0 on success, non-zero on failure.
5770 */
mpi3mr_post_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,int timeout,u16 * ioc_status)5771 static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5772 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5773 {
5774 int retval = 0;
5775
5776 mutex_lock(&mrioc->cfg_cmds.mutex);
5777 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5778 retval = -1;
5779 ioc_err(mrioc, "sending config request failed due to command in use\n");
5780 mutex_unlock(&mrioc->cfg_cmds.mutex);
5781 goto out;
5782 }
5783 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5784 mrioc->cfg_cmds.is_waiting = 1;
5785 mrioc->cfg_cmds.callback = NULL;
5786 mrioc->cfg_cmds.ioc_status = 0;
5787 mrioc->cfg_cmds.ioc_loginfo = 0;
5788
5789 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5790 cfg_req->function = MPI3_FUNCTION_CONFIG;
5791
5792 init_completion(&mrioc->cfg_cmds.done);
5793 dprint_cfg_info(mrioc, "posting config request\n");
5794 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5795 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5796 "mpi3_cfg_req");
5797 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5798 if (retval) {
5799 ioc_err(mrioc, "posting config request failed\n");
5800 goto out_unlock;
5801 }
5802 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5803 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5804 mpi3mr_check_rh_fault_ioc(mrioc,
5805 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5806 ioc_err(mrioc, "config request timed out\n");
5807 retval = -1;
5808 goto out_unlock;
5809 }
5810 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5811 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5812 dprint_cfg_err(mrioc,
5813 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5814 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5815
5816 out_unlock:
5817 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5818 mutex_unlock(&mrioc->cfg_cmds.mutex);
5819
5820 out:
5821 return retval;
5822 }
5823
5824 /**
5825 * mpi3mr_process_cfg_req - config page request processor
5826 * @mrioc: Adapter instance reference
5827 * @cfg_req: Configuration request
5828 * @cfg_hdr: Configuration page header
5829 * @timeout: Timeout in seconds
5830 * @ioc_status: Pointer to return ioc status
5831 * @cfg_buf: Memory pointer to copy config page or header
5832 * @cfg_buf_sz: Size of the memory to get config page or header
5833 *
5834 * This is handler for config page read, write and config page
5835 * header read operations.
5836 *
5837 * This function expects the cfg_req to be populated with page
5838 * type, page number, action for the header read and with page
5839 * address for all other operations.
5840 *
5841 * The cfg_hdr can be passed as null for reading required header
5842 * details for read/write pages the cfg_hdr should point valid
5843 * configuration page header.
5844 *
5845 * This allocates dmaable memory based on the size of the config
5846 * buffer and set the SGE of the cfg_req.
5847 *
5848 * For write actions, the config page data has to be passed in
5849 * the cfg_buf and size of the data has to be mentioned in the
5850 * cfg_buf_sz.
5851 *
5852 * For read/header actions, on successful completion of the
5853 * request with successful ioc_status the data will be copied
5854 * into the cfg_buf limited to a minimum of actual page size and
5855 * cfg_buf_sz
5856 *
5857 *
5858 * Return: 0 on success, non-zero on failure.
5859 */
mpi3mr_process_cfg_req(struct mpi3mr_ioc * mrioc,struct mpi3_config_request * cfg_req,struct mpi3_config_page_header * cfg_hdr,int timeout,u16 * ioc_status,void * cfg_buf,u32 cfg_buf_sz)5860 static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5861 struct mpi3_config_request *cfg_req,
5862 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5863 void *cfg_buf, u32 cfg_buf_sz)
5864 {
5865 struct dma_memory_desc mem_desc;
5866 int retval = -1;
5867 u8 invalid_action = 0;
5868 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5869
5870 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5871
5872 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5873 mem_desc.size = sizeof(struct mpi3_config_page_header);
5874 else {
5875 if (!cfg_hdr) {
5876 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5877 cfg_req->action, cfg_req->page_type,
5878 cfg_req->page_number);
5879 goto out;
5880 }
5881 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5882 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5883 if (cfg_req->action
5884 != MPI3_CONFIG_ACTION_READ_CURRENT)
5885 invalid_action = 1;
5886 break;
5887 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5888 if ((cfg_req->action ==
5889 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5890 (cfg_req->action ==
5891 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5892 invalid_action = 1;
5893 break;
5894 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5895 default:
5896 break;
5897 }
5898 if (invalid_action) {
5899 ioc_err(mrioc,
5900 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5901 cfg_req->action, cfg_req->page_type,
5902 cfg_req->page_number, cfg_hdr->page_attribute);
5903 goto out;
5904 }
5905 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5906 cfg_req->page_length = cfg_hdr->page_length;
5907 cfg_req->page_version = cfg_hdr->page_version;
5908 }
5909
5910 mem_desc.addr = dma_alloc_coherent(&mrioc->pdev->dev,
5911 mem_desc.size, &mem_desc.dma_addr, GFP_KERNEL);
5912
5913 if (!mem_desc.addr)
5914 return retval;
5915
5916 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5917 mem_desc.dma_addr);
5918
5919 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5920 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5921 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5922 cfg_buf_sz));
5923 dprint_cfg_info(mrioc, "config buffer to be written\n");
5924 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5925 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5926 }
5927
5928 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5929 goto out;
5930
5931 retval = 0;
5932 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5933 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5934 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5935 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5936 cfg_buf_sz));
5937 dprint_cfg_info(mrioc, "config buffer read\n");
5938 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5939 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5940 }
5941
5942 out:
5943 if (mem_desc.addr) {
5944 dma_free_coherent(&mrioc->pdev->dev, mem_desc.size,
5945 mem_desc.addr, mem_desc.dma_addr);
5946 mem_desc.addr = NULL;
5947 }
5948
5949 return retval;
5950 }
5951
5952 /**
5953 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5954 * @mrioc: Adapter instance reference
5955 * @ioc_status: Pointer to return ioc status
5956 * @dev_pg0: Pointer to return device page 0
5957 * @pg_sz: Size of the memory allocated to the page pointer
5958 * @form: The form to be used for addressing the page
5959 * @form_spec: Form specific information like device handle
5960 *
5961 * This is handler for config page read for a specific device
5962 * page0. The ioc_status has the controller returned ioc_status.
5963 * This routine doesn't check ioc_status to decide whether the
5964 * page read is success or not and it is the callers
5965 * responsibility.
5966 *
5967 * Return: 0 on success, non-zero on failure.
5968 */
mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_device_page0 * dev_pg0,u16 pg_sz,u32 form,u32 form_spec)5969 int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5970 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5971 {
5972 struct mpi3_config_page_header cfg_hdr;
5973 struct mpi3_config_request cfg_req;
5974 u32 page_address;
5975
5976 memset(dev_pg0, 0, pg_sz);
5977 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5978 memset(&cfg_req, 0, sizeof(cfg_req));
5979
5980 cfg_req.function = MPI3_FUNCTION_CONFIG;
5981 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5982 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5983 cfg_req.page_number = 0;
5984 cfg_req.page_address = 0;
5985
5986 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5987 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5988 ioc_err(mrioc, "device page0 header read failed\n");
5989 goto out_failed;
5990 }
5991 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5992 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5993 *ioc_status);
5994 goto out_failed;
5995 }
5996 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5997 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5998 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5999 cfg_req.page_address = cpu_to_le32(page_address);
6000 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6001 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
6002 ioc_err(mrioc, "device page0 read failed\n");
6003 goto out_failed;
6004 }
6005 return 0;
6006 out_failed:
6007 return -1;
6008 }
6009
6010
6011 /**
6012 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
6013 * @mrioc: Adapter instance reference
6014 * @ioc_status: Pointer to return ioc status
6015 * @phy_pg0: Pointer to return SAS Phy page 0
6016 * @pg_sz: Size of the memory allocated to the page pointer
6017 * @form: The form to be used for addressing the page
6018 * @form_spec: Form specific information like phy number
6019 *
6020 * This is handler for config page read for a specific SAS Phy
6021 * page0. The ioc_status has the controller returned ioc_status.
6022 * This routine doesn't check ioc_status to decide whether the
6023 * page read is success or not and it is the callers
6024 * responsibility.
6025 *
6026 * Return: 0 on success, non-zero on failure.
6027 */
mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page0 * phy_pg0,u16 pg_sz,u32 form,u32 form_spec)6028 int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6029 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
6030 u32 form_spec)
6031 {
6032 struct mpi3_config_page_header cfg_hdr;
6033 struct mpi3_config_request cfg_req;
6034 u32 page_address;
6035
6036 memset(phy_pg0, 0, pg_sz);
6037 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6038 memset(&cfg_req, 0, sizeof(cfg_req));
6039
6040 cfg_req.function = MPI3_FUNCTION_CONFIG;
6041 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6042 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
6043 cfg_req.page_number = 0;
6044 cfg_req.page_address = 0;
6045
6046 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6047 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6048 ioc_err(mrioc, "sas phy page0 header read failed\n");
6049 goto out_failed;
6050 }
6051 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6052 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
6053 *ioc_status);
6054 goto out_failed;
6055 }
6056 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6057 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
6058 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
6059 cfg_req.page_address = cpu_to_le32(page_address);
6060 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6061 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
6062 ioc_err(mrioc, "sas phy page0 read failed\n");
6063 goto out_failed;
6064 }
6065 return 0;
6066 out_failed:
6067 return -1;
6068 }
6069
6070 /**
6071 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
6072 * @mrioc: Adapter instance reference
6073 * @ioc_status: Pointer to return ioc status
6074 * @phy_pg1: Pointer to return SAS Phy page 1
6075 * @pg_sz: Size of the memory allocated to the page pointer
6076 * @form: The form to be used for addressing the page
6077 * @form_spec: Form specific information like phy number
6078 *
6079 * This is handler for config page read for a specific SAS Phy
6080 * page1. The ioc_status has the controller returned ioc_status.
6081 * This routine doesn't check ioc_status to decide whether the
6082 * page read is success or not and it is the callers
6083 * responsibility.
6084 *
6085 * Return: 0 on success, non-zero on failure.
6086 */
mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_phy_page1 * phy_pg1,u16 pg_sz,u32 form,u32 form_spec)6087 int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6088 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
6089 u32 form_spec)
6090 {
6091 struct mpi3_config_page_header cfg_hdr;
6092 struct mpi3_config_request cfg_req;
6093 u32 page_address;
6094
6095 memset(phy_pg1, 0, pg_sz);
6096 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6097 memset(&cfg_req, 0, sizeof(cfg_req));
6098
6099 cfg_req.function = MPI3_FUNCTION_CONFIG;
6100 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6101 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
6102 cfg_req.page_number = 1;
6103 cfg_req.page_address = 0;
6104
6105 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6106 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6107 ioc_err(mrioc, "sas phy page1 header read failed\n");
6108 goto out_failed;
6109 }
6110 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6111 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
6112 *ioc_status);
6113 goto out_failed;
6114 }
6115 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6116 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
6117 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
6118 cfg_req.page_address = cpu_to_le32(page_address);
6119 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6120 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
6121 ioc_err(mrioc, "sas phy page1 read failed\n");
6122 goto out_failed;
6123 }
6124 return 0;
6125 out_failed:
6126 return -1;
6127 }
6128
6129
6130 /**
6131 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
6132 * @mrioc: Adapter instance reference
6133 * @ioc_status: Pointer to return ioc status
6134 * @exp_pg0: Pointer to return SAS Expander page 0
6135 * @pg_sz: Size of the memory allocated to the page pointer
6136 * @form: The form to be used for addressing the page
6137 * @form_spec: Form specific information like device handle
6138 *
6139 * This is handler for config page read for a specific SAS
6140 * Expander page0. The ioc_status has the controller returned
6141 * ioc_status. This routine doesn't check ioc_status to decide
6142 * whether the page read is success or not and it is the callers
6143 * responsibility.
6144 *
6145 * Return: 0 on success, non-zero on failure.
6146 */
mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page0 * exp_pg0,u16 pg_sz,u32 form,u32 form_spec)6147 int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6148 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
6149 u32 form_spec)
6150 {
6151 struct mpi3_config_page_header cfg_hdr;
6152 struct mpi3_config_request cfg_req;
6153 u32 page_address;
6154
6155 memset(exp_pg0, 0, pg_sz);
6156 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6157 memset(&cfg_req, 0, sizeof(cfg_req));
6158
6159 cfg_req.function = MPI3_FUNCTION_CONFIG;
6160 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6161 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
6162 cfg_req.page_number = 0;
6163 cfg_req.page_address = 0;
6164
6165 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6166 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6167 ioc_err(mrioc, "expander page0 header read failed\n");
6168 goto out_failed;
6169 }
6170 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6171 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
6172 *ioc_status);
6173 goto out_failed;
6174 }
6175 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6176 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
6177 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
6178 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
6179 cfg_req.page_address = cpu_to_le32(page_address);
6180 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6181 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
6182 ioc_err(mrioc, "expander page0 read failed\n");
6183 goto out_failed;
6184 }
6185 return 0;
6186 out_failed:
6187 return -1;
6188 }
6189
6190 /**
6191 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
6192 * @mrioc: Adapter instance reference
6193 * @ioc_status: Pointer to return ioc status
6194 * @exp_pg1: Pointer to return SAS Expander page 1
6195 * @pg_sz: Size of the memory allocated to the page pointer
6196 * @form: The form to be used for addressing the page
6197 * @form_spec: Form specific information like phy number
6198 *
6199 * This is handler for config page read for a specific SAS
6200 * Expander page1. The ioc_status has the controller returned
6201 * ioc_status. This routine doesn't check ioc_status to decide
6202 * whether the page read is success or not and it is the callers
6203 * responsibility.
6204 *
6205 * Return: 0 on success, non-zero on failure.
6206 */
mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_sas_expander_page1 * exp_pg1,u16 pg_sz,u32 form,u32 form_spec)6207 int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6208 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
6209 u32 form_spec)
6210 {
6211 struct mpi3_config_page_header cfg_hdr;
6212 struct mpi3_config_request cfg_req;
6213 u32 page_address;
6214
6215 memset(exp_pg1, 0, pg_sz);
6216 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6217 memset(&cfg_req, 0, sizeof(cfg_req));
6218
6219 cfg_req.function = MPI3_FUNCTION_CONFIG;
6220 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6221 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
6222 cfg_req.page_number = 1;
6223 cfg_req.page_address = 0;
6224
6225 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6226 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6227 ioc_err(mrioc, "expander page1 header read failed\n");
6228 goto out_failed;
6229 }
6230 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6231 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
6232 *ioc_status);
6233 goto out_failed;
6234 }
6235 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6236 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
6237 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
6238 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
6239 cfg_req.page_address = cpu_to_le32(page_address);
6240 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6241 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
6242 ioc_err(mrioc, "expander page1 read failed\n");
6243 goto out_failed;
6244 }
6245 return 0;
6246 out_failed:
6247 return -1;
6248 }
6249
6250 /**
6251 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
6252 * @mrioc: Adapter instance reference
6253 * @ioc_status: Pointer to return ioc status
6254 * @encl_pg0: Pointer to return Enclosure page 0
6255 * @pg_sz: Size of the memory allocated to the page pointer
6256 * @form: The form to be used for addressing the page
6257 * @form_spec: Form specific information like device handle
6258 *
6259 * This is handler for config page read for a specific Enclosure
6260 * page0. The ioc_status has the controller returned ioc_status.
6261 * This routine doesn't check ioc_status to decide whether the
6262 * page read is success or not and it is the callers
6263 * responsibility.
6264 *
6265 * Return: 0 on success, non-zero on failure.
6266 */
mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc * mrioc,u16 * ioc_status,struct mpi3_enclosure_page0 * encl_pg0,u16 pg_sz,u32 form,u32 form_spec)6267 int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
6268 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
6269 u32 form_spec)
6270 {
6271 struct mpi3_config_page_header cfg_hdr;
6272 struct mpi3_config_request cfg_req;
6273 u32 page_address;
6274
6275 memset(encl_pg0, 0, pg_sz);
6276 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6277 memset(&cfg_req, 0, sizeof(cfg_req));
6278
6279 cfg_req.function = MPI3_FUNCTION_CONFIG;
6280 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6281 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
6282 cfg_req.page_number = 0;
6283 cfg_req.page_address = 0;
6284
6285 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6286 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6287 ioc_err(mrioc, "enclosure page0 header read failed\n");
6288 goto out_failed;
6289 }
6290 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6291 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
6292 *ioc_status);
6293 goto out_failed;
6294 }
6295 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6296 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
6297 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
6298 cfg_req.page_address = cpu_to_le32(page_address);
6299 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6300 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
6301 ioc_err(mrioc, "enclosure page0 read failed\n");
6302 goto out_failed;
6303 }
6304 return 0;
6305 out_failed:
6306 return -1;
6307 }
6308
6309
6310 /**
6311 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
6312 * @mrioc: Adapter instance reference
6313 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
6314 * @pg_sz: Size of the memory allocated to the page pointer
6315 *
6316 * This is handler for config page read for the SAS IO Unit
6317 * page0. This routine checks ioc_status to decide whether the
6318 * page read is success or not.
6319 *
6320 * Return: 0 on success, non-zero on failure.
6321 */
mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page0 * sas_io_unit_pg0,u16 pg_sz)6322 int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
6323 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
6324 {
6325 struct mpi3_config_page_header cfg_hdr;
6326 struct mpi3_config_request cfg_req;
6327 u16 ioc_status = 0;
6328
6329 memset(sas_io_unit_pg0, 0, pg_sz);
6330 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6331 memset(&cfg_req, 0, sizeof(cfg_req));
6332
6333 cfg_req.function = MPI3_FUNCTION_CONFIG;
6334 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6335 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6336 cfg_req.page_number = 0;
6337 cfg_req.page_address = 0;
6338
6339 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6340 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6341 ioc_err(mrioc, "sas io unit page0 header read failed\n");
6342 goto out_failed;
6343 }
6344 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6345 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
6346 ioc_status);
6347 goto out_failed;
6348 }
6349 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6350
6351 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6352 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
6353 ioc_err(mrioc, "sas io unit page0 read failed\n");
6354 goto out_failed;
6355 }
6356 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6357 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
6358 ioc_status);
6359 goto out_failed;
6360 }
6361 return 0;
6362 out_failed:
6363 return -1;
6364 }
6365
6366 /**
6367 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
6368 * @mrioc: Adapter instance reference
6369 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
6370 * @pg_sz: Size of the memory allocated to the page pointer
6371 *
6372 * This is handler for config page read for the SAS IO Unit
6373 * page1. This routine checks ioc_status to decide whether the
6374 * page read is success or not.
6375 *
6376 * Return: 0 on success, non-zero on failure.
6377 */
mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6378 int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6379 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6380 {
6381 struct mpi3_config_page_header cfg_hdr;
6382 struct mpi3_config_request cfg_req;
6383 u16 ioc_status = 0;
6384
6385 memset(sas_io_unit_pg1, 0, pg_sz);
6386 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6387 memset(&cfg_req, 0, sizeof(cfg_req));
6388
6389 cfg_req.function = MPI3_FUNCTION_CONFIG;
6390 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6391 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6392 cfg_req.page_number = 1;
6393 cfg_req.page_address = 0;
6394
6395 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6396 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6397 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6398 goto out_failed;
6399 }
6400 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6401 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6402 ioc_status);
6403 goto out_failed;
6404 }
6405 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6406
6407 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6408 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6409 ioc_err(mrioc, "sas io unit page1 read failed\n");
6410 goto out_failed;
6411 }
6412 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6413 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
6414 ioc_status);
6415 goto out_failed;
6416 }
6417 return 0;
6418 out_failed:
6419 return -1;
6420 }
6421
6422 /**
6423 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
6424 * @mrioc: Adapter instance reference
6425 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
6426 * @pg_sz: Size of the memory allocated to the page pointer
6427 *
6428 * This is handler for config page write for the SAS IO Unit
6429 * page1. This routine checks ioc_status to decide whether the
6430 * page read is success or not. This will modify both current
6431 * and persistent page.
6432 *
6433 * Return: 0 on success, non-zero on failure.
6434 */
mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_sas_io_unit_page1 * sas_io_unit_pg1,u16 pg_sz)6435 int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
6436 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
6437 {
6438 struct mpi3_config_page_header cfg_hdr;
6439 struct mpi3_config_request cfg_req;
6440 u16 ioc_status = 0;
6441
6442 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6443 memset(&cfg_req, 0, sizeof(cfg_req));
6444
6445 cfg_req.function = MPI3_FUNCTION_CONFIG;
6446 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6447 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
6448 cfg_req.page_number = 1;
6449 cfg_req.page_address = 0;
6450
6451 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6452 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6453 ioc_err(mrioc, "sas io unit page1 header read failed\n");
6454 goto out_failed;
6455 }
6456 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6457 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
6458 ioc_status);
6459 goto out_failed;
6460 }
6461 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
6462
6463 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6464 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6465 ioc_err(mrioc, "sas io unit page1 write current failed\n");
6466 goto out_failed;
6467 }
6468 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6469 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
6470 ioc_status);
6471 goto out_failed;
6472 }
6473
6474 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
6475
6476 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6477 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
6478 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
6479 goto out_failed;
6480 }
6481 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6482 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
6483 ioc_status);
6484 goto out_failed;
6485 }
6486 return 0;
6487 out_failed:
6488 return -1;
6489 }
6490
6491 /**
6492 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
6493 * @mrioc: Adapter instance reference
6494 * @driver_pg1: Pointer to return Driver page 1
6495 * @pg_sz: Size of the memory allocated to the page pointer
6496 *
6497 * This is handler for config page read for the Driver page1.
6498 * This routine checks ioc_status to decide whether the page
6499 * read is success or not.
6500 *
6501 * Return: 0 on success, non-zero on failure.
6502 */
mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page1 * driver_pg1,u16 pg_sz)6503 int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
6504 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
6505 {
6506 struct mpi3_config_page_header cfg_hdr;
6507 struct mpi3_config_request cfg_req;
6508 u16 ioc_status = 0;
6509
6510 memset(driver_pg1, 0, pg_sz);
6511 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6512 memset(&cfg_req, 0, sizeof(cfg_req));
6513
6514 cfg_req.function = MPI3_FUNCTION_CONFIG;
6515 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6516 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6517 cfg_req.page_number = 1;
6518 cfg_req.page_address = 0;
6519
6520 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6521 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6522 ioc_err(mrioc, "driver page1 header read failed\n");
6523 goto out_failed;
6524 }
6525 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6526 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
6527 ioc_status);
6528 goto out_failed;
6529 }
6530 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
6531
6532 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6533 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
6534 ioc_err(mrioc, "driver page1 read failed\n");
6535 goto out_failed;
6536 }
6537 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6538 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
6539 ioc_status);
6540 goto out_failed;
6541 }
6542 return 0;
6543 out_failed:
6544 return -1;
6545 }
6546
6547 /**
6548 * mpi3mr_cfg_get_driver_pg2 - Read current driver page2
6549 * @mrioc: Adapter instance reference
6550 * @driver_pg2: Pointer to return driver page 2
6551 * @pg_sz: Size of the memory allocated to the page pointer
6552 * @page_action: Page action
6553 *
6554 * This is handler for config page read for the driver page2.
6555 * This routine checks ioc_status to decide whether the page
6556 * read is success or not.
6557 *
6558 * Return: 0 on success, non-zero on failure.
6559 */
mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc * mrioc,struct mpi3_driver_page2 * driver_pg2,u16 pg_sz,u8 page_action)6560 int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
6561 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_action)
6562 {
6563 struct mpi3_config_page_header cfg_hdr;
6564 struct mpi3_config_request cfg_req;
6565 u16 ioc_status = 0;
6566
6567 memset(driver_pg2, 0, pg_sz);
6568 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
6569 memset(&cfg_req, 0, sizeof(cfg_req));
6570
6571 cfg_req.function = MPI3_FUNCTION_CONFIG;
6572 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
6573 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
6574 cfg_req.page_number = 2;
6575 cfg_req.page_address = 0;
6576 cfg_req.page_version = MPI3_DRIVER2_PAGEVERSION;
6577
6578 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
6579 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
6580 ioc_err(mrioc, "driver page2 header read failed\n");
6581 goto out_failed;
6582 }
6583 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6584 ioc_err(mrioc, "driver page2 header read failed with\n"
6585 "ioc_status(0x%04x)\n",
6586 ioc_status);
6587 goto out_failed;
6588 }
6589 cfg_req.action = page_action;
6590
6591 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
6592 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg2, pg_sz)) {
6593 ioc_err(mrioc, "driver page2 read failed\n");
6594 goto out_failed;
6595 }
6596 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
6597 ioc_err(mrioc, "driver page2 read failed with\n"
6598 "ioc_status(0x%04x)\n",
6599 ioc_status);
6600 goto out_failed;
6601 }
6602 return 0;
6603 out_failed:
6604 return -1;
6605 }
6606
6607