1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 11#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 12#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,osm-l3.h> 17#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 18#include <dt-bindings/interrupt-controller/arm-gic.h> 19#include <dt-bindings/mailbox/qcom-ipcc.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,gpr.h> 23#include <dt-bindings/soc/qcom,rpmh-rsc.h> 24#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 25#include <dt-bindings/thermal/thermal.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 clocks { 33 xo_board_clk: xo-board-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <38400000>; 37 }; 38 39 sleep_clk: sleep-clk { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <32000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a78c"; 53 reg = <0x0 0x0>; 54 enable-method = "psci"; 55 next-level-cache = <&l2_0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 capacity-dmips-mhz = <1946>; 59 dynamic-power-coefficient = <472>; 60 #cooling-cells = <2>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 operating-points-v2 = <&cpu0_opp_table>; 63 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 64 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 65 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 66 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 67 68 l2_0: l2-cache { 69 compatible = "cache"; 70 cache-level = <2>; 71 cache-unified; 72 next-level-cache = <&l3_0>; 73 }; 74 }; 75 76 cpu1: cpu@100 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a78c"; 79 reg = <0x0 0x100>; 80 enable-method = "psci"; 81 next-level-cache = <&l2_1>; 82 power-domains = <&cpu_pd1>; 83 power-domain-names = "psci"; 84 capacity-dmips-mhz = <1946>; 85 #cooling-cells = <2>; 86 dynamic-power-coefficient = <472>; 87 qcom,freq-domain = <&cpufreq_hw 0>; 88 operating-points-v2 = <&cpu0_opp_table>; 89 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 90 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 91 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 92 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 93 94 l2_1: l2-cache { 95 compatible = "cache"; 96 cache-level = <2>; 97 cache-unified; 98 next-level-cache = <&l3_0>; 99 }; 100 }; 101 102 cpu2: cpu@200 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a78c"; 105 reg = <0x0 0x200>; 106 enable-method = "psci"; 107 next-level-cache = <&l2_2>; 108 power-domains = <&cpu_pd2>; 109 power-domain-names = "psci"; 110 capacity-dmips-mhz = <1946>; 111 #cooling-cells = <2>; 112 dynamic-power-coefficient = <507>; 113 qcom,freq-domain = <&cpufreq_hw 2>; 114 operating-points-v2 = <&cpu2_opp_table>; 115 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 116 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 117 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 118 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 119 120 l2_2: l2-cache { 121 compatible = "cache"; 122 cache-level = <2>; 123 cache-unified; 124 next-level-cache = <&l3_0>; 125 }; 126 }; 127 128 cpu3: cpu@300 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a78c"; 131 reg = <0x0 0x300>; 132 enable-method = "psci"; 133 next-level-cache = <&l2_3>; 134 power-domains = <&cpu_pd3>; 135 power-domain-names = "psci"; 136 capacity-dmips-mhz = <1946>; 137 #cooling-cells = <2>; 138 dynamic-power-coefficient = <507>; 139 qcom,freq-domain = <&cpufreq_hw 2>; 140 operating-points-v2 = <&cpu2_opp_table>; 141 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 142 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 143 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 144 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 145 146 l2_3: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu4: cpu@10000 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a55"; 157 reg = <0x0 0x10000>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_4>; 160 power-domains = <&cpu_pd4>; 161 power-domain-names = "psci"; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 dynamic-power-coefficient = <100>; 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 operating-points-v2 = <&cpu4_opp_table>; 167 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 168 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 169 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 170 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 171 172 l2_4: l2-cache { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_1>; 177 }; 178 }; 179 180 cpu5: cpu@10100 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a55"; 183 reg = <0x0 0x10100>; 184 enable-method = "psci"; 185 next-level-cache = <&l2_5>; 186 power-domains = <&cpu_pd5>; 187 power-domain-names = "psci"; 188 capacity-dmips-mhz = <1024>; 189 #cooling-cells = <2>; 190 dynamic-power-coefficient = <100>; 191 qcom,freq-domain = <&cpufreq_hw 1>; 192 operating-points-v2 = <&cpu4_opp_table>; 193 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 194 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 195 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 196 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 197 198 l2_5: l2-cache { 199 compatible = "cache"; 200 cache-level = <2>; 201 cache-unified; 202 next-level-cache = <&l3_1>; 203 }; 204 }; 205 206 cpu6: cpu@10200 { 207 device_type = "cpu"; 208 compatible = "arm,cortex-a55"; 209 reg = <0x0 0x10200>; 210 enable-method = "psci"; 211 next-level-cache = <&l2_6>; 212 power-domains = <&cpu_pd6>; 213 power-domain-names = "psci"; 214 capacity-dmips-mhz = <1024>; 215 #cooling-cells = <2>; 216 dynamic-power-coefficient = <100>; 217 qcom,freq-domain = <&cpufreq_hw 1>; 218 operating-points-v2 = <&cpu4_opp_table>; 219 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 220 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 221 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 222 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 223 224 l2_6: l2-cache { 225 compatible = "cache"; 226 cache-level = <2>; 227 cache-unified; 228 next-level-cache = <&l3_1>; 229 }; 230 }; 231 232 cpu7: cpu@10300 { 233 device_type = "cpu"; 234 compatible = "arm,cortex-a55"; 235 reg = <0x0 0x10300>; 236 enable-method = "psci"; 237 next-level-cache = <&l2_7>; 238 power-domains = <&cpu_pd7>; 239 power-domain-names = "psci"; 240 capacity-dmips-mhz = <1024>; 241 #cooling-cells = <2>; 242 dynamic-power-coefficient = <100>; 243 qcom,freq-domain = <&cpufreq_hw 1>; 244 operating-points-v2 = <&cpu4_opp_table>; 245 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 246 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 247 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 248 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 249 250 l2_7: l2-cache { 251 compatible = "cache"; 252 cache-level = <2>; 253 cache-unified; 254 next-level-cache = <&l3_1>; 255 }; 256 }; 257 258 cpu-map { 259 cluster0 { 260 core0 { 261 cpu = <&cpu0>; 262 }; 263 264 core1 { 265 cpu = <&cpu1>; 266 }; 267 268 core2 { 269 cpu = <&cpu2>; 270 }; 271 272 core3 { 273 cpu = <&cpu3>; 274 }; 275 }; 276 277 cluster1 { 278 core0 { 279 cpu = <&cpu4>; 280 }; 281 282 core1 { 283 cpu = <&cpu5>; 284 }; 285 286 core2 { 287 cpu = <&cpu6>; 288 }; 289 290 core3 { 291 cpu = <&cpu7>; 292 }; 293 }; 294 }; 295 296 l3_0: l3-cache-0 { 297 compatible = "cache"; 298 cache-level = <3>; 299 cache-unified; 300 }; 301 302 l3_1: l3-cache-1 { 303 compatible = "cache"; 304 cache-level = <3>; 305 cache-unified; 306 }; 307 308 idle-states { 309 entry-method = "psci"; 310 311 little_cpu_sleep_0: cpu-sleep-0-0 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "silver-power-collapse"; 314 arm,psci-suspend-param = <0x40000003>; 315 entry-latency-us = <449>; 316 exit-latency-us = <801>; 317 min-residency-us = <1574>; 318 local-timer-stop; 319 }; 320 321 little_cpu_sleep_1: cpu-sleep-0-1 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "silver-rail-power-collapse"; 324 arm,psci-suspend-param = <0x40000004>; 325 entry-latency-us = <602>; 326 exit-latency-us = <961>; 327 min-residency-us = <4288>; 328 local-timer-stop; 329 }; 330 331 big_cpu_sleep_0: cpu-sleep-1-0 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-power-collapse"; 334 arm,psci-suspend-param = <0x40000003>; 335 entry-latency-us = <549>; 336 exit-latency-us = <901>; 337 min-residency-us = <1774>; 338 local-timer-stop; 339 }; 340 341 big_cpu_sleep_1: cpu-sleep-1-1 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "gold-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <702>; 346 exit-latency-us = <1061>; 347 min-residency-us = <4488>; 348 local-timer-stop; 349 }; 350 }; 351 352 domain-idle-states { 353 silver_cluster_sleep: cluster-sleep-0 { 354 compatible = "domain-idle-state"; 355 arm,psci-suspend-param = <0x41000044>; 356 entry-latency-us = <2552>; 357 exit-latency-us = <2848>; 358 min-residency-us = <5908>; 359 }; 360 361 gold_cluster_sleep: cluster-sleep-1 { 362 compatible = "domain-idle-state"; 363 arm,psci-suspend-param = <0x41000044>; 364 entry-latency-us = <2752>; 365 exit-latency-us = <3048>; 366 min-residency-us = <6118>; 367 }; 368 369 system_sleep: domain-sleep { 370 compatible = "domain-idle-state"; 371 arm,psci-suspend-param = <0x42000144>; 372 entry-latency-us = <3263>; 373 exit-latency-us = <6562>; 374 min-residency-us = <9987>; 375 }; 376 }; 377 }; 378 379 cpu0_opp_table: opp-table-cpu0 { 380 compatible = "operating-points-v2"; 381 opp-shared; 382 383 opp-902400000 { 384 opp-hz = /bits/ 64 <902400000>; 385 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 386 }; 387 388 opp-1017600000 { 389 opp-hz = /bits/ 64 <1017600000>; 390 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 391 }; 392 393 opp-1190400000 { 394 opp-hz = /bits/ 64 <1190400000>; 395 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 396 }; 397 398 opp-1267200000 { 399 opp-hz = /bits/ 64 <1267200000>; 400 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 401 }; 402 403 opp-1344000000 { 404 opp-hz = /bits/ 64 <1344000000>; 405 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 406 }; 407 408 opp-1420800000 { 409 opp-hz = /bits/ 64 <1420800000>; 410 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 411 }; 412 413 opp-1497600000 { 414 opp-hz = /bits/ 64 <1497600000>; 415 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 416 }; 417 418 opp-1574400000 { 419 opp-hz = /bits/ 64 <1574400000>; 420 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 421 }; 422 423 opp-1670400000 { 424 opp-hz = /bits/ 64 <1670400000>; 425 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 426 }; 427 428 opp-1747200000 { 429 opp-hz = /bits/ 64 <1747200000>; 430 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 431 }; 432 433 opp-1824000000 { 434 opp-hz = /bits/ 64 <1824000000>; 435 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 436 }; 437 438 opp-1900800000 { 439 opp-hz = /bits/ 64 <1900800000>; 440 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 441 }; 442 443 opp-1977600000 { 444 opp-hz = /bits/ 64 <1977600000>; 445 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 446 }; 447 448 opp-2054400000 { 449 opp-hz = /bits/ 64 <2054400000>; 450 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 451 }; 452 453 opp-2112000000 { 454 opp-hz = /bits/ 64 <2112000000>; 455 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 456 }; 457 458 }; 459 460 cpu2_opp_table: opp-table-cpu2 { 461 compatible = "operating-points-v2"; 462 opp-shared; 463 464 opp-940800000 { 465 opp-hz = /bits/ 64 <940800000>; 466 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 467 }; 468 469 opp-1094400000 { 470 opp-hz = /bits/ 64 <1094400000>; 471 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 472 }; 473 474 opp-1267200000 { 475 opp-hz = /bits/ 64 <1267200000>; 476 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 477 }; 478 479 opp-1344000000 { 480 opp-hz = /bits/ 64 <1344000000>; 481 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 482 }; 483 484 opp-1420800000 { 485 opp-hz = /bits/ 64 <1420800000>; 486 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 487 }; 488 489 opp-1497600000 { 490 opp-hz = /bits/ 64 <1497600000>; 491 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 492 }; 493 494 opp-1574400000 { 495 opp-hz = /bits/ 64 <1574400000>; 496 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 497 }; 498 499 opp-1632000000 { 500 opp-hz = /bits/ 64 <1632000000>; 501 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 502 }; 503 504 opp-1708800000 { 505 opp-hz = /bits/ 64 <1708800000>; 506 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 507 }; 508 509 opp-1804800000 { 510 opp-hz = /bits/ 64 <1804800000>; 511 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 512 }; 513 514 opp-1900800000 { 515 opp-hz = /bits/ 64 <1900800000>; 516 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 517 }; 518 519 opp-1977600000 { 520 opp-hz = /bits/ 64 <1977600000>; 521 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 522 }; 523 524 opp-2054400000 { 525 opp-hz = /bits/ 64 <2054400000>; 526 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 527 }; 528 529 opp-2131200000 { 530 opp-hz = /bits/ 64 <2131200000>; 531 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 532 }; 533 534 opp-2208000000 { 535 opp-hz = /bits/ 64 <2208000000>; 536 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 537 }; 538 539 opp-2284800000 { 540 opp-hz = /bits/ 64 <2284800000>; 541 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 542 }; 543 544 opp-2361600000 { 545 opp-hz = /bits/ 64 <2361600000>; 546 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 547 }; 548 549 }; 550 551 cpu4_opp_table: opp-table-cpu4 { 552 compatible = "operating-points-v2"; 553 opp-shared; 554 555 opp-844800000 { 556 opp-hz = /bits/ 64 <844800000>; 557 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 558 }; 559 560 opp-1113600000 { 561 opp-hz = /bits/ 64 <1113600000>; 562 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 563 }; 564 565 opp-1209600000 { 566 opp-hz = /bits/ 64 <1209600000>; 567 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 568 }; 569 570 opp-1305600000 { 571 opp-hz = /bits/ 64 <1305600000>; 572 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 573 }; 574 575 opp-1382400000 { 576 opp-hz = /bits/ 64 <1382400000>; 577 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 578 }; 579 580 opp-1459200000 { 581 opp-hz = /bits/ 64 <1459200000>; 582 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 583 }; 584 585 opp-1497600000 { 586 opp-hz = /bits/ 64 <1497600000>; 587 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 588 }; 589 590 opp-1574400000 { 591 opp-hz = /bits/ 64 <1574400000>; 592 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 593 }; 594 595 opp-1651200000 { 596 opp-hz = /bits/ 64 <1651200000>; 597 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 598 }; 599 600 opp-1728000000 { 601 opp-hz = /bits/ 64 <1728000000>; 602 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 603 }; 604 605 opp-1804800000 { 606 opp-hz = /bits/ 64 <1804800000>; 607 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 608 }; 609 610 opp-1881600000 { 611 opp-hz = /bits/ 64 <1881600000>; 612 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 613 }; 614 615 opp-1958400000 { 616 opp-hz = /bits/ 64 <1958400000>; 617 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 618 }; 619 }; 620 621 dummy_eud: dummy-sink { 622 compatible = "arm,coresight-dummy-sink"; 623 624 in-ports { 625 port { 626 eud_in: endpoint { 627 remote-endpoint = <&swao_rep_out1>; 628 }; 629 }; 630 }; 631 }; 632 633 firmware { 634 scm: scm { 635 compatible = "qcom,scm-qcs8300", "qcom,scm"; 636 qcom,dload-mode = <&tcsr 0x13000>; 637 }; 638 }; 639 640 memory@80000000 { 641 device_type = "memory"; 642 /* We expect the bootloader to fill in the size */ 643 reg = <0x0 0x80000000 0x0 0x0>; 644 }; 645 646 clk_virt: interconnect-0 { 647 compatible = "qcom,qcs8300-clk-virt"; 648 #interconnect-cells = <2>; 649 qcom,bcm-voters = <&apps_bcm_voter>; 650 }; 651 652 mc_virt: interconnect-1 { 653 compatible = "qcom,qcs8300-mc-virt"; 654 #interconnect-cells = <2>; 655 qcom,bcm-voters = <&apps_bcm_voter>; 656 }; 657 658 qup_opp_table: opp-table-qup { 659 compatible = "operating-points-v2"; 660 661 opp-120000000 { 662 opp-hz = /bits/ 64 <120000000>; 663 required-opps = <&rpmhpd_opp_svs_l1>; 664 }; 665 }; 666 667 pmu-a55 { 668 compatible = "arm,cortex-a55-pmu"; 669 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 670 }; 671 672 pmu-a78 { 673 compatible = "arm,cortex-a78-pmu"; 674 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 675 }; 676 677 psci { 678 compatible = "arm,psci-1.0"; 679 method = "smc"; 680 681 cpu_pd0: power-domain-cpu0 { 682 #power-domain-cells = <0>; 683 power-domains = <&cluster_pd0>; 684 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 685 }; 686 687 cpu_pd1: power-domain-cpu1 { 688 #power-domain-cells = <0>; 689 power-domains = <&cluster_pd0>; 690 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 691 }; 692 693 cpu_pd2: power-domain-cpu2 { 694 #power-domain-cells = <0>; 695 power-domains = <&cluster_pd0>; 696 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 697 }; 698 699 cpu_pd3: power-domain-cpu3 { 700 #power-domain-cells = <0>; 701 power-domains = <&cluster_pd0>; 702 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 703 }; 704 705 cpu_pd4: power-domain-cpu4 { 706 #power-domain-cells = <0>; 707 power-domains = <&cluster_pd1>; 708 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 709 }; 710 711 cpu_pd5: power-domain-cpu5 { 712 #power-domain-cells = <0>; 713 power-domains = <&cluster_pd1>; 714 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 715 }; 716 717 cpu_pd6: power-domain-cpu6 { 718 #power-domain-cells = <0>; 719 power-domains = <&cluster_pd1>; 720 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 721 }; 722 723 cpu_pd7: power-domain-cpu7 { 724 #power-domain-cells = <0>; 725 power-domains = <&cluster_pd1>; 726 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 727 }; 728 729 cluster_pd0: power-domain-cluster0 { 730 #power-domain-cells = <0>; 731 power-domains = <&system_pd>; 732 domain-idle-states = <&gold_cluster_sleep>; 733 }; 734 735 cluster_pd1: power-domain-cluster1 { 736 #power-domain-cells = <0>; 737 power-domains = <&system_pd>; 738 domain-idle-states = <&silver_cluster_sleep>; 739 }; 740 741 system_pd: power-domain-system { 742 #power-domain-cells = <0>; 743 domain-idle-states = <&system_sleep>; 744 }; 745 }; 746 747 reserved-memory { 748 #address-cells = <2>; 749 #size-cells = <2>; 750 ranges; 751 752 aop_image_mem: aop-image-region@90800000 { 753 reg = <0x0 0x90800000 0x0 0x60000>; 754 no-map; 755 }; 756 757 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 758 compatible = "qcom,cmd-db"; 759 reg = <0x0 0x90860000 0x0 0x20000>; 760 no-map; 761 }; 762 763 smem_mem: smem@90900000 { 764 compatible = "qcom,smem"; 765 reg = <0x0 0x90900000 0x0 0x200000>; 766 no-map; 767 hwlocks = <&tcsr_mutex 3>; 768 }; 769 770 gunyah_md_mem: gunyah-md-region@91a80000 { 771 reg = <0x0 0x91a80000 0x0 0x80000>; 772 no-map; 773 }; 774 775 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 776 reg = <0x0 0x93b00000 0x0 0xf00000>; 777 no-map; 778 }; 779 780 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 781 reg = <0x0 0x94a00000 0x0 0x800000>; 782 no-map; 783 }; 784 785 camera_mem: camera-region@95200000 { 786 reg = <0x0 0x95200000 0x0 0x500000>; 787 no-map; 788 }; 789 790 adsp_mem: adsp-region@95c00000 { 791 no-map; 792 reg = <0x0 0x95c00000 0x0 0x1e00000>; 793 }; 794 795 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 796 reg = <0x0 0x97a00000 0x0 0x80000>; 797 no-map; 798 }; 799 800 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 801 reg = <0x0 0x97a80000 0x0 0x80000>; 802 no-map; 803 }; 804 805 gpdsp_mem: gpdsp-region@97b00000 { 806 reg = <0x0 0x97b00000 0x0 0x1e00000>; 807 no-map; 808 }; 809 810 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 811 reg = <0x0 0x99900000 0x0 0x80000>; 812 no-map; 813 }; 814 815 cdsp_mem: cdsp-region@99980000 { 816 reg = <0x0 0x99980000 0x0 0x1e00000>; 817 no-map; 818 }; 819 820 gpu_microcode_mem: gpu-microcode-region@9b780000 { 821 reg = <0x0 0x9b780000 0x0 0x2000>; 822 no-map; 823 }; 824 825 cvp_mem: cvp-region@9b782000 { 826 reg = <0x0 0x9b782000 0x0 0x700000>; 827 no-map; 828 }; 829 830 video_mem: video-region@9be82000 { 831 reg = <0x0 0x9be82000 0x0 0x700000>; 832 no-map; 833 }; 834 }; 835 836 smp2p-adsp { 837 compatible = "qcom,smp2p"; 838 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 839 IPCC_MPROC_SIGNAL_SMP2P 840 IRQ_TYPE_EDGE_RISING>; 841 mboxes = <&ipcc IPCC_CLIENT_LPASS 842 IPCC_MPROC_SIGNAL_SMP2P>; 843 844 qcom,smem = <443>, <429>; 845 qcom,local-pid = <0>; 846 qcom,remote-pid = <2>; 847 848 smp2p_adsp_in: slave-kernel { 849 qcom,entry-name = "slave-kernel"; 850 interrupt-controller; 851 #interrupt-cells = <2>; 852 }; 853 854 smp2p_adsp_out: master-kernel { 855 qcom,entry-name = "master-kernel"; 856 #qcom,smem-state-cells = <1>; 857 }; 858 }; 859 860 smp2p-cdsp { 861 compatible = "qcom,smp2p"; 862 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 863 IPCC_MPROC_SIGNAL_SMP2P 864 IRQ_TYPE_EDGE_RISING>; 865 mboxes = <&ipcc IPCC_CLIENT_CDSP 866 IPCC_MPROC_SIGNAL_SMP2P>; 867 868 qcom,smem = <94>, <432>; 869 qcom,local-pid = <0>; 870 qcom,remote-pid = <5>; 871 872 smp2p_cdsp_in: slave-kernel { 873 qcom,entry-name = "slave-kernel"; 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 }; 877 878 smp2p_cdsp_out: master-kernel { 879 qcom,entry-name = "master-kernel"; 880 #qcom,smem-state-cells = <1>; 881 }; 882 }; 883 884 smp2p-gpdsp { 885 compatible = "qcom,smp2p"; 886 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 887 IPCC_MPROC_SIGNAL_SMP2P 888 IRQ_TYPE_EDGE_RISING>; 889 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 890 IPCC_MPROC_SIGNAL_SMP2P>; 891 892 qcom,smem = <617>, <616>; 893 qcom,local-pid = <0>; 894 qcom,remote-pid = <17>; 895 896 smp2p_gpdsp_in: slave-kernel { 897 qcom,entry-name = "slave-kernel"; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 }; 901 902 smp2p_gpdsp_out: master-kernel { 903 qcom,entry-name = "master-kernel"; 904 #qcom,smem-state-cells = <1>; 905 }; 906 }; 907 908 soc: soc@0 { 909 compatible = "simple-bus"; 910 ranges = <0 0 0 0 0x10 0>; 911 #address-cells = <2>; 912 #size-cells = <2>; 913 914 gcc: clock-controller@100000 { 915 compatible = "qcom,qcs8300-gcc"; 916 reg = <0x0 0x00100000 0x0 0xc7018>; 917 #clock-cells = <1>; 918 #reset-cells = <1>; 919 #power-domain-cells = <1>; 920 clocks = <&rpmhcc RPMH_CXO_CLK>, 921 <&sleep_clk>, 922 <&pcie0_phy>, 923 <&pcie1_phy>, 924 <0>, 925 <0>, 926 <0>, 927 <0>, 928 <0>, 929 <0>; 930 }; 931 932 ipcc: mailbox@408000 { 933 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 934 reg = <0x0 0x408000 0x0 0x1000>; 935 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-controller; 937 #interrupt-cells = <3>; 938 #mbox-cells = <2>; 939 }; 940 941 qfprom: efuse@784000 { 942 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 943 reg = <0x0 0x00784000 0x0 0x2410>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 947 gpu_speed_bin: gpu-speed-bin@240c { 948 reg = <0x240c 0x1>; 949 bits = <0 8>; 950 }; 951 }; 952 953 gpi_dma0: dma-controller@900000 { 954 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 955 reg = <0x0 0x900000 0x0 0x60000>; 956 #dma-cells = <3>; 957 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 969 iommus = <&apps_smmu 0x416 0x0>; 970 dma-channels = <12>; 971 dma-channel-mask = <0xfff>; 972 dma-coherent; 973 status = "disabled"; 974 }; 975 976 qupv3_id_0: geniqup@9c0000 { 977 compatible = "qcom,geni-se-qup"; 978 reg = <0x0 0x9c0000 0x0 0x2000>; 979 ranges; 980 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 981 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 982 clock-names = "m-ahb", 983 "s-ahb"; 984 #address-cells = <2>; 985 #size-cells = <2>; 986 iommus = <&apps_smmu 0x403 0x0>; 987 dma-coherent; 988 status = "disabled"; 989 990 i2c0: i2c@980000 { 991 compatible = "qcom,geni-i2c"; 992 reg = <0x0 0x980000 0x0 0x4000>; 993 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 994 clock-names = "se"; 995 pinctrl-0 = <&qup_i2c0_data_clk>; 996 pinctrl-names = "default"; 997 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1001 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1002 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1003 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1004 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1005 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1006 interconnect-names = "qup-core", 1007 "qup-config", 1008 "qup-memory"; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 required-opps = <&rpmhpd_opp_low_svs>; 1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1013 dma-names = "tx", 1014 "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 spi0: spi@980000 { 1019 compatible = "qcom,geni-spi"; 1020 reg = <0x0 0x980000 0x0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1022 clock-names = "se"; 1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1024 pinctrl-names = "default"; 1025 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1026 #address-cells = <1>; 1027 #size-cells = <0>; 1028 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1029 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1030 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1031 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1032 interconnect-names = "qup-core", 1033 "qup-config"; 1034 power-domains = <&rpmhpd RPMHPD_CX>; 1035 operating-points-v2 = <&qup_opp_table>; 1036 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1037 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1038 dma-names = "tx", 1039 "rx"; 1040 status = "disabled"; 1041 }; 1042 1043 uart0: serial@980000 { 1044 compatible = "qcom,geni-uart"; 1045 reg = <0x0 0x980000 0x0 0x4000>; 1046 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1047 clock-names = "se"; 1048 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1049 <&qup_uart0_tx>, <&qup_uart0_rx>; 1050 pinctrl-names = "default"; 1051 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1052 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1053 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1054 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1055 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1056 interconnect-names = "qup-core", 1057 "qup-config"; 1058 power-domains = <&rpmhpd RPMHPD_CX>; 1059 operating-points-v2 = <&qup_opp_table>; 1060 status = "disabled"; 1061 }; 1062 1063 i2c1: i2c@984000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0x0 0x984000 0x0 0x4000>; 1066 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1067 clock-names = "se"; 1068 pinctrl-0 = <&qup_i2c1_data_clk>; 1069 pinctrl-names = "default"; 1070 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1074 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1075 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1076 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1077 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1078 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1079 interconnect-names = "qup-core", 1080 "qup-config", 1081 "qup-memory"; 1082 power-domains = <&rpmhpd RPMHPD_CX>; 1083 required-opps = <&rpmhpd_opp_low_svs>; 1084 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1085 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1086 dma-names = "tx", 1087 "rx"; 1088 status = "disabled"; 1089 }; 1090 1091 spi1: spi@984000 { 1092 compatible = "qcom,geni-spi"; 1093 reg = <0x0 0x984000 0x0 0x4000>; 1094 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1095 clock-names = "se"; 1096 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1097 pinctrl-names = "default"; 1098 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1102 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1103 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1104 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1105 interconnect-names = "qup-core", 1106 "qup-config"; 1107 power-domains = <&rpmhpd RPMHPD_CX>; 1108 operating-points-v2 = <&qup_opp_table>; 1109 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1110 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1111 dma-names = "tx", 1112 "rx"; 1113 status = "disabled"; 1114 }; 1115 1116 uart1: serial@984000 { 1117 compatible = "qcom,geni-uart"; 1118 reg = <0x0 0x984000 0x0 0x4000>; 1119 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1120 clock-names = "se"; 1121 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1122 <&qup_uart1_tx>, <&qup_uart1_rx>; 1123 pinctrl-names = "default"; 1124 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1125 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1126 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1127 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1128 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1129 interconnect-names = "qup-core", 1130 "qup-config"; 1131 power-domains = <&rpmhpd RPMHPD_CX>; 1132 operating-points-v2 = <&qup_opp_table>; 1133 status = "disabled"; 1134 }; 1135 1136 i2c2: i2c@988000 { 1137 compatible = "qcom,geni-i2c"; 1138 reg = <0x0 0x988000 0x0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1140 clock-names = "se"; 1141 pinctrl-0 = <&qup_i2c2_data_clk>; 1142 pinctrl-names = "default"; 1143 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1147 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1149 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1150 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1152 interconnect-names = "qup-core", 1153 "qup-config", 1154 "qup-memory"; 1155 power-domains = <&rpmhpd RPMHPD_CX>; 1156 required-opps = <&rpmhpd_opp_low_svs>; 1157 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1158 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1159 dma-names = "tx", 1160 "rx"; 1161 status = "disabled"; 1162 }; 1163 1164 spi2: spi@988000 { 1165 compatible = "qcom,geni-spi"; 1166 reg = <0x0 0x988000 0x0 0x4000>; 1167 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1168 clock-names = "se"; 1169 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1170 pinctrl-names = "default"; 1171 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1175 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1176 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1177 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1178 interconnect-names = "qup-core", 1179 "qup-config"; 1180 power-domains = <&rpmhpd RPMHPD_CX>; 1181 operating-points-v2 = <&qup_opp_table>; 1182 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1183 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1184 dma-names = "tx", 1185 "rx"; 1186 status = "disabled"; 1187 }; 1188 1189 uart2: serial@988000 { 1190 compatible = "qcom,geni-uart"; 1191 reg = <0x0 0x988000 0x0 0x4000>; 1192 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1193 clock-names = "se"; 1194 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1195 <&qup_uart2_tx>, <&qup_uart2_rx>; 1196 pinctrl-names = "default"; 1197 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1198 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1199 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1201 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1202 interconnect-names = "qup-core", 1203 "qup-config"; 1204 power-domains = <&rpmhpd RPMHPD_CX>; 1205 operating-points-v2 = <&qup_opp_table>; 1206 status = "disabled"; 1207 }; 1208 1209 i2c3: i2c@98c000 { 1210 compatible = "qcom,geni-i2c"; 1211 reg = <0x0 0x98c000 0x0 0x4000>; 1212 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1213 clock-names = "se"; 1214 pinctrl-0 = <&qup_i2c3_data_clk>; 1215 pinctrl-names = "default"; 1216 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1220 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1221 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1222 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1223 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1224 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1225 interconnect-names = "qup-core", 1226 "qup-config", 1227 "qup-memory"; 1228 power-domains = <&rpmhpd RPMHPD_CX>; 1229 required-opps = <&rpmhpd_opp_low_svs>; 1230 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1231 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1232 dma-names = "tx", 1233 "rx"; 1234 status = "disabled"; 1235 }; 1236 1237 spi3: spi@98c000 { 1238 compatible = "qcom,geni-spi"; 1239 reg = <0x0 0x98c000 0x0 0x4000>; 1240 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1241 clock-names = "se"; 1242 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1243 pinctrl-names = "default"; 1244 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1245 #address-cells = <1>; 1246 #size-cells = <0>; 1247 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1248 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1249 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1250 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1251 interconnect-names = "qup-core", 1252 "qup-config"; 1253 power-domains = <&rpmhpd RPMHPD_CX>; 1254 operating-points-v2 = <&qup_opp_table>; 1255 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1256 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1257 dma-names = "tx", 1258 "rx"; 1259 status = "disabled"; 1260 }; 1261 1262 uart3: serial@98c000 { 1263 compatible = "qcom,geni-uart"; 1264 reg = <0x0 0x98c000 0x0 0x4000>; 1265 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1266 clock-names = "se"; 1267 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1268 <&qup_uart3_tx>, <&qup_uart3_rx>; 1269 pinctrl-names = "default"; 1270 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1271 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1272 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1273 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1274 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1275 interconnect-names = "qup-core", 1276 "qup-config"; 1277 power-domains = <&rpmhpd RPMHPD_CX>; 1278 operating-points-v2 = <&qup_opp_table>; 1279 status = "disabled"; 1280 }; 1281 1282 i2c4: i2c@990000 { 1283 compatible = "qcom,geni-i2c"; 1284 reg = <0x0 0x990000 0x0 0x4000>; 1285 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1286 clock-names = "se"; 1287 pinctrl-0 = <&qup_i2c4_data_clk>; 1288 pinctrl-names = "default"; 1289 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1293 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1294 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1295 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1296 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1297 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1298 interconnect-names = "qup-core", 1299 "qup-config", 1300 "qup-memory"; 1301 power-domains = <&rpmhpd RPMHPD_CX>; 1302 required-opps = <&rpmhpd_opp_low_svs>; 1303 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1304 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1305 dma-names = "tx", 1306 "rx"; 1307 status = "disabled"; 1308 }; 1309 1310 spi4: spi@990000 { 1311 compatible = "qcom,geni-spi"; 1312 reg = <0x0 0x990000 0x0 0x4000>; 1313 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1314 clock-names = "se"; 1315 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1316 pinctrl-names = "default"; 1317 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1321 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1322 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1323 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1324 interconnect-names = "qup-core", 1325 "qup-config"; 1326 power-domains = <&rpmhpd RPMHPD_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1329 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1330 dma-names = "tx", 1331 "rx"; 1332 status = "disabled"; 1333 }; 1334 1335 uart4: serial@990000 { 1336 compatible = "qcom,geni-uart"; 1337 reg = <0x0 0x990000 0x0 0x4000>; 1338 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1339 clock-names = "se"; 1340 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1341 <&qup_uart4_tx>, <&qup_uart4_rx>; 1342 pinctrl-names = "default"; 1343 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1344 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1345 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1347 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1348 interconnect-names = "qup-core", 1349 "qup-config"; 1350 power-domains = <&rpmhpd RPMHPD_CX>; 1351 operating-points-v2 = <&qup_opp_table>; 1352 status = "disabled"; 1353 }; 1354 1355 i2c5: i2c@994000 { 1356 compatible = "qcom,geni-i2c"; 1357 reg = <0x0 0x994000 0x0 0x4000>; 1358 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1359 clock-names = "se"; 1360 pinctrl-0 = <&qup_i2c5_data_clk>; 1361 pinctrl-names = "default"; 1362 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1363 #address-cells = <1>; 1364 #size-cells = <0>; 1365 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1366 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1367 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1368 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1369 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1370 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1371 interconnect-names = "qup-core", 1372 "qup-config", 1373 "qup-memory"; 1374 power-domains = <&rpmhpd RPMHPD_CX>; 1375 required-opps = <&rpmhpd_opp_low_svs>; 1376 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1377 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1378 dma-names = "tx", 1379 "rx"; 1380 status = "disabled"; 1381 }; 1382 1383 spi5: spi@994000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0x0 0x994000 0x0 0x4000>; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1387 clock-names = "se"; 1388 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1389 pinctrl-names = "default"; 1390 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1391 #address-cells = <1>; 1392 #size-cells = <0>; 1393 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1394 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1395 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1396 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1397 interconnect-names = "qup-core", 1398 "qup-config"; 1399 power-domains = <&rpmhpd RPMHPD_CX>; 1400 operating-points-v2 = <&qup_opp_table>; 1401 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1402 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1403 dma-names = "tx", 1404 "rx"; 1405 status = "disabled"; 1406 }; 1407 1408 uart5: serial@994000 { 1409 compatible = "qcom,geni-uart"; 1410 reg = <0x0 0x994000 0x0 0x4000>; 1411 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1412 clock-names = "se"; 1413 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1414 <&qup_uart5_tx>, <&qup_uart5_rx>; 1415 pinctrl-names = "default"; 1416 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1417 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1418 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1419 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1420 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1421 interconnect-names = "qup-core", 1422 "qup-config"; 1423 power-domains = <&rpmhpd RPMHPD_CX>; 1424 operating-points-v2 = <&qup_opp_table>; 1425 status = "disabled"; 1426 }; 1427 1428 i2c6: i2c@998000 { 1429 compatible = "qcom,geni-i2c"; 1430 reg = <0x0 0x998000 0x0 0x4000>; 1431 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1432 clock-names = "se"; 1433 pinctrl-0 = <&qup_i2c6_data_clk>; 1434 pinctrl-names = "default"; 1435 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1436 #address-cells = <1>; 1437 #size-cells = <0>; 1438 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1439 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1440 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1441 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1442 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1443 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1444 interconnect-names = "qup-core", 1445 "qup-config", 1446 "qup-memory"; 1447 power-domains = <&rpmhpd RPMHPD_CX>; 1448 required-opps = <&rpmhpd_opp_low_svs>; 1449 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1450 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1451 dma-names = "tx", 1452 "rx"; 1453 status = "disabled"; 1454 }; 1455 1456 spi6: spi@998000 { 1457 compatible = "qcom,geni-spi"; 1458 reg = <0x0 0x998000 0x0 0x4000>; 1459 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1460 clock-names = "se"; 1461 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1462 pinctrl-names = "default"; 1463 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1467 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1468 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1469 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1470 interconnect-names = "qup-core", 1471 "qup-config"; 1472 power-domains = <&rpmhpd RPMHPD_CX>; 1473 operating-points-v2 = <&qup_opp_table>; 1474 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1475 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1476 dma-names = "tx", 1477 "rx"; 1478 status = "disabled"; 1479 }; 1480 1481 uart6: serial@998000 { 1482 compatible = "qcom,geni-uart"; 1483 reg = <0x0 0x998000 0x0 0x4000>; 1484 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1485 clock-names = "se"; 1486 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1487 <&qup_uart6_tx>, <&qup_uart6_rx>; 1488 pinctrl-names = "default"; 1489 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1490 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1491 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1492 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1493 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1494 interconnect-names = "qup-core", 1495 "qup-config"; 1496 power-domains = <&rpmhpd RPMHPD_CX>; 1497 operating-points-v2 = <&qup_opp_table>; 1498 status = "disabled"; 1499 }; 1500 1501 uart7: serial@99c000 { 1502 compatible = "qcom,geni-debug-uart"; 1503 reg = <0x0 0x0099c000 0x0 0x4000>; 1504 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1505 clock-names = "se"; 1506 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1507 pinctrl-names = "default"; 1508 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1509 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1510 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1511 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1512 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1513 interconnect-names = "qup-core", 1514 "qup-config"; 1515 power-domains = <&rpmhpd RPMHPD_CX>; 1516 operating-points-v2 = <&qup_opp_table>; 1517 status = "disabled"; 1518 }; 1519 }; 1520 1521 gpi_dma1: dma-controller@a00000 { 1522 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1523 reg = <0x0 0xa00000 0x0 0x60000>; 1524 #dma-cells = <3>; 1525 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1527 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1528 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1529 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1537 iommus = <&apps_smmu 0x456 0x0>; 1538 dma-channels = <12>; 1539 dma-channel-mask = <0xfff>; 1540 dma-coherent; 1541 status = "disabled"; 1542 }; 1543 1544 qupv3_id_1: geniqup@ac0000 { 1545 compatible = "qcom,geni-se-qup"; 1546 reg = <0x0 0xac0000 0x0 0x2000>; 1547 ranges; 1548 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1549 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1550 clock-names = "m-ahb", 1551 "s-ahb"; 1552 #address-cells = <2>; 1553 #size-cells = <2>; 1554 iommus = <&apps_smmu 0x443 0x0>; 1555 dma-coherent; 1556 status = "disabled"; 1557 1558 i2c8: i2c@a80000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0x0 0xa80000 0x0 0x4000>; 1561 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1562 clock-names = "se"; 1563 pinctrl-0 = <&qup_i2c8_data_clk>; 1564 pinctrl-names = "default"; 1565 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1566 #address-cells = <1>; 1567 #size-cells = <0>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1569 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1570 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1571 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1572 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1573 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1574 interconnect-names = "qup-core", 1575 "qup-config", 1576 "qup-memory"; 1577 power-domains = <&rpmhpd RPMHPD_CX>; 1578 required-opps = <&rpmhpd_opp_low_svs>; 1579 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1580 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1581 dma-names = "tx", 1582 "rx"; 1583 status = "disabled"; 1584 }; 1585 1586 spi8: spi@a80000 { 1587 compatible = "qcom,geni-spi"; 1588 reg = <0x0 0xa80000 0x0 0x4000>; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1590 clock-names = "se"; 1591 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1592 pinctrl-names = "default"; 1593 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1594 #address-cells = <1>; 1595 #size-cells = <0>; 1596 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1597 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1598 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1599 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1600 interconnect-names = "qup-core", 1601 "qup-config"; 1602 power-domains = <&rpmhpd RPMHPD_CX>; 1603 operating-points-v2 = <&qup_opp_table>; 1604 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1605 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1606 dma-names = "tx", 1607 "rx"; 1608 status = "disabled"; 1609 }; 1610 1611 uart8: serial@a80000 { 1612 compatible = "qcom,geni-uart"; 1613 reg = <0x0 0xa80000 0x0 0x4000>; 1614 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1615 clock-names = "se"; 1616 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1617 <&qup_uart8_tx>, <&qup_uart8_rx>; 1618 pinctrl-names = "default"; 1619 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1621 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1622 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1623 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1624 interconnect-names = "qup-core", 1625 "qup-config"; 1626 power-domains = <&rpmhpd RPMHPD_CX>; 1627 operating-points-v2 = <&qup_opp_table>; 1628 status = "disabled"; 1629 }; 1630 1631 i2c9: i2c@a84000 { 1632 compatible = "qcom,geni-i2c"; 1633 reg = <0x0 0xa84000 0x0 0x4000>; 1634 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1635 clock-names = "se"; 1636 pinctrl-0 = <&qup_i2c9_data_clk>; 1637 pinctrl-names = "default"; 1638 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1642 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1643 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1644 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1645 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1646 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1647 interconnect-names = "qup-core", 1648 "qup-config", 1649 "qup-memory"; 1650 power-domains = <&rpmhpd RPMHPD_CX>; 1651 required-opps = <&rpmhpd_opp_low_svs>; 1652 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1653 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1654 dma-names = "tx", 1655 "rx"; 1656 status = "disabled"; 1657 }; 1658 1659 spi9: spi@a84000 { 1660 compatible = "qcom,geni-spi"; 1661 reg = <0x0 0xa84000 0x0 0x4000>; 1662 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1663 clock-names = "se"; 1664 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1665 pinctrl-names = "default"; 1666 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1670 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1671 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1672 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1673 interconnect-names = "qup-core", 1674 "qup-config"; 1675 power-domains = <&rpmhpd RPMHPD_CX>; 1676 operating-points-v2 = <&qup_opp_table>; 1677 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1678 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1679 dma-names = "tx", 1680 "rx"; 1681 status = "disabled"; 1682 }; 1683 1684 uart9: serial@a84000 { 1685 compatible = "qcom,geni-uart"; 1686 reg = <0x0 0xa84000 0x0 0x4000>; 1687 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1688 clock-names = "se"; 1689 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1690 <&qup_uart9_tx>, <&qup_uart9_rx>; 1691 pinctrl-names = "default"; 1692 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1693 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1694 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1695 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1696 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1697 interconnect-names = "qup-core", 1698 "qup-config"; 1699 power-domains = <&rpmhpd RPMHPD_CX>; 1700 operating-points-v2 = <&qup_opp_table>; 1701 status = "disabled"; 1702 }; 1703 1704 i2c10: i2c@a88000 { 1705 compatible = "qcom,geni-i2c"; 1706 reg = <0x0 0xa88000 0x0 0x4000>; 1707 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1708 clock-names = "se"; 1709 pinctrl-0 = <&qup_i2c10_data_clk>; 1710 pinctrl-names = "default"; 1711 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1715 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1716 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1717 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1718 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1719 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1720 interconnect-names = "qup-core", 1721 "qup-config", 1722 "qup-memory"; 1723 power-domains = <&rpmhpd RPMHPD_CX>; 1724 required-opps = <&rpmhpd_opp_low_svs>; 1725 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1726 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1727 dma-names = "tx", 1728 "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 spi10: spi@a88000 { 1733 compatible = "qcom,geni-spi"; 1734 reg = <0x0 0xa88000 0x0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1736 clock-names = "se"; 1737 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1738 pinctrl-names = "default"; 1739 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1740 #address-cells = <1>; 1741 #size-cells = <0>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1743 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1745 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1746 interconnect-names = "qup-core", 1747 "qup-config"; 1748 power-domains = <&rpmhpd RPMHPD_CX>; 1749 operating-points-v2 = <&qup_opp_table>; 1750 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1751 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1752 dma-names = "tx", 1753 "rx"; 1754 status = "disabled"; 1755 }; 1756 1757 uart10: serial@a88000 { 1758 compatible = "qcom,geni-uart"; 1759 reg = <0x0 0xa88000 0x0 0x4000>; 1760 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1761 clock-names = "se"; 1762 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1763 <&qup_uart10_tx>, <&qup_uart10_rx>; 1764 pinctrl-names = "default"; 1765 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1766 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1767 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1768 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1769 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1770 interconnect-names = "qup-core", 1771 "qup-config"; 1772 power-domains = <&rpmhpd RPMHPD_CX>; 1773 operating-points-v2 = <&qup_opp_table>; 1774 status = "disabled"; 1775 }; 1776 1777 i2c11: i2c@a8c000 { 1778 compatible = "qcom,geni-i2c"; 1779 reg = <0x0 0xa8c000 0x0 0x4000>; 1780 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1781 clock-names = "se"; 1782 pinctrl-0 = <&qup_i2c11_data_clk>; 1783 pinctrl-names = "default"; 1784 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1785 #address-cells = <1>; 1786 #size-cells = <0>; 1787 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1788 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1789 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1790 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1791 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1792 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1793 interconnect-names = "qup-core", 1794 "qup-config", 1795 "qup-memory"; 1796 power-domains = <&rpmhpd RPMHPD_CX>; 1797 required-opps = <&rpmhpd_opp_low_svs>; 1798 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1799 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1800 dma-names = "tx", 1801 "rx"; 1802 status = "disabled"; 1803 }; 1804 1805 uart11: serial@a8c000 { 1806 compatible = "qcom,geni-uart"; 1807 reg = <0x0 0xa8c000 0x0 0x4000>; 1808 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1809 clock-names = "se"; 1810 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1811 pinctrl-names = "default"; 1812 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1813 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1814 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1815 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1816 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1817 interconnect-names = "qup-core", 1818 "qup-config"; 1819 power-domains = <&rpmhpd RPMHPD_CX>; 1820 operating-points-v2 = <&qup_opp_table>; 1821 status = "disabled"; 1822 }; 1823 1824 i2c12: i2c@a90000 { 1825 compatible = "qcom,geni-i2c"; 1826 reg = <0x0 0xa90000 0x0 0x4000>; 1827 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1828 clock-names = "se"; 1829 pinctrl-0 = <&qup_i2c12_data_clk>; 1830 pinctrl-names = "default"; 1831 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1832 #address-cells = <1>; 1833 #size-cells = <0>; 1834 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1835 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1836 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1837 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1838 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1839 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1840 interconnect-names = "qup-core", 1841 "qup-config", 1842 "qup-memory"; 1843 power-domains = <&rpmhpd RPMHPD_CX>; 1844 required-opps = <&rpmhpd_opp_low_svs>; 1845 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1846 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1847 dma-names = "tx", 1848 "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 spi12: spi@a90000 { 1853 compatible = "qcom,geni-spi"; 1854 reg = <0x0 0xa90000 0x0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1856 clock-names = "se"; 1857 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1858 pinctrl-names = "default"; 1859 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1860 #address-cells = <1>; 1861 #size-cells = <0>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1863 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1864 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1865 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1866 interconnect-names = "qup-core", 1867 "qup-config"; 1868 power-domains = <&rpmhpd RPMHPD_CX>; 1869 operating-points-v2 = <&qup_opp_table>; 1870 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1871 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1872 dma-names = "tx", 1873 "rx"; 1874 status = "disabled"; 1875 }; 1876 1877 uart12: serial@a90000 { 1878 compatible = "qcom,geni-uart"; 1879 reg = <0x0 0xa90000 0x0 0x4000>; 1880 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1881 clock-names = "se"; 1882 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1883 <&qup_uart12_tx>, <&qup_uart12_rx>; 1884 pinctrl-names = "default"; 1885 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1886 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1887 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1888 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1889 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1890 interconnect-names = "qup-core", 1891 "qup-config"; 1892 power-domains = <&rpmhpd RPMHPD_CX>; 1893 operating-points-v2 = <&qup_opp_table>; 1894 status = "disabled"; 1895 }; 1896 1897 i2c13: i2c@a94000 { 1898 compatible = "qcom,geni-i2c"; 1899 reg = <0x0 0xa94000 0x0 0x4000>; 1900 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1901 clock-names = "se"; 1902 pinctrl-0 = <&qup_i2c13_data_clk>; 1903 pinctrl-names = "default"; 1904 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1905 #address-cells = <1>; 1906 #size-cells = <0>; 1907 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1908 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1909 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1910 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1911 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1912 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1913 interconnect-names = "qup-core", 1914 "qup-config", 1915 "qup-memory"; 1916 power-domains = <&rpmhpd RPMHPD_CX>; 1917 required-opps = <&rpmhpd_opp_low_svs>; 1918 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1919 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1920 dma-names = "tx", 1921 "rx"; 1922 status = "disabled"; 1923 }; 1924 1925 spi13: spi@a94000 { 1926 compatible = "qcom,geni-spi"; 1927 reg = <0x0 0xa94000 0x0 0x4000>; 1928 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1929 clock-names = "se"; 1930 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1931 pinctrl-names = "default"; 1932 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1933 #address-cells = <1>; 1934 #size-cells = <0>; 1935 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1936 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1937 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1938 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1939 interconnect-names = "qup-core", 1940 "qup-config"; 1941 power-domains = <&rpmhpd RPMHPD_CX>; 1942 operating-points-v2 = <&qup_opp_table>; 1943 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1944 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1945 dma-names = "tx", 1946 "rx"; 1947 status = "disabled"; 1948 }; 1949 1950 uart13: serial@a94000 { 1951 compatible = "qcom,geni-uart"; 1952 reg = <0x0 0xa94000 0x0 0x4000>; 1953 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1954 clock-names = "se"; 1955 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1956 <&qup_uart13_tx>, <&qup_uart13_rx>; 1957 pinctrl-names = "default"; 1958 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1959 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1960 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1961 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1962 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1963 interconnect-names = "qup-core", 1964 "qup-config"; 1965 power-domains = <&rpmhpd RPMHPD_CX>; 1966 operating-points-v2 = <&qup_opp_table>; 1967 status = "disabled"; 1968 }; 1969 1970 i2c14: i2c@a98000 { 1971 compatible = "qcom,geni-i2c"; 1972 reg = <0x0 0xa98000 0x0 0x4000>; 1973 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1974 clock-names = "se"; 1975 pinctrl-0 = <&qup_i2c14_data_clk>; 1976 pinctrl-names = "default"; 1977 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1978 #address-cells = <1>; 1979 #size-cells = <0>; 1980 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1981 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1982 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1983 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1984 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1985 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1986 interconnect-names = "qup-core", 1987 "qup-config", 1988 "qup-memory"; 1989 power-domains = <&rpmhpd RPMHPD_CX>; 1990 required-opps = <&rpmhpd_opp_low_svs>; 1991 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1992 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1993 dma-names = "tx", 1994 "rx"; 1995 status = "disabled"; 1996 }; 1997 1998 spi14: spi@a98000 { 1999 compatible = "qcom,geni-spi"; 2000 reg = <0x0 0xa98000 0x0 0x4000>; 2001 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2002 clock-names = "se"; 2003 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2004 pinctrl-names = "default"; 2005 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2006 #address-cells = <1>; 2007 #size-cells = <0>; 2008 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2009 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2011 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2012 interconnect-names = "qup-core", 2013 "qup-config"; 2014 power-domains = <&rpmhpd RPMHPD_CX>; 2015 operating-points-v2 = <&qup_opp_table>; 2016 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2017 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2018 dma-names = "tx", 2019 "rx"; 2020 status = "disabled"; 2021 }; 2022 2023 uart14: serial@a98000 { 2024 compatible = "qcom,geni-uart"; 2025 reg = <0x0 0xa98000 0x0 0x4000>; 2026 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2027 clock-names = "se"; 2028 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2029 <&qup_uart14_tx>, <&qup_uart14_rx>; 2030 pinctrl-names = "default"; 2031 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2032 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2033 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2034 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2035 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2036 interconnect-names = "qup-core", 2037 "qup-config"; 2038 power-domains = <&rpmhpd RPMHPD_CX>; 2039 operating-points-v2 = <&qup_opp_table>; 2040 status = "disabled"; 2041 }; 2042 2043 i2c15: i2c@a9c000 { 2044 compatible = "qcom,geni-i2c"; 2045 reg = <0x0 0xa9c000 0x0 0x4000>; 2046 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2047 clock-names = "se"; 2048 pinctrl-0 = <&qup_i2c15_data_clk>; 2049 pinctrl-names = "default"; 2050 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2054 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2055 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2056 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2057 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2058 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2059 interconnect-names = "qup-core", 2060 "qup-config", 2061 "qup-memory"; 2062 power-domains = <&rpmhpd RPMHPD_CX>; 2063 required-opps = <&rpmhpd_opp_low_svs>; 2064 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2065 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2066 dma-names = "tx", 2067 "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi15: spi@a9c000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0x0 0xa9c000 0x0 0x4000>; 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2077 pinctrl-names = "default"; 2078 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2082 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2083 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2084 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2085 interconnect-names = "qup-core", 2086 "qup-config"; 2087 power-domains = <&rpmhpd RPMHPD_CX>; 2088 operating-points-v2 = <&qup_opp_table>; 2089 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2090 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2091 dma-names = "tx", 2092 "rx"; 2093 status = "disabled"; 2094 }; 2095 2096 uart15: serial@a9c000 { 2097 compatible = "qcom,geni-uart"; 2098 reg = <0x0 0xa9c000 0x0 0x4000>; 2099 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2100 clock-names = "se"; 2101 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2102 <&qup_uart15_tx>, <&qup_uart15_rx>; 2103 pinctrl-names = "default"; 2104 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2105 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2106 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2108 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2109 interconnect-names = "qup-core", 2110 "qup-config"; 2111 power-domains = <&rpmhpd RPMHPD_CX>; 2112 operating-points-v2 = <&qup_opp_table>; 2113 status = "disabled"; 2114 }; 2115 }; 2116 2117 gpi_dma3: dma-controller@b00000 { 2118 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2119 reg = <0x0 0xb00000 0x0 0x60000>; 2120 #dma-cells = <3>; 2121 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2125 iommus = <&apps_smmu 0x56 0x0>; 2126 dma-channels = <4>; 2127 dma-channel-mask = <0xf>; 2128 dma-coherent; 2129 status = "disabled"; 2130 }; 2131 2132 qupv3_id_3: geniqup@bc0000 { 2133 compatible = "qcom,geni-se-qup"; 2134 reg = <0x0 0xbc0000 0x0 0x2000>; 2135 ranges; 2136 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2137 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2138 clock-names = "m-ahb", 2139 "s-ahb"; 2140 #address-cells = <2>; 2141 #size-cells = <2>; 2142 iommus = <&apps_smmu 0x43 0x0>; 2143 dma-coherent; 2144 status = "disabled"; 2145 2146 i2c16: i2c@b80000 { 2147 compatible = "qcom,geni-i2c"; 2148 reg = <0x0 0xb80000 0x0 0x4000>; 2149 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2150 clock-names = "se"; 2151 pinctrl-0 = <&qup_i2c16_data_clk>; 2152 pinctrl-names = "default"; 2153 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2157 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2158 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2159 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2160 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2162 interconnect-names = "qup-core", 2163 "qup-config", 2164 "qup-memory"; 2165 power-domains = <&rpmhpd RPMHPD_CX>; 2166 required-opps = <&rpmhpd_opp_low_svs>; 2167 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2168 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2169 dma-names = "tx", 2170 "rx"; 2171 status = "disabled"; 2172 }; 2173 2174 spi16: spi@b80000 { 2175 compatible = "qcom,geni-spi"; 2176 reg = <0x0 0xb80000 0x0 0x4000>; 2177 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2178 clock-names = "se"; 2179 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2180 pinctrl-names = "default"; 2181 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2182 #address-cells = <1>; 2183 #size-cells = <0>; 2184 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2185 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2186 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2187 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2188 interconnect-names = "qup-core", 2189 "qup-config"; 2190 power-domains = <&rpmhpd RPMHPD_CX>; 2191 operating-points-v2 = <&qup_opp_table>; 2192 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2193 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2194 dma-names = "tx", 2195 "rx"; 2196 status = "disabled"; 2197 }; 2198 2199 uart16: serial@b80000 { 2200 compatible = "qcom,geni-uart"; 2201 reg = <0x0 0xb80000 0x0 0x4000>; 2202 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2203 clock-names = "se"; 2204 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2205 <&qup_uart16_tx>, <&qup_uart16_rx>; 2206 pinctrl-names = "default"; 2207 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2208 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2209 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2210 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2211 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2212 interconnect-names = "qup-core", 2213 "qup-config"; 2214 power-domains = <&rpmhpd RPMHPD_CX>; 2215 operating-points-v2 = <&qup_opp_table>; 2216 status = "disabled"; 2217 }; 2218 }; 2219 2220 rng: rng@10d2000 { 2221 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2222 reg = <0x0 0x010d2000 0x0 0x1000>; 2223 }; 2224 2225 config_noc: interconnect@14c0000 { 2226 compatible = "qcom,qcs8300-config-noc"; 2227 reg = <0x0 0x014c0000 0x0 0x13080>; 2228 #interconnect-cells = <2>; 2229 qcom,bcm-voters = <&apps_bcm_voter>; 2230 }; 2231 2232 system_noc: interconnect@1680000 { 2233 compatible = "qcom,qcs8300-system-noc"; 2234 reg = <0x0 0x01680000 0x0 0x15080>; 2235 #interconnect-cells = <2>; 2236 qcom,bcm-voters = <&apps_bcm_voter>; 2237 }; 2238 2239 aggre1_noc: interconnect@16c0000 { 2240 compatible = "qcom,qcs8300-aggre1-noc"; 2241 reg = <0x0 0x016c0000 0x0 0x17080>; 2242 #interconnect-cells = <2>; 2243 qcom,bcm-voters = <&apps_bcm_voter>; 2244 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2245 <&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>, 2246 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 2247 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2248 }; 2249 2250 aggre2_noc: interconnect@1700000 { 2251 compatible = "qcom,qcs8300-aggre2-noc"; 2252 reg = <0x0 0x01700000 0x0 0x1a080>; 2253 #interconnect-cells = <2>; 2254 qcom,bcm-voters = <&apps_bcm_voter>; 2255 clocks = <&rpmhcc RPMH_IPA_CLK>; 2256 }; 2257 2258 pcie_anoc: interconnect@1760000 { 2259 compatible = "qcom,qcs8300-pcie-anoc"; 2260 reg = <0x0 0x01760000 0x0 0xc080>; 2261 #interconnect-cells = <2>; 2262 qcom,bcm-voters = <&apps_bcm_voter>; 2263 }; 2264 2265 gpdsp_anoc: interconnect@1780000 { 2266 compatible = "qcom,qcs8300-gpdsp-anoc"; 2267 reg = <0x0 0x01780000 0x0 0xd080>; 2268 #interconnect-cells = <2>; 2269 qcom,bcm-voters = <&apps_bcm_voter>; 2270 }; 2271 2272 mmss_noc: interconnect@17a0000 { 2273 compatible = "qcom,qcs8300-mmss-noc"; 2274 reg = <0x0 0x017a0000 0x0 0x40000>; 2275 #interconnect-cells = <2>; 2276 qcom,bcm-voters = <&apps_bcm_voter>; 2277 }; 2278 2279 pcie0: pci@1c00000 { 2280 device_type = "pci"; 2281 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2282 reg = <0x0 0x01c00000 0x0 0x3000>, 2283 <0x0 0x40000000 0x0 0xf20>, 2284 <0x0 0x40000f20 0x0 0xa8>, 2285 <0x0 0x40001000 0x0 0x4000>, 2286 <0x0 0x40100000 0x0 0x100000>, 2287 <0x0 0x01c03000 0x0 0x1000>; 2288 reg-names = "parf", 2289 "dbi", 2290 "elbi", 2291 "atu", 2292 "config", 2293 "mhi"; 2294 #address-cells = <3>; 2295 #size-cells = <2>; 2296 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2297 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2298 bus-range = <0x00 0xff>; 2299 2300 dma-coherent; 2301 2302 linux,pci-domain = <0>; 2303 num-lanes = <2>; 2304 2305 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2314 interrupt-names = "msi0", 2315 "msi1", 2316 "msi2", 2317 "msi3", 2318 "msi4", 2319 "msi5", 2320 "msi6", 2321 "msi7", 2322 "global"; 2323 2324 #interrupt-cells = <1>; 2325 interrupt-map-mask = <0 0 0 0x7>; 2326 interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2327 <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2328 <0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2329 <0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2330 2331 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2332 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2333 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2334 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2335 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 2336 clock-names = "aux", 2337 "cfg", 2338 "bus_master", 2339 "bus_slave", 2340 "slave_q2a"; 2341 2342 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 2343 assigned-clock-rates = <19200000>; 2344 2345 interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2346 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2347 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2348 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2349 interconnect-names = "pcie-mem", 2350 "cpu-pcie"; 2351 2352 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, 2353 <0x100 &pcie_smmu 0x0001 0x1>; 2354 2355 resets = <&gcc GCC_PCIE_0_BCR>, 2356 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2357 reset-names = "pci", 2358 "link_down"; 2359 2360 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2361 2362 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2363 eq-presets-16gts = /bits/ 8 <0x55 0x55>; 2364 2365 operating-points-v2 = <&pcie0_opp_table>; 2366 2367 status = "disabled"; 2368 2369 pcie0_opp_table: opp-table { 2370 compatible = "operating-points-v2"; 2371 2372 /* GEN 1 x1 */ 2373 opp-2500000 { 2374 opp-hz = /bits/ 64 <2500000>; 2375 required-opps = <&rpmhpd_opp_svs_l1>; 2376 opp-peak-kBps = <250000 1>; 2377 }; 2378 2379 /* GEN 1 x2 and GEN 2 x1 */ 2380 opp-5000000 { 2381 opp-hz = /bits/ 64 <5000000>; 2382 required-opps = <&rpmhpd_opp_svs_l1>; 2383 opp-peak-kBps = <500000 1>; 2384 }; 2385 2386 /* GEN 2 x2 */ 2387 opp-10000000 { 2388 opp-hz = /bits/ 64 <10000000>; 2389 required-opps = <&rpmhpd_opp_svs_l1>; 2390 opp-peak-kBps = <1000000 1>; 2391 }; 2392 2393 /* GEN 3 x1 */ 2394 opp-8000000 { 2395 opp-hz = /bits/ 64 <8000000>; 2396 required-opps = <&rpmhpd_opp_svs_l1>; 2397 opp-peak-kBps = <984500 1>; 2398 }; 2399 2400 /* GEN 3 x2 and GEN 4 x1 */ 2401 opp-16000000 { 2402 opp-hz = /bits/ 64 <16000000>; 2403 required-opps = <&rpmhpd_opp_nom>; 2404 opp-peak-kBps = <1969000 1>; 2405 }; 2406 2407 /* GEN 4 x2 */ 2408 opp-32000000 { 2409 opp-hz = /bits/ 64 <32000000>; 2410 required-opps = <&rpmhpd_opp_nom>; 2411 opp-peak-kBps = <3938000 1>; 2412 }; 2413 }; 2414 2415 pcieport0: pcie@0 { 2416 device_type = "pci"; 2417 reg = <0x0 0x0 0x0 0x0 0x0>; 2418 bus-range = <0x01 0xff>; 2419 2420 #address-cells = <3>; 2421 #size-cells = <2>; 2422 ranges; 2423 phys = <&pcie0_phy>; 2424 }; 2425 }; 2426 2427 pcie0_phy: phy@1c04000 { 2428 compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; 2429 reg = <0x0 0x01c04000 0x0 0x2000>; 2430 2431 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2432 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2433 <&gcc GCC_PCIE_CLKREF_EN>, 2434 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2435 <&gcc GCC_PCIE_0_PIPE_CLK>, 2436 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>; 2437 clock-names = "aux", 2438 "cfg_ahb", 2439 "ref", 2440 "rchng", 2441 "pipe", 2442 "pipediv2"; 2443 2444 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2445 reset-names = "phy"; 2446 2447 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2448 assigned-clock-rates = <100000000>; 2449 2450 #clock-cells = <0>; 2451 clock-output-names = "pcie_0_pipe_clk"; 2452 2453 #phy-cells = <0>; 2454 2455 status = "disabled"; 2456 }; 2457 2458 pcie1: pci@1c10000 { 2459 device_type = "pci"; 2460 compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p"; 2461 reg = <0x0 0x01c10000 0x0 0x3000>, 2462 <0x0 0x60000000 0x0 0xf20>, 2463 <0x0 0x60000f20 0x0 0xa8>, 2464 <0x0 0x60001000 0x0 0x4000>, 2465 <0x0 0x60100000 0x0 0x100000>, 2466 <0x0 0x01c13000 0x0 0x1000>; 2467 reg-names = "parf", 2468 "dbi", 2469 "elbi", 2470 "atu", 2471 "config", 2472 "mhi"; 2473 #address-cells = <3>; 2474 #size-cells = <2>; 2475 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2476 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x1fd00000>; 2477 bus-range = <0x00 0xff>; 2478 2479 dma-coherent; 2480 2481 linux,pci-domain = <1>; 2482 num-lanes = <4>; 2483 2484 interrupts = <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2492 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>; 2493 interrupt-names = "msi0", 2494 "msi1", 2495 "msi2", 2496 "msi3", 2497 "msi4", 2498 "msi5", 2499 "msi6", 2500 "msi7", 2501 "global"; 2502 #interrupt-cells = <1>; 2503 interrupt-map-mask = <0 0 0 0x7>; 2504 interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2505 <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2506 <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2507 <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2510 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2511 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2512 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2513 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; 2514 clock-names = "aux", 2515 "cfg", 2516 "bus_master", 2517 "bus_slave", 2518 "slave_q2a"; 2519 2520 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2521 assigned-clock-rates = <19200000>; 2522 2523 interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2524 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2525 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2526 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 2527 interconnect-names = "pcie-mem", "cpu-pcie"; 2528 2529 iommu-map = <0x0 &pcie_smmu 0x0080 0x1>, 2530 <0x100 &pcie_smmu 0x0081 0x1>; 2531 2532 resets = <&gcc GCC_PCIE_1_BCR>, 2533 <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; 2534 reset-names = "pci", 2535 "link_down"; 2536 2537 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2538 2539 eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; 2540 eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; 2541 2542 operating-points-v2 = <&pcie1_opp_table>; 2543 2544 status = "disabled"; 2545 2546 pcie1_opp_table: opp-table { 2547 compatible = "operating-points-v2"; 2548 2549 /* GEN 1 x1 */ 2550 opp-2500000 { 2551 opp-hz = /bits/ 64 <2500000>; 2552 required-opps = <&rpmhpd_opp_svs_l1>; 2553 opp-peak-kBps = <250000 1>; 2554 }; 2555 2556 /* GEN 1 x2 and GEN 2 x1 */ 2557 opp-5000000 { 2558 opp-hz = /bits/ 64 <5000000>; 2559 required-opps = <&rpmhpd_opp_svs_l1>; 2560 opp-peak-kBps = <500000 1>; 2561 }; 2562 2563 /* GEN 1 x4 and GEN 2 x2 */ 2564 opp-10000000 { 2565 opp-hz = /bits/ 64 <10000000>; 2566 required-opps = <&rpmhpd_opp_svs_l1>; 2567 opp-peak-kBps = <1000000 1>; 2568 }; 2569 2570 /* GEN 2 x4 */ 2571 opp-20000000 { 2572 opp-hz = /bits/ 64 <20000000>; 2573 required-opps = <&rpmhpd_opp_low_svs>; 2574 opp-peak-kBps = <2000000 1>; 2575 }; 2576 2577 /* GEN 3 x1 */ 2578 opp-8000000 { 2579 opp-hz = /bits/ 64 <8000000>; 2580 required-opps = <&rpmhpd_opp_svs_l1>; 2581 opp-peak-kBps = <984500 1>; 2582 }; 2583 2584 /* GEN 3 x2 and GEN 4 x1 */ 2585 opp-16000000 { 2586 opp-hz = /bits/ 64 <16000000>; 2587 required-opps = <&rpmhpd_opp_nom>; 2588 opp-peak-kBps = <1969000 1>; 2589 }; 2590 2591 /* GEN 3 x4 and GEN 4 x2 */ 2592 opp-32000000 { 2593 opp-hz = /bits/ 64 <32000000>; 2594 required-opps = <&rpmhpd_opp_nom>; 2595 opp-peak-kBps = <3938000 1>; 2596 }; 2597 2598 /* GEN 4 x4 */ 2599 opp-64000000 { 2600 opp-hz = /bits/ 64 <64000000>; 2601 required-opps = <&rpmhpd_opp_nom>; 2602 opp-peak-kBps = <7876000 1>; 2603 }; 2604 }; 2605 2606 pcieport1: pcie@0 { 2607 device_type = "pci"; 2608 reg = <0x0 0x0 0x0 0x0 0x0>; 2609 bus-range = <0x01 0xff>; 2610 2611 #address-cells = <3>; 2612 #size-cells = <2>; 2613 ranges; 2614 phys = <&pcie1_phy>; 2615 }; 2616 }; 2617 2618 pcie1_phy: phy@1c14000 { 2619 compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy"; 2620 reg = <0x0 0x01c14000 0x0 0x4000>; 2621 2622 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2623 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2624 <&gcc GCC_PCIE_CLKREF_EN>, 2625 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2626 <&gcc GCC_PCIE_1_PIPE_CLK>, 2627 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>; 2628 clock-names = "aux", 2629 "cfg_ahb", 2630 "ref", 2631 "rchng", 2632 "pipe", 2633 "pipediv2"; 2634 2635 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2636 assigned-clock-rates = <100000000>; 2637 2638 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2639 reset-names = "phy"; 2640 2641 #clock-cells = <0>; 2642 clock-output-names = "pcie_1_pipe_clk"; 2643 2644 #phy-cells = <0>; 2645 2646 status = "disabled"; 2647 }; 2648 2649 ufs_mem_hc: ufs@1d84000 { 2650 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2651 reg = <0x0 0x01d84000 0x0 0x3000>; 2652 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2653 phys = <&ufs_mem_phy>; 2654 phy-names = "ufsphy"; 2655 lanes-per-direction = <2>; 2656 #reset-cells = <1>; 2657 resets = <&gcc GCC_UFS_PHY_BCR>; 2658 reset-names = "rst"; 2659 2660 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2661 required-opps = <&rpmhpd_opp_nom>; 2662 2663 iommus = <&apps_smmu 0x100 0x0>; 2664 dma-coherent; 2665 2666 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2667 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2668 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2669 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2670 interconnect-names = "ufs-ddr", 2671 "cpu-ufs"; 2672 2673 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2674 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2675 <&gcc GCC_UFS_PHY_AHB_CLK>, 2676 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2677 <&rpmhcc RPMH_CXO_CLK>, 2678 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2679 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2680 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2681 clock-names = "core_clk", 2682 "bus_aggr_clk", 2683 "iface_clk", 2684 "core_clk_unipro", 2685 "ref_clk", 2686 "tx_lane0_sync_clk", 2687 "rx_lane0_sync_clk", 2688 "rx_lane1_sync_clk"; 2689 freq-table-hz = <75000000 300000000>, 2690 <0 0>, 2691 <0 0>, 2692 <75000000 300000000>, 2693 <0 0>, 2694 <0 0>, 2695 <0 0>, 2696 <0 0>; 2697 qcom,ice = <&ice>; 2698 status = "disabled"; 2699 }; 2700 2701 ufs_mem_phy: phy@1d87000 { 2702 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2703 reg = <0x0 0x01d87000 0x0 0xe10>; 2704 /* 2705 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2706 * enables the CXO clock to eDP *and* UFS PHY. 2707 */ 2708 clocks = <&rpmhcc RPMH_CXO_CLK>, 2709 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2710 <&gcc GCC_EDP_REF_CLKREF_EN>; 2711 clock-names = "ref", 2712 "ref_aux", 2713 "qref"; 2714 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2715 2716 resets = <&ufs_mem_hc 0>; 2717 reset-names = "ufsphy"; 2718 2719 #phy-cells = <0>; 2720 status = "disabled"; 2721 }; 2722 2723 cryptobam: dma-controller@1dc4000 { 2724 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2725 reg = <0x0 0x01dc4000 0x0 0x28000>; 2726 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2727 #dma-cells = <1>; 2728 qcom,ee = <0>; 2729 qcom,controlled-remotely; 2730 num-channels = <20>; 2731 qcom,num-ees = <4>; 2732 iommus = <&apps_smmu 0x480 0x00>, 2733 <&apps_smmu 0x481 0x00>; 2734 }; 2735 2736 ice: crypto@1d88000 { 2737 compatible = "qcom,qcs8300-inline-crypto-engine", 2738 "qcom,inline-crypto-engine"; 2739 reg = <0x0 0x01d88000 0x0 0x18000>; 2740 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2741 }; 2742 2743 crypto: crypto@1dfa000 { 2744 compatible = "qcom,qcs8300-qce", "qcom,sm8150-qce", "qcom,qce"; 2745 reg = <0x0 0x01dfa000 0x0 0x6000>; 2746 dmas = <&cryptobam 4>, <&cryptobam 5>; 2747 dma-names = "rx", "tx"; 2748 iommus = <&apps_smmu 0x480 0x0>, 2749 <&apps_smmu 0x481 0x0>; 2750 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE0 QCOM_ICC_TAG_ALWAYS 2751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2752 interconnect-names = "memory"; 2753 }; 2754 2755 tcsr_mutex: hwlock@1f40000 { 2756 compatible = "qcom,tcsr-mutex"; 2757 reg = <0x0 0x01f40000 0x0 0x20000>; 2758 #hwlock-cells = <1>; 2759 }; 2760 2761 tcsr: syscon@1fc0000 { 2762 compatible = "qcom,qcs8300-tcsr", "syscon"; 2763 reg = <0x0 0x1fc0000 0x0 0x30000>; 2764 }; 2765 2766 remoteproc_adsp: remoteproc@3000000 { 2767 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2768 reg = <0x0 0x3000000 0x0 0x00100>; 2769 2770 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2771 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2772 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2773 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2774 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2775 interrupt-names = "wdog", 2776 "fatal", 2777 "ready", 2778 "handover", 2779 "stop-ack"; 2780 2781 clocks = <&rpmhcc RPMH_CXO_CLK>; 2782 clock-names = "xo"; 2783 2784 power-domains = <&rpmhpd RPMHPD_LCX>, 2785 <&rpmhpd RPMHPD_LMX>; 2786 power-domain-names = "lcx", 2787 "lmx"; 2788 2789 memory-region = <&adsp_mem>; 2790 2791 qcom,qmp = <&aoss_qmp>; 2792 2793 qcom,smem-states = <&smp2p_adsp_out 0>; 2794 qcom,smem-state-names = "stop"; 2795 2796 status = "disabled"; 2797 2798 remoteproc_adsp_glink: glink-edge { 2799 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2800 IPCC_MPROC_SIGNAL_GLINK_QMP 2801 IRQ_TYPE_EDGE_RISING>; 2802 mboxes = <&ipcc IPCC_CLIENT_LPASS 2803 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2804 2805 label = "lpass"; 2806 qcom,remote-pid = <2>; 2807 2808 fastrpc { 2809 compatible = "qcom,fastrpc"; 2810 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2811 label = "adsp"; 2812 memory-region = <&adsp_rpc_remote_heap_mem>; 2813 qcom,vmids = <QCOM_SCM_VMID_LPASS 2814 QCOM_SCM_VMID_ADSP_HEAP>; 2815 #address-cells = <1>; 2816 #size-cells = <0>; 2817 2818 compute-cb@3 { 2819 compatible = "qcom,fastrpc-compute-cb"; 2820 reg = <3>; 2821 iommus = <&apps_smmu 0x2003 0x0>; 2822 dma-coherent; 2823 }; 2824 2825 compute-cb@4 { 2826 compatible = "qcom,fastrpc-compute-cb"; 2827 reg = <4>; 2828 iommus = <&apps_smmu 0x2004 0x0>; 2829 dma-coherent; 2830 }; 2831 2832 compute-cb@5 { 2833 compatible = "qcom,fastrpc-compute-cb"; 2834 reg = <5>; 2835 iommus = <&apps_smmu 0x2005 0x0>; 2836 dma-coherent; 2837 }; 2838 }; 2839 2840 gpr { 2841 compatible = "qcom,gpr"; 2842 qcom,glink-channels = "adsp_apps"; 2843 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2844 qcom,intents = <512 20>; 2845 #address-cells = <1>; 2846 #size-cells = <0>; 2847 2848 q6apm: service@1 { 2849 compatible = "qcom,q6apm"; 2850 reg = <GPR_APM_MODULE_IID>; 2851 #sound-dai-cells = <0>; 2852 qcom,protection-domain = "avs/audio", 2853 "msm/adsp/audio_pd"; 2854 2855 q6apmbedai: bedais { 2856 compatible = "qcom,q6apm-lpass-dais"; 2857 #sound-dai-cells = <1>; 2858 }; 2859 2860 q6apmdai: dais { 2861 compatible = "qcom,q6apm-dais"; 2862 iommus = <&apps_smmu 0x2001 0x0>; 2863 }; 2864 }; 2865 2866 q6prm: service@2 { 2867 compatible = "qcom,q6prm"; 2868 reg = <GPR_PRM_MODULE_IID>; 2869 qcom,protection-domain = "avs/audio", 2870 "msm/adsp/audio_pd"; 2871 2872 q6prmcc: clock-controller { 2873 compatible = "qcom,q6prm-lpass-clocks"; 2874 #clock-cells = <2>; 2875 }; 2876 }; 2877 }; 2878 }; 2879 }; 2880 2881 lpass_tlmm: pinctrl@3440000 { 2882 compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; 2883 reg = <0x0 0x03440000 0x0 0x20000>, 2884 <0x0 0x034d0000 0x0 0x10000>; 2885 2886 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2887 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2888 clock-names = "core", "audio"; 2889 2890 gpio-controller; 2891 #gpio-cells = <2>; 2892 gpio-ranges = <&lpass_tlmm 0 0 23>; 2893 2894 quad_mclk_active: quad-mclk-state { 2895 clk-pins { 2896 pins = "gpio5"; 2897 function = "ext_mclk1_c"; 2898 drive-strength = <8>; 2899 bias-disable; 2900 }; 2901 }; 2902 2903 quad_mi2s_active: quad-active-state { 2904 data-pins { 2905 pins = "gpio2", "gpio3"; 2906 function = "qua_mi2s_data"; 2907 drive-strength = <8>; 2908 bias-disable; 2909 }; 2910 2911 sclk-pins { 2912 pins = "gpio0"; 2913 function = "qua_mi2s_sclk"; 2914 drive-strength = <8>; 2915 bias-disable; 2916 }; 2917 2918 ws-pins { 2919 pins = "gpio1"; 2920 function = "qua_mi2s_ws"; 2921 drive-strength = <8>; 2922 bias-disable; 2923 }; 2924 }; 2925 2926 lpi_i2s4_active: lpi_i2s4-active-state { 2927 data0-pins { 2928 pins = "gpio17"; 2929 function = "i2s4_data"; 2930 drive-strength = <8>; 2931 bias-disable; 2932 }; 2933 2934 clk-pins { 2935 pins = "gpio12"; 2936 function = "i2s4_clk"; 2937 drive-strength = <8>; 2938 bias-disable; 2939 }; 2940 2941 ws-pins { 2942 pins = "gpio13"; 2943 function = "i2s4_ws"; 2944 drive-strength = <8>; 2945 bias-disable; 2946 }; 2947 }; 2948 }; 2949 2950 lpass_ag_noc: interconnect@3c40000 { 2951 compatible = "qcom,qcs8300-lpass-ag-noc"; 2952 reg = <0x0 0x03c40000 0x0 0x17200>; 2953 #interconnect-cells = <2>; 2954 qcom,bcm-voters = <&apps_bcm_voter>; 2955 }; 2956 2957 ctcu@4001000 { 2958 compatible = "qcom,qcs8300-ctcu", "qcom,sa8775p-ctcu"; 2959 reg = <0x0 0x04001000 0x0 0x1000>; 2960 2961 clocks = <&aoss_qmp>; 2962 clock-names = "apb"; 2963 2964 in-ports { 2965 #address-cells = <1>; 2966 #size-cells = <0>; 2967 2968 port@0 { 2969 reg = <0>; 2970 2971 ctcu_in0: endpoint { 2972 remote-endpoint = <&etr0_out>; 2973 }; 2974 }; 2975 2976 port@1 { 2977 reg = <1>; 2978 2979 ctcu_in1: endpoint { 2980 remote-endpoint = <&etr1_out>; 2981 }; 2982 }; 2983 }; 2984 }; 2985 2986 stm@4002000 { 2987 compatible = "arm,coresight-stm", "arm,primecell"; 2988 reg = <0x0 0x04002000 0x0 0x1000>, 2989 <0x0 0x16280000 0x0 0x180000>; 2990 reg-names = "stm-base", 2991 "stm-stimulus-base"; 2992 2993 clocks = <&aoss_qmp>; 2994 clock-names = "apb_pclk"; 2995 2996 out-ports { 2997 port { 2998 stm_out: endpoint { 2999 remote-endpoint = <&funnel0_in7>; 3000 }; 3001 }; 3002 }; 3003 }; 3004 3005 tpda@4004000 { 3006 compatible = "qcom,coresight-tpda", "arm,primecell"; 3007 reg = <0x0 0x04004000 0x0 0x1000>; 3008 3009 clocks = <&aoss_qmp>; 3010 clock-names = "apb_pclk"; 3011 3012 in-ports { 3013 #address-cells = <1>; 3014 #size-cells = <0>; 3015 3016 port@0 { 3017 reg = <0>; 3018 3019 swao_rep_out0: endpoint { 3020 remote-endpoint = <&qdss_rep_in>; 3021 }; 3022 }; 3023 3024 port@1 { 3025 reg = <1>; 3026 3027 qdss_tpda_in1: endpoint { 3028 remote-endpoint = <&qdss_tpdm1_out>; 3029 }; 3030 }; 3031 }; 3032 3033 out-ports { 3034 port { 3035 qdss_tpda_out: endpoint { 3036 remote-endpoint = <&funnel0_in6>; 3037 }; 3038 }; 3039 }; 3040 }; 3041 3042 tpdm@400f000 { 3043 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3044 reg = <0x0 0x0400f000 0x0 0x1000>; 3045 3046 clocks = <&aoss_qmp>; 3047 clock-names = "apb_pclk"; 3048 3049 qcom,cmb-element-bits = <32>; 3050 qcom,cmb-msrs-num = <32>; 3051 3052 out-ports { 3053 port { 3054 qdss_tpdm1_out: endpoint { 3055 remote-endpoint = <&qdss_tpda_in1>; 3056 }; 3057 }; 3058 }; 3059 }; 3060 3061 funnel@4041000 { 3062 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3063 reg = <0x0 0x04041000 0x0 0x1000>; 3064 3065 clocks = <&aoss_qmp>; 3066 clock-names = "apb_pclk"; 3067 3068 in-ports { 3069 #address-cells = <1>; 3070 #size-cells = <0>; 3071 3072 port@6 { 3073 reg = <6>; 3074 3075 funnel0_in6: endpoint { 3076 remote-endpoint = <&qdss_tpda_out>; 3077 }; 3078 }; 3079 3080 port@7 { 3081 reg = <7>; 3082 3083 funnel0_in7: endpoint { 3084 remote-endpoint = <&stm_out>; 3085 }; 3086 }; 3087 }; 3088 3089 out-ports { 3090 port { 3091 funnel0_out: endpoint { 3092 remote-endpoint = <&qdss_funnel_in0>; 3093 }; 3094 }; 3095 }; 3096 }; 3097 3098 funnel@4042000 { 3099 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3100 reg = <0x0 0x04042000 0x0 0x1000>; 3101 3102 clocks = <&aoss_qmp>; 3103 clock-names = "apb_pclk"; 3104 3105 in-ports { 3106 #address-cells = <1>; 3107 #size-cells = <0>; 3108 3109 port@4 { 3110 reg = <4>; 3111 3112 funnel1_in4: endpoint { 3113 remote-endpoint = <&apss_funnel1_out>; 3114 }; 3115 }; 3116 3117 port@5 { 3118 reg = <5>; 3119 3120 funnel1_in5: endpoint { 3121 remote-endpoint = <&dlct0_funnel_out>; 3122 }; 3123 }; 3124 3125 port@6 { 3126 reg = <6>; 3127 3128 funnel1_in6: endpoint { 3129 remote-endpoint = <&dlmm_funnel_out>; 3130 }; 3131 }; 3132 3133 port@7 { 3134 reg = <7>; 3135 3136 funnel1_in7: endpoint { 3137 remote-endpoint = <&dlst_ch_funnel_out>; 3138 }; 3139 }; 3140 }; 3141 3142 out-ports { 3143 port { 3144 funnel1_out: endpoint { 3145 remote-endpoint = <&qdss_funnel_in1>; 3146 }; 3147 }; 3148 }; 3149 }; 3150 3151 funnel@4045000 { 3152 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3153 reg = <0x0 0x04045000 0x0 0x1000>; 3154 3155 clocks = <&aoss_qmp>; 3156 clock-names = "apb_pclk"; 3157 3158 in-ports { 3159 #address-cells = <1>; 3160 #size-cells = <0>; 3161 3162 port@0 { 3163 reg = <0>; 3164 3165 qdss_funnel_in0: endpoint { 3166 remote-endpoint = <&funnel0_out>; 3167 }; 3168 }; 3169 3170 port@1 { 3171 reg = <1>; 3172 3173 qdss_funnel_in1: endpoint { 3174 remote-endpoint = <&funnel1_out>; 3175 }; 3176 }; 3177 }; 3178 3179 out-ports { 3180 port { 3181 qdss_funnel_out: endpoint { 3182 remote-endpoint = <&aoss_funnel_in7>; 3183 }; 3184 }; 3185 }; 3186 }; 3187 3188 replicator@4046000 { 3189 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3190 reg = <0x0 0x04046000 0x0 0x1000>; 3191 3192 clocks = <&aoss_qmp>; 3193 clock-names = "apb_pclk"; 3194 3195 in-ports { 3196 port { 3197 qdss_rep_in: endpoint { 3198 remote-endpoint = <&swao_rep_out0>; 3199 }; 3200 }; 3201 }; 3202 3203 out-ports { 3204 port { 3205 qdss_rep_out0: endpoint { 3206 remote-endpoint = <&etr_rep_in>; 3207 }; 3208 }; 3209 }; 3210 }; 3211 3212 tmc@4048000 { 3213 compatible = "arm,coresight-tmc", "arm,primecell"; 3214 reg = <0x0 0x04048000 0x0 0x1000>; 3215 3216 clocks = <&aoss_qmp>; 3217 clock-names = "apb_pclk"; 3218 iommus = <&apps_smmu 0x04c0 0x00>; 3219 3220 arm,scatter-gather; 3221 3222 in-ports { 3223 port { 3224 etr0_in: endpoint { 3225 remote-endpoint = <&etr_rep_out0>; 3226 }; 3227 }; 3228 }; 3229 3230 out-ports { 3231 port { 3232 etr0_out: endpoint { 3233 remote-endpoint = <&ctcu_in0>; 3234 }; 3235 }; 3236 }; 3237 }; 3238 3239 replicator@404e000 { 3240 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3241 reg = <0x0 0x0404e000 0x0 0x1000>; 3242 3243 clocks = <&aoss_qmp>; 3244 clock-names = "apb_pclk"; 3245 3246 in-ports { 3247 port { 3248 etr_rep_in: endpoint { 3249 remote-endpoint = <&qdss_rep_out0>; 3250 }; 3251 }; 3252 }; 3253 3254 out-ports { 3255 #address-cells = <1>; 3256 #size-cells = <0>; 3257 3258 port@0 { 3259 reg = <0>; 3260 3261 etr_rep_out0: endpoint { 3262 remote-endpoint = <&etr0_in>; 3263 }; 3264 }; 3265 3266 port@1 { 3267 reg = <1>; 3268 3269 etr_rep_out1: endpoint { 3270 remote-endpoint = <&etr1_in>; 3271 }; 3272 }; 3273 }; 3274 }; 3275 3276 tmc@404f000 { 3277 compatible = "arm,coresight-tmc", "arm,primecell"; 3278 reg = <0x0 0x0404f000 0x0 0x1000>; 3279 3280 clocks = <&aoss_qmp>; 3281 clock-names = "apb_pclk"; 3282 iommus = <&apps_smmu 0x04a0 0x40>; 3283 3284 arm,scatter-gather; 3285 arm,buffer-size = <0x400000>; 3286 3287 in-ports { 3288 port { 3289 etr1_in: endpoint { 3290 remote-endpoint = <&etr_rep_out1>; 3291 }; 3292 }; 3293 }; 3294 3295 out-ports { 3296 port { 3297 etr1_out: endpoint { 3298 remote-endpoint = <&ctcu_in1>; 3299 }; 3300 }; 3301 }; 3302 }; 3303 3304 tpdm@4841000 { 3305 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3306 reg = <0x0 0x04841000 0x0 0x1000>; 3307 3308 clocks = <&aoss_qmp>; 3309 clock-names = "apb_pclk"; 3310 3311 qcom,cmb-element-bits = <32>; 3312 qcom,cmb-msrs-num = <32>; 3313 3314 out-ports { 3315 port { 3316 prng_tpdm_out: endpoint { 3317 remote-endpoint = <&dlct0_tpda_in19>; 3318 }; 3319 }; 3320 }; 3321 }; 3322 3323 tpdm@4850000 { 3324 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3325 reg = <0x0 0x04850000 0x0 0x1000>; 3326 3327 clocks = <&aoss_qmp>; 3328 clock-names = "apb_pclk"; 3329 3330 qcom,cmb-element-bits = <64>; 3331 qcom,cmb-msrs-num = <32>; 3332 qcom,dsb-element-bits = <32>; 3333 qcom,dsb-msrs-num = <32>; 3334 3335 out-ports { 3336 port { 3337 pimem_tpdm_out: endpoint { 3338 remote-endpoint = <&dlct0_tpda_in25>; 3339 }; 3340 }; 3341 }; 3342 }; 3343 3344 tpdm@4860000 { 3345 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3346 reg = <0x0 0x04860000 0x0 0x1000>; 3347 3348 clocks = <&aoss_qmp>; 3349 clock-names = "apb_pclk"; 3350 3351 qcom,dsb-element-bits = <32>; 3352 qcom,dsb-msrs-num = <32>; 3353 3354 out-ports { 3355 port { 3356 dlst_ch_tpdm0_out: endpoint { 3357 remote-endpoint = <&dlst_ch_tpda_in8>; 3358 }; 3359 }; 3360 }; 3361 }; 3362 3363 tpda@4864000 { 3364 compatible = "qcom,coresight-tpda", "arm,primecell"; 3365 reg = <0x0 0x04864000 0x0 0x1000>; 3366 3367 clocks = <&aoss_qmp>; 3368 clock-names = "apb_pclk"; 3369 3370 in-ports { 3371 #address-cells = <1>; 3372 #size-cells = <0>; 3373 3374 port@8 { 3375 reg = <8>; 3376 3377 dlst_ch_tpda_in8: endpoint { 3378 remote-endpoint = <&dlst_ch_tpdm0_out>; 3379 }; 3380 }; 3381 }; 3382 3383 out-ports { 3384 port { 3385 dlst_ch_tpda_out: endpoint { 3386 remote-endpoint = <&dlst_ch_funnel_in0>; 3387 }; 3388 }; 3389 }; 3390 }; 3391 3392 funnel@4865000 { 3393 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3394 reg = <0x0 0x04865000 0x0 0x1000>; 3395 3396 clocks = <&aoss_qmp>; 3397 clock-names = "apb_pclk"; 3398 3399 in-ports { 3400 #address-cells = <1>; 3401 #size-cells = <0>; 3402 3403 port@0 { 3404 reg = <0>; 3405 3406 dlst_ch_funnel_in0: endpoint { 3407 remote-endpoint = <&dlst_ch_tpda_out>; 3408 }; 3409 }; 3410 3411 port@4 { 3412 reg = <4>; 3413 3414 dlst_ch_funnel_in4: endpoint { 3415 remote-endpoint = <&dlst_funnel_out>; 3416 }; 3417 }; 3418 3419 port@6 { 3420 reg = <6>; 3421 3422 dlst_ch_funnel_in6: endpoint { 3423 remote-endpoint = <&gdsp_funnel_out>; 3424 }; 3425 }; 3426 }; 3427 3428 out-ports { 3429 port { 3430 dlst_ch_funnel_out: endpoint { 3431 remote-endpoint = <&funnel1_in7>; 3432 }; 3433 }; 3434 }; 3435 }; 3436 3437 tpdm@4980000 { 3438 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3439 reg = <0x0 0x04980000 0x0 0x1000>; 3440 3441 clocks = <&aoss_qmp>; 3442 clock-names = "apb_pclk"; 3443 3444 qcom,dsb-element-bits = <32>; 3445 qcom,dsb-msrs-num = <32>; 3446 3447 out-ports { 3448 port { 3449 turing2_tpdm_out: endpoint { 3450 remote-endpoint = <&turing2_funnel_in0>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 funnel@4983000 { 3457 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3458 reg = <0x0 0x04983000 0x0 0x1000>; 3459 3460 clocks = <&aoss_qmp>; 3461 clock-names = "apb_pclk"; 3462 3463 in-ports { 3464 port { 3465 turing2_funnel_in0: endpoint { 3466 remote-endpoint = <&turing2_tpdm_out>; 3467 }; 3468 }; 3469 }; 3470 3471 out-ports { 3472 port { 3473 turing2_funnel_out0: endpoint { 3474 remote-endpoint = <&gdsp_tpda_in5>; 3475 }; 3476 }; 3477 }; 3478 }; 3479 3480 tpdm@4ac0000 { 3481 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3482 reg = <0x0 0x04ac0000 0x0 0x1000>; 3483 3484 clocks = <&aoss_qmp>; 3485 clock-names = "apb_pclk"; 3486 3487 qcom,dsb-element-bits = <32>; 3488 qcom,dsb-msrs-num = <32>; 3489 3490 out-ports { 3491 port { 3492 dlmm_tpdm0_out: endpoint { 3493 remote-endpoint = <&dlmm_tpda_in27>; 3494 }; 3495 }; 3496 }; 3497 }; 3498 3499 tpda@4ac4000 { 3500 compatible = "qcom,coresight-tpda", "arm,primecell"; 3501 reg = <0x0 0x04ac4000 0x0 0x1000>; 3502 3503 clocks = <&aoss_qmp>; 3504 clock-names = "apb_pclk"; 3505 3506 in-ports { 3507 #address-cells = <1>; 3508 #size-cells = <0>; 3509 3510 port@1b { 3511 reg = <27>; 3512 3513 dlmm_tpda_in27: endpoint { 3514 remote-endpoint = <&dlmm_tpdm0_out>; 3515 }; 3516 }; 3517 }; 3518 3519 out-ports { 3520 port { 3521 dlmm_tpda_out: endpoint { 3522 remote-endpoint = <&dlmm_funnel_in0>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 funnel@4ac5000 { 3529 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3530 reg = <0x0 0x04ac5000 0x0 0x1000>; 3531 3532 clocks = <&aoss_qmp>; 3533 clock-names = "apb_pclk"; 3534 3535 in-ports { 3536 port { 3537 dlmm_funnel_in0: endpoint { 3538 remote-endpoint = <&dlmm_tpda_out>; 3539 }; 3540 }; 3541 }; 3542 3543 out-ports { 3544 port { 3545 dlmm_funnel_out: endpoint { 3546 remote-endpoint = <&funnel1_in6>; 3547 }; 3548 }; 3549 }; 3550 }; 3551 3552 tpdm@4ad0000 { 3553 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3554 reg = <0x0 0x04ad0000 0x0 0x1000>; 3555 3556 clocks = <&aoss_qmp>; 3557 clock-names = "apb_pclk"; 3558 3559 qcom,dsb-element-bits = <32>; 3560 qcom,dsb-msrs-num = <32>; 3561 3562 out-ports { 3563 port { 3564 dlct0_tpdm0_out: endpoint { 3565 remote-endpoint = <&dlct0_tpda_in26>; 3566 }; 3567 }; 3568 }; 3569 }; 3570 3571 tpda@4ad3000 { 3572 compatible = "qcom,coresight-tpda", "arm,primecell"; 3573 reg = <0x0 0x04ad3000 0x0 0x1000>; 3574 3575 clocks = <&aoss_qmp>; 3576 clock-names = "apb_pclk"; 3577 3578 in-ports { 3579 #address-cells = <1>; 3580 #size-cells = <0>; 3581 3582 port@13 { 3583 reg = <19>; 3584 3585 dlct0_tpda_in19: endpoint { 3586 remote-endpoint = <&prng_tpdm_out>; 3587 }; 3588 }; 3589 3590 port@19 { 3591 reg = <25>; 3592 3593 dlct0_tpda_in25: endpoint { 3594 remote-endpoint = <&pimem_tpdm_out>; 3595 }; 3596 }; 3597 3598 port@1a { 3599 reg = <26>; 3600 3601 dlct0_tpda_in26: endpoint { 3602 remote-endpoint = <&dlct0_tpdm0_out>; 3603 }; 3604 }; 3605 }; 3606 3607 out-ports { 3608 port { 3609 dlct0_tpda_out: endpoint { 3610 remote-endpoint = <&dlct0_funnel_in0>; 3611 }; 3612 }; 3613 }; 3614 }; 3615 3616 funnel@4ad4000 { 3617 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3618 reg = <0x0 0x04ad4000 0x0 0x1000>; 3619 3620 clocks = <&aoss_qmp>; 3621 clock-names = "apb_pclk"; 3622 3623 in-ports { 3624 #address-cells = <1>; 3625 #size-cells = <0>; 3626 3627 port@0 { 3628 reg = <0>; 3629 3630 dlct0_funnel_in0: endpoint { 3631 remote-endpoint = <&dlct0_tpda_out>; 3632 }; 3633 }; 3634 3635 port@4 { 3636 reg = <4>; 3637 3638 dlct0_funnel_in4: endpoint { 3639 remote-endpoint = <&ddr_funnel5_out>; 3640 }; 3641 }; 3642 }; 3643 3644 out-ports { 3645 port { 3646 dlct0_funnel_out: endpoint { 3647 remote-endpoint = <&funnel1_in5>; 3648 }; 3649 }; 3650 }; 3651 }; 3652 3653 funnel@4b04000 { 3654 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3655 reg = <0x0 0x04b04000 0x0 0x1000>; 3656 3657 clocks = <&aoss_qmp>; 3658 clock-names = "apb_pclk"; 3659 3660 in-ports { 3661 #address-cells = <1>; 3662 #size-cells = <0>; 3663 3664 port@6 { 3665 reg = <6>; 3666 3667 aoss_funnel_in6: endpoint { 3668 remote-endpoint = <&aoss_tpda_out>; 3669 }; 3670 }; 3671 3672 port@7 { 3673 reg = <7>; 3674 3675 aoss_funnel_in7: endpoint { 3676 remote-endpoint = <&qdss_funnel_out>; 3677 }; 3678 }; 3679 }; 3680 3681 out-ports { 3682 port { 3683 aoss_funnel_out: endpoint { 3684 remote-endpoint = <&etf0_in>; 3685 }; 3686 }; 3687 }; 3688 }; 3689 3690 tmc_etf: tmc@4b05000 { 3691 compatible = "arm,coresight-tmc", "arm,primecell"; 3692 reg = <0x0 0x04b05000 0x0 0x1000>; 3693 3694 clocks = <&aoss_qmp>; 3695 clock-names = "apb_pclk"; 3696 3697 in-ports { 3698 port { 3699 etf0_in: endpoint { 3700 remote-endpoint = <&aoss_funnel_out>; 3701 }; 3702 }; 3703 }; 3704 3705 out-ports { 3706 port { 3707 etf0_out: endpoint { 3708 remote-endpoint = <&swao_rep_in>; 3709 }; 3710 }; 3711 }; 3712 }; 3713 3714 replicator@4b06000 { 3715 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3716 reg = <0x0 0x04b06000 0x0 0x1000>; 3717 3718 clocks = <&aoss_qmp>; 3719 clock-names = "apb_pclk"; 3720 3721 in-ports { 3722 port { 3723 swao_rep_in: endpoint { 3724 remote-endpoint = <&etf0_out>; 3725 }; 3726 }; 3727 }; 3728 3729 out-ports { 3730 #address-cells = <1>; 3731 #size-cells = <0>; 3732 3733 port@1 { 3734 reg = <1>; 3735 3736 swao_rep_out1: endpoint { 3737 remote-endpoint = <&eud_in>; 3738 }; 3739 }; 3740 }; 3741 }; 3742 3743 tpda@4b08000 { 3744 compatible = "qcom,coresight-tpda", "arm,primecell"; 3745 reg = <0x0 0x04b08000 0x0 0x1000>; 3746 3747 clocks = <&aoss_qmp>; 3748 clock-names = "apb_pclk"; 3749 3750 in-ports { 3751 #address-cells = <1>; 3752 #size-cells = <0>; 3753 3754 port@0 { 3755 reg = <0>; 3756 3757 aoss_tpda_in0: endpoint { 3758 remote-endpoint = <&aoss_tpdm0_out>; 3759 }; 3760 }; 3761 3762 port@1 { 3763 reg = <1>; 3764 3765 aoss_tpda_in1: endpoint { 3766 remote-endpoint = <&aoss_tpdm1_out>; 3767 }; 3768 }; 3769 3770 port@2 { 3771 reg = <2>; 3772 3773 aoss_tpda_in2: endpoint { 3774 remote-endpoint = <&aoss_tpdm2_out>; 3775 }; 3776 }; 3777 3778 port@3 { 3779 reg = <3>; 3780 3781 aoss_tpda_in3: endpoint { 3782 remote-endpoint = <&aoss_tpdm3_out>; 3783 }; 3784 }; 3785 3786 port@4 { 3787 reg = <4>; 3788 3789 aoss_tpda_in4: endpoint { 3790 remote-endpoint = <&aoss_tpdm4_out>; 3791 }; 3792 }; 3793 }; 3794 3795 out-ports { 3796 port { 3797 aoss_tpda_out: endpoint { 3798 remote-endpoint = <&aoss_funnel_in6>; 3799 }; 3800 }; 3801 }; 3802 }; 3803 3804 tpdm@4b09000 { 3805 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3806 reg = <0x0 0x04b09000 0x0 0x1000>; 3807 3808 clocks = <&aoss_qmp>; 3809 clock-names = "apb_pclk"; 3810 3811 qcom,cmb-element-bits = <64>; 3812 qcom,cmb-msrs-num = <32>; 3813 3814 out-ports { 3815 port { 3816 aoss_tpdm0_out: endpoint { 3817 remote-endpoint = <&aoss_tpda_in0>; 3818 }; 3819 }; 3820 }; 3821 }; 3822 3823 tpdm@4b0a000 { 3824 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3825 reg = <0x0 0x04b0a000 0x0 0x1000>; 3826 3827 clocks = <&aoss_qmp>; 3828 clock-names = "apb_pclk"; 3829 3830 qcom,cmb-element-bits = <64>; 3831 qcom,cmb-msrs-num = <32>; 3832 3833 out-ports { 3834 port { 3835 aoss_tpdm1_out: endpoint { 3836 remote-endpoint = <&aoss_tpda_in1>; 3837 }; 3838 }; 3839 }; 3840 }; 3841 3842 tpdm@4b0b000 { 3843 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3844 reg = <0x0 0x04b0b000 0x0 0x1000>; 3845 3846 clocks = <&aoss_qmp>; 3847 clock-names = "apb_pclk"; 3848 3849 qcom,cmb-element-bits = <64>; 3850 qcom,cmb-msrs-num = <32>; 3851 3852 out-ports { 3853 port { 3854 aoss_tpdm2_out: endpoint { 3855 remote-endpoint = <&aoss_tpda_in2>; 3856 }; 3857 }; 3858 }; 3859 }; 3860 3861 tpdm@4b0c000 { 3862 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3863 reg = <0x0 0x04b0c000 0x0 0x1000>; 3864 3865 clocks = <&aoss_qmp>; 3866 clock-names = "apb_pclk"; 3867 3868 qcom,cmb-element-bits = <64>; 3869 qcom,cmb-msrs-num = <32>; 3870 3871 out-ports { 3872 port { 3873 aoss_tpdm3_out: endpoint { 3874 remote-endpoint = <&aoss_tpda_in3>; 3875 }; 3876 }; 3877 }; 3878 }; 3879 3880 tpdm@4b0d000 { 3881 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3882 reg = <0x0 0x04b0d000 0x0 0x1000>; 3883 3884 clocks = <&aoss_qmp>; 3885 clock-names = "apb_pclk"; 3886 3887 qcom,dsb-element-bits = <32>; 3888 qcom,dsb-msrs-num = <32>; 3889 3890 out-ports { 3891 port { 3892 aoss_tpdm4_out: endpoint { 3893 remote-endpoint = <&aoss_tpda_in4>; 3894 }; 3895 }; 3896 }; 3897 }; 3898 3899 cti@4b13000 { 3900 compatible = "arm,coresight-cti", "arm,primecell"; 3901 reg = <0x0 0x04b13000 0x0 0x1000>; 3902 3903 clocks = <&aoss_qmp>; 3904 clock-names = "apb_pclk"; 3905 }; 3906 3907 tpdm@4b80000 { 3908 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3909 reg = <0x0 0x04b80000 0x0 0x1000>; 3910 3911 clocks = <&aoss_qmp>; 3912 clock-names = "apb_pclk"; 3913 3914 qcom,dsb-element-bits = <32>; 3915 qcom,dsb-msrs-num = <32>; 3916 3917 out-ports { 3918 port { 3919 turing0_tpdm0_out: endpoint { 3920 remote-endpoint = <&turing0_tpda_in0>; 3921 }; 3922 }; 3923 }; 3924 }; 3925 3926 tpda@4b86000 { 3927 compatible = "qcom,coresight-tpda", "arm,primecell"; 3928 reg = <0x0 0x04b86000 0x0 0x1000>; 3929 3930 clocks = <&aoss_qmp>; 3931 clock-names = "apb_pclk"; 3932 3933 in-ports { 3934 port { 3935 turing0_tpda_in0: endpoint { 3936 remote-endpoint = <&turing0_tpdm0_out>; 3937 }; 3938 }; 3939 }; 3940 3941 out-ports { 3942 port { 3943 turing0_tpda_out: endpoint { 3944 remote-endpoint = <&turing0_funnel_in0>; 3945 }; 3946 }; 3947 }; 3948 }; 3949 3950 funnel@4b87000 { 3951 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3952 reg = <0x0 0x04b87000 0x0 0x1000>; 3953 3954 clocks = <&aoss_qmp>; 3955 clock-names = "apb_pclk"; 3956 3957 in-ports { 3958 port { 3959 turing0_funnel_in0: endpoint { 3960 remote-endpoint = <&turing0_tpda_out>; 3961 }; 3962 }; 3963 }; 3964 3965 out-ports { 3966 port { 3967 turing0_funnel_out: endpoint { 3968 remote-endpoint = <&gdsp_funnel_in4>; 3969 }; 3970 }; 3971 }; 3972 }; 3973 3974 cti@4b8b000 { 3975 compatible = "arm,coresight-cti", "arm,primecell"; 3976 reg = <0x0 0x04b8b000 0x0 0x1000>; 3977 3978 clocks = <&aoss_qmp>; 3979 clock-names = "apb_pclk"; 3980 }; 3981 3982 tpdm@4c40000 { 3983 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3984 reg = <0x0 0x04c40000 0x0 0x1000>; 3985 3986 clocks = <&aoss_qmp>; 3987 clock-names = "apb_pclk"; 3988 3989 qcom,dsb-element-bits = <32>; 3990 qcom,dsb-msrs-num = <32>; 3991 3992 out-ports { 3993 port { 3994 gdsp_tpdm0_out: endpoint { 3995 remote-endpoint = <&gdsp_tpda_in8>; 3996 }; 3997 }; 3998 }; 3999 }; 4000 4001 tpda@4c44000 { 4002 compatible = "qcom,coresight-tpda", "arm,primecell"; 4003 reg = <0x0 0x04c44000 0x0 0x1000>; 4004 4005 clocks = <&aoss_qmp>; 4006 clock-names = "apb_pclk"; 4007 4008 in-ports { 4009 #address-cells = <1>; 4010 #size-cells = <0>; 4011 4012 port@5 { 4013 reg = <5>; 4014 4015 gdsp_tpda_in5: endpoint { 4016 remote-endpoint = <&turing2_funnel_out0>; 4017 }; 4018 }; 4019 4020 port@8 { 4021 reg = <8>; 4022 4023 gdsp_tpda_in8: endpoint { 4024 remote-endpoint = <&gdsp_tpdm0_out>; 4025 }; 4026 }; 4027 }; 4028 4029 out-ports { 4030 port { 4031 gdsp_tpda_out: endpoint { 4032 remote-endpoint = <&gdsp_funnel_in0>; 4033 }; 4034 }; 4035 }; 4036 }; 4037 4038 funnel@4c45000 { 4039 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4040 reg = <0x0 0x04c45000 0x0 0x1000>; 4041 4042 clocks = <&aoss_qmp>; 4043 clock-names = "apb_pclk"; 4044 4045 in-ports { 4046 #address-cells = <1>; 4047 #size-cells = <0>; 4048 4049 port@0 { 4050 reg = <0>; 4051 4052 gdsp_funnel_in0: endpoint { 4053 remote-endpoint = <&gdsp_tpda_out>; 4054 }; 4055 }; 4056 4057 port@4 { 4058 reg = <4>; 4059 4060 gdsp_funnel_in4: endpoint { 4061 remote-endpoint = <&turing0_funnel_out>; 4062 }; 4063 }; 4064 }; 4065 4066 out-ports { 4067 port { 4068 gdsp_funnel_out: endpoint { 4069 remote-endpoint = <&dlst_ch_funnel_in6>; 4070 }; 4071 }; 4072 }; 4073 }; 4074 4075 tpdm@4c50000 { 4076 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4077 reg = <0x0 0x04c50000 0x0 0x1000>; 4078 4079 clocks = <&aoss_qmp>; 4080 clock-names = "apb_pclk"; 4081 4082 qcom,dsb-element-bits = <32>; 4083 qcom,dsb-msrs-num = <32>; 4084 4085 out-ports { 4086 port { 4087 dlst_tpdm0_out: endpoint { 4088 remote-endpoint = <&dlst_tpda_in8>; 4089 }; 4090 }; 4091 }; 4092 }; 4093 4094 tpda@4c54000 { 4095 compatible = "qcom,coresight-tpda", "arm,primecell"; 4096 reg = <0x0 0x04c54000 0x0 0x1000>; 4097 4098 clocks = <&aoss_qmp>; 4099 clock-names = "apb_pclk"; 4100 4101 in-ports { 4102 #address-cells = <1>; 4103 #size-cells = <0>; 4104 4105 port@8 { 4106 reg = <8>; 4107 4108 dlst_tpda_in8: endpoint { 4109 remote-endpoint = <&dlst_tpdm0_out>; 4110 }; 4111 }; 4112 }; 4113 4114 out-ports { 4115 port { 4116 dlst_tpda_out: endpoint { 4117 remote-endpoint = <&dlst_funnel_in0>; 4118 }; 4119 }; 4120 }; 4121 }; 4122 4123 funnel@4c55000 { 4124 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4125 reg = <0x0 0x04c55000 0x0 0x1000>; 4126 4127 clocks = <&aoss_qmp>; 4128 clock-names = "apb_pclk"; 4129 4130 in-ports { 4131 port { 4132 dlst_funnel_in0: endpoint { 4133 remote-endpoint = <&dlst_tpda_out>; 4134 }; 4135 }; 4136 }; 4137 4138 out-ports { 4139 port { 4140 dlst_funnel_out: endpoint { 4141 remote-endpoint = <&dlst_ch_funnel_in4>; 4142 }; 4143 }; 4144 }; 4145 }; 4146 4147 tpdm@4e00000 { 4148 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4149 reg = <0x0 0x04e00000 0x0 0x1000>; 4150 4151 clocks = <&aoss_qmp>; 4152 clock-names = "apb_pclk"; 4153 4154 qcom,dsb-element-bits = <32>; 4155 qcom,dsb-msrs-num = <32>; 4156 qcom,cmb-element-bits = <32>; 4157 qcom,cmb-msrs-num = <32>; 4158 4159 out-ports { 4160 port { 4161 ddr_tpdm3_out: endpoint { 4162 remote-endpoint = <&ddr_tpda_in4>; 4163 }; 4164 }; 4165 }; 4166 }; 4167 4168 tpda@4e03000 { 4169 compatible = "qcom,coresight-tpda", "arm,primecell"; 4170 reg = <0x0 0x04e03000 0x0 0x1000>; 4171 4172 clocks = <&aoss_qmp>; 4173 clock-names = "apb_pclk"; 4174 4175 in-ports { 4176 #address-cells = <1>; 4177 #size-cells = <0>; 4178 4179 port@0 { 4180 reg = <0>; 4181 4182 ddr_tpda_in0: endpoint { 4183 remote-endpoint = <&ddr_funnel0_out0>; 4184 }; 4185 }; 4186 4187 port@1 { 4188 reg = <1>; 4189 4190 ddr_tpda_in1: endpoint { 4191 remote-endpoint = <&ddr_funnel1_out0>; 4192 }; 4193 }; 4194 4195 port@4 { 4196 reg = <4>; 4197 4198 ddr_tpda_in4: endpoint { 4199 remote-endpoint = <&ddr_tpdm3_out>; 4200 }; 4201 }; 4202 }; 4203 4204 out-ports { 4205 port { 4206 ddr_tpda_out: endpoint { 4207 remote-endpoint = <&ddr_funnel5_in0>; 4208 }; 4209 }; 4210 }; 4211 }; 4212 4213 funnel@4e04000 { 4214 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4215 reg = <0x0 0x04e04000 0x0 0x1000>; 4216 4217 clocks = <&aoss_qmp>; 4218 clock-names = "apb_pclk"; 4219 4220 in-ports { 4221 port { 4222 ddr_funnel5_in0: endpoint { 4223 remote-endpoint = <&ddr_tpda_out>; 4224 }; 4225 }; 4226 }; 4227 4228 out-ports { 4229 port { 4230 ddr_funnel5_out: endpoint { 4231 remote-endpoint = <&dlct0_funnel_in4>; 4232 }; 4233 }; 4234 }; 4235 }; 4236 4237 tpdm@4e10000 { 4238 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4239 reg = <0x0 0x04e10000 0x0 0x1000>; 4240 4241 clocks = <&aoss_qmp>; 4242 clock-names = "apb_pclk"; 4243 4244 qcom,dsb-element-bits = <32>; 4245 qcom,dsb-msrs-num = <32>; 4246 4247 out-ports { 4248 port { 4249 ddr_tpdm0_out: endpoint { 4250 remote-endpoint = <&ddr_funnel0_in0>; 4251 }; 4252 }; 4253 }; 4254 }; 4255 4256 funnel@4e12000 { 4257 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4258 reg = <0x0 0x04e12000 0x0 0x1000>; 4259 4260 clocks = <&aoss_qmp>; 4261 clock-names = "apb_pclk"; 4262 4263 in-ports { 4264 port { 4265 ddr_funnel0_in0: endpoint { 4266 remote-endpoint = <&ddr_tpdm0_out>; 4267 }; 4268 }; 4269 }; 4270 4271 out-ports { 4272 port { 4273 ddr_funnel0_out0: endpoint { 4274 remote-endpoint = <&ddr_tpda_in0>; 4275 }; 4276 }; 4277 }; 4278 }; 4279 4280 tpdm@4e20000 { 4281 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4282 reg = <0x0 0x04e20000 0x0 0x1000>; 4283 4284 clocks = <&aoss_qmp>; 4285 clock-names = "apb_pclk"; 4286 4287 qcom,dsb-element-bits = <32>; 4288 qcom,dsb-msrs-num = <32>; 4289 4290 out-ports { 4291 port { 4292 ddr_tpdm1_out: endpoint { 4293 remote-endpoint = <&ddr_funnel1_in0>; 4294 }; 4295 }; 4296 }; 4297 }; 4298 4299 funnel@4e22000 { 4300 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4301 reg = <0x0 0x04e22000 0x0 0x1000>; 4302 4303 clocks = <&aoss_qmp>; 4304 clock-names = "apb_pclk"; 4305 4306 in-ports { 4307 port { 4308 ddr_funnel1_in0: endpoint { 4309 remote-endpoint = <&ddr_tpdm1_out>; 4310 }; 4311 }; 4312 }; 4313 4314 out-ports { 4315 port { 4316 ddr_funnel1_out0: endpoint { 4317 remote-endpoint = <&ddr_tpda_in1>; 4318 }; 4319 }; 4320 }; 4321 }; 4322 4323 etm@6040000 { 4324 compatible = "arm,primecell"; 4325 reg = <0x0 0x06040000 0x0 0x1000>; 4326 cpu = <&cpu0>; 4327 4328 clocks = <&aoss_qmp>; 4329 clock-names = "apb_pclk"; 4330 4331 arm,coresight-loses-context-with-cpu; 4332 qcom,skip-power-up; 4333 4334 out-ports { 4335 port { 4336 etm0_out: endpoint { 4337 remote-endpoint = <&apss_funnel0_in0>; 4338 }; 4339 }; 4340 }; 4341 }; 4342 4343 etm@6140000 { 4344 compatible = "arm,primecell"; 4345 reg = <0x0 0x06140000 0x0 0x1000>; 4346 cpu = <&cpu1>; 4347 4348 clocks = <&aoss_qmp>; 4349 clock-names = "apb_pclk"; 4350 4351 arm,coresight-loses-context-with-cpu; 4352 qcom,skip-power-up; 4353 4354 out-ports { 4355 port { 4356 etm1_out: endpoint { 4357 remote-endpoint = <&apss_funnel0_in1>; 4358 }; 4359 }; 4360 }; 4361 }; 4362 4363 etm@6240000 { 4364 compatible = "arm,primecell"; 4365 reg = <0x0 0x06240000 0x0 0x1000>; 4366 cpu = <&cpu2>; 4367 4368 clocks = <&aoss_qmp>; 4369 clock-names = "apb_pclk"; 4370 4371 arm,coresight-loses-context-with-cpu; 4372 qcom,skip-power-up; 4373 4374 out-ports { 4375 port { 4376 etm2_out: endpoint { 4377 remote-endpoint = <&apss_funnel0_in2>; 4378 }; 4379 }; 4380 }; 4381 }; 4382 4383 etm@6340000 { 4384 compatible = "arm,primecell"; 4385 reg = <0x0 0x06340000 0x0 0x1000>; 4386 cpu = <&cpu3>; 4387 4388 clocks = <&aoss_qmp>; 4389 clock-names = "apb_pclk"; 4390 4391 arm,coresight-loses-context-with-cpu; 4392 qcom,skip-power-up; 4393 4394 out-ports { 4395 port { 4396 etm3_out: endpoint { 4397 remote-endpoint = <&apss_funnel0_in3>; 4398 }; 4399 }; 4400 }; 4401 }; 4402 4403 etm@6440000 { 4404 compatible = "arm,primecell"; 4405 reg = <0x0 0x06440000 0x0 0x1000>; 4406 cpu = <&cpu4>; 4407 4408 clocks = <&aoss_qmp>; 4409 clock-names = "apb_pclk"; 4410 4411 arm,coresight-loses-context-with-cpu; 4412 qcom,skip-power-up; 4413 4414 out-ports { 4415 port { 4416 etm4_out: endpoint { 4417 remote-endpoint = <&apss_funnel0_in4>; 4418 }; 4419 }; 4420 }; 4421 }; 4422 4423 etm@6540000 { 4424 compatible = "arm,primecell"; 4425 reg = <0x0 0x06540000 0x0 0x1000>; 4426 cpu = <&cpu5>; 4427 4428 clocks = <&aoss_qmp>; 4429 clock-names = "apb_pclk"; 4430 4431 arm,coresight-loses-context-with-cpu; 4432 qcom,skip-power-up; 4433 4434 out-ports { 4435 port { 4436 etm5_out: endpoint { 4437 remote-endpoint = <&apss_funnel0_in5>; 4438 }; 4439 }; 4440 }; 4441 }; 4442 4443 etm@6640000 { 4444 compatible = "arm,primecell"; 4445 reg = <0x0 0x06640000 0x0 0x1000>; 4446 cpu = <&cpu6>; 4447 4448 clocks = <&aoss_qmp>; 4449 clock-names = "apb_pclk"; 4450 4451 arm,coresight-loses-context-with-cpu; 4452 qcom,skip-power-up; 4453 4454 out-ports { 4455 port { 4456 etm6_out: endpoint { 4457 remote-endpoint = <&apss_funnel0_in6>; 4458 }; 4459 }; 4460 }; 4461 }; 4462 4463 etm@6740000 { 4464 compatible = "arm,primecell"; 4465 reg = <0x0 0x06740000 0x0 0x1000>; 4466 cpu = <&cpu7>; 4467 4468 clocks = <&aoss_qmp>; 4469 clock-names = "apb_pclk"; 4470 4471 arm,coresight-loses-context-with-cpu; 4472 qcom,skip-power-up; 4473 4474 out-ports { 4475 port { 4476 etm7_out: endpoint { 4477 remote-endpoint = <&apss_funnel0_in7>; 4478 }; 4479 }; 4480 }; 4481 }; 4482 4483 funnel@6800000 { 4484 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4485 reg = <0x0 0x06800000 0x0 0x1000>; 4486 4487 clocks = <&aoss_qmp>; 4488 clock-names = "apb_pclk"; 4489 4490 in-ports { 4491 #address-cells = <1>; 4492 #size-cells = <0>; 4493 4494 port@0 { 4495 reg = <0>; 4496 4497 apss_funnel0_in0: endpoint { 4498 remote-endpoint = <&etm0_out>; 4499 }; 4500 }; 4501 4502 port@1 { 4503 reg = <1>; 4504 4505 apss_funnel0_in1: endpoint { 4506 remote-endpoint = <&etm1_out>; 4507 }; 4508 }; 4509 4510 port@2 { 4511 reg = <2>; 4512 4513 apss_funnel0_in2: endpoint { 4514 remote-endpoint = <&etm2_out>; 4515 }; 4516 }; 4517 4518 port@3 { 4519 reg = <3>; 4520 4521 apss_funnel0_in3: endpoint { 4522 remote-endpoint = <&etm3_out>; 4523 }; 4524 }; 4525 4526 port@4 { 4527 reg = <4>; 4528 4529 apss_funnel0_in4: endpoint { 4530 remote-endpoint = <&etm4_out>; 4531 }; 4532 }; 4533 4534 port@5 { 4535 reg = <5>; 4536 4537 apss_funnel0_in5: endpoint { 4538 remote-endpoint = <&etm5_out>; 4539 }; 4540 }; 4541 4542 port@6 { 4543 reg = <6>; 4544 4545 apss_funnel0_in6: endpoint { 4546 remote-endpoint = <&etm6_out>; 4547 }; 4548 }; 4549 4550 port@7 { 4551 reg = <7>; 4552 4553 apss_funnel0_in7: endpoint { 4554 remote-endpoint = <&etm7_out>; 4555 }; 4556 }; 4557 }; 4558 4559 out-ports { 4560 port { 4561 apss_funnel0_out: endpoint { 4562 remote-endpoint = <&apss_funnel1_in0>; 4563 }; 4564 }; 4565 }; 4566 }; 4567 4568 funnel@6810000 { 4569 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4570 reg = <0x0 0x06810000 0x0 0x1000>; 4571 4572 clocks = <&aoss_qmp>; 4573 clock-names = "apb_pclk"; 4574 4575 in-ports { 4576 #address-cells = <1>; 4577 #size-cells = <0>; 4578 4579 port@0 { 4580 reg = <0>; 4581 4582 apss_funnel1_in0: endpoint { 4583 remote-endpoint = <&apss_funnel0_out>; 4584 }; 4585 }; 4586 4587 port@3 { 4588 reg = <3>; 4589 4590 apss_funnel1_in3: endpoint { 4591 remote-endpoint = <&apss_tpda_out>; 4592 }; 4593 }; 4594 }; 4595 4596 out-ports { 4597 port { 4598 apss_funnel1_out: endpoint { 4599 remote-endpoint = <&funnel1_in4>; 4600 }; 4601 }; 4602 }; 4603 }; 4604 4605 cti@682b000 { 4606 compatible = "arm,coresight-cti", "arm,primecell"; 4607 reg = <0x0 0x0682b000 0x0 0x1000>; 4608 4609 clocks = <&aoss_qmp>; 4610 clock-names = "apb_pclk"; 4611 }; 4612 4613 tpdm@6860000 { 4614 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4615 reg = <0x0 0x06860000 0x0 0x1000>; 4616 4617 clocks = <&aoss_qmp>; 4618 clock-names = "apb_pclk"; 4619 4620 qcom,cmb-element-bits = <64>; 4621 qcom,cmb-msrs-num = <32>; 4622 4623 out-ports { 4624 port { 4625 apss_tpdm3_out: endpoint { 4626 remote-endpoint = <&apss_tpda_in3>; 4627 }; 4628 }; 4629 }; 4630 }; 4631 4632 tpdm@6861000 { 4633 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4634 reg = <0x0 0x06861000 0x0 0x1000>; 4635 4636 clocks = <&aoss_qmp>; 4637 clock-names = "apb_pclk"; 4638 4639 qcom,dsb-element-bits = <32>; 4640 qcom,dsb-msrs-num = <32>; 4641 4642 out-ports { 4643 port { 4644 apss_tpdm4_out: endpoint { 4645 remote-endpoint = <&apss_tpda_in4>; 4646 }; 4647 }; 4648 }; 4649 }; 4650 4651 tpda@6863000 { 4652 compatible = "qcom,coresight-tpda", "arm,primecell"; 4653 reg = <0x0 0x06863000 0x0 0x1000>; 4654 4655 clocks = <&aoss_qmp>; 4656 clock-names = "apb_pclk"; 4657 4658 in-ports { 4659 #address-cells = <1>; 4660 #size-cells = <0>; 4661 4662 port@0 { 4663 reg = <0>; 4664 4665 apss_tpda_in0: endpoint { 4666 remote-endpoint = <&apss_tpdm0_out>; 4667 }; 4668 }; 4669 4670 port@1 { 4671 reg = <1>; 4672 4673 apss_tpda_in1: endpoint { 4674 remote-endpoint = <&apss_tpdm1_out>; 4675 }; 4676 }; 4677 4678 port@2 { 4679 reg = <2>; 4680 4681 apss_tpda_in2: endpoint { 4682 remote-endpoint = <&apss_tpdm2_out>; 4683 }; 4684 }; 4685 4686 port@3 { 4687 reg = <3>; 4688 4689 apss_tpda_in3: endpoint { 4690 remote-endpoint = <&apss_tpdm3_out>; 4691 }; 4692 }; 4693 4694 port@4 { 4695 reg = <4>; 4696 4697 apss_tpda_in4: endpoint { 4698 remote-endpoint = <&apss_tpdm4_out>; 4699 }; 4700 }; 4701 }; 4702 4703 out-ports { 4704 port { 4705 apss_tpda_out: endpoint { 4706 remote-endpoint = <&apss_funnel1_in3>; 4707 }; 4708 }; 4709 }; 4710 }; 4711 4712 tpdm@68a0000 { 4713 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4714 reg = <0x0 0x068a0000 0x0 0x1000>; 4715 4716 clocks = <&aoss_qmp>; 4717 clock-names = "apb_pclk"; 4718 4719 qcom,cmb-element-bits = <32>; 4720 qcom,cmb-msrs-num = <32>; 4721 4722 out-ports { 4723 port { 4724 apss_tpdm1_out: endpoint { 4725 remote-endpoint = <&apss_tpda_in1>; 4726 }; 4727 }; 4728 }; 4729 }; 4730 4731 tpdm@68b0000 { 4732 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4733 reg = <0x0 0x068b0000 0x0 0x1000>; 4734 4735 clocks = <&aoss_qmp>; 4736 clock-names = "apb_pclk"; 4737 4738 qcom,cmb-element-bits = <32>; 4739 qcom,cmb-msrs-num = <32>; 4740 4741 out-ports { 4742 port { 4743 apss_tpdm0_out: endpoint { 4744 remote-endpoint = <&apss_tpda_in0>; 4745 }; 4746 }; 4747 }; 4748 }; 4749 4750 tpdm@68c0000 { 4751 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4752 reg = <0x0 0x068c0000 0x0 0x1000>; 4753 4754 clocks = <&aoss_qmp>; 4755 clock-names = "apb_pclk"; 4756 4757 qcom,dsb-element-bits = <32>; 4758 qcom,dsb-msrs-num = <32>; 4759 4760 out-ports { 4761 port { 4762 apss_tpdm2_out: endpoint { 4763 remote-endpoint = <&apss_tpda_in2>; 4764 }; 4765 }; 4766 }; 4767 }; 4768 4769 cti@68e0000 { 4770 compatible = "arm,coresight-cti", "arm,primecell"; 4771 reg = <0x0 0x068e0000 0x0 0x1000>; 4772 4773 clocks = <&aoss_qmp>; 4774 clock-names = "apb_pclk"; 4775 }; 4776 4777 cti@68f0000 { 4778 compatible = "arm,coresight-cti", "arm,primecell"; 4779 reg = <0x0 0x068f0000 0x0 0x1000>; 4780 4781 clocks = <&aoss_qmp>; 4782 clock-names = "apb_pclk"; 4783 }; 4784 4785 cti@6900000 { 4786 compatible = "arm,coresight-cti", "arm,primecell"; 4787 reg = <0x0 0x06900000 0x0 0x1000>; 4788 4789 clocks = <&aoss_qmp>; 4790 clock-names = "apb_pclk"; 4791 }; 4792 4793 sdhc_1: mmc@87c4000 { 4794 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4795 reg = <0x0 0x087c4000 0x0 0x1000>, 4796 <0x0 0x087c5000 0x0 0x1000>; 4797 reg-names = "hc", 4798 "cqhci"; 4799 4800 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4801 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4802 interrupt-names = "hc_irq", 4803 "pwr_irq"; 4804 4805 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4806 <&gcc GCC_SDCC1_APPS_CLK>, 4807 <&rpmhcc RPMH_CXO_CLK>; 4808 clock-names = "iface", 4809 "core", 4810 "xo"; 4811 4812 resets = <&gcc GCC_SDCC1_BCR>; 4813 4814 power-domains = <&rpmhpd RPMHPD_CX>; 4815 operating-points-v2 = <&sdhc1_opp_table>; 4816 iommus = <&apps_smmu 0x0 0x0>; 4817 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4818 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4819 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4820 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4821 interconnect-names = "sdhc-ddr", 4822 "cpu-sdhc"; 4823 4824 pinctrl-names = "default", "sleep"; 4825 pinctrl-0 = <&sdc1_state_on>; 4826 pinctrl-1 = <&sdc1_state_off>; 4827 4828 qcom,dll-config = <0x000f64ee>; 4829 qcom,ddr-config = <0x80040868>; 4830 bus-width = <8>; 4831 supports-cqe; 4832 dma-coherent; 4833 4834 mmc-ddr-1_8v; 4835 mmc-hs200-1_8v; 4836 mmc-hs400-1_8v; 4837 mmc-hs400-enhanced-strobe; 4838 4839 status = "disabled"; 4840 4841 sdhc1_opp_table: opp-table { 4842 compatible = "operating-points-v2"; 4843 4844 opp-50000000 { 4845 opp-hz = /bits/ 64 <50000000>; 4846 required-opps = <&rpmhpd_opp_low_svs>; 4847 }; 4848 4849 opp-100000000 { 4850 opp-hz = /bits/ 64 <100000000>; 4851 required-opps = <&rpmhpd_opp_svs>; 4852 }; 4853 4854 opp-200000000 { 4855 opp-hz = /bits/ 64 <200000000>; 4856 required-opps = <&rpmhpd_opp_svs_l1>; 4857 }; 4858 4859 opp-384000000 { 4860 opp-hz = /bits/ 64 <384000000>; 4861 required-opps = <&rpmhpd_opp_nom>; 4862 }; 4863 }; 4864 }; 4865 4866 usb_1_hsphy: phy@8904000 { 4867 compatible = "qcom,qcs8300-usb-hs-phy", 4868 "qcom,usb-snps-hs-7nm-phy"; 4869 reg = <0x0 0x08904000 0x0 0x400>; 4870 4871 clocks = <&rpmhcc RPMH_CXO_CLK>; 4872 clock-names = "ref"; 4873 4874 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4875 4876 #phy-cells = <0>; 4877 4878 status = "disabled"; 4879 }; 4880 4881 usb_2_hsphy: phy@8906000 { 4882 compatible = "qcom,qcs8300-usb-hs-phy", 4883 "qcom,usb-snps-hs-7nm-phy"; 4884 reg = <0x0 0x08906000 0x0 0x400>; 4885 4886 clocks = <&rpmhcc RPMH_CXO_CLK>; 4887 clock-names = "ref"; 4888 4889 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4890 4891 #phy-cells = <0>; 4892 4893 status = "disabled"; 4894 }; 4895 4896 usb_qmpphy: phy@8907000 { 4897 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4898 reg = <0x0 0x08907000 0x0 0x2000>; 4899 4900 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4901 <&gcc GCC_USB_CLKREF_EN>, 4902 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4903 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4904 clock-names = "aux", 4905 "ref", 4906 "com_aux", 4907 "pipe"; 4908 4909 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4910 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4911 reset-names = "phy", "phy_phy"; 4912 4913 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4914 4915 #clock-cells = <0>; 4916 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4917 4918 #phy-cells = <0>; 4919 4920 status = "disabled"; 4921 }; 4922 4923 serdes0: phy@8909000 { 4924 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4925 reg = <0x0 0x08909000 0x0 0x00000e10>; 4926 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4927 clock-names = "sgmi_ref"; 4928 #phy-cells = <0>; 4929 status = "disabled"; 4930 }; 4931 4932 refgen: regulator@891c000 { 4933 compatible = "qcom,qcs8300-refgen-regulator", 4934 "qcom,sm8250-refgen-regulator"; 4935 reg = <0x0 0x0891c000 0x0 0x84>; 4936 }; 4937 4938 gpu: gpu@3d00000 { 4939 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4940 reg = <0x0 0x03d00000 0x0 0x40000>, 4941 <0x0 0x03d9e000 0x0 0x1000>, 4942 <0x0 0x03d61000 0x0 0x800>; 4943 reg-names = "kgsl_3d0_reg_memory", 4944 "cx_mem", 4945 "cx_dbgc"; 4946 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4947 iommus = <&adreno_smmu 0 0xc00>, 4948 <&adreno_smmu 1 0xc00>; 4949 operating-points-v2 = <&gpu_opp_table>; 4950 qcom,gmu = <&gmu>; 4951 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4952 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4953 interconnect-names = "gfx-mem"; 4954 #cooling-cells = <2>; 4955 4956 nvmem-cells = <&gpu_speed_bin>; 4957 nvmem-cell-names = "speed_bin"; 4958 4959 status = "disabled"; 4960 4961 gpu_zap_shader: zap-shader { 4962 memory-region = <&gpu_microcode_mem>; 4963 }; 4964 4965 gpu_opp_table: opp-table { 4966 compatible = "operating-points-v2"; 4967 4968 opp-877000000 { 4969 opp-hz = /bits/ 64 <877000000>; 4970 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4971 opp-peak-kBps = <12484375>; 4972 opp-supported-hw = <0x1>; 4973 }; 4974 4975 opp-780000000 { 4976 opp-hz = /bits/ 64 <780000000>; 4977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4978 opp-peak-kBps = <10687500>; 4979 opp-supported-hw = <0x1>; 4980 }; 4981 4982 opp-599000000 { 4983 opp-hz = /bits/ 64 <599000000>; 4984 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4985 opp-peak-kBps = <8171875>; 4986 opp-supported-hw = <0x3>; 4987 }; 4988 4989 opp-479000000 { 4990 opp-hz = /bits/ 64 <479000000>; 4991 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4992 opp-peak-kBps = <5285156>; 4993 opp-supported-hw = <0x3>; 4994 }; 4995 }; 4996 }; 4997 4998 gmu: gmu@3d6a000 { 4999 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 5000 reg = <0x0 0x03d6a000 0x0 0x34000>, 5001 <0x0 0x03de0000 0x0 0x10000>, 5002 <0x0 0x0b290000 0x0 0x10000>; 5003 reg-names = "gmu", "rscc", "gmu_pdc"; 5004 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 5006 interrupt-names = "hfi", "gmu"; 5007 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 5008 <&gpucc GPU_CC_CXO_CLK>, 5009 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 5010 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5011 <&gpucc GPU_CC_AHB_CLK>, 5012 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 5013 clock-names = "gmu", 5014 "cxo", 5015 "axi", 5016 "memnoc", 5017 "ahb", 5018 "hub"; 5019 power-domains = <&gpucc GPU_CC_CX_GDSC>, 5020 <&gpucc GPU_CC_GX_GDSC>; 5021 power-domain-names = "cx", 5022 "gx"; 5023 iommus = <&adreno_smmu 5 0xc00>; 5024 operating-points-v2 = <&gmu_opp_table>; 5025 5026 gmu_opp_table: opp-table { 5027 compatible = "operating-points-v2"; 5028 5029 opp-500000000 { 5030 opp-hz = /bits/ 64 <500000000>; 5031 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5032 }; 5033 }; 5034 }; 5035 5036 gpucc: clock-controller@3d90000 { 5037 compatible = "qcom,qcs8300-gpucc"; 5038 reg = <0x0 0x03d90000 0x0 0xa000>; 5039 clocks = <&rpmhcc RPMH_CXO_CLK>, 5040 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 5041 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 5042 clock-names = "bi_tcxo", 5043 "gcc_gpu_gpll0_clk_src", 5044 "gcc_gpu_gpll0_div_clk_src"; 5045 #clock-cells = <1>; 5046 #reset-cells = <1>; 5047 #power-domain-cells = <1>; 5048 }; 5049 5050 adreno_smmu: iommu@3da0000 { 5051 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 5052 "qcom,smmu-500", "arm,mmu-500"; 5053 reg = <0x0 0x3da0000 0x0 0x20000>; 5054 #iommu-cells = <2>; 5055 #global-interrupts = <2>; 5056 5057 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 5065 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 5066 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 5067 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 5068 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 5069 5070 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 5071 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 5072 <&gpucc GPU_CC_AHB_CLK>, 5073 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 5074 <&gpucc GPU_CC_CX_GMU_CLK>, 5075 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 5076 <&gpucc GPU_CC_HUB_AON_CLK>; 5077 5078 clock-names = "gcc_gpu_memnoc_gfx_clk", 5079 "gcc_gpu_snoc_dvm_gfx_clk", 5080 "gpu_cc_ahb_clk", 5081 "gpu_cc_hlos1_vote_gpu_smmu_clk", 5082 "gpu_cc_cx_gmu_clk", 5083 "gpu_cc_hub_cx_int_clk", 5084 "gpu_cc_hub_aon_clk"; 5085 power-domains = <&gpucc GPU_CC_CX_GDSC>; 5086 dma-coherent; 5087 }; 5088 5089 pmu@9091000 { 5090 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 5091 reg = <0x0 0x9091000 0x0 0x1000>; 5092 5093 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 5094 5095 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 5096 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5097 5098 operating-points-v2 = <&llcc_bwmon_opp_table>; 5099 5100 llcc_bwmon_opp_table: opp-table { 5101 compatible = "operating-points-v2"; 5102 5103 opp-0 { 5104 opp-peak-kBps = <762000>; 5105 }; 5106 5107 opp-1 { 5108 opp-peak-kBps = <1720000>; 5109 }; 5110 5111 opp-2 { 5112 opp-peak-kBps = <2086000>; 5113 }; 5114 5115 opp-3 { 5116 opp-peak-kBps = <2601000>; 5117 }; 5118 5119 opp-4 { 5120 opp-peak-kBps = <2929000>; 5121 }; 5122 5123 opp-5 { 5124 opp-peak-kBps = <5931000>; 5125 }; 5126 5127 opp-6 { 5128 opp-peak-kBps = <6515000>; 5129 }; 5130 5131 opp-7 { 5132 opp-peak-kBps = <7984000>; 5133 }; 5134 5135 opp-8 { 5136 opp-peak-kBps = <10437000>; 5137 }; 5138 5139 opp-9 { 5140 opp-peak-kBps = <12195000>; 5141 }; 5142 }; 5143 }; 5144 5145 pmu@90b5400 { 5146 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5147 reg = <0x0 0x90b5400 0x0 0x600>; 5148 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5149 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5150 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5151 5152 operating-points-v2 = <&cpu_bwmon_opp_table>; 5153 5154 cpu_bwmon_opp_table: opp-table { 5155 compatible = "operating-points-v2"; 5156 5157 opp-0 { 5158 opp-peak-kBps = <9155000>; 5159 }; 5160 5161 opp-1 { 5162 opp-peak-kBps = <12298000>; 5163 }; 5164 5165 opp-2 { 5166 opp-peak-kBps = <14236000>; 5167 }; 5168 5169 opp-3 { 5170 opp-peak-kBps = <16265000>; 5171 }; 5172 }; 5173 }; 5174 5175 pmu@90b6400 { 5176 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 5177 reg = <0x0 0x90b6400 0x0 0x600>; 5178 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5179 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5180 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 5181 5182 operating-points-v2 = <&cpu_bwmon_opp_table>; 5183 }; 5184 5185 dc_noc: interconnect@90e0000 { 5186 compatible = "qcom,qcs8300-dc-noc"; 5187 reg = <0x0 0x090e0000 0x0 0x5080>; 5188 #interconnect-cells = <2>; 5189 qcom,bcm-voters = <&apps_bcm_voter>; 5190 }; 5191 5192 gem_noc: interconnect@9100000 { 5193 compatible = "qcom,qcs8300-gem-noc"; 5194 reg = <0x0 0x9100000 0x0 0xf7080>; 5195 #interconnect-cells = <2>; 5196 qcom,bcm-voters = <&apps_bcm_voter>; 5197 clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; 5198 }; 5199 5200 llcc: system-cache-controller@9200000 { 5201 compatible = "qcom,qcs8300-llcc"; 5202 reg = <0x0 0x09200000 0x0 0x80000>, 5203 <0x0 0x09300000 0x0 0x80000>, 5204 <0x0 0x09400000 0x0 0x80000>, 5205 <0x0 0x09500000 0x0 0x80000>, 5206 <0x0 0x09a00000 0x0 0x80000>; 5207 reg-names = "llcc0_base", 5208 "llcc1_base", 5209 "llcc2_base", 5210 "llcc3_base", 5211 "llcc_broadcast_base"; 5212 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 5213 }; 5214 5215 usb_1: usb@a600000 { 5216 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5217 reg = <0x0 0x0a600000 0x0 0xfc100>; 5218 5219 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5220 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5221 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5222 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5223 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 5224 clock-names = "cfg_noc", 5225 "core", 5226 "iface", 5227 "sleep", 5228 "mock_utmi"; 5229 5230 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5231 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5232 assigned-clock-rates = <19200000>, <200000000>; 5233 5234 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 5235 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 5236 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 5237 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5238 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5239 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 5240 interrupt-names = "dwc_usb3", 5241 "pwr_event", 5242 "hs_phy_irq", 5243 "dp_hs_phy_irq", 5244 "dm_hs_phy_irq", 5245 "ss_phy_irq"; 5246 5247 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 5248 required-opps = <&rpmhpd_opp_nom>; 5249 5250 resets = <&gcc GCC_USB30_PRIM_BCR>; 5251 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 5252 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5253 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5254 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 5255 interconnect-names = "usb-ddr", "apps-usb"; 5256 5257 iommus = <&apps_smmu 0x80 0x0>; 5258 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 5259 phy-names = "usb2-phy", "usb3-phy"; 5260 snps,dis_enblslpm_quirk; 5261 snps,dis-u1-entry-quirk; 5262 snps,dis-u2-entry-quirk; 5263 snps,dis_u2_susphy_quirk; 5264 snps,dis_u3_susphy_quirk; 5265 5266 usb-role-switch; 5267 wakeup-source; 5268 5269 status = "disabled"; 5270 5271 ports { 5272 #address-cells = <1>; 5273 #size-cells = <0>; 5274 5275 port@0 { 5276 reg = <0>; 5277 5278 usb_1_dwc3_hs: endpoint { 5279 }; 5280 }; 5281 5282 port@1 { 5283 reg = <1>; 5284 5285 usb_1_dwc3_ss: endpoint { 5286 }; 5287 }; 5288 }; 5289 }; 5290 5291 usb_2: usb@a400000 { 5292 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 5293 reg = <0x0 0x0a400000 0x0 0xfc100>; 5294 5295 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 5296 <&gcc GCC_USB20_MASTER_CLK>, 5297 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 5298 <&gcc GCC_USB20_SLEEP_CLK>, 5299 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 5300 clock-names = "cfg_noc", 5301 "core", 5302 "iface", 5303 "sleep", 5304 "mock_utmi"; 5305 5306 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 5307 <&gcc GCC_USB20_MASTER_CLK>; 5308 assigned-clock-rates = <19200000>, <120000000>; 5309 5310 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 5311 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 5312 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 5313 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 5314 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 5315 interrupt-names = "dwc_usb3", 5316 "pwr_event", 5317 "hs_phy_irq", 5318 "dp_hs_phy_irq", 5319 "dm_hs_phy_irq"; 5320 5321 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 5322 required-opps = <&rpmhpd_opp_nom>; 5323 5324 resets = <&gcc GCC_USB20_PRIM_BCR>; 5325 5326 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 5327 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5328 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5329 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 5330 interconnect-names = "usb-ddr", "apps-usb"; 5331 5332 iommus = <&apps_smmu 0x20 0x0>; 5333 5334 phys = <&usb_2_hsphy>; 5335 phy-names = "usb2-phy"; 5336 maximum-speed = "high-speed"; 5337 5338 snps,dis-u1-entry-quirk; 5339 snps,dis-u2-entry-quirk; 5340 snps,dis_u2_susphy_quirk; 5341 snps,dis_u3_susphy_quirk; 5342 snps,dis_enblslpm_quirk; 5343 5344 qcom,select-utmi-as-pipe-clk; 5345 wakeup-source; 5346 5347 usb-role-switch; 5348 5349 status = "disabled"; 5350 5351 port { 5352 usb_2_dwc3_hs: endpoint { 5353 }; 5354 }; 5355 }; 5356 5357 iris: video-codec@aa00000 { 5358 compatible = "qcom,qcs8300-iris"; 5359 5360 reg = <0x0 0x0aa00000 0x0 0xf0000>; 5361 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 5362 5363 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 5364 <&videocc VIDEO_CC_MVS0_GDSC>, 5365 <&rpmhpd RPMHPD_MX>, 5366 <&rpmhpd RPMHPD_MMCX>; 5367 power-domain-names = "venus", 5368 "vcodec0", 5369 "mxc", 5370 "mmcx"; 5371 5372 operating-points-v2 = <&iris_opp_table>; 5373 5374 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 5375 <&videocc VIDEO_CC_MVS0C_CLK>, 5376 <&videocc VIDEO_CC_MVS0_CLK>; 5377 clock-names = "iface", 5378 "core", 5379 "vcodec0_core"; 5380 5381 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5382 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5383 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 5384 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5385 interconnect-names = "cpu-cfg", 5386 "video-mem"; 5387 5388 memory-region = <&video_mem>; 5389 5390 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 5391 reset-names = "bus"; 5392 5393 iommus = <&apps_smmu 0x0880 0x0400>, 5394 <&apps_smmu 0x0887 0x0400>; 5395 dma-coherent; 5396 5397 status = "disabled"; 5398 5399 iris_opp_table: opp-table { 5400 compatible = "operating-points-v2"; 5401 5402 opp-366000000 { 5403 opp-hz = /bits/ 64 <366000000>; 5404 required-opps = <&rpmhpd_opp_svs_l1>, 5405 <&rpmhpd_opp_svs_l1>; 5406 }; 5407 5408 opp-444000000 { 5409 opp-hz = /bits/ 64 <444000000>; 5410 required-opps = <&rpmhpd_opp_svs_l1>, 5411 <&rpmhpd_opp_nom>; 5412 }; 5413 5414 opp-533000000 { 5415 opp-hz = /bits/ 64 <533000000>; 5416 required-opps = <&rpmhpd_opp_nom>, 5417 <&rpmhpd_opp_turbo>; 5418 }; 5419 5420 opp-560000000 { 5421 opp-hz = /bits/ 64 <560000000>; 5422 required-opps = <&rpmhpd_opp_nom>, 5423 <&rpmhpd_opp_turbo_l1>; 5424 }; 5425 }; 5426 }; 5427 5428 videocc: clock-controller@abf0000 { 5429 compatible = "qcom,qcs8300-videocc"; 5430 reg = <0x0 0x0abf0000 0x0 0x10000>; 5431 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 5432 <&rpmhcc RPMH_CXO_CLK>, 5433 <&rpmhcc RPMH_CXO_CLK_A>, 5434 <&sleep_clk>; 5435 power-domains = <&rpmhpd RPMHPD_MMCX>; 5436 #clock-cells = <1>; 5437 #reset-cells = <1>; 5438 #power-domain-cells = <1>; 5439 }; 5440 5441 cci0: cci@ac13000 { 5442 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5443 reg = <0x0 0x0ac13000 0x0 0x1000>; 5444 5445 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5446 5447 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5448 <&camcc CAM_CC_CCI_0_CLK>; 5449 clock-names = "ahb", 5450 "cci"; 5451 5452 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5453 5454 pinctrl-0 = <&cci0_0_default &cci0_1_default>; 5455 pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; 5456 pinctrl-names = "default", "sleep"; 5457 5458 #address-cells = <1>; 5459 #size-cells = <0>; 5460 5461 status = "disabled"; 5462 5463 cci0_i2c0: i2c-bus@0 { 5464 reg = <0>; 5465 clock-frequency = <1000000>; 5466 #address-cells = <1>; 5467 #size-cells = <0>; 5468 }; 5469 5470 cci0_i2c1: i2c-bus@1 { 5471 reg = <1>; 5472 clock-frequency = <1000000>; 5473 #address-cells = <1>; 5474 #size-cells = <0>; 5475 }; 5476 }; 5477 5478 cci1: cci@ac14000 { 5479 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5480 reg = <0x0 0x0ac14000 0x0 0x1000>; 5481 5482 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5483 5484 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5485 <&camcc CAM_CC_CCI_1_CLK>; 5486 clock-names = "ahb", 5487 "cci"; 5488 5489 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5490 5491 pinctrl-0 = <&cci1_0_default &cci1_1_default>; 5492 pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; 5493 pinctrl-names = "default", "sleep"; 5494 5495 #address-cells = <1>; 5496 #size-cells = <0>; 5497 5498 status = "disabled"; 5499 5500 cci1_i2c0: i2c-bus@0 { 5501 reg = <0>; 5502 clock-frequency = <1000000>; 5503 #address-cells = <1>; 5504 #size-cells = <0>; 5505 }; 5506 5507 cci1_i2c1: i2c-bus@1 { 5508 reg = <1>; 5509 clock-frequency = <1000000>; 5510 #address-cells = <1>; 5511 #size-cells = <0>; 5512 }; 5513 }; 5514 5515 cci2: cci@ac15000 { 5516 compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; 5517 reg = <0x0 0x0ac15000 0x0 0x1000>; 5518 5519 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 5520 5521 clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, 5522 <&camcc CAM_CC_CCI_2_CLK>; 5523 clock-names = "ahb", 5524 "cci"; 5525 5526 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5527 5528 pinctrl-0 = <&cci2_0_default &cci2_1_default>; 5529 pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; 5530 pinctrl-names = "default", "sleep"; 5531 5532 #address-cells = <1>; 5533 #size-cells = <0>; 5534 5535 status = "disabled"; 5536 5537 cci2_i2c0: i2c-bus@0 { 5538 reg = <0>; 5539 clock-frequency = <1000000>; 5540 #address-cells = <1>; 5541 #size-cells = <0>; 5542 }; 5543 5544 cci2_i2c1: i2c-bus@1 { 5545 reg = <1>; 5546 clock-frequency = <1000000>; 5547 #address-cells = <1>; 5548 #size-cells = <0>; 5549 }; 5550 }; 5551 5552 camss: isp@ac78000 { 5553 compatible = "qcom,qcs8300-camss"; 5554 5555 reg = <0x0 0xac78000 0x0 0x1000>, 5556 <0x0 0xac7a000 0x0 0xf00>, 5557 <0x0 0xac7c000 0x0 0xf00>, 5558 <0x0 0xac84000 0x0 0xf00>, 5559 <0x0 0xac88000 0x0 0xf00>, 5560 <0x0 0xac8c000 0x0 0xf00>, 5561 <0x0 0xac90000 0x0 0xf00>, 5562 <0x0 0xac94000 0x0 0xf00>, 5563 <0x0 0xac9c000 0x0 0x2000>, 5564 <0x0 0xac9e000 0x0 0x2000>, 5565 <0x0 0xaca0000 0x0 0x2000>, 5566 <0x0 0xacac000 0x0 0x400>, 5567 <0x0 0xacad000 0x0 0x400>, 5568 <0x0 0xacae000 0x0 0x400>, 5569 <0x0 0xac4d000 0x0 0xf000>, 5570 <0x0 0xac60000 0x0 0xf000>, 5571 <0x0 0xac85000 0x0 0xd00>, 5572 <0x0 0xac89000 0x0 0xd00>, 5573 <0x0 0xac8d000 0x0 0xd00>, 5574 <0x0 0xac91000 0x0 0xd00>, 5575 <0x0 0xac95000 0x0 0xd00>; 5576 reg-names = "csid_wrapper", 5577 "csid0", 5578 "csid1", 5579 "csid_lite0", 5580 "csid_lite1", 5581 "csid_lite2", 5582 "csid_lite3", 5583 "csid_lite4", 5584 "csiphy0", 5585 "csiphy1", 5586 "csiphy2", 5587 "tpg0", 5588 "tpg1", 5589 "tpg2", 5590 "vfe0", 5591 "vfe1", 5592 "vfe_lite0", 5593 "vfe_lite1", 5594 "vfe_lite2", 5595 "vfe_lite3", 5596 "vfe_lite4"; 5597 5598 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5599 <&camcc CAM_CC_CORE_AHB_CLK>, 5600 <&camcc CAM_CC_CPAS_AHB_CLK>, 5601 <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, 5602 <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, 5603 <&camcc CAM_CC_CPAS_IFE_0_CLK>, 5604 <&camcc CAM_CC_CPAS_IFE_1_CLK>, 5605 <&camcc CAM_CC_CSID_CLK>, 5606 <&camcc CAM_CC_CSIPHY0_CLK>, 5607 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5608 <&camcc CAM_CC_CSIPHY1_CLK>, 5609 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5610 <&camcc CAM_CC_CSIPHY2_CLK>, 5611 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5612 <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, 5613 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5614 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5615 <&camcc CAM_CC_ICP_AHB_CLK>, 5616 <&camcc CAM_CC_IFE_0_CLK>, 5617 <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, 5618 <&camcc CAM_CC_IFE_1_CLK>, 5619 <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, 5620 <&camcc CAM_CC_IFE_LITE_CLK>, 5621 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 5622 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 5623 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 5624 clock-names = "camnoc_axi", 5625 "core_ahb", 5626 "cpas_ahb", 5627 "cpas_fast_ahb_clk", 5628 "cpas_vfe_lite", 5629 "cpas_vfe0", 5630 "cpas_vfe1", 5631 "csid", 5632 "csiphy0", 5633 "csiphy0_timer", 5634 "csiphy1", 5635 "csiphy1_timer", 5636 "csiphy2", 5637 "csiphy2_timer", 5638 "csiphy_rx", 5639 "gcc_axi_hf", 5640 "gcc_axi_sf", 5641 "icp_ahb", 5642 "vfe0", 5643 "vfe0_fast_ahb", 5644 "vfe1", 5645 "vfe1_fast_ahb", 5646 "vfe_lite", 5647 "vfe_lite_ahb", 5648 "vfe_lite_cphy_rx", 5649 "vfe_lite_csid"; 5650 5651 interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, 5652 <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, 5653 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5654 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5655 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 5656 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 5657 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 5658 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5659 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5660 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5661 <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, 5662 <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, 5663 <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, 5664 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5665 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5666 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5667 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 5668 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 5669 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 5670 <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; 5671 interrupt-names = "csid0", 5672 "csid1", 5673 "csid_lite0", 5674 "csid_lite1", 5675 "csid_lite2", 5676 "csid_lite3", 5677 "csid_lite4", 5678 "csiphy0", 5679 "csiphy1", 5680 "csiphy2", 5681 "tpg0", 5682 "tpg1", 5683 "tpg2", 5684 "vfe0", 5685 "vfe1", 5686 "vfe_lite0", 5687 "vfe_lite1", 5688 "vfe_lite2", 5689 "vfe_lite3", 5690 "vfe_lite4"; 5691 5692 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5693 &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5694 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5696 interconnect-names = "ahb", 5697 "hf_0"; 5698 5699 iommus = <&apps_smmu 0x2400 0x20>; 5700 5701 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5702 power-domain-names = "top"; 5703 5704 status = "disabled"; 5705 5706 ports { 5707 #address-cells = <1>; 5708 #size-cells = <0>; 5709 5710 port@0 { 5711 reg = <0>; 5712 }; 5713 5714 port@1 { 5715 reg = <1>; 5716 }; 5717 5718 port@2 { 5719 reg = <2>; 5720 }; 5721 }; 5722 }; 5723 5724 camcc: clock-controller@ade0000 { 5725 compatible = "qcom,qcs8300-camcc"; 5726 reg = <0x0 0x0ade0000 0x0 0x20000>; 5727 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 5728 <&rpmhcc RPMH_CXO_CLK>, 5729 <&rpmhcc RPMH_CXO_CLK_A>, 5730 <&sleep_clk>; 5731 power-domains = <&rpmhpd RPMHPD_MMCX>; 5732 #clock-cells = <1>; 5733 #reset-cells = <1>; 5734 #power-domain-cells = <1>; 5735 }; 5736 5737 mdss: display-subsystem@ae00000 { 5738 compatible = "qcom,qcs8300-mdss"; 5739 reg = <0x0 0x0ae00000 0x0 0x1000>; 5740 reg-names = "mdss"; 5741 5742 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 5743 5744 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5745 <&gcc GCC_DISP_HF_AXI_CLK>, 5746 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>; 5747 5748 resets = <&dispcc MDSS_DISP_CC_MDSS_CORE_BCR>; 5749 5750 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5751 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5752 <&mmss_noc MASTER_MDP1 QCOM_ICC_TAG_ALWAYS 5753 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5754 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5755 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 5756 interconnect-names = "mdp0-mem", 5757 "mdp1-mem", 5758 "cpu-cfg"; 5759 5760 power-domains = <&dispcc MDSS_DISP_CC_MDSS_CORE_GDSC>; 5761 5762 iommus = <&apps_smmu 0x1000 0x402>; 5763 5764 interrupt-controller; 5765 #interrupt-cells = <1>; 5766 5767 #address-cells = <2>; 5768 #size-cells = <2>; 5769 ranges; 5770 5771 status = "disabled"; 5772 5773 mdss_mdp: display-controller@ae01000 { 5774 compatible = "qcom,qcs8300-dpu", "qcom,sa8775p-dpu"; 5775 reg = <0x0 0x0ae01000 0x0 0x8f000>, 5776 <0x0 0x0aeb0000 0x0 0x2008>; 5777 reg-names = "mdp", "vbif"; 5778 5779 interrupts-extended = <&mdss 0>; 5780 5781 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5782 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5783 <&dispcc MDSS_DISP_CC_MDSS_MDP_LUT_CLK>, 5784 <&dispcc MDSS_DISP_CC_MDSS_MDP_CLK>, 5785 <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5786 clock-names = "nrt_bus", 5787 "iface", 5788 "lut", 5789 "core", 5790 "vsync"; 5791 5792 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_VSYNC_CLK>; 5793 assigned-clock-rates = <19200000>; 5794 5795 operating-points-v2 = <&mdp_opp_table>; 5796 power-domains = <&rpmhpd RPMHPD_MMCX>; 5797 5798 ports { 5799 #address-cells = <1>; 5800 #size-cells = <0>; 5801 5802 port@0 { 5803 reg = <0>; 5804 5805 dpu_intf0_out: endpoint { 5806 5807 remote-endpoint = <&mdss_dp0_in>; 5808 }; 5809 }; 5810 5811 port@1 { 5812 reg = <1>; 5813 5814 dpu_intf1_out: endpoint { 5815 5816 remote-endpoint = <&mdss_dsi0_in>; 5817 }; 5818 }; 5819 }; 5820 5821 mdp_opp_table: opp-table { 5822 compatible = "operating-points-v2"; 5823 5824 opp-375000000 { 5825 opp-hz = /bits/ 64 <375000000>; 5826 required-opps = <&rpmhpd_opp_svs_l1>; 5827 }; 5828 5829 opp-500000000 { 5830 opp-hz = /bits/ 64 <500000000>; 5831 required-opps = <&rpmhpd_opp_nom>; 5832 }; 5833 5834 opp-575000000 { 5835 opp-hz = /bits/ 64 <575000000>; 5836 required-opps = <&rpmhpd_opp_turbo>; 5837 }; 5838 5839 opp-650000000 { 5840 opp-hz = /bits/ 64 <650000000>; 5841 required-opps = <&rpmhpd_opp_turbo_l1>; 5842 }; 5843 }; 5844 }; 5845 5846 mdss_dsi0: dsi@ae94000 { 5847 compatible = "qcom,qcs8300-dsi-ctrl", 5848 "qcom,sa8775p-dsi-ctrl", 5849 "qcom,mdss-dsi-ctrl"; 5850 reg = <0x0 0x0ae94000 0x0 0x400>; 5851 reg-names = "dsi_ctrl"; 5852 5853 interrupt-parent = <&mdss>; 5854 interrupts = <4>; 5855 5856 clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK>, 5857 <&dispcc MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK>, 5858 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK>, 5859 <&dispcc MDSS_DISP_CC_MDSS_ESC0_CLK>, 5860 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5861 <&gcc GCC_DISP_HF_AXI_CLK>; 5862 clock-names = "byte", 5863 "byte_intf", 5864 "pixel", 5865 "core", 5866 "iface", 5867 "bus"; 5868 5869 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC>, 5870 <&dispcc MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC>; 5871 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 5872 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 5873 5874 phys = <&mdss_dsi0_phy>; 5875 5876 operating-points-v2 = <&mdss_dsi_opp_table>; 5877 power-domains = <&rpmhpd RPMHPD_MMCX>; 5878 5879 refgen-supply = <&refgen>; 5880 5881 #address-cells = <1>; 5882 #size-cells = <0>; 5883 5884 status = "disabled"; 5885 5886 ports { 5887 #address-cells = <1>; 5888 #size-cells = <0>; 5889 5890 port@0 { 5891 reg = <0>; 5892 5893 mdss_dsi0_in: endpoint { 5894 5895 remote-endpoint = <&dpu_intf1_out>; 5896 }; 5897 }; 5898 5899 port@1 { 5900 reg = <1>; 5901 5902 mdss_dsi0_out: endpoint { 5903 }; 5904 }; 5905 }; 5906 5907 mdss_dsi_opp_table: opp-table { 5908 compatible = "operating-points-v2"; 5909 5910 opp-358000000 { 5911 opp-hz = /bits/ 64 <358000000>; 5912 required-opps = <&rpmhpd_opp_svs_l1>; 5913 }; 5914 }; 5915 }; 5916 5917 mdss_dsi0_phy: phy@ae94400 { 5918 compatible = "qcom,qcs8300-dsi-phy-5nm", 5919 "qcom,sa8775p-dsi-phy-5nm"; 5920 reg = <0x0 0x0ae94400 0x0 0x200>, 5921 <0x0 0x0ae94600 0x0 0x280>, 5922 <0x0 0x0ae94900 0x0 0x280>; 5923 reg-names = "dsi_phy", 5924 "dsi_phy_lane", 5925 "dsi_pll"; 5926 5927 #clock-cells = <1>; 5928 #phy-cells = <0>; 5929 5930 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5931 <&rpmhcc RPMH_CXO_CLK>; 5932 clock-names = "iface", 5933 "ref"; 5934 5935 status = "disabled"; 5936 }; 5937 5938 mdss_dp0_phy: phy@aec2a00 { 5939 compatible = "qcom,qcs8300-edp-phy", "qcom,sa8775p-edp-phy"; 5940 5941 reg = <0x0 0x0aec2a00 0x0 0x19c>, 5942 <0x0 0x0aec2200 0x0 0xec>, 5943 <0x0 0x0aec2600 0x0 0xec>, 5944 <0x0 0x0aec2000 0x0 0x1c8>; 5945 5946 clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5947 <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>; 5948 clock-names = "aux", 5949 "cfg_ahb"; 5950 5951 power-domains = <&rpmhpd RPMHPD_MX>; 5952 5953 #clock-cells = <1>; 5954 #phy-cells = <0>; 5955 5956 status = "disabled"; 5957 }; 5958 5959 mdss_dp0: displayport-controller@af54000 { 5960 compatible = "qcom,qcs8300-dp", "qcom,sa8775p-dp"; 5961 5962 reg = <0x0 0x0af54000 0x0 0x200>, 5963 <0x0 0x0af54200 0x0 0x200>, 5964 <0x0 0x0af55000 0x0 0xc00>, 5965 <0x0 0x0af56000 0x0 0x09c>, 5966 <0x0 0x0af57000 0x0 0x09c>, 5967 <0x0 0x0af58000 0x0 0x09c>, 5968 <0x0 0x0af59000 0x0 0x09c>, 5969 <0x0 0x0af5a000 0x0 0x23c>, 5970 <0x0 0x0af5b000 0x0 0x23c>; 5971 5972 interrupts-extended = <&mdss 12>; 5973 5974 clocks = <&dispcc MDSS_DISP_CC_MDSS_AHB_CLK>, 5975 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, 5976 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, 5977 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5978 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>, 5979 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK>, 5980 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK>, 5981 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK>; 5982 clock-names = "core_iface", 5983 "core_aux", 5984 "ctrl_link", 5985 "ctrl_link_iface", 5986 "stream_pixel", 5987 "stream_1_pixel", 5988 "stream_2_pixel", 5989 "stream_3_pixel"; 5990 assigned-clocks = <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5991 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, 5992 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>, 5993 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC>, 5994 <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC>; 5995 assigned-clock-parents = <&mdss_dp0_phy 0>, 5996 <&mdss_dp0_phy 1>, 5997 <&mdss_dp0_phy 1>, 5998 <&mdss_dp0_phy 1>, 5999 <&mdss_dp0_phy 1>; 6000 phys = <&mdss_dp0_phy>; 6001 phy-names = "dp"; 6002 6003 operating-points-v2 = <&dp_opp_table>; 6004 power-domains = <&rpmhpd RPMHPD_MMCX>; 6005 6006 #sound-dai-cells = <0>; 6007 6008 status = "disabled"; 6009 6010 ports { 6011 #address-cells = <1>; 6012 #size-cells = <0>; 6013 6014 port@0 { 6015 reg = <0>; 6016 6017 mdss_dp0_in: endpoint { 6018 remote-endpoint = <&dpu_intf0_out>; 6019 }; 6020 }; 6021 6022 port@1 { 6023 reg = <1>; 6024 6025 mdss_dp0_out: endpoint { }; 6026 }; 6027 }; 6028 6029 dp_opp_table: opp-table { 6030 compatible = "operating-points-v2"; 6031 6032 opp-162000000 { 6033 opp-hz = /bits/ 64 <162000000>; 6034 required-opps = <&rpmhpd_opp_low_svs>; 6035 }; 6036 6037 opp-270000000 { 6038 opp-hz = /bits/ 64 <270000000>; 6039 required-opps = <&rpmhpd_opp_svs>; 6040 }; 6041 6042 opp-540000000 { 6043 opp-hz = /bits/ 64 <540000000>; 6044 required-opps = <&rpmhpd_opp_svs_l1>; 6045 }; 6046 6047 opp-810000000 { 6048 opp-hz = /bits/ 64 <810000000>; 6049 required-opps = <&rpmhpd_opp_nom>; 6050 }; 6051 }; 6052 }; 6053 }; 6054 6055 dispcc: clock-controller@af00000 { 6056 compatible = "qcom,sa8775p-dispcc0"; 6057 reg = <0x0 0x0af00000 0x0 0x20000>; 6058 clocks = <&gcc GCC_DISP_AHB_CLK>, 6059 <&rpmhcc RPMH_CXO_CLK>, 6060 <&rpmhcc RPMH_CXO_CLK_A>, 6061 <&sleep_clk>, 6062 <&mdss_dp0_phy 0>, 6063 <&mdss_dp0_phy 1>, 6064 <0>, <0>, 6065 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 6066 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 6067 <0>, <0>; 6068 power-domains = <&rpmhpd RPMHPD_MMCX>; 6069 #clock-cells = <1>; 6070 #reset-cells = <1>; 6071 #power-domain-cells = <1>; 6072 }; 6073 6074 pdc: interrupt-controller@b220000 { 6075 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 6076 reg = <0x0 0xb220000 0x0 0x30000>, 6077 <0x0 0x17c000f0 0x0 0x64>; 6078 interrupt-parent = <&intc>; 6079 #interrupt-cells = <2>; 6080 interrupt-controller; 6081 qcom,pdc-ranges = <0 480 40>, 6082 <40 140 14>, 6083 <54 263 1>, 6084 <55 306 4>, 6085 <59 312 3>, 6086 <62 374 2>, 6087 <64 434 2>, 6088 <66 438 2>, 6089 <70 520 1>, 6090 <73 523 1>, 6091 <118 568 6>, 6092 <124 609 3>, 6093 <159 638 1>, 6094 <160 720 3>, 6095 <169 728 30>, 6096 <199 416 2>, 6097 <201 449 1>, 6098 <202 89 1>, 6099 <203 451 1>, 6100 <204 462 1>, 6101 <205 264 1>, 6102 <206 579 1>, 6103 <207 653 1>, 6104 <208 656 1>, 6105 <209 659 1>, 6106 <210 122 1>, 6107 <211 699 1>, 6108 <212 705 1>, 6109 <213 450 1>, 6110 <214 643 2>, 6111 <216 646 5>, 6112 <221 390 5>, 6113 <226 700 2>, 6114 <228 440 1>, 6115 <229 663 1>, 6116 <230 524 2>, 6117 <232 612 3>, 6118 <235 723 5>; 6119 }; 6120 6121 tsens2: thermal-sensor@c251000 { 6122 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6123 reg = <0x0 0x0c251000 0x0 0x1000>, 6124 <0x0 0x0c224000 0x0 0x1000>; 6125 interrupts = <GIC_SPI 572 IRQ_TYPE_LEVEL_HIGH>, 6126 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 6127 interrupt-names = "uplow", "critical"; 6128 #qcom,sensors = <10>; 6129 #thermal-sensor-cells = <1>; 6130 }; 6131 6132 tsens3: thermal-sensor@c252000 { 6133 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6134 reg = <0x0 0x0c252000 0x0 0x1000>, 6135 <0x0 0x0c225000 0x0 0x1000>; 6136 interrupts = <GIC_SPI 573 IRQ_TYPE_LEVEL_HIGH>, 6137 <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 6138 interrupt-names = "uplow", "critical"; 6139 #qcom,sensors = <10>; 6140 #thermal-sensor-cells = <1>; 6141 }; 6142 6143 tsens0: thermal-sensor@c263000 { 6144 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6145 reg = <0x0 0x0c263000 0x0 0x1000>, 6146 <0x0 0x0c222000 0x0 0x1000>; 6147 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 6148 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 6149 interrupt-names = "uplow", "critical"; 6150 #qcom,sensors = <10>; 6151 #thermal-sensor-cells = <1>; 6152 }; 6153 6154 tsens1: thermal-sensor@c265000 { 6155 compatible = "qcom,qcs8300-tsens", "qcom,tsens-v2"; 6156 reg = <0x0 0x0c265000 0x0 0x1000>, 6157 <0x0 0x0c223000 0x0 0x1000>; 6158 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 6159 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 6160 interrupt-names = "uplow", "critical"; 6161 #qcom,sensors = <10>; 6162 #thermal-sensor-cells = <1>; 6163 }; 6164 6165 aoss_qmp: power-management@c300000 { 6166 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 6167 reg = <0x0 0x0c300000 0x0 0x400>; 6168 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 6169 IPCC_MPROC_SIGNAL_GLINK_QMP 6170 IRQ_TYPE_EDGE_RISING>; 6171 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 6172 #clock-cells = <0>; 6173 }; 6174 6175 sram@c3f0000 { 6176 compatible = "qcom,rpmh-stats"; 6177 reg = <0x0 0x0c3f0000 0x0 0x400>; 6178 }; 6179 6180 spmi_bus: spmi@c440000 { 6181 compatible = "qcom,spmi-pmic-arb"; 6182 reg = <0x0 0x0c440000 0x0 0x1100>, 6183 <0x0 0x0c600000 0x0 0x2000000>, 6184 <0x0 0x0e600000 0x0 0x100000>, 6185 <0x0 0x0e700000 0x0 0xa0000>, 6186 <0x0 0x0c40a000 0x0 0x26000>; 6187 reg-names = "core", 6188 "chnls", 6189 "obsrvr", 6190 "intr", 6191 "cnfg"; 6192 qcom,channel = <0>; 6193 qcom,ee = <0>; 6194 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 6195 interrupt-names = "periph_irq"; 6196 interrupt-controller; 6197 #interrupt-cells = <4>; 6198 #address-cells = <2>; 6199 #size-cells = <0>; 6200 }; 6201 6202 tlmm: pinctrl@f100000 { 6203 compatible = "qcom,qcs8300-tlmm"; 6204 reg = <0x0 0x0f100000 0x0 0x300000>; 6205 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 6206 gpio-controller; 6207 #gpio-cells = <2>; 6208 gpio-ranges = <&tlmm 0 0 134>; 6209 interrupt-controller; 6210 #interrupt-cells = <2>; 6211 wakeup-parent = <&pdc>; 6212 6213 cam0_default: cam0-default-state { 6214 pins = "gpio67"; 6215 function = "cam_mclk"; 6216 drive-strength = <2>; 6217 bias-disable; 6218 }; 6219 6220 cam1_default: cam1-default-state { 6221 pins = "gpio68"; 6222 function = "cam_mclk"; 6223 drive-strength = <2>; 6224 bias-disable; 6225 }; 6226 6227 cam2_default: cam2-default-state { 6228 pins = "gpio69"; 6229 function = "cam_mclk"; 6230 drive-strength = <2>; 6231 bias-disable; 6232 }; 6233 6234 cci0_0_default: cci0-0-default-state { 6235 sda-pins { 6236 pins = "gpio57"; 6237 function = "cci_i2c_sda"; 6238 drive-strength = <2>; 6239 bias-pull-up = <2200>; 6240 }; 6241 6242 scl-pins { 6243 pins = "gpio58"; 6244 function = "cci_i2c_scl"; 6245 drive-strength = <2>; 6246 bias-pull-up = <2200>; 6247 }; 6248 }; 6249 6250 cci0_0_sleep: cci0-0-sleep-state { 6251 sda-pins { 6252 pins = "gpio57"; 6253 function = "cci_i2c_sda"; 6254 drive-strength = <2>; 6255 bias-pull-down; 6256 }; 6257 6258 scl-pins { 6259 pins = "gpio58"; 6260 function = "cci_i2c_scl"; 6261 drive-strength = <2>; 6262 bias-pull-down; 6263 }; 6264 }; 6265 6266 cci0_1_default: cci0-1-default-state { 6267 sda-pins { 6268 pins = "gpio29"; 6269 function = "cci_i2c_sda"; 6270 drive-strength = <2>; 6271 bias-pull-up = <2200>; 6272 }; 6273 6274 scl-pins { 6275 pins = "gpio30"; 6276 function = "cci_i2c_scl"; 6277 drive-strength = <2>; 6278 bias-pull-up = <2200>; 6279 }; 6280 }; 6281 6282 cci0_1_sleep: cci0-1-sleep-state { 6283 sda-pins { 6284 pins = "gpio29"; 6285 function = "cci_i2c_sda"; 6286 drive-strength = <2>; 6287 bias-pull-down; 6288 }; 6289 6290 scl-pins { 6291 pins = "gpio30"; 6292 function = "cci_i2c_scl"; 6293 drive-strength = <2>; 6294 bias-pull-down; 6295 }; 6296 }; 6297 6298 cci1_0_default: cci1-0-default-state { 6299 sda-pins { 6300 pins = "gpio59"; 6301 function = "cci_i2c_sda"; 6302 drive-strength = <2>; 6303 bias-pull-up = <2200>; 6304 }; 6305 6306 scl-pins { 6307 pins = "gpio60"; 6308 function = "cci_i2c_scl"; 6309 drive-strength = <2>; 6310 bias-pull-up = <2200>; 6311 }; 6312 }; 6313 6314 cci1_0_sleep: cci1-0-sleep-state { 6315 sda-pins { 6316 pins = "gpio59"; 6317 function = "cci_i2c_sda"; 6318 drive-strength = <2>; 6319 bias-pull-down; 6320 }; 6321 6322 scl-pins { 6323 pins = "gpio60"; 6324 function = "cci_i2c_scl"; 6325 drive-strength = <2>; 6326 bias-pull-down; 6327 }; 6328 }; 6329 6330 cci1_1_default: cci1-1-default-state { 6331 sda-pins { 6332 pins = "gpio31"; 6333 function = "cci_i2c_sda"; 6334 drive-strength = <2>; 6335 bias-pull-up = <2200>; 6336 }; 6337 6338 scl-pins { 6339 pins = "gpio32"; 6340 function = "cci_i2c_scl"; 6341 drive-strength = <2>; 6342 bias-pull-up = <2200>; 6343 }; 6344 }; 6345 6346 cci1_1_sleep: cci1-1-sleep-state { 6347 sda-pins { 6348 pins = "gpio31"; 6349 function = "cci_i2c_sda"; 6350 drive-strength = <2>; 6351 bias-pull-down; 6352 }; 6353 6354 scl-pins { 6355 pins = "gpio32"; 6356 function = "cci_i2c_scl"; 6357 drive-strength = <2>; 6358 bias-pull-down; 6359 }; 6360 }; 6361 6362 cci2_0_default: cci2-0-default-state { 6363 sda-pins { 6364 pins = "gpio61"; 6365 function = "cci_i2c_sda"; 6366 drive-strength = <2>; 6367 bias-pull-up = <2200>; 6368 }; 6369 6370 scl-pins { 6371 pins = "gpio62"; 6372 function = "cci_i2c_scl"; 6373 drive-strength = <2>; 6374 bias-pull-up = <2200>; 6375 }; 6376 }; 6377 6378 cci2_0_sleep: cci2-0-sleep-state { 6379 sda-pins { 6380 pins = "gpio61"; 6381 function = "cci_i2c_sda"; 6382 drive-strength = <2>; 6383 bias-pull-down; 6384 }; 6385 6386 scl-pins { 6387 pins = "gpio62"; 6388 function = "cci_i2c_scl"; 6389 drive-strength = <2>; 6390 bias-pull-down; 6391 }; 6392 }; 6393 6394 cci2_1_default: cci2-1-default-state { 6395 sda-pins { 6396 pins = "gpio54"; 6397 function = "cci_i2c_sda"; 6398 drive-strength = <2>; 6399 bias-pull-up = <2200>; 6400 }; 6401 6402 scl-pins { 6403 pins = "gpio55"; 6404 function = "cci_i2c_scl"; 6405 drive-strength = <2>; 6406 bias-pull-up = <2200>; 6407 }; 6408 }; 6409 6410 cci2_1_sleep: cci2-1-sleep-state { 6411 sda-pins { 6412 pins = "gpio54"; 6413 function = "cci_i2c_sda"; 6414 drive-strength = <2>; 6415 bias-pull-down; 6416 }; 6417 6418 scl-pins { 6419 pins = "gpio55"; 6420 function = "cci_i2c_scl"; 6421 drive-strength = <2>; 6422 bias-pull-down; 6423 }; 6424 }; 6425 6426 dp_hot_plug_det: dp-hot-plug-det-state { 6427 pins = "gpio94"; 6428 function = "edp0_hot"; 6429 bias-disable; 6430 }; 6431 6432 hs0_mi2s_active: hs0-mi2s-active-state { 6433 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 6434 function = "hs0_mi2s"; 6435 drive-strength = <8>; 6436 bias-disable; 6437 }; 6438 6439 mi2s1_active: mi2s1-active-state { 6440 data0-pins { 6441 pins = "gpio100"; 6442 function = "mi2s1_data0"; 6443 drive-strength = <8>; 6444 bias-disable; 6445 }; 6446 6447 data1-pins { 6448 pins = "gpio101"; 6449 function = "mi2s1_data1"; 6450 drive-strength = <8>; 6451 bias-disable; 6452 }; 6453 6454 sclk-pins { 6455 pins = "gpio98"; 6456 function = "mi2s1_sck"; 6457 drive-strength = <8>; 6458 bias-disable; 6459 }; 6460 6461 ws-pins { 6462 pins = "gpio99"; 6463 function = "mi2s1_ws"; 6464 drive-strength = <8>; 6465 bias-disable; 6466 }; 6467 }; 6468 6469 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 6470 pins = "gpio17", "gpio18"; 6471 function = "qup0_se0"; 6472 }; 6473 6474 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 6475 pins = "gpio19", "gpio20"; 6476 function = "qup0_se1"; 6477 }; 6478 6479 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 6480 pins = "gpio33", "gpio34"; 6481 function = "qup0_se2"; 6482 }; 6483 6484 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6485 pins = "gpio25", "gpio26"; 6486 function = "qup0_se3"; 6487 }; 6488 6489 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6490 pins = "gpio29", "gpio30"; 6491 function = "qup0_se4"; 6492 }; 6493 6494 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6495 pins = "gpio21", "gpio22"; 6496 function = "qup0_se5"; 6497 }; 6498 6499 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6500 pins = "gpio80", "gpio81"; 6501 function = "qup0_se6"; 6502 }; 6503 6504 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6505 pins = "gpio37", "gpio38"; 6506 function = "qup1_se0"; 6507 }; 6508 6509 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6510 pins = "gpio39", "gpio40"; 6511 function = "qup1_se1"; 6512 }; 6513 6514 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6515 pins = "gpio84", "gpio85"; 6516 function = "qup1_se2"; 6517 }; 6518 6519 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6520 pins = "gpio41", "gpio42"; 6521 function = "qup1_se3"; 6522 }; 6523 6524 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6525 pins = "gpio45", "gpio46"; 6526 function = "qup1_se4"; 6527 }; 6528 6529 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6530 pins = "gpio49", "gpio50"; 6531 function = "qup1_se5"; 6532 }; 6533 6534 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6535 pins = "gpio89", "gpio90"; 6536 function = "qup1_se6"; 6537 }; 6538 6539 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6540 pins = "gpio91", "gpio92"; 6541 function = "qup1_se7"; 6542 }; 6543 6544 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 6545 pins = "gpio10", "gpio11"; 6546 function = "qup2_se0"; 6547 }; 6548 6549 qup_spi0_data_clk: qup-spi0-data-clk-state { 6550 pins = "gpio17", "gpio18", "gpio19"; 6551 function = "qup0_se0"; 6552 }; 6553 6554 qup_spi0_cs: qup-spi0-cs-state { 6555 pins = "gpio20"; 6556 function = "qup0_se0"; 6557 }; 6558 6559 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6560 pins = "gpio20"; 6561 function = "gpio"; 6562 }; 6563 6564 qup_spi1_data_clk: qup-spi1-data-clk-state { 6565 pins = "gpio19", "gpio20", "gpio17"; 6566 function = "qup0_se1"; 6567 }; 6568 6569 qup_spi1_cs: qup-spi1-cs-state { 6570 pins = "gpio18"; 6571 function = "qup0_se1"; 6572 }; 6573 6574 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6575 pins = "gpio18"; 6576 function = "gpio"; 6577 }; 6578 6579 qup_spi2_data_clk: qup-spi2-data-clk-state { 6580 pins = "gpio33", "gpio34", "gpio35"; 6581 function = "qup0_se2"; 6582 }; 6583 6584 qup_spi2_cs: qup-spi2-cs-state { 6585 pins = "gpio36"; 6586 function = "qup0_se2"; 6587 }; 6588 6589 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6590 pins = "gpio36"; 6591 function = "gpio"; 6592 }; 6593 6594 qup_spi3_data_clk: qup-spi3-data-clk-state { 6595 pins = "gpio25", "gpio26", "gpio27"; 6596 function = "qup0_se3"; 6597 }; 6598 6599 qup_spi3_cs: qup-spi3-cs-state { 6600 pins = "gpio28"; 6601 function = "qup0_se3"; 6602 }; 6603 6604 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6605 pins = "gpio28"; 6606 function = "gpio"; 6607 }; 6608 6609 qup_spi4_data_clk: qup-spi4-data-clk-state { 6610 pins = "gpio29", "gpio30", "gpio31"; 6611 function = "qup0_se4"; 6612 }; 6613 6614 qup_spi4_cs: qup-spi4-cs-state { 6615 pins = "gpio32"; 6616 function = "qup0_se4"; 6617 }; 6618 6619 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6620 pins = "gpio32"; 6621 function = "gpio"; 6622 }; 6623 6624 qup_spi5_data_clk: qup-spi5-data-clk-state { 6625 pins = "gpio21", "gpio22", "gpio23"; 6626 function = "qup0_se5"; 6627 }; 6628 6629 qup_spi5_cs: qup-spi5-cs-state { 6630 pins = "gpio24"; 6631 function = "qup0_se5"; 6632 }; 6633 6634 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6635 pins = "gpio24"; 6636 function = "gpio"; 6637 }; 6638 6639 qup_spi6_data_clk: qup-spi6-data-clk-state { 6640 pins = "gpio80", "gpio81", "gpio82"; 6641 function = "qup0_se6"; 6642 }; 6643 6644 qup_spi6_cs: qup-spi6-cs-state { 6645 pins = "gpio83"; 6646 function = "qup0_se6"; 6647 }; 6648 6649 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6650 pins = "gpio83"; 6651 function = "gpio"; 6652 }; 6653 6654 qup_spi8_data_clk: qup-spi8-data-clk-state { 6655 pins = "gpio37", "gpio38", "gpio39"; 6656 function = "qup1_se0"; 6657 }; 6658 6659 qup_spi8_cs: qup-spi8-cs-state { 6660 pins = "gpio40"; 6661 function = "qup1_se0"; 6662 }; 6663 6664 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6665 pins = "gpio40"; 6666 function = "gpio"; 6667 }; 6668 6669 qup_spi9_data_clk: qup-spi9-data-clk-state { 6670 pins = "gpio39", "gpio40", "gpio37"; 6671 function = "qup1_se1"; 6672 }; 6673 6674 qup_spi9_cs: qup-spi9-cs-state { 6675 pins = "gpio38"; 6676 function = "qup1_se1"; 6677 }; 6678 6679 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6680 pins = "gpio38"; 6681 function = "gpio"; 6682 }; 6683 6684 qup_spi10_data_clk: qup-spi10-data-clk-state { 6685 pins = "gpio84", "gpio85", "gpio86"; 6686 function = "qup1_se2"; 6687 }; 6688 6689 qup_spi10_cs: qup-spi10-cs-state { 6690 pins = "gpio87"; 6691 function = "qup1_se2"; 6692 }; 6693 6694 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6695 pins = "gpio87"; 6696 function = "gpio"; 6697 }; 6698 6699 qup_spi12_data_clk: qup-spi12-data-clk-state { 6700 pins = "gpio45", "gpio46", "gpio47"; 6701 function = "qup1_se4"; 6702 }; 6703 6704 qup_spi12_cs: qup-spi12-cs-state { 6705 pins = "gpio48"; 6706 function = "qup1_se4"; 6707 }; 6708 6709 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6710 pins = "gpio48"; 6711 function = "gpio"; 6712 }; 6713 6714 qup_spi13_data_clk: qup-spi13-data-clk-state { 6715 pins = "gpio49", "gpio50", "gpio51"; 6716 function = "qup1_se5"; 6717 }; 6718 6719 qup_spi13_cs: qup-spi13-cs-state { 6720 pins = "gpio52"; 6721 function = "qup1_se5"; 6722 }; 6723 6724 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6725 pins = "gpio52"; 6726 function = "gpio"; 6727 }; 6728 6729 qup_spi14_data_clk: qup-spi14-data-clk-state { 6730 pins = "gpio89", "gpio90", "gpio91"; 6731 function = "qup1_se6"; 6732 }; 6733 6734 qup_spi14_cs: qup-spi14-cs-state { 6735 pins = "gpio92"; 6736 function = "qup1_se6"; 6737 }; 6738 6739 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6740 pins = "gpio92"; 6741 function = "gpio"; 6742 }; 6743 6744 qup_spi15_data_clk: qup-spi15-data-clk-state { 6745 pins = "gpio91", "gpio92", "gpio89"; 6746 function = "qup1_se7"; 6747 }; 6748 6749 qup_spi15_cs: qup-spi15-cs-state { 6750 pins = "gpio90"; 6751 function = "qup1_se7"; 6752 }; 6753 6754 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6755 pins = "gpio90"; 6756 function = "gpio"; 6757 }; 6758 6759 qup_spi16_data_clk: qup-spi16-data-clk-state { 6760 pins = "gpio10", "gpio11", "gpio12"; 6761 function = "qup2_se0"; 6762 }; 6763 6764 qup_spi16_cs: qup-spi16-cs-state { 6765 pins = "gpio13"; 6766 function = "qup2_se0"; 6767 }; 6768 6769 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 6770 pins = "gpio13"; 6771 function = "gpio"; 6772 }; 6773 6774 qup_uart0_cts: qup-uart0-cts-state { 6775 pins = "gpio17"; 6776 function = "qup0_se0"; 6777 }; 6778 6779 qup_uart0_rts: qup-uart0-rts-state { 6780 pins = "gpio18"; 6781 function = "qup0_se0"; 6782 }; 6783 6784 qup_uart0_tx: qup-uart0-tx-state { 6785 pins = "gpio19"; 6786 function = "qup0_se0"; 6787 }; 6788 6789 qup_uart0_rx: qup-uart0-rx-state { 6790 pins = "gpio20"; 6791 function = "qup0_se0"; 6792 }; 6793 6794 qup_uart1_cts: qup-uart1-cts-state { 6795 pins = "gpio19"; 6796 function = "qup0_se1"; 6797 }; 6798 6799 qup_uart1_rts: qup-uart1-rts-state { 6800 pins = "gpio20"; 6801 function = "qup0_se1"; 6802 }; 6803 6804 qup_uart1_tx: qup-uart1-tx-state { 6805 pins = "gpio17"; 6806 function = "qup0_se1"; 6807 }; 6808 6809 qup_uart1_rx: qup-uart1-rx-state { 6810 pins = "gpio18"; 6811 function = "qup0_se1"; 6812 }; 6813 6814 qup_uart2_cts: qup-uart2-cts-state { 6815 pins = "gpio33"; 6816 function = "qup0_se2"; 6817 }; 6818 6819 qup_uart2_rts: qup-uart2-rts-state { 6820 pins = "gpio34"; 6821 function = "qup0_se2"; 6822 }; 6823 6824 qup_uart2_tx: qup-uart2-tx-state { 6825 pins = "gpio35"; 6826 function = "qup0_se2"; 6827 }; 6828 6829 qup_uart2_rx: qup-uart2-rx-state { 6830 pins = "gpio36"; 6831 function = "qup0_se2"; 6832 }; 6833 6834 qup_uart3_cts: qup-uart3-cts-state { 6835 pins = "gpio25"; 6836 function = "qup0_se3"; 6837 }; 6838 6839 qup_uart3_rts: qup-uart3-rts-state { 6840 pins = "gpio26"; 6841 function = "qup0_se3"; 6842 }; 6843 6844 qup_uart3_tx: qup-uart3-tx-state { 6845 pins = "gpio27"; 6846 function = "qup0_se3"; 6847 }; 6848 6849 qup_uart3_rx: qup-uart3-rx-state { 6850 pins = "gpio28"; 6851 function = "qup0_se3"; 6852 }; 6853 6854 qup_uart4_cts: qup-uart4-cts-state { 6855 pins = "gpio29"; 6856 function = "qup0_se4"; 6857 }; 6858 6859 qup_uart4_rts: qup-uart4-rts-state { 6860 pins = "gpio30"; 6861 function = "qup0_se4"; 6862 }; 6863 6864 qup_uart4_tx: qup-uart4-tx-state { 6865 pins = "gpio31"; 6866 function = "qup0_se4"; 6867 }; 6868 6869 qup_uart4_rx: qup-uart4-rx-state { 6870 pins = "gpio32"; 6871 function = "qup0_se4"; 6872 }; 6873 6874 qup_uart5_cts: qup-uart5-cts-state { 6875 pins = "gpio21"; 6876 function = "qup0_se5"; 6877 }; 6878 6879 qup_uart5_rts: qup-uart5-rts-state { 6880 pins = "gpio22"; 6881 function = "qup0_se5"; 6882 }; 6883 6884 qup_uart5_tx: qup-uart5-tx-state { 6885 pins = "gpio23"; 6886 function = "qup0_se5"; 6887 }; 6888 6889 qup_uart5_rx: qup-uart5-rx-state { 6890 pins = "gpio23"; 6891 function = "qup0_se5"; 6892 }; 6893 6894 qup_uart6_cts: qup-uart6-cts-state { 6895 pins = "gpio80"; 6896 function = "qup0_se6"; 6897 }; 6898 6899 qup_uart6_rts: qup-uart6-rts-state { 6900 pins = "gpio81"; 6901 function = "qup0_se6"; 6902 }; 6903 6904 qup_uart6_tx: qup-uart6-tx-state { 6905 pins = "gpio82"; 6906 function = "qup0_se6"; 6907 }; 6908 6909 qup_uart6_rx: qup-uart6-rx-state { 6910 pins = "gpio83"; 6911 function = "qup0_se6"; 6912 }; 6913 6914 qup_uart7_tx: qup-uart7-tx-state { 6915 pins = "gpio43"; 6916 function = "qup0_se7"; 6917 }; 6918 6919 qup_uart7_rx: qup-uart7-rx-state { 6920 pins = "gpio44"; 6921 function = "qup0_se7"; 6922 }; 6923 6924 qup_uart8_cts: qup-uart8-cts-state { 6925 pins = "gpio37"; 6926 function = "qup1_se0"; 6927 }; 6928 6929 qup_uart8_rts: qup-uart8-rts-state { 6930 pins = "gpio38"; 6931 function = "qup1_se0"; 6932 }; 6933 6934 qup_uart8_tx: qup-uart8-tx-state { 6935 pins = "gpio39"; 6936 function = "qup1_se0"; 6937 }; 6938 6939 qup_uart8_rx: qup-uart8-rx-state { 6940 pins = "gpio40"; 6941 function = "qup1_se0"; 6942 }; 6943 6944 qup_uart9_cts: qup-uart9-cts-state { 6945 pins = "gpio39"; 6946 function = "qup1_se1"; 6947 }; 6948 6949 qup_uart9_rts: qup-uart9-rts-state { 6950 pins = "gpio40"; 6951 function = "qup1_se1"; 6952 }; 6953 6954 qup_uart9_tx: qup-uart9-tx-state { 6955 pins = "gpio37"; 6956 function = "qup1_se1"; 6957 }; 6958 6959 qup_uart9_rx: qup-uart9-rx-state { 6960 pins = "gpio38"; 6961 function = "qup1_se1"; 6962 }; 6963 6964 qup_uart10_cts: qup-uart10-cts-state { 6965 pins = "gpio84"; 6966 function = "qup1_se2"; 6967 }; 6968 6969 qup_uart10_rts: qup-uart10-rts-state { 6970 pins = "gpio85"; 6971 function = "qup1_se2"; 6972 }; 6973 6974 qup_uart10_tx: qup-uart10-tx-state { 6975 pins = "gpio86"; 6976 function = "qup1_se2"; 6977 }; 6978 6979 qup_uart10_rx: qup-uart10-rx-state { 6980 pins = "gpio87"; 6981 function = "qup1_se2"; 6982 }; 6983 6984 qup_uart11_tx: qup-uart11-tx-state { 6985 pins = "gpio41"; 6986 function = "qup1_se3"; 6987 }; 6988 6989 qup_uart11_rx: qup-uart11-rx-state { 6990 pins = "gpio42"; 6991 function = "qup1_se3"; 6992 }; 6993 6994 qup_uart12_cts: qup-uart12-cts-state { 6995 pins = "gpio45"; 6996 function = "qup1_se4"; 6997 }; 6998 6999 qup_uart12_rts: qup-uart12-rts-state { 7000 pins = "gpio46"; 7001 function = "qup1_se4"; 7002 }; 7003 7004 qup_uart12_tx: qup-uart12-tx-state { 7005 pins = "gpio47"; 7006 function = "qup1_se4"; 7007 }; 7008 7009 qup_uart12_rx: qup-uart12-rx-state { 7010 pins = "gpio48"; 7011 function = "qup1_se4"; 7012 }; 7013 7014 qup_uart13_cts: qup-uart13-cts-state { 7015 pins = "gpio49"; 7016 function = "qup1_se5"; 7017 }; 7018 7019 qup_uart13_rts: qup-uart13-rts-state { 7020 pins = "gpio50"; 7021 function = "qup1_se5"; 7022 }; 7023 7024 qup_uart13_tx: qup-uart13-tx-state { 7025 pins = "gpio51"; 7026 function = "qup1_se5"; 7027 }; 7028 7029 qup_uart13_rx: qup-uart13-rx-state { 7030 pins = "gpio52"; 7031 function = "qup1_se5"; 7032 }; 7033 7034 qup_uart14_cts: qup-uart14-cts-state { 7035 pins = "gpio89"; 7036 function = "qup1_se6"; 7037 }; 7038 7039 qup_uart14_rts: qup-uart14-rts-state { 7040 pins = "gpio90"; 7041 function = "qup1_se6"; 7042 }; 7043 7044 qup_uart14_tx: qup-uart14-tx-state { 7045 pins = "gpio91"; 7046 function = "qup1_se6"; 7047 }; 7048 7049 qup_uart14_rx: qup-uart14-rx-state { 7050 pins = "gpio92"; 7051 function = "qup1_se6"; 7052 }; 7053 7054 qup_uart15_cts: qup-uart15-cts-state { 7055 pins = "gpio91"; 7056 function = "qup1_se7"; 7057 }; 7058 7059 qup_uart15_rts: qup-uart15-rts-state { 7060 pins = "gpio92"; 7061 function = "qup1_se7"; 7062 }; 7063 7064 qup_uart15_tx: qup-uart15-tx-state { 7065 pins = "gpio89"; 7066 function = "qup1_se7"; 7067 }; 7068 7069 qup_uart15_rx: qup-uart15-rx-state { 7070 pins = "gpio90"; 7071 function = "qup1_se7"; 7072 }; 7073 7074 qup_uart16_cts: qup-uart16-cts-state { 7075 pins = "gpio10"; 7076 function = "qup2_se0"; 7077 }; 7078 7079 qup_uart16_rts: qup-uart16-rts-state { 7080 pins = "gpio11"; 7081 function = "qup2_se0"; 7082 }; 7083 7084 qup_uart16_tx: qup-uart16-tx-state { 7085 pins = "gpio12"; 7086 function = "qup2_se0"; 7087 }; 7088 7089 qup_uart16_rx: qup-uart16-rx-state { 7090 pins = "gpio13"; 7091 function = "qup2_se0"; 7092 }; 7093 7094 sdc1_state_on: sdc1-on-state { 7095 clk-pins { 7096 pins = "sdc1_clk"; 7097 drive-strength = <16>; 7098 bias-disable; 7099 }; 7100 7101 cmd-pins { 7102 pins = "sdc1_cmd"; 7103 drive-strength = <10>; 7104 bias-pull-up; 7105 }; 7106 7107 data-pins { 7108 pins = "sdc1_data"; 7109 drive-strength = <10>; 7110 bias-pull-up; 7111 }; 7112 7113 rclk-pins { 7114 pins = "sdc1_rclk"; 7115 bias-pull-down; 7116 }; 7117 }; 7118 7119 sdc1_state_off: sdc1-off-state { 7120 clk-pins { 7121 pins = "sdc1_clk"; 7122 drive-strength = <2>; 7123 bias-bus-hold; 7124 }; 7125 7126 cmd-pins { 7127 pins = "sdc1_cmd"; 7128 drive-strength = <2>; 7129 bias-bus-hold; 7130 }; 7131 7132 data-pins { 7133 pins = "sdc1_data"; 7134 drive-strength = <2>; 7135 bias-bus-hold; 7136 }; 7137 7138 rclk-pins { 7139 pins = "sdc1_rclk"; 7140 bias-bus-hold; 7141 }; 7142 }; 7143 }; 7144 7145 sram: sram@146d8000 { 7146 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 7147 reg = <0x0 0x146d8000 0x0 0x1000>; 7148 ranges = <0x0 0x0 0x146d8000 0x1000>; 7149 7150 #address-cells = <1>; 7151 #size-cells = <1>; 7152 7153 pil-reloc@94c { 7154 compatible = "qcom,pil-reloc-info"; 7155 reg = <0x94c 0xc8>; 7156 }; 7157 }; 7158 7159 apps_smmu: iommu@15000000 { 7160 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7161 7162 reg = <0x0 0x15000000 0x0 0x100000>; 7163 #iommu-cells = <2>; 7164 #global-interrupts = <2>; 7165 dma-coherent; 7166 7167 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 7168 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 7169 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 7170 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 7171 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 7172 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 7173 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 7174 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 7175 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 7176 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 7177 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 7178 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 7179 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 7180 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 7181 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 7182 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 7183 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 7184 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 7185 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 7186 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 7187 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 7188 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 7189 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 7190 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 7191 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 7192 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 7193 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 7194 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 7195 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 7196 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 7197 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 7198 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 7199 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 7200 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 7201 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 7202 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 7203 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 7204 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 7205 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 7206 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 7207 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 7208 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 7209 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 7210 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 7211 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 7212 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 7213 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 7214 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 7215 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 7216 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 7217 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 7218 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 7219 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 7220 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 7221 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 7222 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 7223 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 7224 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 7225 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 7226 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 7227 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 7228 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 7229 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 7230 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 7231 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 7232 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 7233 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 7234 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 7235 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 7236 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 7237 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 7238 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 7239 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 7240 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 7241 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 7242 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 7243 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 7244 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 7245 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 7246 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 7247 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 7248 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 7249 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 7250 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 7251 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 7252 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 7253 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 7254 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 7255 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 7256 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 7257 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 7258 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 7259 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 7260 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 7261 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 7262 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 7263 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 7264 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 7265 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 7266 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 7267 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 7268 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 7269 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 7270 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 7271 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 7272 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 7273 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 7274 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 7275 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 7276 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 7277 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 7278 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 7279 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 7280 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 7281 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 7282 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 7283 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 7284 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 7285 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 7286 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 7287 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 7288 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 7289 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 7290 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 7291 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 7292 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 7293 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 7294 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 7295 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 7296 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 7297 }; 7298 7299 pcie_smmu: iommu@15200000 { 7300 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 7301 reg = <0x0 0x15200000 0x0 0x80000>; 7302 #iommu-cells = <2>; 7303 #global-interrupts = <2>; 7304 dma-coherent; 7305 7306 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 7307 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 7308 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 7309 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 7310 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 7311 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 7312 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 7313 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 7314 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 7315 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 7316 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 7317 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 7318 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 7319 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 7320 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 7321 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 7322 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 7323 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 7324 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 7325 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 7326 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 7327 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 7328 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 7329 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 7330 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 7331 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 7332 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 7333 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 7334 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 7335 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 7336 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 7337 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 7338 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 7339 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 7340 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 7341 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 7342 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 7343 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 7344 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 7345 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 7346 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 7347 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 7348 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 7349 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 7350 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 7351 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 7352 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 7353 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 7354 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 7355 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 7356 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 7357 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 7358 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 7359 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 7360 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 7361 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 7362 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 7363 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 7364 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 7365 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 7366 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 7367 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 7368 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 7369 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 7370 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 7371 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 7372 }; 7373 7374 intc: interrupt-controller@17a00000 { 7375 compatible = "arm,gic-v3"; 7376 reg = <0x0 0x17a00000 0x0 0x10000>, 7377 <0x0 0x17a60000 0x0 0x100000>; 7378 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 7379 #interrupt-cells = <3>; 7380 interrupt-controller; 7381 #redistributor-regions = <1>; 7382 redistributor-stride = <0x0 0x20000>; 7383 }; 7384 7385 watchdog@17c10000 { 7386 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 7387 reg = <0x0 0x17c10000 0x0 0x1000>; 7388 clocks = <&sleep_clk>; 7389 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 7390 }; 7391 7392 timer@17c20000 { 7393 compatible = "arm,armv7-timer-mem"; 7394 reg = <0x0 0x17c20000 0x0 0x1000>; 7395 ranges = <0x0 0x0 0x0 0x20000000>; 7396 #address-cells = <1>; 7397 #size-cells = <1>; 7398 7399 frame@17c21000 { 7400 reg = <0x17c21000 0x1000>, 7401 <0x17c22000 0x1000>; 7402 frame-number = <0>; 7403 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 7404 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 7405 }; 7406 7407 frame@17c23000 { 7408 reg = <0x17c23000 0x1000>; 7409 frame-number = <1>; 7410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 7411 status = "disabled"; 7412 }; 7413 7414 frame@17c25000 { 7415 reg = <0x17c25000 0x1000>; 7416 frame-number = <2>; 7417 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 7418 status = "disabled"; 7419 }; 7420 7421 frame@17c27000 { 7422 reg = <0x17c27000 0x1000>; 7423 frame-number = <3>; 7424 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 7425 status = "disabled"; 7426 }; 7427 7428 frame@17c29000 { 7429 reg = <0x17c29000 0x1000>; 7430 frame-number = <4>; 7431 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 7432 status = "disabled"; 7433 }; 7434 7435 frame@17c2b000 { 7436 reg = <0x17c2b000 0x1000>; 7437 frame-number = <5>; 7438 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 7439 status = "disabled"; 7440 }; 7441 7442 frame@17c2d000 { 7443 reg = <0x17c2d000 0x1000>; 7444 frame-number = <6>; 7445 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 7446 status = "disabled"; 7447 }; 7448 }; 7449 7450 apps_rsc: rsc@18200000 { 7451 compatible = "qcom,rpmh-rsc"; 7452 reg = <0x0 0x18200000 0x0 0x10000>, 7453 <0x0 0x18210000 0x0 0x10000>, 7454 <0x0 0x18220000 0x0 0x10000>; 7455 reg-names = "drv-0", 7456 "drv-1", 7457 "drv-2"; 7458 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 7459 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 7460 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 7461 7462 power-domains = <&system_pd>; 7463 label = "apps_rsc"; 7464 7465 qcom,tcs-offset = <0xd00>; 7466 qcom,drv-id = <2>; 7467 qcom,tcs-config = <ACTIVE_TCS 2>, 7468 <SLEEP_TCS 3>, 7469 <WAKE_TCS 3>, 7470 <CONTROL_TCS 0>; 7471 7472 apps_bcm_voter: bcm-voter { 7473 compatible = "qcom,bcm-voter"; 7474 }; 7475 7476 rpmhcc: clock-controller { 7477 compatible = "qcom,sa8775p-rpmh-clk"; 7478 #clock-cells = <1>; 7479 clocks = <&xo_board_clk>; 7480 clock-names = "xo"; 7481 }; 7482 7483 rpmhpd: power-controller { 7484 compatible = "qcom,qcs8300-rpmhpd"; 7485 #power-domain-cells = <1>; 7486 operating-points-v2 = <&rpmhpd_opp_table>; 7487 7488 rpmhpd_opp_table: opp-table { 7489 compatible = "operating-points-v2"; 7490 7491 rpmhpd_opp_ret: opp-0 { 7492 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 7493 }; 7494 7495 rpmhpd_opp_min_svs: opp-1 { 7496 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 7497 }; 7498 7499 rpmhpd_opp_low_svs: opp-2 { 7500 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 7501 }; 7502 7503 rpmhpd_opp_svs: opp-3 { 7504 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 7505 }; 7506 7507 rpmhpd_opp_svs_l1: opp-4 { 7508 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 7509 }; 7510 7511 rpmhpd_opp_nom: opp-5 { 7512 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7513 }; 7514 7515 rpmhpd_opp_nom_l1: opp-6 { 7516 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7517 }; 7518 7519 rpmhpd_opp_nom_l2: opp-7 { 7520 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 7521 }; 7522 7523 rpmhpd_opp_turbo: opp-8 { 7524 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7525 }; 7526 7527 rpmhpd_opp_turbo_l1: opp-9 { 7528 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7529 }; 7530 }; 7531 }; 7532 }; 7533 7534 epss_l3_cl0: interconnect@18590000 { 7535 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7536 "qcom,epss-l3"; 7537 reg = <0x0 0x18590000 0x0 0x1000>; 7538 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7539 clock-names = "xo", "alternate"; 7540 #interconnect-cells = <1>; 7541 }; 7542 7543 cpufreq_hw: cpufreq@18591000 { 7544 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 7545 reg = <0x0 0x18591000 0x0 0x1000>, 7546 <0x0 0x18593000 0x0 0x1000>, 7547 <0x0 0x18594000 0x0 0x1000>; 7548 reg-names = "freq-domain0", 7549 "freq-domain1", 7550 "freq-domain2"; 7551 7552 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7553 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 7554 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 7555 interrupt-names = "dcvsh-irq-0", 7556 "dcvsh-irq-1", 7557 "dcvsh-irq-2"; 7558 7559 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7560 clock-names = "xo", "alternate"; 7561 7562 #freq-domain-cells = <1>; 7563 }; 7564 7565 epss_l3_cl1: interconnect@18592000 { 7566 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 7567 "qcom,epss-l3"; 7568 reg = <0x0 0x18592000 0x0 0x1000>; 7569 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7570 clock-names = "xo", "alternate"; 7571 #interconnect-cells = <1>; 7572 }; 7573 7574 remoteproc_gpdsp: remoteproc@20c00000 { 7575 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 7576 reg = <0x0 0x20c00000 0x0 0x10000>; 7577 7578 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 7579 <&smp2p_gpdsp_in 0 0>, 7580 <&smp2p_gpdsp_in 1 0>, 7581 <&smp2p_gpdsp_in 2 0>, 7582 <&smp2p_gpdsp_in 3 0>; 7583 interrupt-names = "wdog", 7584 "fatal", 7585 "ready", 7586 "handover", 7587 "stop-ack"; 7588 7589 clocks = <&rpmhcc RPMH_CXO_CLK>; 7590 clock-names = "xo"; 7591 7592 power-domains = <&rpmhpd RPMHPD_CX>, 7593 <&rpmhpd RPMHPD_MXC>; 7594 power-domain-names = "cx", 7595 "mxc"; 7596 7597 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 7598 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 7599 7600 memory-region = <&gpdsp_mem>; 7601 7602 qcom,qmp = <&aoss_qmp>; 7603 7604 qcom,smem-states = <&smp2p_gpdsp_out 0>; 7605 qcom,smem-state-names = "stop"; 7606 7607 status = "disabled"; 7608 7609 glink-edge { 7610 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 7611 IPCC_MPROC_SIGNAL_GLINK_QMP 7612 IRQ_TYPE_EDGE_RISING>; 7613 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 7614 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7615 7616 label = "gpdsp"; 7617 qcom,remote-pid = <17>; 7618 }; 7619 }; 7620 7621 ethernet0: ethernet@23040000 { 7622 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 7623 reg = <0x0 0x23040000 0x0 0x00010000>, 7624 <0x0 0x23056000 0x0 0x00000100>; 7625 reg-names = "stmmaceth", "rgmii"; 7626 7627 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 7628 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 7629 interrupt-names = "macirq", "sfty"; 7630 7631 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 7632 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 7633 <&gcc GCC_EMAC0_PTP_CLK>, 7634 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 7635 clock-names = "stmmaceth", 7636 "pclk", 7637 "ptp_ref", 7638 "phyaux"; 7639 power-domains = <&gcc GCC_EMAC0_GDSC>; 7640 7641 phys = <&serdes0>; 7642 phy-names = "serdes"; 7643 7644 iommus = <&apps_smmu 0x120 0xf>; 7645 dma-coherent; 7646 7647 snps,tso; 7648 snps,pbl = <32>; 7649 rx-fifo-depth = <16384>; 7650 tx-fifo-depth = <20480>; 7651 7652 status = "disabled"; 7653 }; 7654 7655 nspa_noc: interconnect@260c0000 { 7656 compatible = "qcom,qcs8300-nspa-noc"; 7657 reg = <0x0 0x260c0000 0x0 0x16080>; 7658 #interconnect-cells = <2>; 7659 qcom,bcm-voters = <&apps_bcm_voter>; 7660 }; 7661 7662 remoteproc_cdsp: remoteproc@26300000 { 7663 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 7664 reg = <0x0 0x26300000 0x0 0x10000>; 7665 7666 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 7667 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 7668 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 7669 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 7670 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 7671 interrupt-names = "wdog", 7672 "fatal", 7673 "ready", 7674 "handover", 7675 "stop-ack"; 7676 7677 clocks = <&rpmhcc RPMH_CXO_CLK>; 7678 clock-names = "xo"; 7679 7680 power-domains = <&rpmhpd RPMHPD_CX>, 7681 <&rpmhpd RPMHPD_MXC>, 7682 <&rpmhpd RPMHPD_NSP0>; 7683 7684 power-domain-names = "cx", 7685 "mxc", 7686 "nsp"; 7687 7688 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 7689 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 7690 7691 memory-region = <&cdsp_mem>; 7692 7693 qcom,qmp = <&aoss_qmp>; 7694 7695 qcom,smem-states = <&smp2p_cdsp_out 0>; 7696 qcom,smem-state-names = "stop"; 7697 7698 status = "disabled"; 7699 7700 glink-edge { 7701 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 7702 IPCC_MPROC_SIGNAL_GLINK_QMP 7703 IRQ_TYPE_EDGE_RISING>; 7704 mboxes = <&ipcc IPCC_CLIENT_CDSP 7705 IPCC_MPROC_SIGNAL_GLINK_QMP>; 7706 7707 label = "cdsp"; 7708 qcom,remote-pid = <5>; 7709 7710 fastrpc { 7711 compatible = "qcom,fastrpc"; 7712 qcom,glink-channels = "fastrpcglink-apps-dsp"; 7713 label = "cdsp"; 7714 #address-cells = <1>; 7715 #size-cells = <0>; 7716 7717 compute-cb@1 { 7718 compatible = "qcom,fastrpc-compute-cb"; 7719 reg = <1>; 7720 iommus = <&apps_smmu 0x19c1 0x0440>, 7721 <&apps_smmu 0x1961 0x0400>; 7722 dma-coherent; 7723 }; 7724 7725 compute-cb@2 { 7726 compatible = "qcom,fastrpc-compute-cb"; 7727 reg = <2>; 7728 iommus = <&apps_smmu 0x19c2 0x0440>, 7729 <&apps_smmu 0x1962 0x0400>; 7730 dma-coherent; 7731 }; 7732 7733 compute-cb@3 { 7734 compatible = "qcom,fastrpc-compute-cb"; 7735 reg = <3>; 7736 iommus = <&apps_smmu 0x19c3 0x0440>, 7737 <&apps_smmu 0x1963 0x0400>; 7738 dma-coherent; 7739 }; 7740 7741 compute-cb@4 { 7742 compatible = "qcom,fastrpc-compute-cb"; 7743 reg = <4>; 7744 iommus = <&apps_smmu 0x19c4 0x0440>, 7745 <&apps_smmu 0x1964 0x0400>; 7746 dma-coherent; 7747 }; 7748 7749 compute-cb@5 { 7750 compatible = "qcom,fastrpc-compute-cb"; 7751 reg = <5>; 7752 iommus = <&apps_smmu 0x19c5 0x0400>; 7753 dma-coherent; 7754 }; 7755 7756 compute-cb@6 { 7757 compatible = "qcom,fastrpc-compute-cb"; 7758 reg = <6>; 7759 iommus = <&apps_smmu 0x19c6 0x0400>; 7760 dma-coherent; 7761 }; 7762 7763 compute-cb@7 { 7764 compatible = "qcom,fastrpc-compute-cb"; 7765 reg = <7>; 7766 iommus = <&apps_smmu 0x19c7 0x0400>; 7767 dma-coherent; 7768 }; 7769 7770 compute-cb@8 { 7771 compatible = "qcom,fastrpc-compute-cb"; 7772 reg = <8>; 7773 iommus = <&apps_smmu 0x19c8 0x0400>; 7774 dma-coherent; 7775 }; 7776 7777 compute-cb@9 { 7778 compatible = "qcom,fastrpc-compute-cb"; 7779 reg = <9>; 7780 iommus = <&apps_smmu 0x19c9 0x0400>; 7781 dma-coherent; 7782 }; 7783 7784 compute-cb@11 { 7785 compatible = "qcom,fastrpc-compute-cb"; 7786 reg = <0xb>; 7787 iommus = <&apps_smmu 0x19cb 0x0400>; 7788 dma-coherent; 7789 }; 7790 7791 compute-cb@12 { 7792 compatible = "qcom,fastrpc-compute-cb"; 7793 reg = <0xc>; 7794 iommus = <&apps_smmu 0x19cc 0x000>; 7795 dma-coherent; 7796 }; 7797 }; 7798 }; 7799 }; 7800 }; 7801 7802 thermal_zones: thermal-zones { 7803 aoss-0-thermal { 7804 thermal-sensors = <&tsens0 0>; 7805 7806 trips { 7807 aoss0-critical { 7808 temperature = <125000>; 7809 hysteresis = <1000>; 7810 type = "critical"; 7811 }; 7812 }; 7813 }; 7814 7815 cpu-0-0-0-thermal { 7816 thermal-sensors = <&tsens0 1>; 7817 7818 trips { 7819 cpu-critical { 7820 temperature = <125000>; 7821 hysteresis = <1000>; 7822 type = "critical"; 7823 }; 7824 }; 7825 }; 7826 7827 cpu-0-1-0-thermal { 7828 thermal-sensors = <&tsens0 2>; 7829 7830 trips { 7831 cpu-critical { 7832 temperature = <125000>; 7833 hysteresis = <1000>; 7834 type = "critical"; 7835 }; 7836 }; 7837 }; 7838 7839 cpu-0-2-0-thermal { 7840 thermal-sensors = <&tsens0 3>; 7841 7842 trips { 7843 cpu-critical { 7844 temperature = <125000>; 7845 hysteresis = <1000>; 7846 type = "critical"; 7847 }; 7848 }; 7849 }; 7850 7851 cpu-0-3-0-thermal { 7852 thermal-sensors = <&tsens0 4>; 7853 7854 trips { 7855 cpu-critical { 7856 temperature = <125000>; 7857 hysteresis = <1000>; 7858 type = "critical"; 7859 }; 7860 }; 7861 }; 7862 7863 gpuss-0-thermal { 7864 thermal-sensors = <&tsens0 5>; 7865 7866 trips { 7867 gpuss0_alert0: trip-point0 { 7868 temperature = <115000>; 7869 hysteresis = <5000>; 7870 type = "passive"; 7871 }; 7872 7873 gpuss0-critical { 7874 temperature = <125000>; 7875 hysteresis = <1000>; 7876 type = "critical"; 7877 }; 7878 }; 7879 7880 cooling-maps { 7881 map0 { 7882 trip = <&gpuss0_alert0>; 7883 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7884 }; 7885 }; 7886 }; 7887 7888 audio-thermal { 7889 thermal-sensors = <&tsens0 6>; 7890 7891 trips { 7892 audio-critical { 7893 temperature = <125000>; 7894 hysteresis = <1000>; 7895 type = "critical"; 7896 }; 7897 }; 7898 }; 7899 7900 camss-0-thermal { 7901 thermal-sensors = <&tsens0 7>; 7902 7903 trips { 7904 camss-critical { 7905 temperature = <125000>; 7906 hysteresis = <1000>; 7907 type = "critical"; 7908 }; 7909 }; 7910 }; 7911 7912 pcie-0-thermal { 7913 thermal-sensors = <&tsens0 8>; 7914 7915 trips { 7916 pcie-critical { 7917 temperature = <125000>; 7918 hysteresis = <1000>; 7919 type = "critical"; 7920 }; 7921 }; 7922 }; 7923 7924 cpuss-0-0-thermal { 7925 thermal-sensors = <&tsens0 9>; 7926 7927 trips { 7928 cpuss0-critical { 7929 temperature = <125000>; 7930 hysteresis = <1000>; 7931 type = "critical"; 7932 }; 7933 }; 7934 }; 7935 7936 aoss-1-thermal { 7937 thermal-sensors = <&tsens1 0>; 7938 7939 trips { 7940 aoss1-critical { 7941 temperature = <125000>; 7942 hysteresis = <1000>; 7943 type = "critical"; 7944 }; 7945 }; 7946 }; 7947 7948 cpu-0-0-1-thermal { 7949 thermal-sensors = <&tsens1 1>; 7950 7951 trips { 7952 cpu-critical { 7953 temperature = <125000>; 7954 hysteresis = <1000>; 7955 type = "critical"; 7956 }; 7957 }; 7958 }; 7959 7960 cpu-0-1-1-thermal { 7961 thermal-sensors = <&tsens1 2>; 7962 7963 trips { 7964 cpu-critical { 7965 temperature = <125000>; 7966 hysteresis = <1000>; 7967 type = "critical"; 7968 }; 7969 }; 7970 }; 7971 7972 cpu-0-2-1-thermal { 7973 thermal-sensors = <&tsens1 3>; 7974 7975 trips { 7976 cpu-critical { 7977 temperature = <125000>; 7978 hysteresis = <1000>; 7979 type = "critical"; 7980 }; 7981 }; 7982 }; 7983 7984 cpu-0-3-1-thermal { 7985 thermal-sensors = <&tsens1 4>; 7986 7987 trips { 7988 cpu-critical { 7989 temperature = <125000>; 7990 hysteresis = <1000>; 7991 type = "critical"; 7992 }; 7993 }; 7994 }; 7995 7996 gpuss-1-thermal { 7997 thermal-sensors = <&tsens1 5>; 7998 7999 trips { 8000 gpuss1_alert0: trip-point0 { 8001 temperature = <115000>; 8002 hysteresis = <5000>; 8003 type = "passive"; 8004 }; 8005 8006 gpuss1-critical { 8007 temperature = <125000>; 8008 hysteresis = <1000>; 8009 type = "critical"; 8010 }; 8011 }; 8012 8013 cooling-maps { 8014 map0 { 8015 trip = <&gpuss1_alert0>; 8016 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 8017 }; 8018 }; 8019 }; 8020 8021 video-thermal { 8022 thermal-sensors = <&tsens1 6>; 8023 8024 trips { 8025 video-critical { 8026 temperature = <125000>; 8027 hysteresis = <1000>; 8028 type = "critical"; 8029 }; 8030 }; 8031 }; 8032 8033 camss-1-thermal { 8034 thermal-sensors = <&tsens1 7>; 8035 8036 trips { 8037 camss1-critical { 8038 temperature = <125000>; 8039 hysteresis = <1000>; 8040 type = "critical"; 8041 }; 8042 }; 8043 }; 8044 8045 pcie-1-thermal { 8046 thermal-sensors = <&tsens1 8>; 8047 8048 trips { 8049 pcie-critical { 8050 temperature = <125000>; 8051 hysteresis = <1000>; 8052 type = "critical"; 8053 }; 8054 }; 8055 }; 8056 8057 cpuss-0-1-thermal { 8058 thermal-sensors = <&tsens1 9>; 8059 8060 trips { 8061 cpuss0-critical { 8062 temperature = <125000>; 8063 hysteresis = <1000>; 8064 type = "critical"; 8065 }; 8066 }; 8067 }; 8068 8069 aoss-2-thermal { 8070 thermal-sensors = <&tsens2 0>; 8071 8072 trips { 8073 aoss2-critical { 8074 temperature = <125000>; 8075 hysteresis = <1000>; 8076 type = "critical"; 8077 }; 8078 }; 8079 }; 8080 8081 cpu-1-0-0-thermal { 8082 thermal-sensors = <&tsens2 1>; 8083 8084 trips { 8085 cpu-critical { 8086 temperature = <125000>; 8087 hysteresis = <1000>; 8088 type = "critical"; 8089 }; 8090 }; 8091 }; 8092 8093 cpu-1-1-0-thermal { 8094 thermal-sensors = <&tsens2 2>; 8095 8096 trips { 8097 cpu-critical { 8098 temperature = <125000>; 8099 hysteresis = <1000>; 8100 type = "critical"; 8101 }; 8102 }; 8103 }; 8104 8105 cpu-1-2-0-thermal { 8106 thermal-sensors = <&tsens2 3>; 8107 8108 trips { 8109 cpu-critical { 8110 temperature = <125000>; 8111 hysteresis = <1000>; 8112 type = "critical"; 8113 }; 8114 }; 8115 }; 8116 8117 cpu-1-3-0-thermal { 8118 thermal-sensors = <&tsens2 4>; 8119 8120 trips { 8121 cpu-critical { 8122 temperature = <125000>; 8123 hysteresis = <1000>; 8124 type = "critical"; 8125 }; 8126 }; 8127 }; 8128 8129 nsp-0-0-0-thermal { 8130 thermal-sensors = <&tsens2 5>; 8131 8132 trips { 8133 nsp-critical { 8134 temperature = <125000>; 8135 hysteresis = <1000>; 8136 type = "critical"; 8137 }; 8138 }; 8139 }; 8140 8141 nsp-0-1-0-thermal { 8142 thermal-sensors = <&tsens2 6>; 8143 8144 trips { 8145 nsp-critical { 8146 temperature = <125000>; 8147 hysteresis = <1000>; 8148 type = "critical"; 8149 }; 8150 }; 8151 }; 8152 8153 nsp-0-2-0-thermal { 8154 thermal-sensors = <&tsens2 7>; 8155 8156 trips { 8157 nsp-critical { 8158 temperature = <125000>; 8159 hysteresis = <1000>; 8160 type = "critical"; 8161 }; 8162 }; 8163 }; 8164 8165 ddrss-0-thermal { 8166 thermal-sensors = <&tsens2 8>; 8167 8168 trips { 8169 ddrss-critical { 8170 temperature = <125000>; 8171 hysteresis = <1000>; 8172 type = "critical"; 8173 }; 8174 }; 8175 }; 8176 8177 cpuss-1-0-thermal { 8178 thermal-sensors = <&tsens2 9>; 8179 8180 trips { 8181 cpuss1-critical { 8182 temperature = <125000>; 8183 hysteresis = <1000>; 8184 type = "critical"; 8185 }; 8186 }; 8187 }; 8188 8189 aoss-3-thermal { 8190 thermal-sensors = <&tsens3 0>; 8191 8192 trips { 8193 aoss3-critical { 8194 temperature = <125000>; 8195 hysteresis = <1000>; 8196 type = "critical"; 8197 }; 8198 }; 8199 }; 8200 8201 cpu-1-0-1-thermal { 8202 thermal-sensors = <&tsens3 1>; 8203 8204 trips { 8205 cpu-critical { 8206 temperature = <125000>; 8207 hysteresis = <1000>; 8208 type = "critical"; 8209 }; 8210 }; 8211 }; 8212 8213 cpu-1-1-1-thermal { 8214 thermal-sensors = <&tsens3 2>; 8215 8216 trips { 8217 cpu-critical { 8218 temperature = <125000>; 8219 hysteresis = <1000>; 8220 type = "critical"; 8221 }; 8222 }; 8223 }; 8224 8225 cpu-1-2-1-thermal { 8226 thermal-sensors = <&tsens3 3>; 8227 8228 trips { 8229 cpu-critical { 8230 temperature = <125000>; 8231 hysteresis = <1000>; 8232 type = "critical"; 8233 }; 8234 }; 8235 }; 8236 8237 cpu-1-3-1-thermal { 8238 thermal-sensors = <&tsens3 4>; 8239 8240 trips { 8241 cpu-critical { 8242 temperature = <125000>; 8243 hysteresis = <1000>; 8244 type = "critical"; 8245 }; 8246 }; 8247 }; 8248 8249 nsp-0-0-1-thermal { 8250 thermal-sensors = <&tsens3 5>; 8251 8252 trips { 8253 nsp-critical { 8254 temperature = <125000>; 8255 hysteresis = <1000>; 8256 type = "critical"; 8257 }; 8258 }; 8259 }; 8260 8261 nsp-0-1-1-thermal { 8262 thermal-sensors = <&tsens3 6>; 8263 8264 trips { 8265 nsp-critical { 8266 temperature = <125000>; 8267 hysteresis = <1000>; 8268 type = "critical"; 8269 }; 8270 }; 8271 }; 8272 8273 nsp-0-2-1-thermal { 8274 thermal-sensors = <&tsens3 7>; 8275 8276 trips { 8277 nsp-critical { 8278 temperature = <125000>; 8279 hysteresis = <1000>; 8280 type = "critical"; 8281 }; 8282 }; 8283 }; 8284 8285 ddrss-1-thermal { 8286 thermal-sensors = <&tsens3 8>; 8287 8288 trips { 8289 ddrss-critical { 8290 temperature = <125000>; 8291 hysteresis = <1000>; 8292 type = "critical"; 8293 }; 8294 }; 8295 }; 8296 8297 cpuss-1-1-thermal { 8298 thermal-sensors = <&tsens3 9>; 8299 8300 trips { 8301 cpuss1-critical { 8302 temperature = <125000>; 8303 hysteresis = <1000>; 8304 type = "critical"; 8305 }; 8306 }; 8307 }; 8308 }; 8309 8310 timer { 8311 compatible = "arm,armv8-timer"; 8312 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 8313 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 8314 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 8315 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 8316 }; 8317}; 8318