1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Spreadtrum SC9860 SoC 4 * 5 * Copyright (C) 2016, Spreadtrum Communications Inc. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "whale2.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0 { 20 core0 { 21 cpu = <&CPU0>; 22 }; 23 core1 { 24 cpu = <&CPU1>; 25 }; 26 core2 { 27 cpu = <&CPU2>; 28 }; 29 core3 { 30 cpu = <&CPU3>; 31 }; 32 }; 33 34 cluster1 { 35 core0 { 36 cpu = <&CPU4>; 37 }; 38 core1 { 39 cpu = <&CPU5>; 40 }; 41 core2 { 42 cpu = <&CPU6>; 43 }; 44 core3 { 45 cpu = <&CPU7>; 46 }; 47 }; 48 }; 49 50 CPU0: cpu@530000 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 reg = <0x0 0x530000>; 54 enable-method = "psci"; 55 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 56 }; 57 58 CPU1: cpu@530001 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53"; 61 reg = <0x0 0x530001>; 62 enable-method = "psci"; 63 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 64 }; 65 66 CPU2: cpu@530002 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0 0x530002>; 70 enable-method = "psci"; 71 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 72 }; 73 74 CPU3: cpu@530003 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 reg = <0x0 0x530003>; 78 enable-method = "psci"; 79 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 80 }; 81 82 CPU4: cpu@530100 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x530100>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 88 }; 89 90 CPU5: cpu@530101 { 91 device_type = "cpu"; 92 compatible = "arm,cortex-a53"; 93 reg = <0x0 0x530101>; 94 enable-method = "psci"; 95 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 96 }; 97 98 CPU6: cpu@530102 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a53"; 101 reg = <0x0 0x530102>; 102 enable-method = "psci"; 103 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 104 }; 105 106 CPU7: cpu@530103 { 107 device_type = "cpu"; 108 compatible = "arm,cortex-a53"; 109 reg = <0x0 0x530103>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CORE_PD &CLUSTER_PD>; 112 }; 113 }; 114 115 idle-states { 116 entry-method = "psci"; 117 118 CORE_PD: core_pd { 119 compatible = "arm,idle-state"; 120 entry-latency-us = <1000>; 121 exit-latency-us = <700>; 122 min-residency-us = <2500>; 123 local-timer-stop; 124 arm,psci-suspend-param = <0x00010002>; 125 }; 126 127 CLUSTER_PD: cluster_pd { 128 compatible = "arm,idle-state"; 129 entry-latency-us = <1000>; 130 exit-latency-us = <1000>; 131 min-residency-us = <3000>; 132 local-timer-stop; 133 arm,psci-suspend-param = <0x01010003>; 134 }; 135 }; 136 137 psci { 138 compatible = "arm,psci-0.2"; 139 method = "smc"; 140 }; 141 142 timer { 143 compatible = "arm,armv8-timer"; 144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) 145 | IRQ_TYPE_LEVEL_LOW)>, 146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) 147 | IRQ_TYPE_LEVEL_LOW)>, 148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) 149 | IRQ_TYPE_LEVEL_LOW)>, 150 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) 151 | IRQ_TYPE_LEVEL_LOW)>; 152 }; 153 154 pmu { 155 compatible = "arm,cortex-a53-pmu"; 156 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-affinity = <&CPU0>, 165 <&CPU1>, 166 <&CPU2>, 167 <&CPU3>, 168 <&CPU4>, 169 <&CPU5>, 170 <&CPU6>, 171 <&CPU7>; 172 }; 173 174 soc { 175 gic: interrupt-controller@12001000 { 176 compatible = "arm,gic-400"; 177 reg = <0 0x12001000 0 0x1000>, 178 <0 0x12002000 0 0x2000>, 179 <0 0x12004000 0 0x2000>, 180 <0 0x12006000 0 0x2000>; 181 #interrupt-cells = <3>; 182 interrupt-controller; 183 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) 184 | IRQ_TYPE_LEVEL_HIGH)>; 185 }; 186 187 ap_clk: clock-controller@20000000 { 188 compatible = "sprd,sc9860-ap-clk"; 189 reg = <0 0x20000000 0 0x400>; 190 clocks = <&ext_26m>, <&pll 0>, 191 <&pmu_gate 0>; 192 #clock-cells = <1>; 193 }; 194 195 aon_prediv: aon-prediv@402d0000 { 196 compatible = "sprd,sc9860-aon-prediv"; 197 reg = <0 0x402d0000 0 0x400>; 198 clocks = <&ext_26m>, <&pll 0>, 199 <&pmu_gate 0>; 200 #clock-cells = <1>; 201 }; 202 203 204 aonsecure_clk: clock-controller@40880000 { 205 compatible = "sprd,sc9860-aonsecure-clk"; 206 reg = <0 0x40880000 0 0x400>; 207 clocks = <&ext_26m>, <&pll 0>; 208 #clock-cells = <1>; 209 }; 210 211 gpu_clk: clock-controller@60200000 { 212 compatible = "sprd,sc9860-gpu-clk"; 213 reg = <0 0x60200000 0 0x400>; 214 clocks = <&pll 0>; 215 #clock-cells = <1>; 216 }; 217 218 vsp_clk: clock-controller@61000000 { 219 compatible = "sprd,sc9860-vsp-clk"; 220 reg = <0 0x61000000 0 0x400>; 221 clocks = <&ext_26m>, <&pll 0>; 222 #clock-cells = <1>; 223 }; 224 225 cam_clk: clock-controller@62000000 { 226 compatible = "sprd,sc9860-cam-clk"; 227 reg = <0 0x62000000 0 0x4000>; 228 clocks = <&ext_26m>, <&pll 0>; 229 #clock-cells = <1>; 230 }; 231 232 disp_clk: clock-controller@63000000 { 233 compatible = "sprd,sc9860-disp-clk"; 234 reg = <0 0x63000000 0 0x400>; 235 clocks = <&ext_26m>, <&pll 0>; 236 #clock-cells = <1>; 237 }; 238 239 funnel@10001000 { /* SoC Funnel */ 240 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 241 reg = <0 0x10001000 0 0x1000>; 242 clocks = <&ext_26m>; 243 clock-names = "apb_pclk"; 244 out-ports { 245 port { 246 soc_funnel_out_port: endpoint { 247 remote-endpoint = <&etb_in>; 248 }; 249 }; 250 }; 251 252 in-ports { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 port@0 { 257 reg = <0>; 258 soc_funnel_in_port0: endpoint { 259 remote-endpoint = 260 <&main_funnel_out_port>; 261 }; 262 }; 263 264 port@4 { 265 reg = <4>; 266 soc_funnel_in_port1: endpoint { 267 remote-endpoint = 268 <&stm_out_port>; 269 }; 270 }; 271 }; 272 }; 273 274 etb@10003000 { 275 compatible = "arm,coresight-tmc", "arm,primecell"; 276 reg = <0 0x10003000 0 0x1000>; 277 clocks = <&ext_26m>; 278 clock-names = "apb_pclk"; 279 out-ports { 280 port { 281 etb_in: endpoint { 282 remote-endpoint = 283 <&soc_funnel_out_port>; 284 }; 285 }; 286 }; 287 }; 288 289 stm@10006000 { 290 compatible = "arm,coresight-stm", "arm,primecell"; 291 reg = <0 0x10006000 0 0x1000>, 292 <0 0x01000000 0 0x180000>; 293 reg-names = "stm-base", "stm-stimulus-base"; 294 clocks = <&ext_26m>; 295 clock-names = "apb_pclk"; 296 out-ports { 297 port { 298 stm_out_port: endpoint { 299 remote-endpoint = 300 <&soc_funnel_in_port1>; 301 }; 302 }; 303 }; 304 }; 305 306 funnel@11001000 { /* Cluster0 Funnel */ 307 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 308 reg = <0 0x11001000 0 0x1000>; 309 clocks = <&ext_26m>; 310 clock-names = "apb_pclk"; 311 out-ports { 312 port { 313 cluster0_funnel_out_port: endpoint { 314 remote-endpoint = 315 <&cluster0_etf_in>; 316 }; 317 }; 318 }; 319 320 in-ports { 321 #address-cells = <1>; 322 #size-cells = <0>; 323 324 port@0 { 325 reg = <0>; 326 cluster0_funnel_in_port0: endpoint { 327 remote-endpoint = <&etm0_out>; 328 }; 329 }; 330 331 port@1 { 332 reg = <1>; 333 cluster0_funnel_in_port1: endpoint { 334 remote-endpoint = <&etm1_out>; 335 }; 336 }; 337 338 port@2 { 339 reg = <2>; 340 cluster0_funnel_in_port2: endpoint { 341 remote-endpoint = <&etm2_out>; 342 }; 343 }; 344 345 port@4 { 346 reg = <4>; 347 cluster0_funnel_in_port3: endpoint { 348 remote-endpoint = <&etm3_out>; 349 }; 350 }; 351 }; 352 }; 353 354 funnel@11002000 { /* Cluster1 Funnel */ 355 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 356 reg = <0 0x11002000 0 0x1000>; 357 clocks = <&ext_26m>; 358 clock-names = "apb_pclk"; 359 out-ports { 360 port { 361 cluster1_funnel_out_port: endpoint { 362 remote-endpoint = 363 <&cluster1_etf_in>; 364 }; 365 }; 366 }; 367 368 in-ports { 369 #address-cells = <1>; 370 #size-cells = <0>; 371 372 port@0 { 373 reg = <0>; 374 cluster1_funnel_in_port0: endpoint { 375 remote-endpoint = <&etm4_out>; 376 }; 377 }; 378 379 port@1 { 380 reg = <1>; 381 cluster1_funnel_in_port1: endpoint { 382 remote-endpoint = <&etm5_out>; 383 }; 384 }; 385 386 port@2 { 387 reg = <2>; 388 cluster1_funnel_in_port2: endpoint { 389 remote-endpoint = <&etm6_out>; 390 }; 391 }; 392 393 port@3 { 394 reg = <3>; 395 cluster1_funnel_in_port3: endpoint { 396 remote-endpoint = <&etm7_out>; 397 }; 398 }; 399 }; 400 }; 401 402 etf@11003000 { /* ETF on Cluster0 */ 403 compatible = "arm,coresight-tmc", "arm,primecell"; 404 reg = <0 0x11003000 0 0x1000>; 405 clocks = <&ext_26m>; 406 clock-names = "apb_pclk"; 407 408 out-ports { 409 port { 410 cluster0_etf_out: endpoint { 411 remote-endpoint = 412 <&main_funnel_in_port0>; 413 }; 414 }; 415 }; 416 417 in-ports { 418 port { 419 cluster0_etf_in: endpoint { 420 remote-endpoint = 421 <&cluster0_funnel_out_port>; 422 }; 423 }; 424 }; 425 }; 426 427 etf@11004000 { /* ETF on Cluster1 */ 428 compatible = "arm,coresight-tmc", "arm,primecell"; 429 reg = <0 0x11004000 0 0x1000>; 430 clocks = <&ext_26m>; 431 clock-names = "apb_pclk"; 432 433 out-ports { 434 port { 435 cluster1_etf_out: endpoint { 436 remote-endpoint = 437 <&main_funnel_in_port1>; 438 }; 439 }; 440 }; 441 442 in-ports { 443 port { 444 cluster1_etf_in: endpoint { 445 remote-endpoint = 446 <&cluster1_funnel_out_port>; 447 }; 448 }; 449 }; 450 }; 451 452 funnel@11005000 { /* Main Funnel */ 453 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 454 reg = <0 0x11005000 0 0x1000>; 455 clocks = <&ext_26m>; 456 clock-names = "apb_pclk"; 457 458 out-ports { 459 port { 460 main_funnel_out_port: endpoint { 461 remote-endpoint = 462 <&soc_funnel_in_port0>; 463 }; 464 }; 465 }; 466 467 in-ports { 468 #address-cells = <1>; 469 #size-cells = <0>; 470 471 port@0 { 472 reg = <0>; 473 main_funnel_in_port0: endpoint { 474 remote-endpoint = 475 <&cluster0_etf_out>; 476 }; 477 }; 478 479 port@1 { 480 reg = <1>; 481 main_funnel_in_port1: endpoint { 482 remote-endpoint = 483 <&cluster1_etf_out>; 484 }; 485 }; 486 }; 487 }; 488 489 etm@11440000 { 490 compatible = "arm,coresight-etm4x", "arm,primecell"; 491 reg = <0 0x11440000 0 0x1000>; 492 cpu = <&CPU0>; 493 clocks = <&ext_26m>; 494 clock-names = "apb_pclk"; 495 496 out-ports { 497 port { 498 etm0_out: endpoint { 499 remote-endpoint = 500 <&cluster0_funnel_in_port0>; 501 }; 502 }; 503 }; 504 }; 505 506 etm@11540000 { 507 compatible = "arm,coresight-etm4x", "arm,primecell"; 508 reg = <0 0x11540000 0 0x1000>; 509 cpu = <&CPU1>; 510 clocks = <&ext_26m>; 511 clock-names = "apb_pclk"; 512 513 out-ports { 514 port { 515 etm1_out: endpoint { 516 remote-endpoint = 517 <&cluster0_funnel_in_port1>; 518 }; 519 }; 520 }; 521 }; 522 523 etm@11640000 { 524 compatible = "arm,coresight-etm4x", "arm,primecell"; 525 reg = <0 0x11640000 0 0x1000>; 526 cpu = <&CPU2>; 527 clocks = <&ext_26m>; 528 clock-names = "apb_pclk"; 529 530 out-ports { 531 port { 532 etm2_out: endpoint { 533 remote-endpoint = 534 <&cluster0_funnel_in_port2>; 535 }; 536 }; 537 }; 538 }; 539 540 etm@11740000 { 541 compatible = "arm,coresight-etm4x", "arm,primecell"; 542 reg = <0 0x11740000 0 0x1000>; 543 cpu = <&CPU3>; 544 clocks = <&ext_26m>; 545 clock-names = "apb_pclk"; 546 547 out-ports { 548 port { 549 etm3_out: endpoint { 550 remote-endpoint = 551 <&cluster0_funnel_in_port3>; 552 }; 553 }; 554 }; 555 }; 556 557 etm@11840000 { 558 compatible = "arm,coresight-etm4x", "arm,primecell"; 559 reg = <0 0x11840000 0 0x1000>; 560 cpu = <&CPU4>; 561 clocks = <&ext_26m>; 562 clock-names = "apb_pclk"; 563 564 out-ports { 565 port { 566 etm4_out: endpoint { 567 remote-endpoint = 568 <&cluster1_funnel_in_port0>; 569 }; 570 }; 571 }; 572 }; 573 574 etm@11940000 { 575 compatible = "arm,coresight-etm4x", "arm,primecell"; 576 reg = <0 0x11940000 0 0x1000>; 577 cpu = <&CPU5>; 578 clocks = <&ext_26m>; 579 clock-names = "apb_pclk"; 580 581 out-ports { 582 port { 583 etm5_out: endpoint { 584 remote-endpoint = 585 <&cluster1_funnel_in_port1>; 586 }; 587 }; 588 }; 589 }; 590 591 etm@11a40000 { 592 compatible = "arm,coresight-etm4x", "arm,primecell"; 593 reg = <0 0x11a40000 0 0x1000>; 594 cpu = <&CPU6>; 595 clocks = <&ext_26m>; 596 clock-names = "apb_pclk"; 597 598 out-ports { 599 port { 600 etm6_out: endpoint { 601 remote-endpoint = 602 <&cluster1_funnel_in_port2>; 603 }; 604 }; 605 }; 606 }; 607 608 etm@11b40000 { 609 compatible = "arm,coresight-etm4x", "arm,primecell"; 610 reg = <0 0x11b40000 0 0x1000>; 611 cpu = <&CPU7>; 612 clocks = <&ext_26m>; 613 clock-names = "apb_pclk"; 614 615 out-ports { 616 port { 617 etm7_out: endpoint { 618 remote-endpoint = 619 <&cluster1_funnel_in_port3>; 620 }; 621 }; 622 }; 623 }; 624 }; 625}; 626